{"id":2231238,"url":"http://patchwork.ozlabs.org/api/patches/2231238/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260430122602.126722-4-aleksandr.loktionov@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430122602.126722-4-aleksandr.loktionov@intel.com>","list_archive_url":null,"date":"2026-04-30T12:26:00","name":"[3/5] ice: add correct handling of SMA/u.FL states","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ce883c100a947c4d06ca22d57518d642278a144d","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/?format=json","name":"Aleksandr Loktionov","email":"aleksandr.loktionov@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260430122602.126722-4-aleksandr.loktionov@intel.com/mbox/","series":[{"id":502294,"url":"http://patchwork.ozlabs.org/api/series/502294/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=502294","date":"2026-04-30T12:25:58","name":"ice: five small fixes and cleanups","version":1,"mbox":"http://patchwork.ozlabs.org/series/502294/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231238/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231238/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=c1oGfeRT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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a=\"78689190\"","E=Sophos;i=\"6.23,208,1770624000\"; d=\"scan'208\";a=\"78689190\"","E=Sophos;i=\"6.23,208,1770624000\"; d=\"scan'208\";a=\"233538433\""],"X-ExtLoop1":"1","From":"Aleksandr Loktionov ","To":"intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com,\n aleksandr.loktionov@intel.com","Cc":"netdev@vger.kernel.org","Date":"Thu, 30 Apr 2026 14:26:00 +0200","Message-ID":"<20260430122602.126722-4-aleksandr.loktionov@intel.com>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20260430122602.126722-1-aleksandr.loktionov@intel.com>","References":"<20260430122602.126722-1-aleksandr.loktionov@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777551969; x=1809087969;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=iMyBM89b2seTFG8wKFYplgNuifzMOqRBwqYX3WhqWOE=;\n b=l4Uynsl/p4DItv2+ucCAlT4nqgRQHVDm1zALqYYL/9FmgDRQDZsDftBO\n oLQeyAzO8wX8gCD7wCt3CWvnv1scLXnN+wwWH3n9PyI44EfJQl4Vam/Gt\n T93qD8JtMdihJ8HZL4J7tQZrOph1VoZ+uYbixlk3LwFVWJHcvf8nmfBAZ\n i6UtLGLKx5aPeZKaBUOgbHUvuCii171BAzQ/uo28jiGjW4qbUFFAu8LeW\n Vv2hIm0OmEz3/uX4koTUhKA5YVL6WNkQJMZ2cDCzzgI+XUURTJddpksHv\n qndUAmmXE++hkLj3RZWKPj+VJHE4h4j4uHxFEiYpaO9yi/viJxR200ANu\n w==;","X-Mailman-Original-Authentication-Results":["smtp2.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp2.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=l4Uynsl/"],"Subject":"[Intel-wired-lan] [PATCH 3/5] ice: add correct handling of SMA/u.FL\n states","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"The ICE_SMA2_UFL2_RX_DIS bit name is wrong: the bit is active high\n(setting it *enables* RX for u.FL2 / SMA2), not active low. Rename\nit to ICE_SMA2_UFL2_RX_EN and invert the use sites in ice_dpll.c so\nthat enabling the u.FL2 pin clears the bit (as it used to do) and\ndisabling sets it.\n\nFixes: 2dd5d03c77e2 (\"ice: redesign dpll sma/u.fl pins control\")\nSigned-off-by: Aleksandr Loktionov \n---\n drivers/net/ethernet/intel/ice/ice_dpll.c | 6 +++---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 ++--\n 2 files changed, 5 insertions(+), 5 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c\nindex 62f75701d..7e8bb63 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dpll.c\n+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c\n@@ -672,7 +672,7 @@ ice_dpll_sw_pins_update(struct ice_pf *pf)\n \t\tp->active = false;\n \n \tp = &d->ufl[ICE_DPLL_PIN_SW_2_IDX];\n-\tp->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_DIS);\n+\tp->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_EN);\n \td->sma_data = data;\n \n \treturn 0;\n@@ -1264,10 +1264,10 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv,\n \tcase ICE_DPLL_PIN_SW_2_IDX:\n \t\tif (state == DPLL_PIN_STATE_SELECTABLE) {\n \t\t\tdata |= ICE_SMA2_DIR_EN;\n-\t\t\tdata &= ~ICE_SMA2_UFL2_RX_DIS;\n+\t\t\tdata &= ~ICE_SMA2_UFL2_RX_EN;\n \t\t\tenable = true;\n \t\t} else if (state == DPLL_PIN_STATE_DISCONNECTED) {\n-\t\t\tdata |= ICE_SMA2_UFL2_RX_DIS;\n+\t\t\tdata |= ICE_SMA2_UFL2_RX_EN;\n \t\t\tenable = false;\n \t\t} else {\n \t\t\tgoto unlock;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\nindex c1aa408..278d757 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n@@ -655,12 +655,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw)\n /* SMA controller pin control */\n #define ICE_SMA1_DIR_EN\t\tBIT(4)\n #define ICE_SMA1_TX_EN\t\tBIT(5)\n-#define ICE_SMA2_UFL2_RX_DIS\tBIT(3)\n+#define ICE_SMA2_UFL2_RX_EN\tBIT(3)\n #define ICE_SMA2_DIR_EN\t\tBIT(6)\n #define ICE_SMA2_TX_EN\t\tBIT(7)\n \n #define ICE_SMA1_MASK\t\t(ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)\n-#define ICE_SMA2_MASK\t\t(ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \\\n+#define ICE_SMA2_MASK\t\t(ICE_SMA2_UFL2_RX_EN | ICE_SMA2_DIR_EN | \\\n \t\t\t\t ICE_SMA2_TX_EN)\n #define ICE_SMA2_INACTIVE_MASK\t(ICE_SMA2_DIR_EN | ICE_SMA2_TX_EN)\n #define ICE_ALL_SMA_MASK\t(ICE_SMA1_MASK | ICE_SMA2_MASK)\n","prefixes":["3/5"]}