{"id":2231232,"url":"http://patchwork.ozlabs.org/api/patches/2231232/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/0880332fd0d61e2f4d497da8dd7fd10c9d65dd9a.1777551598.git.michal.simek@amd.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<0880332fd0d61e2f4d497da8dd7fd10c9d65dd9a.1777551598.git.michal.simek@amd.com>","list_archive_url":null,"date":"2026-04-30T12:20:03","name":"[3/4] spi: cadence: Use reset_reset_bulk() for proper reset cycling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6461e9eb3b9bfa68367ec1731e32985ad2dab19a","submitter":{"id":84271,"url":"http://patchwork.ozlabs.org/api/people/84271/?format=json","name":"Michal Simek","email":"michal.simek@amd.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/0880332fd0d61e2f4d497da8dd7fd10c9d65dd9a.1777551598.git.michal.simek@amd.com/mbox/","series":[{"id":502293,"url":"http://patchwork.ozlabs.org/api/series/502293/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502293","date":"2026-04-30T12:20:00","name":"reset: Introduce reset_reset.*() API","version":1,"mbox":"http://patchwork.ozlabs.org/series/502293/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231232/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231232/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=B3eXS3CS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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helo=satlexmb07.amd.com; pr=C","From":"Michal Simek ","To":", ","CC":"Andrew Goodbody , Naman Trivedi\n , Padmarao Begari ,\n Senthil Nathan Thangaraj , Tom Rini\n , Venkatesh Yadav Abbarapu ","Subject":"[PATCH 3/4] spi: cadence: Use reset_reset_bulk() for proper reset\n cycling","Date":"Thu, 30 Apr 2026 14:20:03 +0200","Message-ID":"\n <0880332fd0d61e2f4d497da8dd7fd10c9d65dd9a.1777551598.git.michal.simek@amd.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"","References":"","MIME-Version":"1.0","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1229; i=michal.simek@amd.com;\n h=from:subject:message-id; bh=aDBzux14Uqhs4it5zfGmwEPklBvVPBOPXJhXQYq9GCs=;\n b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWR+9vjN+UZKnHWF/AS7/2eqMx55MMw0nPJ7zwe7bgcug\n XecwWXPO0pZGMQ4GGTFFFmmM+k4rPl2banY8sh8mDmsTCBDGLg4BWAindoM/yuWaAdPs7c8tq2p\n Yrr8DYvK45l5giI5z5rlpntMuXtn2mxGhi9Nvxb86P9dv+LcD5ky0clMWWJHax7PtOn4LBCzcsX\n b56wA","X-Developer-Key":"i=michal.simek@amd.com; a=openpgp;\n fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"DS3PEPF000099DF:EE_|CY5PR12MB6551:EE_","X-MS-Office365-Filtering-Correlation-Id":"60cca7db-c09b-40f6-cc90-08dea6b2e7ff","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|22082099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n Sce0luRAcUvc2aCaLemrcdbIugLxepaF/T8958vecGjJS0d21enMj6q41UiQ5sPT4Ajldb7LcsQRqoRP9/mmjguR7ezwyq1csAzpJKxmG1v1wkzr5AVSxTeBzATo1NhPsuAwNMpVnd0JrXj5x5Ga6EcyYmK282DeFAYVc22LSKWnXR87tBQ9lEBhVLQhvjsYTv9unoilZYi7GHg1/hDrvCLOlU3eK0v1XXJ8r2E008WltRAjCpZs5re0/DvO060l2hgqI9TjzQ7Ei7WKZH1fP7NsUQtBFN+IKvDCXBzzBCSicK4Nkx6MoAFfYzk/qsT2+HMWQpwqOsVpVCQBVTRvdAVetlwRSLDTv+Ox2oxCWf7xlVZKWkqE1sqHa+Buy6ERODKdvNUp16T/rZqYJPelCKvsZ1jZiEV33UAe6++HQOv4gWhyyWrt4Y4cZ3ATJCgPxVcnhZ0iPYCi/nD4ZvKfuW6u3NB0/FTJQZY/wE7dBzG9sy5Sr92+w7bJNm0v6G8vGSXfQKnHO7VO5z82ARwqhBfBGskheuh0SjJeVpeoOtAH+BWUtc1dWThE65VzX1jEQSB0bEEnz4a0otclz9LS+0W1poAKsQV5LNmafosqDys5Zw8yF55S2UaFmYCXRYVac8DT/ziaFBt7F9j+ZFMP3Xkn7zlefz47wsUrtC33VAqO3RYV+yOglE9+Av6mx7E1y9YNPBpLzEj2pu4FsYZwbQGkPojSAv2POYC1rpBFj4xEoOxOsfycwngay/GhelOmI8/W0bZrJ+dGJh6smg1A2g==","X-Forefront-Antispam-Report":"CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n DS3PEPF000099DF.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY5PR12MB6551","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Use the new reset_reset_bulk() API to properly cycle reset signals\nduring probe instead of just deasserting them. This ensures the\ncontroller is properly reset before initialization.\n\nSigned-off-by: Michal Simek \n---\n\n drivers/spi/cadence_qspi.c | 19 ++-----------------\n 1 file changed, 2 insertions(+), 17 deletions(-)","diff":"diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c\nindex 2a4a49c5f1cf..b9f2481b9cd3 100644\n--- a/drivers/spi/cadence_qspi.c\n+++ b/drivers/spi/cadence_qspi.c\n@@ -255,23 +255,8 @@ static int cadence_spi_probe(struct udevice *bus)\n \t}\n \n \tpriv->resets = devm_reset_bulk_get_optional(bus);\n-\tif (priv->resets) {\n-\t\t/* Assert all OSPI reset lines */\n-\t\tret = reset_assert_bulk(priv->resets);\n-\t\tif (ret) {\n-\t\t\tdev_err(bus, \"Failed to assert OSPI reset: %d\\n\", ret);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tudelay(10);\n-\n-\t\t/* Deassert all OSPI reset lines */\n-\t\tret = reset_deassert_bulk(priv->resets);\n-\t\tif (ret) {\n-\t\t\tdev_err(bus, \"Failed to deassert OSPI reset: %d\\n\", ret);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n+\tif (priv->resets)\n+\t\treset_reset_bulk(priv->resets);\n \n \tif (!priv->qspi_is_init) {\n \t\tcadence_qspi_apb_controller_init(priv);\n","prefixes":["3/4"]}