{"id":2231218,"url":"http://patchwork.ozlabs.org/api/patches/2231218/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/75160eb268d7a445e8483b357f7814bef30b12d4.1777550306.git.michal.simek@amd.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<75160eb268d7a445e8483b357f7814bef30b12d4.1777550306.git.michal.simek@amd.com>","list_archive_url":null,"date":"2026-04-30T11:58:28","name":"riscv: Exclude ACLINT for TARGET_XILINX_MBV","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1ab54680bc0cfab091d620730611944d4be0fcac","submitter":{"id":84271,"url":"http://patchwork.ozlabs.org/api/people/84271/?format=json","name":"Michal Simek","email":"michal.simek@amd.com"},"delegate":{"id":20174,"url":"http://patchwork.ozlabs.org/api/users/20174/?format=json","username":"Andes","first_name":"Andes","last_name":"","email":"uboot@andestech.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/75160eb268d7a445e8483b357f7814bef30b12d4.1777550306.git.michal.simek@amd.com/mbox/","series":[{"id":502285,"url":"http://patchwork.ozlabs.org/api/series/502285/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502285","date":"2026-04-30T11:58:28","name":"riscv: Exclude ACLINT for TARGET_XILINX_MBV","version":1,"mbox":"http://patchwork.ozlabs.org/series/502285/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231218/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231218/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=zoyCLqcP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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helo=satlexmb07.amd.com; pr=C","From":"Michal Simek ","To":", ","CC":"Leo , Rick Chen , Tom Rini\n ","Subject":"[PATCH] riscv: Exclude ACLINT for TARGET_XILINX_MBV","Date":"Thu, 30 Apr 2026 13:58:28 +0200","Message-ID":"\n <75160eb268d7a445e8483b357f7814bef30b12d4.1777550306.git.michal.simek@amd.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1244; i=michal.simek@amd.com;\n h=from:subject:message-id; bh=6mPBMWM9L8C/d4tdELYEW0GgG9EwfbXw0AoSXmWmcy0=;\n b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWR+dn7+u+4M+0m32+qsHF7ntzY8md1ac+G0x70PbmcNn\n zc++MNwr6OUhUGMg0FWTJFlOpOOw5pv15aKLY/Mh5nDygQyhIGLUwAmcvsoI8P6JalPIzwPSqxt\n icmM8HO6ubv+If/qvlJrBbPOhG7+tBWMDKeeWgv8XhuXpBSaFpzPJdPnNE1ut8fU+oeqRRU+6rK\n rWQA=","X-Developer-Key":"i=michal.simek@amd.com; a=openpgp;\n fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BN2PEPF0000449F:EE_|DM6PR12MB4433:EE_","X-MS-Office365-Filtering-Correlation-Id":"2746f9f5-b77f-4bdb-f482-08dea6afd70b","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|1800799024|376014|82310400026|36860700016|18002099003|56012099003;","X-Microsoft-Antispam-Message-Info":"\n B0d+VhJ8J+ZoW5CpKMoep/XgmcHRkYouslAWKFkq90DjcMdUJHuW4CjmTemd+dJfeZXam89IaPGRofP4mIJF+Oy2dBMdpawFL1WxzpgdAwbObSN0cmNNC6v7SIPRCppomZ+jlwh8CXIwiEAi5mbfJawpFEIr7koa4u4hYwO4lsPxRHj0FD5iQQxkXQnCbt3GVf1zIvrXYC+kVwbtikm9AKYGLO4M8O9fWVBEmhjYXEN4Fj8KKCEosJs63hYKCGPPcUBaR4sSpGXrjkI/uapiR9tXF83KWqfF1dCip1I1ufVkfpE4gf73vkGNvLFghCB+ngBW8yDKaUAo5EVH/35Th3QKbPKOCuUUIBP0IkC6UflUtQClvaOUtTw7PeCwcNT4Bpym7Es6Nscv1mER8JDV5R+/DviMciBf2hIM92YT0F7yUBx5K+FSoG2RrO15av3F6U5WdcxMnWBGhOBDtvm6TTOrt2gJ+tv9/j8FUTMaQLds4eWOgQ4ElAR0ubKKSWb0XivbL/krGp6oJWJ7R3sSy1Jfky5ra7zD9DKlbhtXgUO+hnp/rzI5A6eRewhdHZ2H0je6VUvvRYhgs8uDSX1Dr1DhKVvbpiJBC7tTa2tZ4PlH/MUr3OQDikivcR15vLdJJCAZrR/2Yvips/VjS0P2Azdqq8Yi5WwQusxWdMEXkF60OLaO53QGswWEismVs+WrkAEHx1Z8l/P1zspc9L2/d3EYDg+SPHvP08KDb42/byFOqiEIlM12bsvXFTjtUzBn9Fzwtpj+YgebNJohjNE0eg==","X-Forefront-Antispam-Report":"CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BN2PEPF0000449F.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM6PR12MB4433","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced\nCore Local Interruptor) hardware block. The timer functionality is\nprovided through a different mechanism.\n\nExclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied\nfor TARGET_XILINX_MBV while keeping the default behavior for other\ngeneric RISC-V targets that do have ACLINT hardware.\n\n spl/u-boot-spl: all -1382 data -360 rodata -200 text -822\n\nSigned-off-by: Michal Simek \n---\n\n arch/riscv/cpu/generic/Kconfig | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig\nindex 2baba2299238..8d53c69ba38c 100644\n--- a/arch/riscv/cpu/generic/Kconfig\n+++ b/arch/riscv/cpu/generic/Kconfig\n@@ -10,8 +10,8 @@ config GENERIC_RISCV\n \timply CPU\n \timply CPU_RISCV\n \timply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)\n-\timply RISCV_ACLINT if RISCV_MMODE\n-\timply SPL_RISCV_ACLINT if SPL_RISCV_MMODE\n+\timply RISCV_ACLINT if RISCV_MMODE && !TARGET_XILINX_MBV\n+\timply SPL_RISCV_ACLINT if SPL_RISCV_MMODE && !TARGET_XILINX_MBV\n \timply CMD_CPU\n \timply SPL_CPU\n \timply SPL_OPENSBI\n","prefixes":[]}