{"id":2231129,"url":"http://patchwork.ozlabs.org/api/patches/2231129/?format=json","web_url":"http://patchwork.ozlabs.org/project/ltp/patch/20260430110755.331002-2-piotr.kubaj@intel.com/","project":{"id":59,"url":"http://patchwork.ozlabs.org/api/projects/59/?format=json","name":"Linux Test Project development","link_name":"ltp","list_id":"ltp.lists.linux.it","list_email":"ltp@lists.linux.it","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430110755.331002-2-piotr.kubaj@intel.com>","list_archive_url":null,"date":"2026-04-30T11:07:56","name":"[v8] high_freq_hwp_cap_cppc.c: new test","commit_ref":null,"pull_url":null,"state":"needs-review-ack","archived":false,"hash":"0e3662034f97329784cc5a2a02c0140d9a0ef624","submitter":{"id":92049,"url":"http://patchwork.ozlabs.org/api/people/92049/?format=json","name":"Kubaj, Piotr","email":"piotr.kubaj@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/ltp/patch/20260430110755.331002-2-piotr.kubaj@intel.com/mbox/","series":[{"id":502281,"url":"http://patchwork.ozlabs.org/api/series/502281/?format=json","web_url":"http://patchwork.ozlabs.org/project/ltp/list/?series=502281","date":"2026-04-30T11:07:56","name":"[v8] high_freq_hwp_cap_cppc.c: new test","version":8,"mbox":"http://patchwork.ozlabs.org/series/502281/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231129/comments/","check":"warning","checks":"http://patchwork.ozlabs.org/api/patches/2231129/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","ltp@lists.linux.it"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","ltp@picard.linux.it"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=BsHVCExv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.linux.it\n (client-ip=2001:1418:10:5::2; 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a=\"77659207\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"77659207\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"236335823\""],"X-ExtLoop1":"1","From":"Piotr Kubaj ","To":"ltp@lists.linux.it","Date":"Thu, 30 Apr 2026 13:07:56 +0200","Message-ID":"<20260430110755.331002-2-piotr.kubaj@intel.com>","X-Mailer":"git-send-email 2.47.3","MIME-Version":"1.0","X-Spam-Status":"No, score=0.1 required=7.0 tests=DKIM_SIGNED,DKIM_VALID,\n DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS shortcircuit=no\n autolearn=disabled version=4.0.1","X-Spam-Checker-Version":"SpamAssassin 4.0.1 (2024-03-25) on in-4.smtp.seeweb.it","X-Virus-Scanned":"clamav-milter 1.0.9 at in-4.smtp.seeweb.it","X-Virus-Status":"Clean","Subject":"[LTP] [PATCH v8] high_freq_hwp_cap_cppc.c: new test","X-BeenThere":"ltp@lists.linux.it","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Linux Test Project ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"helena.anna.dubel@intel.com, tomasz.ossowski@intel.com,\n rafael.j.wysocki@intel.com, daniel.niestepski@intel.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Errors-To":"ltp-bounces+incoming=patchwork.ozlabs.org@lists.linux.it","Sender":"\"ltp\" "},"content":"Verify for all online logical CPUs that their highest performance value are\nthe same for HWP Capability MSR 0x771 and CPPC sysfs file.\n\nSigned-off-by: Piotr Kubaj \n---\nMoved path string outside of the loop, per Andrea's review.\n\"online\" sysfs node is only available for CPUs other than cpu0.\n runtest/power_management_tests | 1 +\n testcases/kernel/power_management/.gitignore | 1 +\n .../power_management/high_freq_hwp_cap_cppc.c | 86 +++++++++++++++++++\n 3 files changed, 88 insertions(+)\n create mode 100644 testcases/kernel/power_management/.gitignore\n create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c","diff":"diff --git a/runtest/power_management_tests b/runtest/power_management_tests\nindex b670da6ec..4da57ee72 100644\n--- a/runtest/power_management_tests\n+++ b/runtest/power_management_tests\n@@ -1,4 +1,5 @@\n #POWER_MANAGEMENT\n+high_freq_hwp_cap_cppc high_freq_hwp_cap_cppc\n runpwtests03 runpwtests03.sh\n runpwtests04 runpwtests04.sh\n runpwtests06 runpwtests06.sh\ndiff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore\nnew file mode 100644\nindex 000000000..03f0c83e4\n--- /dev/null\n+++ b/testcases/kernel/power_management/.gitignore\n@@ -0,0 +1 @@\n+high_freq_hwp_cap_cppc\ndiff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c\nnew file mode 100644\nindex 000000000..fb1b8edc7\n--- /dev/null\n+++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c\n@@ -0,0 +1,86 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (C) 2026 Piotr Kubaj \n+ */\n+\n+/*\\\n+ * Verify for all online logical CPUs that their highest performance value are\n+ * the same for HWP Capability MSR 0x771 and CPPC sysfs file.\n+ */\n+\n+#include \"tst_test.h\"\n+#include \"tst_safe_prw.h\"\n+\n+#define MSR_HWP_CAPABILITIES\t0x771\n+#define HIGHEST_PERF_MASK\t0xFF\n+\n+static int nproc;\n+\n+static void setup(void)\n+{\n+\tnproc = tst_ncpus_conf();\n+}\n+\n+static void run(void)\n+{\n+\tbool status = true;\n+\tchar path[PATH_MAX];\n+\n+\tfor (int i = 0; i < nproc; i++) {\n+\t\tint online = 1;\n+\t\tunsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;\n+\n+\t\tsnprintf(path, sizeof(path), \"/sys/devices/system/cpu/cpu%d/online\", i);\n+\t\tif (i)\n+\t\t\tSAFE_FILE_SCANF(path, \"%d\", &online);\n+\n+\t\tif (!online) {\n+\t\t\ttst_res(TINFO, \"CPU%d offline, skipping\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tsnprintf(path, sizeof(path), \"/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf\", i);\n+\t\tif (access(path, F_OK) == -1) {\n+\t\t\ttst_res(TCONF | TERRNO, \"CPPC sysfs not available, skipping\");\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tSAFE_FILE_SCANF(path, \"%llu\", &sysfs_highest_perf);\n+\t\ttst_res(TDEBUG, \"%s: %llu\", path, sysfs_highest_perf);\n+\n+\t\tsnprintf(path, sizeof(path), \"/dev/cpu/%d/msr\", i);\n+\t\tint fd = SAFE_OPEN(path, O_RDONLY);\n+\n+\t\tSAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), MSR_HWP_CAPABILITIES);\n+\t\tSAFE_CLOSE(fd);\n+\t\tmsr_highest_perf &= HIGHEST_PERF_MASK;\n+\t\ttst_res(TDEBUG, \"%s: %llu\", path, msr_highest_perf);\n+\n+\t\tif (msr_highest_perf != sysfs_highest_perf) {\n+\t\t\ttst_res(TINFO, \"cpu%d: sysfs=%llu MSR=%llu\",\n+\t\t\t\ti, sysfs_highest_perf, msr_highest_perf);\n+\t\t\tstatus = false;\n+\t\t}\n+\t}\n+\n+\tif (status)\n+\t\ttst_res(TPASS, \"Sysfs and MSR values are equal\");\n+\telse\n+\t\ttst_res(TFAIL, \"Highest performance values differ between sysfs and MSR\");\n+}\n+\n+static struct tst_test test = {\n+\t.needs_kconfigs = (const char *const []) {\n+\t\t\"CONFIG_ACPI_CPPC_LIB\",\n+\t\t\"CONFIG_X86_MSR\",\n+\t\tNULL\n+\t},\n+\t.needs_root = 1,\n+\t.setup = setup,\n+\t.supported_archs = (const char *const []) {\n+\t\t\"x86\",\n+\t\t\"x86_64\",\n+\t\tNULL\n+\t},\n+\t.test_all = run\n+};\n","prefixes":["v8"]}