{"id":2230873,"url":"http://patchwork.ozlabs.org/api/patches/2230873/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-7-zhenzhong.duan@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430071315.354333-7-zhenzhong.duan@intel.com>","list_archive_url":null,"date":"2026-04-30T07:13:02","name":"[v4,06/15] intel_iommu: Export some functions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e85868af388a6e4b522f1dc692af7a379b866589","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-7-zhenzhong.duan@intel.com/mbox/","series":[{"id":502222,"url":"http://patchwork.ozlabs.org/api/series/502222/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502222","date":"2026-04-30T07:12:57","name":"intel_iommu: Enable PASID support for passthrough device","version":4,"mbox":"http://patchwork.ozlabs.org/series/502222/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230873/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230873/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=SXNHAtsi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 30 Apr 2026 03:13:59 -0400","from orviesa007.jf.intel.com ([10.64.159.147])\n by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:13:54 -0700","from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:13:51 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777533237; x=1809069237;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Q4Fw4ltwvutTLAbtZBqSgsuKVIFYq+CsbSlbzEQGT3k=;\n b=SXNHAtsiVrALEVaFTV9q7lcIFlRCuBzf/rEOX4bHC1CxuKSMVyXuKEii\n hR1JfWiXLOYHwuTtUsObp6aP1dwfjsl2eCgy/jcmciTdQcCeFRTPX1kui\n QVxs16DlsRqV/8FAYhUkkpke9CyOI+H/cIZBdf/oiOgNV+44WSZ5R2K2K\n zntQQxvrUJ3nmmgHbpa5HggX4BCmqkX11KGoOeFqryF+pALg7A4ZPX9Uk\n 2Go+fyPa/hMPOBKGkPexj3fgnGboH9N9l289CQ7dUmPZhxcpzSI++G5mv\n qaq85XL43DZlnLo9fhN8zrtEcaTTmd/PNpyfPvOh0lS2TV/gR2TmGILBb A==;","X-CSE-ConnectionGUID":["cAbkaFGzRg2tRU8xpNH1bw==","7aqVwRynRfeAkxYqcZk00w=="],"X-CSE-MsgGUID":["fyaUeXmqS1KK+CVFYVOt7w==","ngSa8bLVRrKUdoHH98oB1g=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11771\"; a=\"81051615\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"81051615\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"234771518\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ,\n Clement Mathieu--Drif ","Subject":"[PATCH v4 06/15] intel_iommu: Export some functions","Date":"Thu, 30 Apr 2026 03:13:02 -0400","Message-ID":"<20260430071315.354333-7-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260430071315.354333-1-zhenzhong.duan@intel.com>","References":"<20260430071315.354333-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=192.198.163.13;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Export some functions for accel code usages. Inline functions and MACROs\nare moved to internal header files. Then accel code in following patches\ncould access them.\n\nSigned-off-by: Zhenzhong Duan \nReviewed-by: Clement Mathieu--Drif \nReviewed-by: Yi Liu \nTested-by: Xudong Hao \n---\n hw/i386/intel_iommu_internal.h | 31 +++++++++++++++++++++++++\n hw/i386/intel_iommu.c | 42 ++++++++--------------------------\n 2 files changed, 40 insertions(+), 33 deletions(-)","diff":"diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex db4f186a3e..c7e107fe87 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -620,6 +620,12 @@ typedef struct VTDRootEntry VTDRootEntry;\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL\n #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL\n \n+/* context entry operations */\n+#define VTD_CE_GET_PASID_DIR_TABLE(ce) \\\n+ ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)\n+#define VTD_CE_GET_PRE(ce) \\\n+ ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)\n+\n typedef struct VTDPASIDCacheInfo {\n uint8_t type;\n uint16_t did;\n@@ -746,4 +752,29 @@ static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *pe)\n {\n return (VTD_SM_PASID_ENTRY_PGTT(pe) == VTD_SM_PASID_ENTRY_FST);\n }\n+\n+static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)\n+{\n+ return pdire->val & 1;\n+}\n+\n+static inline bool vtd_pe_present(VTDPASIDEntry *pe)\n+{\n+ return pe->val[0] & VTD_PASID_ENTRY_P;\n+}\n+\n+static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n+{\n+ return memcmp(p1, p2, sizeof(*p1));\n+}\n+\n+int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n+ VTDPASIDDirEntry *pdire);\n+int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\n+ dma_addr_t addr, VTDPASIDEntry *pe);\n+int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n+ uint8_t devfn, VTDContextEntry *ce);\n+int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n+ VTDPASIDEntry *pe, uint32_t pasid);\n+VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid);\n #endif\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex d1946e3a59..6715cc4383 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -42,12 +42,6 @@\n #include \"migration/vmstate.h\"\n #include \"trace.h\"\n \n-/* context entry operations */\n-#define VTD_CE_GET_PASID_DIR_TABLE(ce) \\\n- ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)\n-#define VTD_CE_GET_PRE(ce) \\\n- ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)\n-\n /*\n * Paging mode for first-stage translation (VTD spec Figure 9-6)\n * 00: 4-level paging, 01: 5-level paging\n@@ -831,18 +825,12 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe)\n }\n }\n \n-static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)\n-{\n- return pdire->val & 1;\n-}\n-\n /**\n * Caller of this function should check present bit if wants\n * to use pdir entry for further usage except for fpd bit check.\n */\n-static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,\n- uint32_t pasid,\n- VTDPASIDDirEntry *pdire)\n+int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n+ VTDPASIDDirEntry *pdire)\n {\n uint32_t index;\n dma_addr_t addr, entry_size;\n@@ -860,15 +848,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,\n return 0;\n }\n \n-static inline bool vtd_pe_present(VTDPASIDEntry *pe)\n-{\n- return pe->val[0] & VTD_PASID_ENTRY_P;\n-}\n-\n-static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,\n- uint32_t pasid,\n- dma_addr_t addr,\n- VTDPASIDEntry *pe)\n+int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\n+ dma_addr_t addr, VTDPASIDEntry *pe)\n {\n uint8_t pgtt;\n uint32_t index;\n@@ -954,8 +935,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,\n return 0;\n }\n \n-static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n- VTDPASIDEntry *pe, uint32_t pasid)\n+int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n+ VTDPASIDEntry *pe, uint32_t pasid)\n {\n dma_addr_t pasid_dir_base;\n \n@@ -1526,8 +1507,8 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce)\n }\n \n /* Map a device to its corresponding domain (context-entry) */\n-static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n- uint8_t devfn, VTDContextEntry *ce)\n+int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n+ uint8_t devfn, VTDContextEntry *ce)\n {\n VTDRootEntry re;\n int ret_fr;\n@@ -1909,7 +1890,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(IntelIOMMUState *s,\n vtd_find_as_by_sid_and_pasid, &key);\n }\n \n-static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)\n+VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)\n {\n return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID);\n }\n@@ -3133,11 +3114,6 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as,\n return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid);\n }\n \n-static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n-{\n- return memcmp(p1, p2, sizeof(*p1));\n-}\n-\n /* Update or invalidate pasid cache based on the pasid entry in guest memory. */\n static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value,\n gpointer user_data)\n","prefixes":["v4","06/15"]}