{"id":2230866,"url":"http://patchwork.ozlabs.org/api/patches/2230866/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-3-81d068025b97@fairphone.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430-sm6350-lpi-tlmm-v2-3-81d068025b97@fairphone.com>","list_archive_url":null,"date":"2026-04-30T07:10:43","name":"[v2,3/5] pinctrl: qcom: Add SM6350 LPASS LPI TLMM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"78ff83aef80475b4d304b12074fb84c89ea9f5f5","submitter":{"id":83060,"url":"http://patchwork.ozlabs.org/api/people/83060/?format=json","name":"Luca Weiss","email":"luca.weiss@fairphone.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-3-81d068025b97@fairphone.com/mbox/","series":[{"id":502221,"url":"http://patchwork.ozlabs.org/api/series/502221/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502221","date":"2026-04-30T07:10:40","name":"Add LPASS LPI pin controller support for SM6350","version":2,"mbox":"http://patchwork.ozlabs.org/series/502221/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230866/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230866/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=fairphone.com header.i=@fairphone.com\n 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(PDT)","From":"Luca Weiss ","Date":"Thu, 30 Apr 2026 09:10:43 +0200","Subject":"[PATCH v2 3/5] pinctrl: qcom: Add SM6350 LPASS LPI TLMM","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260430-sm6350-lpi-tlmm-v2-3-81d068025b97@fairphone.com>","References":"<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>","In-Reply-To":"<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>","To":"Bjorn Andersson ,\n Linus Walleij , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley , Konrad Dybcio ,\n Srinivas Kandagatla ","Cc":"~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Luca Weiss ,\n Dmitry Baryshkov ,\n Konrad Dybcio ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777533047; l=7602;\n i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id;\n bh=1VUcOzChGoZs59Eb985aPOcVmtdrVUb87O94jKmVrkU=;\n b=NOR70N9HENNOMf67HjUFcXrc6eHseNG2okNLHnUXiUGcZeS299hLbEmuV6zb/5YF1QPbZ6ska\n OdV+jHcLMYtBMHS6eD7k7MHyxkT8A57HprPvsdIWN+3gy+w1pO0wdAb","X-Developer-Key":"i=luca.weiss@fairphone.com; a=ed25519;\n pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8="},"content":"Add support for the pin controller block on SM6350 Low Power Island.\n\nReviewed-by: Dmitry Baryshkov \nReviewed-by: Konrad Dybcio \nSigned-off-by: Luca Weiss \n---\n drivers/pinctrl/qcom/Kconfig | 9 ++\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c | 149 ++++++++++++++++++++++++\n 3 files changed, 159 insertions(+)","diff":"diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig\nindex 80af372a1147..ea7e10149e47 100644\n--- a/drivers/pinctrl/qcom/Kconfig\n+++ b/drivers/pinctrl/qcom/Kconfig\n@@ -118,6 +118,15 @@ config PINCTRL_SM6115_LPASS_LPI\n \t Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI\n \t (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform.\n \n+config PINCTRL_SM6350_LPASS_LPI\n+\ttristate \"Qualcomm Technologies Inc SM6350 LPASS LPI pin controller driver\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\tdepends on PINCTRL_LPASS_LPI\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n+\t Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI\n+\t (Low Power Island) found on the Qualcomm Technologies Inc SM6350 platform.\n+\n config PINCTRL_SM8250_LPASS_LPI\n \ttristate \"Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex 84bda3ada874..94e23a66ca3e 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o\n obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o\n obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o\n obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o\n+obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) += pinctrl-sm6350-lpass-lpi.o\n obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o\n obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o\n obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c\nnew file mode 100644\nindex 000000000000..4d06abcfedfd\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c\n@@ -0,0 +1,149 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2026, Luca Weiss \n+ */\n+\n+#include \n+#include \n+#include \n+\n+#include \"pinctrl-lpass-lpi.h\"\n+\n+enum lpass_lpi_functions {\n+\tLPI_MUX_dmic1_clk,\n+\tLPI_MUX_dmic1_data,\n+\tLPI_MUX_dmic2_clk,\n+\tLPI_MUX_dmic2_data,\n+\tLPI_MUX_dmic3_clk,\n+\tLPI_MUX_dmic3_data,\n+\tLPI_MUX_i2s1_clk,\n+\tLPI_MUX_i2s1_data,\n+\tLPI_MUX_i2s1_ws,\n+\tLPI_MUX_i2s2_clk,\n+\tLPI_MUX_i2s2_data,\n+\tLPI_MUX_i2s2_ws,\n+\tLPI_MUX_qua_mi2s_data,\n+\tLPI_MUX_qua_mi2s_sclk,\n+\tLPI_MUX_qua_mi2s_ws,\n+\tLPI_MUX_swr_rx_clk,\n+\tLPI_MUX_swr_rx_data,\n+\tLPI_MUX_swr_tx_clk,\n+\tLPI_MUX_swr_tx_data,\n+\tLPI_MUX_wsa_swr_clk,\n+\tLPI_MUX_wsa_swr_data,\n+\tLPI_MUX_gpio,\n+\tLPI_MUX__,\n+};\n+\n+static const struct pinctrl_pin_desc sm6350_lpi_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+};\n+\n+static const char * const swr_tx_clk_groups[] = { \"gpio0\" };\n+static const char * const swr_tx_data_groups[] = { \"gpio1\", \"gpio2\", \"gpio14\" };\n+static const char * const swr_rx_clk_groups[] = { \"gpio3\" };\n+static const char * const swr_rx_data_groups[] = { \"gpio4\", \"gpio5\" };\n+static const char * const dmic1_clk_groups[] = { \"gpio6\" };\n+static const char * const dmic1_data_groups[] = { \"gpio7\" };\n+static const char * const dmic2_clk_groups[] = { \"gpio8\" };\n+static const char * const dmic2_data_groups[] = { \"gpio9\" };\n+static const char * const i2s2_clk_groups[] = { \"gpio10\" };\n+static const char * const i2s2_ws_groups[] = { \"gpio11\" };\n+static const char * const dmic3_clk_groups[] = { \"gpio12\" };\n+static const char * const dmic3_data_groups[] = { \"gpio13\" };\n+static const char * const qua_mi2s_sclk_groups[] = { \"gpio0\" };\n+static const char * const qua_mi2s_ws_groups[] = { \"gpio1\" };\n+static const char * const qua_mi2s_data_groups[] = { \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\" };\n+static const char * const i2s1_clk_groups[] = { \"gpio6\" };\n+static const char * const i2s1_ws_groups[] = { \"gpio7\" };\n+static const char * const i2s1_data_groups[] = { \"gpio8\", \"gpio9\" };\n+static const char * const wsa_swr_clk_groups[] = { \"gpio10\" };\n+static const char * const wsa_swr_data_groups[] = { \"gpio11\" };\n+static const char * const i2s2_data_groups[] = { \"gpio12\", \"gpio13\" };\n+\n+static const struct lpi_pingroup sm6350_groups[] = {\n+\tLPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),\n+\tLPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),\n+\tLPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),\n+\tLPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),\n+\tLPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),\n+\tLPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _),\n+\tLPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),\n+\tLPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),\n+\tLPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),\n+\tLPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),\n+\tLPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),\n+\tLPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),\n+\tLPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),\n+\tLPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),\n+\tLPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _),\n+};\n+\n+static const struct lpi_function sm6350_functions[] = {\n+\tLPI_FUNCTION(dmic1_clk),\n+\tLPI_FUNCTION(dmic1_data),\n+\tLPI_FUNCTION(dmic2_clk),\n+\tLPI_FUNCTION(dmic2_data),\n+\tLPI_FUNCTION(dmic3_clk),\n+\tLPI_FUNCTION(dmic3_data),\n+\tLPI_FUNCTION(i2s1_clk),\n+\tLPI_FUNCTION(i2s1_data),\n+\tLPI_FUNCTION(i2s1_ws),\n+\tLPI_FUNCTION(i2s2_clk),\n+\tLPI_FUNCTION(i2s2_data),\n+\tLPI_FUNCTION(i2s2_ws),\n+\tLPI_FUNCTION(qua_mi2s_data),\n+\tLPI_FUNCTION(qua_mi2s_sclk),\n+\tLPI_FUNCTION(qua_mi2s_ws),\n+\tLPI_FUNCTION(swr_rx_clk),\n+\tLPI_FUNCTION(swr_rx_data),\n+\tLPI_FUNCTION(swr_tx_clk),\n+\tLPI_FUNCTION(swr_tx_data),\n+\tLPI_FUNCTION(wsa_swr_clk),\n+\tLPI_FUNCTION(wsa_swr_data),\n+};\n+\n+static const struct lpi_pinctrl_variant_data sm6350_lpi_data = {\n+\t.pins = sm6350_lpi_pins,\n+\t.npins = ARRAY_SIZE(sm6350_lpi_pins),\n+\t.groups = sm6350_groups,\n+\t.ngroups = ARRAY_SIZE(sm6350_groups),\n+\t.functions = sm6350_functions,\n+\t.nfunctions = ARRAY_SIZE(sm6350_functions),\n+};\n+\n+static const struct of_device_id lpi_pinctrl_of_match[] = {\n+\t{\n+\t .compatible = \"qcom,sm6350-lpass-lpi-pinctrl\",\n+\t .data = &sm6350_lpi_data,\n+\t},\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);\n+\n+static struct platform_driver lpi_pinctrl_driver = {\n+\t.driver = {\n+\t\t .name = \"qcom-sm6350-lpass-lpi-pinctrl\",\n+\t\t .of_match_table = lpi_pinctrl_of_match,\n+\t},\n+\t.probe = lpi_pinctrl_probe,\n+\t.remove = lpi_pinctrl_remove,\n+};\n+\n+module_platform_driver(lpi_pinctrl_driver);\n+MODULE_DESCRIPTION(\"Qualcomm SM6350 LPI GPIO pin control driver\");\n+MODULE_LICENSE(\"GPL\");\n","prefixes":["v2","3/5"]}