{"id":2230853,"url":"http://patchwork.ozlabs.org/api/patches/2230853/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/afL5pUs4StfArj_E@cowardly-lion.the-meissners.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-30T06:41:41","name":"GCC 17, PowerPC Dense Math V7 (patch 3/7) -- Add -mdense-math switch","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"117108ff2cc731321d17449d0c840d73c65fc77e","submitter":{"id":73991,"url":"http://patchwork.ozlabs.org/api/people/73991/?format=json","name":"Michael Meissner","email":"meissner@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/afL5pUs4StfArj_E@cowardly-lion.the-meissners.org/mbox/","series":[{"id":502214,"url":"http://patchwork.ozlabs.org/api/series/502214/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502214","date":"2026-04-30T06:41:41","name":"GCC 17, PowerPC Dense Math V7 (patch 3/7) -- Add -mdense-math switch","version":1,"mbox":"http://patchwork.ozlabs.org/series/502214/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230853/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230853/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=o6R7NpNl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-TM-AS-GCONF":"00","X-Authority-Analysis":"v=2.4 cv=AqDeGu9P c=1 sm=1 tr=0 ts=69f2f9ac cx=c_pps\n a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=Jz-Qs_lQuOGvCERg6MEA:9 a=CjuIK1q_8ugA:10","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDMwMDA2MCBTYWx0ZWRfX53kKY0RwPs0K\n XC8xFYFPSBlEUJ7D5Mnus80JzcwiMiHW4RXsaFpTMhLyozLp5dNwyMA/E4oZck1xDmN1IBPxRWF\n 1DeKd+xG9BTFHKqSMwnL+SVB37HDiDmaOyxTo99ulLpbpoNzVdanCk/8ARXyc2Ax40IKMH5L8Gi\n Mimb3gQtFxTR2wrHFSwvfEz6ECkJKCDVEqWIIl4YlTtZgyg6s1q1lbGNrVxqVnTgt5zffeTkmQD\n 5f50F4dtBCh5fcQo6PuU3VfjDwdSrg9xKJUnTq1+yL1KfehbJybV/Io68OISnNA/92T80mgMAlY\n ZcQEXSz4bmb40z3sAsBJ9/LtfwGVwN8YqPrJLgmbRhgEUHYBAxxx5Jn7ibrR7ML1wG4eKniZQYV\n HNBzl0+q3YKGB9jsmTFt5rDp/oUF+dJ5a4E3e1d74jtR5KYarYSH61IvK5Mp8b8bEmcazwxisnT\n XD2RADLUKh+lH1V+cJg==","X-Proofpoint-GUID":"B9sr6_shA3eVMTNm-8GDnoN4WywykoyB","X-Proofpoint-ORIG-GUID":"B9sr6_shA3eVMTNm-8GDnoN4WywykoyB","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015\n lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300060","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This is part three of the dense math register patches for the PowerPC.\nThis is the 7th version of the dense math patches.\n\nVersion 6 of the dense math register patches were posted on April 21st,\n2026.\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713352.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713353.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713354.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713355.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713356.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713357.html\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nThis patch (patch #3) is the same as patch #2 in the V6 patches.\n\nThis patch adds the -mdense-math option for -mcpu=future. The next set of\npatches will support for using dense math registers with the MMA instructions.\nAll this patch does is add the option. A future patch will implement support\nfor dense math registers, and another patch will then switch the MMA\ninstructions to use dense math registers.\n\nFor users, the following macros are defined:\n\n\t__MMA_NO_DENSE_MATH__\tISA 3.1 MMA support.\n\t__MMA_DENSE_MATH__\tMMA with dense math registers.\n\nWithin the compiler, the following macros are defined:\n\n\tTARGET_MMA_NO_DENSE_MATH\tISA 3.1 MMA support.\n\tTARGET_MMA_DENSE_MATH\t\tMMA with dense math registers.\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\n2026-04-29 Michael Meissner \n\ngcc/\n\n\t* config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define\n\t__MMA_DENSE_MATH__ if we have MMA that uses dense math register\n\taccumulators. Define __MMA_NO_DENSE_MATH__ if we have MMA but we are\n\tusing ISA 3.1 where the accumulators are overlaid over VSX registers\n\t0..32. Define __DENSE_MATH__ if we have dense math registers.\n\t* config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not\n\tallow -mdense-math unless -mcpu=future is used.\n\t(rs6000_opt_masks): Add -mdense-math support.\n\t* config/rs6000/rs6000.h (TARGET_MMA_DENSE_MATH): New macro.\n\t(TARGET_MMA_NO_DENSE_MATH): Likewise.\n\t* config/rs6000/rs6000.opt (-mdense-math): New option.\n\t* doc/invoke.texi (RS/6000 and PowerPC Options): Add -mdense-math.\n---\n gcc/config/rs6000/rs6000-c.cc | 22 ++++++++++++++++++++--\n gcc/config/rs6000/rs6000.cc | 10 ++++++++++\n gcc/config/rs6000/rs6000.h | 6 ++++++\n gcc/config/rs6000/rs6000.opt | 4 ++++\n gcc/doc/invoke.texi | 7 +++++++\n 5 files changed, 47 insertions(+), 2 deletions(-)","diff":"diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc\nindex 3fa7c04a7ce..ce7d836541f 100644\n--- a/gcc/config/rs6000/rs6000-c.cc\n+++ b/gcc/config/rs6000/rs6000-c.cc\n@@ -587,9 +587,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)\n if (rs6000_cpu == PROCESSOR_CELL)\n rs6000_define_or_undefine_macro (define_p, \"__PPU__\");\n \n- /* Tell the user if we support the MMA instructions. */\n+ /* Tell the user if we support the MMA instructions. Also tell them if we\n+ have MMA with ISA 3.1 that uses accumulators overlaid over VSX registers\n+ 0..31 or if we have support with separate dense math accumulators. */\n if ((flags & OPTION_MASK_MMA) != 0)\n- rs6000_define_or_undefine_macro (define_p, \"__MMA__\");\n+ {\n+ rs6000_define_or_undefine_macro (define_p, \"__MMA__\");\n+ if ((flags & OPTION_MASK_DENSE_MATH) != 0)\n+\t{\n+\t rs6000_define_or_undefine_macro (define_p, \"__MMA_DENSE_MATH__\");\n+\t rs6000_define_or_undefine_macro (false, \"__MMA_NO_DENSE_MATH__\");\n+\t}\n+ else\n+\t{\n+\t rs6000_define_or_undefine_macro (false, \"__MMA_DENSE_MATH__\");\n+\t rs6000_define_or_undefine_macro (define_p, \"__MMA_NO_DENSE_MATH__\");\n+\t}\n+ }\n+ /* Tell the user if we support the dense math registers for use with MMA and\n+ cryptography. */\n+ if ((flags & OPTION_MASK_DENSE_MATH) != 0)\n+ rs6000_define_or_undefine_macro (define_p, \"__DENSE_MATH__\");\n /* Whether pc-relative code is being generated. */\n if ((flags & OPTION_MASK_PCREL) != 0)\n rs6000_define_or_undefine_macro (define_p, \"__PCREL__\");\ndiff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc\nindex 38df0b43f6f..31ab5bdccf1 100644\n--- a/gcc/config/rs6000/rs6000.cc\n+++ b/gcc/config/rs6000/rs6000.cc\n@@ -4410,6 +4410,15 @@ rs6000_option_override_internal (bool global_init_p)\n if (!TARGET_PCREL && TARGET_PCREL_OPT)\n rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;\n \n+ /* Turn off dense math register support on non-future systems. */\n+ if (TARGET_DENSE_MATH && !TARGET_FUTURE)\n+ {\n+ if ((rs6000_isa_flags_explicit & OPTION_MASK_DENSE_MATH) != 0)\n+\terror (\"%qs requires %qs\", \"-mdense-math\", \"-mcpu=future\");\n+\n+ rs6000_isa_flags &= ~OPTION_MASK_DENSE_MATH;\n+ }\n+\n if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)\n rs6000_print_isa_options (stderr, 0, \"after subtarget\", rs6000_isa_flags);\n \n@@ -24463,6 +24472,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =\n \t\t\t\t\t\t\t\tfalse, true },\n { \"cmpb\",\t\t\tOPTION_MASK_CMPB,\t\tfalse, true },\n { \"crypto\",\t\t\tOPTION_MASK_CRYPTO,\t\tfalse, true },\n+ { \"dense-math\",\t\tOPTION_MASK_DENSE_MATH,\t\tfalse, true },\n { \"direct-move\",\t\t0,\t\t\t\tfalse, true },\n { \"dlmzb\",\t\t\tOPTION_MASK_DLMZB,\t\tfalse, true },\n { \"efficient-unaligned-vsx\",\tOPTION_MASK_EFFICIENT_UNALIGNED_VSX,\ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex 04709f0dcd6..91e60085515 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -500,6 +500,12 @@ extern int rs6000_vector_align[];\n #define TARGET_MINMAX\t(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT\t\t\\\n \t\t\t && (TARGET_P9_MINMAX || !flag_trapping_math))\n \n+/* Define if the MMA subsystem uses ISA 3.1 where the accumulators are overlaid\n+ over VSX registers 0..31 or whether MMA uses separate dense math\n+ accumulators. */\n+#define TARGET_MMA_DENSE_MATH\t\t(TARGET_MMA && TARGET_DENSE_MATH)\n+#define TARGET_MMA_NO_DENSE_MATH\t(TARGET_MMA && !TARGET_DENSE_MATH)\n+\n /* In switching from using target_flags to using rs6000_isa_flags, the options\n machinery creates OPTION_MASK_ instead of MASK_. The MASK_\n options that have not yet been replaced by their OPTION_MASK_\ndiff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt\nindex 2b6ec5222fc..5bf1b98e4e7 100644\n--- a/gcc/config/rs6000/rs6000.opt\n+++ b/gcc/config/rs6000/rs6000.opt\n@@ -638,6 +638,10 @@ mieee128-constant\n Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save\n Generate (do not generate) code that uses the LXVKQ instruction.\n \n+mdense-math\n+Target Mask(DENSE_MATH) Var(rs6000_isa_flags)\n+Generate (do not generate) instructions that use dense math registers.\n+\n ; Documented parameters\n \n -param=rs6000-vect-unroll-limit=\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 2ee0af8faae..e3c5fc4cc9a 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -32820,6 +32820,13 @@ This option is enabled by default.\n Enable or disable warnings about deprecated @samp{vector long ...} Altivec\n type usage. This option is enabled by default.\n \n+@opindex mdense-math\n+@opindex mno-dense-math\n+@item -mdense-math\n+@itemx -mno-dense-math\n+Generate (do not generate) code that uses the dense math registers.\n+This option is enabled by default.\n+\n @end table\n \n @node RX Options\n","prefixes":[]}