{"id":2230747,"url":"http://patchwork.ozlabs.org/api/patches/2230747/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-11-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430002046.59739-11-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-30T00:20:09","name":"[v3,10/47] target/arm: Enable EnFPM bits for FEAT_FPMR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9d4b3a35a37fabb68d54fcc13a685340538be697","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-11-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230747/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230747/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gYTeefYM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zj54dsXz1yHv\n\tfor ; Thu, 30 Apr 2026 10:26:17 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIF9q-0006YV-94; Wed, 29 Apr 2026 20:21:35 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIF9b-0006O9-3q\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:20 -0400","from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIF9X-0006Gs-M2\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:18 -0400","by mail-pf1-x434.google.com with SMTP id\n d2e1a72fcca58-834f1075805so248784b3a.2\n for ; Wed, 29 Apr 2026 17:21:15 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x434.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/helper.c | 9 +++++++++\n 1 file changed, 9 insertions(+)","diff":"diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 304db1a479..7a17fd39e5 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -787,6 +787,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)\n if (cpu_isar_feature(aa64_mec, cpu)) {\n valid_mask |= SCR_MECEN;\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ valid_mask |= SCR_ENFPM;\n+ }\n } else {\n valid_mask &= ~(SCR_RW | SCR_ST);\n if (cpu_isar_feature(aa32_ras, cpu)) {\n@@ -3953,6 +3956,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,\n if (cpu_isar_feature(aa64_gcs, cpu)) {\n valid_mask |= HCRX_GCSEN;\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ valid_mask |= HCRX_ENFPM;\n+ }\n \n /* Clear RES0 bits. */\n env->cp15.hcrx_el2 = value & valid_mask;\n@@ -4026,6 +4032,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)\n if (cpu_isar_feature(aa64_gcs, cpu)) {\n hcrx |= HCRX_GCSEN;\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ hcrx |= HCRX_ENFPM;\n+ }\n return hcrx;\n }\n if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) {\n","prefixes":["v3","10/47"]}