{"id":2230745,"url":"http://patchwork.ozlabs.org/api/patches/2230745/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-41-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430002046.59739-41-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-30T00:20:39","name":"[v3,40/47] target/arm: Implement MOVT (vector to table)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"00554f08ff359803bfa352eb7cf05fd8ac9cba51","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-41-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230745/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230745/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=XI9upLLu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zj24Gj9z1yHv\n\tfor ; Thu, 30 Apr 2026 10:26:14 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFDx-0006dL-NE; Wed, 29 Apr 2026 20:25:49 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDe-0006QZ-Qm\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:35 -0400","from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDY-0007Tg-RF\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:26 -0400","by mail-pj1-x102f.google.com with SMTP id\n 98e67ed59e1d1-362bb3260f1so188755a91.2\n for ; Wed, 29 Apr 2026 17:25:24 -0700 (PDT)","from stoup.. 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helo=mail-pj1-x102f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sme.c | 18 ++++++++++++++++++\n target/arm/tcg/sme.decode | 2 ++\n 3 files changed, 25 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 15e9821ce5..4b228b4f3b 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1556,6 +1556,11 @@ static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64);\n }\n \n+static inline bool isar_feature_aa64_sme_lutv2(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, LUTv2);\n+}\n+\n static inline bool isar_feature_aa64_sme2(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) != 0;\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 2f79c458e1..214427db1f 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -391,6 +391,24 @@ static bool do_movt(DisasContext *s, arg_MOVT_rzt *a,\n TRANS_FEAT(MOVT_rzt, aa64_sme2, do_movt, a, tcg_gen_ld_i64)\n TRANS_FEAT(MOVT_ztr, aa64_sme2, do_movt, a, tcg_gen_st_i64)\n \n+static bool trans_MOVT_ztz(DisasContext *s, arg_MOVT_ztz *a)\n+{\n+ if (!dc_isar_feature(aa64_sme_lutv2, s)) {\n+ return false;\n+ }\n+ if (sme_sm_enabled_check(s) && sme2_zt0_enabled_check(s)) {\n+ int svl = streaming_vec_reg_size(s);\n+ int tsize = MIN(svl, 64);\n+ int offset = (a->off % (64 / tsize)) * tsize;\n+\n+ tcg_gen_gvec_mov(MO_64,\n+ offsetof(CPUARMState, za_state.zt0) + offset,\n+ vec_full_reg_offset(s, a->rt), tsize,\n+ offset ? tsize : 64);\n+ }\n+ return true;\n+}\n+\n static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)\n {\n typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i64);\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 2b9e41a75a..339de72b8a 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -141,6 +141,8 @@ MOVAZ_zt4 11000000 11 00011 0 v:1 .. 00110 za:3 zr:3 00 \\\n MOVT_rzt 1100 0000 0100 1100 0 off:3 00 11111 rt:5\n MOVT_ztr 1100 0000 0100 1110 0 off:3 00 11111 rt:5\n \n+MOVT_ztz 1100 0000 0100 1111 00 off:2 00 11111 rt:5\n+\n ### SME Memory\n \n &ldst esz rs pg rn rm za off v:bool st:bool\n","prefixes":["v3","40/47"]}