{"id":2230739,"url":"http://patchwork.ozlabs.org/api/patches/2230739/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-24-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430002046.59739-24-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-30T00:20:22","name":"[v3,23/47] target/arm: Rename SME BFCVT patterns to BFCVT_hs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"982a4902d7b895177d53340764d70893d10b0efa","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-24-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230739/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230739/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=jmrGTSoV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZgJ3GySz1yJr\n\tfor ; Thu, 30 Apr 2026 10:24:44 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFAG-00070M-Lh; Wed, 29 Apr 2026 20:22:00 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFA2-0006pU-Vo\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:51 -0400","from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFA0-0006ND-RX\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:46 -0400","by mail-pg1-x52a.google.com with SMTP id\n 41be03b00d2f7-c76d797b180so171812a12.2\n for ; Wed, 29 Apr 2026 17:21:44 -0700 (PDT)","from stoup.. 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helo=mail-pg1-x52a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The existing pattern is BFCVT (single-precision to BFloat16).\nIn preparation for introducing more insns of the same name,\nappend the operand sizes.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/tcg/helper-sme-defs.h | 2 +-\n target/arm/tcg/sme_helper.c | 2 +-\n target/arm/tcg/translate-sme.c | 4 ++--\n target/arm/tcg/sme.decode | 2 +-\n 4 files changed, 5 insertions(+), 5 deletions(-)","diff":"diff --git a/target/arm/tcg/helper-sme-defs.h b/target/arm/tcg/helper-sme-defs.h\nindex c551797c6f..01aad4c231 100644\n--- a/target/arm/tcg/helper-sme-defs.h\n+++ b/target/arm/tcg/helper-sme-defs.h\n@@ -250,7 +250,7 @@ DEF_HELPER_FLAGS_5(sme2_umlsll_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,\n DEF_HELPER_FLAGS_5(sme2_usmlall_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)\n DEF_HELPER_FLAGS_5(sme2_sumlall_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)\n \n-DEF_HELPER_FLAGS_4(sme2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_4(sme2_bfcvt_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_4(sme2_bfcvtn, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvt_n, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvtn, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)\ndiff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c\nindex 7ef6f5d71b..30355662d9 100644\n--- a/target/arm/tcg/sme_helper.c\n+++ b/target/arm/tcg/sme_helper.c\n@@ -1726,7 +1726,7 @@ DO_MLALL_IDX(sme2_sumlall_idx_s, uint32_t, int8_t, uint8_t, H4, H1, +)\n #undef DO_MLALL_IDX\n \n /* Convert and compress */\n-void HELPER(sme2_bfcvt)(void *vd, void *vs, float_status *fpst, uint32_t desc)\n+void HELPER(sme2_bfcvt_hs)(void *vd, void *vs, float_status *fpst, uint32_t desc)\n {\n ARMVectorReg scratch;\n size_t oprsz = simd_oprsz(desc);\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex e2d17de165..88c1d78c40 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -1448,8 +1448,8 @@ static bool do_zz_fpst(DisasContext *s, arg_zz_n *a, int data,\n return true;\n }\n \n-TRANS_FEAT(BFCVT, aa64_sme2, do_zz_fpst, a, 0,\n- FPST_A64, gen_helper_sme2_bfcvt)\n+TRANS_FEAT(BFCVT_hs, aa64_sme2, do_zz_fpst, a, 0,\n+ FPST_A64, gen_helper_sme2_bfcvt_hs)\n TRANS_FEAT(BFCVTN, aa64_sme2, do_zz_fpst, a, 0,\n FPST_A64, gen_helper_sme2_bfcvtn)\n TRANS_FEAT(FCVT_n, aa64_sme2, do_zz_fpst, a, 0,\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex ee874be1a6..7a8e1abb59 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -789,7 +789,7 @@ SUB_aaz_d 11000001 111 000010 .. 111 ...00 11 ... @az_4x4_o3\n @zz_4x2_n1 ........ ... ..... ...... .... . ..... \\\n &zz_n n=1 zd=%zd_ax4 zn=%zn_ax2\n \n-BFCVT 11000001 011 00000 111000 ....0 ..... @zz_1x2\n+BFCVT_hs 11000001 011 00000 111000 ....0 ..... @zz_1x2\n BFCVTN 11000001 011 00000 111000 ....1 ..... @zz_1x2\n \n FCVT_n 11000001 001 00000 111000 ....0 ..... @zz_1x2\n","prefixes":["v3","23/47"]}