{"id":2230700,"url":"http://patchwork.ozlabs.org/api/patches/2230700/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-27-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430000524.56046-27-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-30T00:05:09","name":"[v2,26/40] fpu: Return struct from parts{64,128}_muladd","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a46cee037049c7ae61a7a7b738775b695a83ea53","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-27-richard.henderson@linaro.org/mbox/","series":[{"id":502170,"url":"http://patchwork.ozlabs.org/api/series/502170/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502170","date":"2026-04-30T00:04:48","name":"fpu: Export some internals for targets","version":2,"mbox":"http://patchwork.ozlabs.org/series/502170/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230700/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230700/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=NH7gTYap;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZMP0zZhz1yJr\n\tfor ; Thu, 30 Apr 2026 10:10:57 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIEwM-0001T3-Ov; Wed, 29 Apr 2026 20:07:38 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIEvI-0007zr-71\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:39 -0400","from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIEvF-0001t2-QS\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:31 -0400","by mail-pf1-x435.google.com with SMTP id\n d2e1a72fcca58-82fbdd60b64so249425b3a.3\n for ; Wed, 29 Apr 2026 17:06:28 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"At the same time, export.\n\nSigned-off-by: Richard Henderson \n---\n include/fpu/softfloat-parts.h | 9 ++++\n fpu/softfloat.c | 83 +++++++++++++++++------------------\n fpu/softfloat-parts.c.inc | 38 ++++++++--------\n 3 files changed, 69 insertions(+), 61 deletions(-)","diff":"diff --git a/include/fpu/softfloat-parts.h b/include/fpu/softfloat-parts.h\nindex 1876264d43..d54bd6bf62 100644\n--- a/include/fpu/softfloat-parts.h\n+++ b/include/fpu/softfloat-parts.h\n@@ -187,6 +187,15 @@ FloatParts64 parts64_div(const FloatParts64 *a, const FloatParts64 *b,\n FloatParts128 parts128_div(const FloatParts128 *a, const FloatParts128 *b,\n float_status *s);\n \n+FloatParts64 parts64_muladd(const FloatParts64 *a,\n+ const FloatParts64 *b,\n+ const FloatParts64 *c,\n+ int flags, float_status *s);\n+FloatParts128 parts128_muladd(const FloatParts128 *a,\n+ const FloatParts128 *b,\n+ const FloatParts128 *c,\n+ int flags, float_status *s);\n+\n FloatParts64 parts64_round_to_int(const FloatParts64 *a,\n FloatRoundMode rmode,\n int scale, float_status *s,\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 2e5c1d4a32..c5a27e562f 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -1907,18 +1907,18 @@ float16_muladd_scalbn(float16 a, float16 b, float16 c,\n FloatParts64 pa = float16_unpack_canonical(a, status);\n FloatParts64 pb = float16_unpack_canonical(b, status);\n FloatParts64 pc = float16_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n+ FloatParts64 pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Before rounding, scale. */\n if (scale) {\n- parts64_scalbn(pr, scale, status);\n+ parts64_scalbn(&pr, scale, status);\n }\n- parts64_uncanon(pr, status, &float16_params, false);\n+ parts64_uncanon(&pr, status, &float16_params, false);\n /* After rounding, apply negate result, especially for -0.0. */\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &float16_params);\n+ return pack_raw64(&pr, &float16_params);\n }\n \n float16 float16_muladd(float16 a, float16 b, float16 c,\n@@ -1934,18 +1934,18 @@ float32_muladd_scalbn(float32 a, float32 b, float32 c,\n FloatParts64 pa = float32_unpack_canonical(a, status);\n FloatParts64 pb = float32_unpack_canonical(b, status);\n FloatParts64 pc = float32_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n+ FloatParts64 pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Before rounding, scale. */\n if (scale) {\n- parts64_scalbn(pr, scale, status);\n+ parts64_scalbn(&pr, scale, status);\n }\n- parts64_uncanon(pr, status, &float32_params, false);\n+ parts64_uncanon(&pr, status, &float32_params, false);\n /* After rounding, apply negate result, especially for -0.0. */\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &float32_params);\n+ return pack_raw64(&pr, &float32_params);\n }\n \n float64 QEMU_SOFTFLOAT_ATTR\n@@ -1955,18 +1955,18 @@ float64_muladd_scalbn(float64 a, float64 b, float64 c,\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n FloatParts64 pc = float64_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n+ FloatParts64 pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Before rounding, scale. */\n if (scale) {\n- parts64_scalbn(pr, scale, status);\n+ parts64_scalbn(&pr, scale, status);\n }\n- parts64_uncanon(pr, status, &float64_params, false);\n+ parts64_uncanon(&pr, status, &float64_params, false);\n /* After rounding, apply negate result, especially for -0.0. */\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &float64_params);\n+ return pack_raw64(&pr, &float64_params);\n }\n \n static bool force_soft_fma;\n@@ -2116,14 +2116,14 @@ float64 float64r32_muladd(float64 a, float64 b, float64 c,\n FloatParts64 pa = float64_unpack_canonical(a, status);\n FloatParts64 pb = float64_unpack_canonical(b, status);\n FloatParts64 pc = float64_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n+ FloatParts64 pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &float32_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &float32_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return float64r32_pack_raw(pr);\n+ return float64r32_pack_raw(&pr);\n }\n \n bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,\n@@ -2132,14 +2132,14 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,\n FloatParts64 pa = bfloat16_unpack_canonical(a, status);\n FloatParts64 pb = bfloat16_unpack_canonical(b, status);\n FloatParts64 pc = bfloat16_unpack_canonical(c, status);\n- FloatParts64 *pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n+ FloatParts64 pr = parts64_muladd(&pa, &pb, &pc, flags, status);\n \n /* Round before applying negate result. */\n- parts64_uncanon(pr, status, &bfloat16_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts64_uncanon(&pr, status, &bfloat16_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return pack_raw64(pr, &bfloat16_params);\n+ return pack_raw64(&pr, &bfloat16_params);\n }\n \n float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n@@ -2148,14 +2148,14 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n FloatParts128 pa = float128_unpack_canonical(a, status);\n FloatParts128 pb = float128_unpack_canonical(b, status);\n FloatParts128 pc = float128_unpack_canonical(c, status);\n- FloatParts128 *pr = parts128_muladd(&pa, &pb, &pc, flags, status);\n+ FloatParts128 pr = parts128_muladd(&pa, &pb, &pc, flags, status);\n \n /* Round before applying negate result. */\n- parts128_uncanon(pr, status, &float128_params, false);\n- if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n- pr->sign ^= 1;\n+ parts128_uncanon(&pr, status, &float128_params, false);\n+ if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) {\n+ pr.sign ^= 1;\n }\n- return float128_pack_raw(pr);\n+ return float128_pack_raw(&pr);\n }\n \n /*\n@@ -5127,7 +5127,7 @@ float32 float32_exp2(float32 a, float_status *status)\n rp = float64_unpack_canonical(float64_one, status);\n for (int i = 0; i < 15; i++) {\n tp = float64_unpack_canonical(float32_exp2_coefficients[i], status);\n- rp = *parts64_muladd(&tp, &xnp, &rp, 0, status);\n+ rp = parts64_muladd(&tp, &xnp, &rp, 0, status);\n xnp = *parts64_mul(&xnp, &xp, status);\n }\n \n@@ -5176,7 +5176,7 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n n->sign = a->sign ^ b->sign;\n *cc = 0;\n } else {\n- FloatParts64 *q, q_buf, *r_precise, r_precise_buf;\n+ FloatParts64 *q, q_buf, r_precise;\n int float_exception_flags = 0;\n bool is_q_smallish;\n uint32_t r_flags;\n@@ -5205,12 +5205,11 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n 0, status, fmt);\n \n /* Compute precise remainder */\n- r_precise_buf = *b;\n- r_precise = parts64_muladd(&r_precise_buf, n, a,\n+ r_precise = parts64_muladd(b, n, a,\n float_muladd_negate_product, status);\n \n /* Round remainder to the target format */\n- *r = *r_precise;\n+ *r = r_precise;\n status->float_exception_flags = 0;\n *r = parts64_round_to_fmt(r, status, fmt);\n r_flags = status->float_exception_flags;\n@@ -5234,17 +5233,17 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n * toward zero) or incremented.\n */\n saved_r_sign = r->sign;\n- saved_r_precise_sign = r_precise->sign;\n+ saved_r_precise_sign = r_precise.sign;\n r->sign = false;\n- r_precise->sign = false;\n- if (parts64_compare(r, r_precise, status, true) <\n+ r_precise.sign = false;\n+ if (parts64_compare(r, &r_precise, status, true) <\n float_relation_equal) {\n *dxc = 0x8;\n } else {\n *dxc = 0xc;\n }\n r->sign = saved_r_sign;\n- r_precise->sign = saved_r_precise_sign;\n+ r_precise.sign = saved_r_precise_sign;\n }\n }\n }\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 77465cce6e..09b79f8d44 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -679,9 +679,8 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,\n * Requires A and C extracted into a double-sized structure to provide the\n * extra space for the widening multiply.\n */\n-static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n- FloatPartsN *c,\n- int flags, float_status *s)\n+FloatPartsN partsN(muladd)(const FloatPartsN *a, const FloatPartsN *b,\n+ const FloatPartsN *c, int flags, float_status *s)\n {\n int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n int c_mask = float_cmask(c->cls);\n@@ -719,10 +718,13 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n }\n \n /* Narrow with sticky bit, for proper rounding later. */\n- fracN(truncjam)(a, &p_widen);\n- a->sign = p_widen.sign;\n- a->exp = p_widen.exp;\n- return a;\n+ FloatPartsN r = {\n+ .sign = p_widen.sign,\n+ .exp = p_widen.exp,\n+ .cls = float_class_normal,\n+ };\n+ fracN(truncjam)(&r, &p_widen);\n+ return r;\n }\n \n /*\n@@ -732,8 +734,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n * off to the target-specific pick-a-NaN routine.\n */\n if (unlikely(abc_mask & float_cmask_anynan)) {\n- *a = partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask);\n- return a;\n+ return partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask);\n }\n \n if (unlikely(ab_mask == float_cmask_infzero)) {\n@@ -750,9 +751,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n }\n /* Inf + C == Inf */\n record_denormals_used(abc_mask, s);\n- a->sign = p_sign;\n- a->cls = float_class_inf;\n- return a;\n+ return (FloatPartsN){ .sign = p_sign, .cls = float_class_inf };\n }\n record_denormals_used(abc_mask, s);\n \n@@ -767,19 +766,20 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n if (!(c_mask & float_cmask_zero)\n || p_sign == c_sign\n || (flags & float_muladd_suppress_add_product_zero)) {\n- c->sign = c_sign;\n- return c;\n+ FloatPartsN r = *c;\n+ r.sign = c_sign;\n+ return r;\n }\n \n return_sub_zero:\n /* 0 - 0 == -0 for round_down, +0 otherwise. */\n- a->sign = s->float_rounding_mode == float_round_down;\n- a->cls = float_class_zero;\n- return a;\n+ return (FloatPartsN){\n+ .sign = s->float_rounding_mode == float_round_down,\n+ .cls = float_class_zero\n+ };\n \n d_nan:\n- *a = partsN(default_nan)(s);\n- return a;\n+ return partsN(default_nan)(s);\n }\n \n /*\n","prefixes":["v2","26/40"]}