{"id":2230600,"url":"http://patchwork.ozlabs.org/api/patches/2230600/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429222445.26301-3-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260429222445.26301-3-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-29T22:23:59","name":"[PULL,02/48] fpu: Drop parts_uncanon","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"77d6b3706e71cb2b333da4e4c8c25514f5986ac5","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429222445.26301-3-richard.henderson@linaro.org/mbox/","series":[{"id":502161,"url":"http://patchwork.ozlabs.org/api/series/502161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502161","date":"2026-04-29T22:23:57","name":"[PULL,01/48] fpu: Drop parts_canonicalize","version":1,"mbox":"http://patchwork.ozlabs.org/series/502161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230600/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230600/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Gnu5x5Kh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5X2S3Qg3z1yHZ\n\tfor ; Thu, 30 Apr 2026 08:26:08 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIDL4-0008NF-EP; Wed, 29 Apr 2026 18:25:02 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIDL2-0008Mk-5W\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 18:25:00 -0400","from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIDL0-0004V9-20\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 18:24:59 -0400","by mail-pj1-x102d.google.com with SMTP id\n 98e67ed59e1d1-356337f058aso124201a91.2\n for ; Wed, 29 Apr 2026 15:24:57 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use parts{64,128}_uncanon at each call site.\n\nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Richard Henderson \n---\n fpu/softfloat.c | 44 ++++++++++++++++++--------------------------\n 1 file changed, 18 insertions(+), 26 deletions(-)","diff":"diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex f9997f5236..7c13a7848e 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -814,14 +814,6 @@ static void parts128_uncanon_normal(FloatParts128 *p, float_status *status,\n #define parts_uncanon_normal(A, S, F, X) \\\n PARTS_GENERIC_64_128(uncanon_normal, A)(A, S, F, X)\n \n-static void parts64_uncanon(FloatParts64 *p, float_status *status,\n- const FloatFmt *fmt, bool saturate);\n-static void parts128_uncanon(FloatParts128 *p, float_status *status,\n- const FloatFmt *fmt, bool saturate);\n-\n-#define parts_uncanon(A, S, F, X) \\\n- PARTS_GENERIC_64_128(uncanon, A)(A, S, F, X)\n-\n static void parts64_add_normal(FloatParts64 *a, FloatParts64 *b);\n static void parts128_add_normal(FloatParts128 *a, FloatParts128 *b);\n static void parts256_add_normal(FloatParts256 *a, FloatParts256 *b);\n@@ -1756,7 +1748,7 @@ static float8_e4m3 float8_e4m3_round_pack_canonical(FloatParts64 *p,\n float_status *s,\n bool saturate)\n {\n- parts_uncanon(p, s, &float8_e4m3_params, saturate);\n+ parts64_uncanon(p, s, &float8_e4m3_params, saturate);\n return float8_e4m3_pack_raw(p);\n }\n \n@@ -1764,7 +1756,7 @@ static float8_e5m2 float8_e5m2_round_pack_canonical(FloatParts64 *p,\n float_status *s,\n bool saturate)\n {\n- parts_uncanon(p, s, &float8_e5m2_params, saturate);\n+ parts64_uncanon(p, s, &float8_e5m2_params, saturate);\n return float8_e5m2_pack_raw(p);\n }\n \n@@ -1772,7 +1764,7 @@ static float16 float16a_round_pack_canonical(FloatParts64 *p,\n float_status *s,\n const FloatFmt *params)\n {\n- parts_uncanon(p, s, params, false);\n+ parts64_uncanon(p, s, params, false);\n return float16_pack_raw(p);\n }\n \n@@ -1785,7 +1777,7 @@ static float16 float16_round_pack_canonical(FloatParts64 *p,\n static bfloat16 bfloat16_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- parts_uncanon(p, s, &bfloat16_params, false);\n+ parts64_uncanon(p, s, &bfloat16_params, false);\n return bfloat16_pack_raw(p);\n }\n \n@@ -1799,7 +1791,7 @@ static void float32_unpack_canonical(FloatParts64 *p, float32 f,\n static float32 float32_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- parts_uncanon(p, s, &float32_params, false);\n+ parts64_uncanon(p, s, &float32_params, false);\n return float32_pack_raw(p);\n }\n \n@@ -1813,14 +1805,14 @@ static void float64_unpack_canonical(FloatParts64 *p, float64 f,\n static float64 float64_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- parts_uncanon(p, s, &float64_params, false);\n+ parts64_uncanon(p, s, &float64_params, false);\n return float64_pack_raw(p);\n }\n \n static float64 float64r32_pack_raw(FloatParts64 *p)\n {\n /*\n- * In parts_uncanon, we placed the fraction for float32 at the lsb.\n+ * In parts64_uncanon, we placed the fraction for float32 at the lsb.\n * We need to adjust the fraction higher so that the least N bits are\n * zero, and the fraction is adjacent to the float64 implicit bit.\n */\n@@ -1862,7 +1854,7 @@ static float64 float64r32_pack_raw(FloatParts64 *p)\n static float64 float64r32_round_pack_canonical(FloatParts64 *p,\n float_status *s)\n {\n- parts_uncanon(p, s, &float32_params, false);\n+ parts64_uncanon(p, s, &float32_params, false);\n return float64r32_pack_raw(p);\n }\n \n@@ -1876,7 +1868,7 @@ static void float128_unpack_canonical(FloatParts128 *p, float128 f,\n static float128 float128_round_pack_canonical(FloatParts128 *p,\n float_status *s)\n {\n- parts_uncanon(p, s, &float128_params, false);\n+ parts128_uncanon(p, s, &float128_params, false);\n return float128_pack_raw(p);\n }\n \n@@ -1924,7 +1916,7 @@ static floatx80 floatx80_round_pack_canonical(FloatParts128 *p,\n case float_class_normal:\n case float_class_denormal:\n if (s->floatx80_rounding_precision == floatx80_precision_x) {\n- parts_uncanon_normal(p, s, fmt, false);\n+ parts128_uncanon_normal(p, s, fmt, false);\n frac = p->frac_hi;\n exp = p->exp;\n } else {\n@@ -1933,7 +1925,7 @@ static floatx80 floatx80_round_pack_canonical(FloatParts128 *p,\n p64.sign = p->sign;\n p64.exp = p->exp;\n frac_truncjam(&p64, p);\n- parts_uncanon_normal(&p64, s, fmt, false);\n+ parts64_uncanon_normal(&p64, s, fmt, false);\n frac = p64.frac;\n exp = p64.exp;\n }\n@@ -2331,7 +2323,7 @@ float16_muladd_scalbn(float16 a, float16 b, float16 c,\n pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n \n /* Round before applying negate result. */\n- parts_uncanon(pr, status, &float16_params, false);\n+ parts64_uncanon(pr, status, &float16_params, false);\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -2356,7 +2348,7 @@ float32_muladd_scalbn(float32 a, float32 b, float32 c,\n pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n \n /* Round before applying negate result. */\n- parts_uncanon(pr, status, &float32_params, false);\n+ parts64_uncanon(pr, status, &float32_params, false);\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -2375,7 +2367,7 @@ float64_muladd_scalbn(float64 a, float64 b, float64 c,\n pr = parts_muladd_scalbn(&pa, &pb, &pc, scale, flags, status);\n \n /* Round before applying negate result. */\n- parts_uncanon(pr, status, &float64_params, false);\n+ parts64_uncanon(pr, status, &float64_params, false);\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -2534,7 +2526,7 @@ float64 float64r32_muladd(float64 a, float64 b, float64 c,\n pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n \n /* Round before applying negate result. */\n- parts_uncanon(pr, status, &float32_params, false);\n+ parts64_uncanon(pr, status, &float32_params, false);\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -2552,7 +2544,7 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,\n pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n \n /* Round before applying negate result. */\n- parts_uncanon(pr, status, &bfloat16_params, false);\n+ parts64_uncanon(pr, status, &bfloat16_params, false);\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -2570,7 +2562,7 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c,\n pr = parts_muladd_scalbn(&pa, &pb, &pc, 0, flags, status);\n \n /* Round before applying negate result. */\n- parts_uncanon(pr, status, &float128_params, false);\n+ parts128_uncanon(pr, status, &float128_params, false);\n if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) {\n pr->sign ^= 1;\n }\n@@ -5600,7 +5592,7 @@ static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b,\n /* Round remainder to the target format */\n *r = *r_precise;\n status->float_exception_flags = 0;\n- parts_uncanon(r, status, fmt, false);\n+ parts64_uncanon(r, status, fmt, false);\n r_flags = status->float_exception_flags;\n r->frac &= (1ULL << fmt->frac_size) - 1;\n parts64_canonicalize(r, status, fmt);\n","prefixes":["PULL","02/48"]}