{"id":2228732,"url":"http://patchwork.ozlabs.org/api/patches/2228732/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-27T09:26:09","name":"[v2,5/7] clk: qcom: sc7280: Add UFS clock support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ff613a5bfa8aee87902440736da45c42c24a2a04","submitter":{"id":90810,"url":"http://patchwork.ozlabs.org/api/people/90810/?format=json","name":"Balaji Selvanathan","email":"balaji.selvanathan@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com/mbox/","series":[{"id":501613,"url":"http://patchwork.ozlabs.org/api/series/501613/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501613","date":"2026-04-27T09:26:04","name":"Add UFS clock support for Qualcomm SoCs","version":2,"mbox":"http://patchwork.ozlabs.org/series/501613/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228732/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228732/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ERxshGxe;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=P3yJgFnV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"ERxshGxe\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"P3yJgFnV\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=balaji.selvanathan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3yrQ3fJmz1xvV\n\tfor ; Mon, 27 Apr 2026 19:27:02 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 34421842EF;\n\tMon, 27 Apr 2026 11:26:47 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id B1330842CE; Mon, 27 Apr 2026 11:26:45 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 715B5842EF\n for ; Mon, 27 Apr 2026 11:26:43 +0200 (CEST)","from pps.filterd (m0279869.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63R8TA181501431\n for ; Mon, 27 Apr 2026 09:26:42 GMT","from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4drnqrne0s-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Mon, 27 Apr 2026 09:26:41 +0000 (GMT)","by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-82fa2165c3eso6119431b3a.0\n for ; Mon, 27 Apr 2026 02:26:41 -0700 (PDT)","from hu-bselvana-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add UFS clock support for sc7280 including register definitions,\nrate configuration, and gate clocks.\n\nReviewed-by: Sumit Garg \nSigned-off-by: Balaji Selvanathan \n---\nChanges in v2:\n- No changes\n---\n drivers/clk/qcom/clock-sc7280.c | 52 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 52 insertions(+)","diff":"diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c\nindex 7b6ed826023..2c73c26484f 100644\n--- a/drivers/clk/qcom/clock-sc7280.c\n+++ b/drivers/clk/qcom/clock-sc7280.c\n@@ -23,6 +23,10 @@\n #define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058\n #define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c\n #define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054\n+#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024\n+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c\n+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0\n+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084\n \n static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {\n \tF(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),\n@@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {\n \t{ }\n };\n \n+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {\n+\tF(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {\n+\tF(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),\n+\t{ }\n+};\n+\n+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),\n+\t{ }\n+};\n+\n static ulong sc7280_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)\n \tcase GCC_PCIE1_PHY_RCHNG_CLK:\n \t\tclk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);\n \t\treturn 100000000;\n+\tcase GCC_UFS_PHY_AXI_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_ICE_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_PHY_AUX_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_UNIPRO_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n \tdefault:\n \t\treturn rate;\n \t}\n@@ -147,6 +198,7 @@ static const struct gate_clk sc7280_clks[] = {\n \tGATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),\n \tGATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),\n+\tGATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)),\n \tGATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)),\n","prefixes":["v2","5/7"]}