{"id":2228730,"url":"http://patchwork.ozlabs.org/api/patches/2228730/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-27T09:26:07","name":"[v2,3/7] clk: qcom: sa8775p: Add UFS clock support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"292df5920fe5ea9f42fcf0a9138c30a6ecdc720d","submitter":{"id":90810,"url":"http://patchwork.ozlabs.org/api/people/90810/?format=json","name":"Balaji Selvanathan","email":"balaji.selvanathan@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com/mbox/","series":[{"id":501613,"url":"http://patchwork.ozlabs.org/api/series/501613/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501613","date":"2026-04-27T09:26:04","name":"Add UFS clock support for Qualcomm SoCs","version":2,"mbox":"http://patchwork.ozlabs.org/series/501613/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228730/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228730/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=YuTmAouo;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=iBgmSsVh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"YuTmAouo\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"iBgmSsVh\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=balaji.selvanathan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3yr501J5z1xvV\n\tfor ; Mon, 27 Apr 2026 19:26:44 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 953858421D;\n\tMon, 27 Apr 2026 11:26:35 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id 7617E83693; Mon, 27 Apr 2026 11:26:34 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 4957E8421D\n for ; Mon, 27 Apr 2026 11:26:32 +0200 (CEST)","from pps.filterd (m0279873.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63R8TChH2913900\n for ; Mon, 27 Apr 2026 09:26:31 GMT","from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dt26xgtp2-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Mon, 27 Apr 2026 09:26:30 +0000 (GMT)","by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-82f9429f49cso12508483b3a.3\n for ; Mon, 27 Apr 2026 02:26:30 -0700 (PDT)","from hu-bselvana-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com>","References":"<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>","In-Reply-To":"<20260427-ufs_clk-v2-0-36e10a7c0ef6@oss.qualcomm.com>","To":"u-boot@lists.denx.de, Sumit Garg ,\n u-boot-qcom@groups.io","Cc":"Lukasz Majewski , Tom Rini ,\n Casey Connolly ,\n Neil Armstrong ,\n David Wronek ,\n Jens Reidel , Luca Weiss ,\n Swathi Tamilselvan ,\n Aswin Murugan ,\n Bhupesh Sharma ,\n Neha Malcom Francis ,\n Julien Stephan ,\n Marek Vasut ,\n Balaji Selvanathan ,\n Sumit Garg ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777281967; l=4187;\n i=balaji.selvanathan@oss.qualcomm.com; s=20260213; h=from:subject:message-id;\n bh=NjbNyT4G64RajSzfnmoJw7JlyCD8amDeMxakxwyy39s=;\n b=4yf5HP+eTScmwK1FNBBHmIONKcgOQoL8rdSfQEqeXoyROOTt4KOFMf/cAx+vcaNUOt1RjWcCT\n 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","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add UFS clock support for SA8775P including register definitions,\nrate configuration, and gate clocks.\n\nReviewed-by: Sumit Garg \nSigned-off-by: Balaji Selvanathan \n---\nChanges in v2:\n- No changes\n---\n drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 63 insertions(+)","diff":"diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c\nindex 4957abf6f58..7eec4aeae48 100644\n--- a/drivers/clk/qcom/clock-sa8775p.c\n+++ b/drivers/clk/qcom/clock-sa8775p.c\n@@ -19,6 +19,11 @@\n #define USB30_PRIM_MASTER_CLK_CMD_RCGR\t\t0x1b028\n #define USB3_PRIM_PHY_AUX_CMD_RCGR\t\t0x1b06c\n \n+#define UFS_PHY_AXI_CLK_CMD_RCGR\t\t0x8302c\n+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR\t\t0x83074\n+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR\t\t0x830a8\n+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR\t0x8308c\n+\n #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)\n #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)\n #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)\n@@ -44,9 +49,35 @@\n \n #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)\n \n+/* UFS AXI clock frequency table */\n+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {\n+\tF(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+/* UFS ICE CORE clock frequency table */\n+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+/* UFS UNIPRO CORE clock frequency table */\n+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {\n+\tF(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),\n+\tF(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),\n+\tF(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n static ulong sa8775p_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct freq_tbl *freq;\n \n \tif (clk->id < priv->data->num_clks)\n \t\tdebug(\"%s: %s, requested rate=%ld\\n\", __func__,\n@@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)\n \t\t\t\t 5, 0, 0, CFG_CLK_SRC_GPLL0, 8);\n \t\tclk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);\n \t\treturn rate;\n+\tcase GCC_UFS_PHY_AXI_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_UNIPRO_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_ICE_CORE_CLK:\n+\t\tfreq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);\n+\t\tclk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,\n+\t\t\t\t freq->pre_div, freq->m, freq->n, freq->src, 8);\n+\t\treturn freq->freq;\n+\tcase GCC_UFS_PHY_PHY_AUX_CLK:\n+\t\tclk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);\n+\t\treturn 19200000;\n \tdefault:\n \t\treturn 0;\n \t}\n@@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = {\n \n \t/* QUP Wrapper 3 clocks */\n \tGATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT),\n+\n+\t/* UFS PHY clocks */\n+\tGATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1),\n+\tGATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1),\n+\tGATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1),\n+\tGATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1),\n+\tGATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1),\n+\tGATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1),\n+\tGATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1),\n+\tGATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1),\n+\tGATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1),\n+\n+\t/* EDP reference clock (used by UFS PHY) */\n+\tGATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1),\n };\n \n static int sa8775p_enable(struct clk *clk)\n","prefixes":["v2","3/7"]}