{"id":2228719,"url":"http://patchwork.ozlabs.org/api/patches/2228719/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427085843.42460-7-fengchengwen@huawei.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260427085843.42460-7-fengchengwen@huawei.com>","list_archive_url":null,"date":"2026-04-27T08:58:43","name":"[v5,6/6] vfio/pci: Add PCIe TPH SET_ST interface","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"be27e6a07d44355541670291bb36898e539cd66f","submitter":{"id":92756,"url":"http://patchwork.ozlabs.org/api/people/92756/?format=json","name":"Chengwen Feng","email":"fengchengwen@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427085843.42460-7-fengchengwen@huawei.com/mbox/","series":[{"id":501609,"url":"http://patchwork.ozlabs.org/api/series/501609/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501609","date":"2026-04-27T08:58:42","name":"vfio/pci: Add PCIe TPH support","version":5,"mbox":"http://patchwork.ozlabs.org/series/501609/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228719/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228719/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=VPtHSXNd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=h9yLoUwpdj5EaJiOK+YfHQeAEjuC/guILsPN7rtymFU=;\n\tb=VPtHSXNdvuv7Kwi8uR/jfoNwky3iwhb2eiwbdD43o71svcbhUP4itYiaQ3Y9Iq7KxhKEXeaCb\n\tLkXkK+6HXqwUZhxSoN3hmsv6Auu/HRDDUHOE3ixgx+OmpwsUg7LRWodLfpXCVavNw89cpSWAzL+\n\t2k0Ozp0H4mHm2BU5fnDNKp4=","From":"Chengwen Feng ","To":", ","CC":", ,\n\t, ,\n\t, , ","Subject":"[PATCH v5 6/6] vfio/pci: Add PCIe TPH SET_ST interface","Date":"Mon, 27 Apr 2026 16:58:43 +0800","Message-ID":"<20260427085843.42460-7-fengchengwen@huawei.com>","X-Mailer":"git-send-email 2.17.1","In-Reply-To":"<20260427085843.42460-1-fengchengwen@huawei.com>","References":"<20260427085843.42460-1-fengchengwen@huawei.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain","X-ClientProxiedBy":"kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)"},"content":"Add VFIO_PCI_TPH_SET_ST operation to support batch programming of steering\ntag entries. If any entry fails, roll back successfully programmed entries\nto 0 to prevent inconsistent device state.\n\nSigned-off-by: Chengwen Feng \n---\n drivers/vfio/pci/vfio_pci_core.c | 69 ++++++++++++++++++++++++++++++++\n 1 file changed, 69 insertions(+)","diff":"diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex 74596ef278b5..ce62d7026b27 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1586,6 +1586,73 @@ static int vfio_pci_tph_get_st(struct vfio_pci_core_device *vdev,\n \treturn err;\n }\n \n+static int vfio_pci_tph_set_st(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct pci_dev *pdev = vdev->pdev;\n+\tstruct vfio_pci_tph_entry *ents;\n+\tstruct vfio_pci_tph_st st;\n+\tenum tph_mem_type mtype;\n+\tint i = 0, j, err, size;\n+\tu32 tab_loc;\n+\tu16 st_val;\n+\n+\ttab_loc = pcie_tph_get_st_table_loc(pdev);\n+\tif (tab_loc != PCI_TPH_LOC_CAP && tab_loc != PCI_TPH_LOC_MSIX)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (copy_from_user(&st, uarg, sizeof(st)))\n+\t\treturn -EFAULT;\n+\n+\tif (!st.count || st.count > VFIO_PCI_TPH_MAX_ENTRIES)\n+\t\treturn -EINVAL;\n+\n+\tsize = st.count * sizeof(*ents);\n+\tents = kvmalloc(size, GFP_KERNEL);\n+\tif (!ents)\n+\t\treturn -ENOMEM;\n+\n+\tif (copy_from_user(ents, uarg + sizeof(st), size)) {\n+\t\terr = -EFAULT;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (; i < st.count; i++) {\n+\t\tif (ents[i].cpu == U32_MAX) {\n+\t\t\terr = pcie_tph_set_st_entry(pdev, ents[i].index, 0);\n+\t\t\tif (err)\n+\t\t\t\tgoto out;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_VM) {\n+\t\t\tmtype = TPH_MEM_TYPE_VM;\n+\t\t} else if (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_PM) {\n+\t\t\tmtype = TPH_MEM_TYPE_PM;\n+\t\t} else {\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\terr = pcie_tph_get_cpu_st(pdev, mtype, ents[i].cpu, &st_val);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t\terr = pcie_tph_set_st_entry(pdev, ents[i].index, st_val);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t}\n+\n+out:\n+\tif (err) {\n+\t\t/* Roll back previously programmed entries to 0 */\n+\t\tfor (j = 0; j < i; j++)\n+\t\t\tpcie_tph_set_st_entry(pdev, ents[j].index, 0);\n+\t}\n+\tkvfree(ents);\n+\treturn err;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1608,6 +1675,8 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\treturn vfio_pci_tph_disable(vdev);\n \tcase VFIO_PCI_TPH_GET_ST:\n \t\treturn vfio_pci_tph_get_st(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_SET_ST:\n+\t\treturn vfio_pci_tph_set_st(vdev, &op, uarg + minsz);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n","prefixes":["v5","6/6"]}