{"id":2228715,"url":"http://patchwork.ozlabs.org/api/patches/2228715/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427085843.42460-5-fengchengwen@huawei.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260427085843.42460-5-fengchengwen@huawei.com>","list_archive_url":null,"date":"2026-04-27T08:58:41","name":"[v5,4/6] vfio/pci: Add PCIe TPH enable/disable support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6168a4a28eeb2721d087cb0bc86a64a6f2f9f16d","submitter":{"id":92756,"url":"http://patchwork.ozlabs.org/api/people/92756/?format=json","name":"Chengwen Feng","email":"fengchengwen@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260427085843.42460-5-fengchengwen@huawei.com/mbox/","series":[{"id":501609,"url":"http://patchwork.ozlabs.org/api/series/501609/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501609","date":"2026-04-27T08:58:42","name":"vfio/pci: Add PCIe TPH support","version":5,"mbox":"http://patchwork.ozlabs.org/series/501609/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228715/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228715/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=FkFs2rwZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=jQ3yJVq5/FQBn3/W/nSTwvpau9Q+Bc+rzoj4pREwzXc=;\n\tb=FkFs2rwZD20QodBYrOhbMbj35K2kJUZ44mW0KU39JHs3dk2onPG88ZNnhVqpj7gFcYcK8hN22\n\tRy6VQ/Wju5ApZJ1GjVlHdGYytWNCHS2gMa8v8H/j8LFO3M7bJqHtyt9XsJYcuyrLWxHzJuuT2Cq\n\tKIFcUEFOzluy4zQKBCLNSvs=","From":"Chengwen Feng ","To":", ","CC":", ,\n\t, ,\n\t, , ","Subject":"[PATCH v5 4/6] vfio/pci: Add PCIe TPH enable/disable support","Date":"Mon, 27 Apr 2026 16:58:41 +0800","Message-ID":"<20260427085843.42460-5-fengchengwen@huawei.com>","X-Mailer":"git-send-email 2.17.1","In-Reply-To":"<20260427085843.42460-1-fengchengwen@huawei.com>","References":"<20260427085843.42460-1-fengchengwen@huawei.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain","X-ClientProxiedBy":"kwepems100002.china.huawei.com (7.221.188.206) To\n kwepemk500009.china.huawei.com (7.202.194.94)"},"content":"Add support to enable and disable TPH function with mode selection.\n\nRestrict unsafe device-specific TPH mode to be allowed only when module\nparameter enable_unsafe_tph_ds_mode=1 is set.\n\nSync TPH software state after device reset to avoid state mismatch caused\nby FLR hardware reset.\n\nSigned-off-by: Chengwen Feng \n---\n drivers/vfio/pci/vfio_pci_core.c | 47 ++++++++++++++++++++++++++++++++\n 1 file changed, 47 insertions(+)","diff":"diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex 6c498fbef2dc..d1f7f2933e66 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1246,6 +1246,13 @@ static int vfio_pci_ioctl_reset(struct vfio_pci_core_device *vdev,\n \n \tvfio_pci_dma_buf_move(vdev, true);\n \tret = pci_try_reset_function(vdev->pdev);\n+\tif (!ret) {\n+\t\t/*\n+\t\t * FLR clears TPH hardware state, but pci/tph.c software state\n+\t\t * remains enabled. Explicitly disable to sync state.\n+\t\t */\n+\t\tpcie_disable_tph(vdev->pdev);\n+\t}\n \tif (__vfio_pci_memory_enabled(vdev))\n \t\tvfio_pci_dma_buf_move(vdev, false);\n \tup_write(&vdev->memory_lock);\n@@ -1488,6 +1495,42 @@ static int vfio_pci_tph_get_cap(struct vfio_pci_core_device *vdev,\n \treturn 0;\n }\n \n+static int vfio_pci_tph_enable(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct pci_dev *pdev = vdev->pdev;\n+\tstruct vfio_pci_tph_ctrl ctrl;\n+\tint mode;\n+\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, ctrl))\n+\t\treturn -EINVAL;\n+\n+\tif (copy_from_user(&ctrl, uarg, sizeof(ctrl)))\n+\t\treturn -EFAULT;\n+\n+\tif (ctrl.mode != VFIO_PCI_TPH_MODE_IV &&\n+\t ctrl.mode != VFIO_PCI_TPH_MODE_DS)\n+\t\treturn -EINVAL;\n+\n+\tif (ctrl.mode == VFIO_PCI_TPH_MODE_DS && !enable_unsafe_tph_ds_mode)\n+\t\treturn -EOPNOTSUPP;\n+\n+\t/* Reserved must be zero */\n+\tif (memchr_inv(ctrl.reserved, 0, sizeof(ctrl.reserved)))\n+\t\treturn -EINVAL;\n+\n+\tmode = (ctrl.mode == VFIO_PCI_TPH_MODE_IV) ? PCI_TPH_ST_IV_MODE :\n+\t\t\t\t\t\t PCI_TPH_ST_DS_MODE;\n+\treturn pcie_enable_tph(pdev, mode);\n+}\n+\n+static int vfio_pci_tph_disable(struct vfio_pci_core_device *vdev)\n+{\n+\tpcie_disable_tph(vdev->pdev);\n+\treturn 0;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1504,6 +1547,10 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \tswitch (op.op) {\n \tcase VFIO_PCI_TPH_GET_CAP:\n \t\treturn vfio_pci_tph_get_cap(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_ENABLE:\n+\t\treturn vfio_pci_tph_enable(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_DISABLE:\n+\t\treturn vfio_pci_tph_disable(vdev);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n","prefixes":["v5","4/6"]}