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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n AM3PEPF0000A799.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch improves handling of 2-element vec_concats in\naarch64_vector_init_fallback (); where previously the aarch64_vec_concat\ninsn was emitted only for pairs of vectors, we now allow scalar operands\nas well. Furthermore, if the two operands are the same, we can now emit a\nvec_duplicate instead of a vec_concat, leading to better code generation.\n\nThis is backed by the new combine{z,_internal}{,_be} insn patterns, that\nwere each split between integral 16- and 32-bit modes (only involving GPRs\nand memory), and the rest (requiring the \"w\" alternatives as well).\n\nThe effect of the changes is illustrated by the changes to vec-init-23.c,\nintroduced in the previous patch (and a handful of other vector-init\nrelated tests).\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-simd.md (*aarch64_combine_internal):\n\tNew insn patterns.\n\t(*aarch64_combine_internal_be): Likewise.\n\t(*aarch64_combinez): Likewise.\n\t(*aarch64_combinez_be): Likewise.\n\t(@aarch64_vec_concat): Support smaller vector and scalar modes.\n\t* config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback):\n\tHandle the case of two scalar elements.\n\t* config/aarch64/iterators.md (SSUB64): New mode iterator.\n\t(VSSUB64): Likewise.\n\t(VSSUB32_I) : Likewise.\n\t(VSSUB64_F): Likewise.\n\t(VS32_I_SUB64_F): Likewise.\n\t(single_wx): Define attribute for sub-64-bit vector and scalar modes.\n\t(VDBL): Likewise.\n\t(single_dwx): New mode attribute.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/sve/gather_load_10.c: Adjust testcase.\n\t* gcc.target/aarch64/sve/slp_1.c: Likewise.\n\t* gcc.target/aarch64/vec-init-18.c: Likewise.\n\t* gcc.target/aarch64/vec-init-23.c: Likewise.\n\t* gcc.target/aarch64/vec-init-single-const.c: Likewise.\n---\n gcc/config/aarch64/aarch64-simd.md | 115 +++++++++++++++++-\n gcc/config/aarch64/aarch64.cc | 19 +--\n gcc/config/aarch64/iterators.md | 39 +++++-\n .../gcc.target/aarch64/sve/gather_load_10.c | 3 +-\n gcc/testsuite/gcc.target/aarch64/sve/slp_1.c | 4 +-\n .../gcc.target/aarch64/vec-init-18.c | 7 +-\n .../gcc.target/aarch64/vec-init-23.c | 85 ++++++-------\n .../aarch64/vec-init-single-const.c | 4 +-\n 8 files changed, 209 insertions(+), 67 deletions(-)","diff":"diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 4bb26621efc..b57d4e29807 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -4814,6 +4814,34 @@\n }\n )\n \n+(define_insn \"*aarch64_combine_internal\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+\t (match_operand:VS32_I_SUB64_F 1 \"register_operand\")\n+\t (match_operand:VS32_I_SUB64_F 2 \"aarch64_simd_nonimmediate_operand\")))]\n+ \"TARGET_FLOAT\n+ && !BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n+ [ w , w , w ; neon_permute , simd ] uzp1\\t%0., %1., %2.\n+ [ w , 0 , w ; neon_move , simd ] mov\\t%0.[1], %2.[0]\n+ [ w , 0 , Utv ; neon_load1_one_lane , simd ] ld1\\t{%0.}[1], %2\n+ [ w , 0 , r ; neon_from_gp , simd ] ins\\t%0.[1], %2\n+ [ ?r , 0 , r ; bfm , * ] bfi\\t%0, %2, , \n+ }\n+)\n+\n+(define_insn \"*aarch64_combine_internal\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+\t (match_operand:VSSUB32_I 1 \"register_operand\")\n+\t (match_operand:VSSUB32_I 2 \"aarch64_simd_nonimmediate_operand\")))]\n+ \"TARGET_FLOAT\n+ && !BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n+ [ r , 0 , r ; bfm , * ] bfi\\t%0, %2, , \n+ }\n+)\n+\n (define_insn \"*aarch64_combine_internal_be\"\n [(set (match_operand: 0 \"aarch64_reg_or_mem_pair_operand\")\n \t(vec_concat:\n@@ -4833,6 +4861,35 @@\n }\n )\n \n+(define_insn \"*aarch64_combine_internal_be\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+\t (match_operand:VS32_I_SUB64_F 2 \"aarch64_simd_nonimmediate_operand\")\n+\t (match_operand:VS32_I_SUB64_F 1 \"register_operand\")))]\n+ \"TARGET_FLOAT\n+ && BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n+ [ w , w , w ; neon_permute , simd ] uzp1\\t%0., %1., %2.\n+ [ w , 0 , w ; neon_move , simd ] mov\\t%0.[1], %2.[0]\n+ [ w , 0 , Utv ; neon_load1_one_lane , simd ] ld1\\t{%0.}[1], %2\n+ [ w , 0 , r ; neon_from_gp , simd ] ins\\t%0.[1], %2\n+ [ ?r , 0 , r ; bfm , * ] bfi\\t%0, %2, , \n+ }\n+)\n+\n+(define_insn \"*aarch64_combine_internal_be\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+\t (match_operand:VSSUB32_I 2 \"aarch64_simd_nonimmediate_operand\")\n+\t (match_operand:VSSUB32_I 1 \"register_operand\")))]\n+ \"TARGET_FLOAT\n+ && BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n+ [ r , 0 , r ; bfm , * ] bfi\\t%0, %2, , \n+ }\n+)\n+\n+\n ;; In this insn, operand 1 should be low, and operand 2 the high part of the\n ;; dest vector.\n \n@@ -4849,6 +4906,33 @@\n }\n )\n \n+(define_insn \"*aarch64_combinez\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+ (match_operand:VSSUB32_I 1 \"nonimmediate_operand\")\n+\t (match_operand:VSSUB32_I 2 \"aarch64_simd_or_scalar_imm_zero\")))]\n+ \"TARGET_FLOAT && !BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 ; attrs: type ]\n+ [ r , r ; mov_reg ] uxt\\t%w0, %w1\n+ [ r , m ; load_4 ] ldr\\t%0, %1\n+ }\n+)\n+\n+(define_insn \"*aarch64_combinez\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+ (match_operand:VS32_I_SUB64_F 1 \"nonimmediate_operand\")\n+\t (match_operand:VS32_I_SUB64_F 2 \"aarch64_simd_or_scalar_imm_zero\")))]\n+ \"TARGET_FLOAT && !BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 ; attrs: type ]\n+ [ w , w ; neon_move ] fmov\\t%0, %1\n+ [ w , r ; neon_from_gp ] fmov\\t%0, %1\n+ [ w , m ; neon_load1_1reg ] ldr\\t%0, %1\n+ [ r , r ; mov_reg ] uxtw\\t%x0, %w1\n+ [ r , m ; load_4 ] ldr\\t%0, %1\n+ }\n+)\n+\n (define_insn \"*aarch64_combinez_be\"\n [(set (match_operand: 0 \"register_operand\")\n (vec_concat:\n@@ -4862,14 +4946,41 @@\n }\n )\n \n+(define_insn \"*aarch64_combinez_be\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+\t (match_operand:VSSUB32_I 2 \"aarch64_simd_or_scalar_imm_zero\")\n+ (match_operand:VSSUB32_I 1 \"nonimmediate_operand\")))]\n+ \"TARGET_FLOAT && BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 ; attrs: type ]\n+ [ r , r ; mov_reg ] uxt\\t%w0, %w1\n+ [ r , m ; load_4 ] ldr\\t%0, %1\n+ }\n+)\n+\n+(define_insn \"*aarch64_combinez_be\"\n+ [(set (match_operand: 0 \"register_operand\")\n+\t(vec_concat:\n+\t (match_operand:VS32_I_SUB64_F 2 \"aarch64_simd_or_scalar_imm_zero\")\n+ (match_operand:VS32_I_SUB64_F 1 \"nonimmediate_operand\")))]\n+ \"TARGET_FLOAT && BYTES_BIG_ENDIAN\"\n+ {@ [ cons: =0 , 1 ; attrs: type ]\n+ [ w , w ; neon_move ] fmov\\t%0, %1\n+ [ w , r ; neon_from_gp ] fmov\\t%0, %1\n+ [ w , m ; neon_load1_1reg ] ldr\\t%0, %1\n+ [ r , r ; mov_reg ] uxtw\\t%x0, %w1\n+ [ r , m ; load_4 ] ldr\\t%0, %1\n+ }\n+)\n+\n ;; Form a vector whose first half (in array order) comes from operand 1\n ;; and whose second half (in array order) comes from operand 2.\n ;; This operand order follows the RTL vec_concat operation.\n (define_expand \"@aarch64_vec_concat\"\n [(set (match_operand: 0 \"register_operand\")\n \t(vec_concat:\n-\t (match_operand:VDCSIF 1 \"general_operand\")\n-\t (match_operand:VDCSIF 2 \"general_operand\")))]\n+\t (match_operand:VDUP 1 \"general_operand\")\n+\t (match_operand:VDUP 2 \"general_operand\")))]\n \"TARGET_FLOAT\"\n {\n int lo = BYTES_BIG_ENDIAN ? 2 : 1;\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 5b1afa50ff8..f08cf032708 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -25502,19 +25502,24 @@ aarch64_expand_vector_init_fallback (rtx target, rtx vals)\n rtx v0 = XVECEXP (vals, 0, 0);\n bool all_same = true;\n \n- /* This is a special vec_init where N is not an element mode but a\n+ /* This is a special vec_init where N is either an element mode or a\n vector mode with half the elements of M. We expect to find two entries\n of mode N in VALS and we must put their concatentation into TARGET. */\n- if (XVECLEN (vals, 0) == 2 && VECTOR_MODE_P (GET_MODE (XVECEXP (vals, 0, 0))))\n+ if (XVECLEN (vals, 0) == 2 && GET_MODE (v0) != VOIDmode)\n {\n- machine_mode narrow_mode = GET_MODE (XVECEXP (vals, 0, 0));\n+ rtx v1 = XVECEXP (vals, 0, 1);\n+ machine_mode narrow_mode = GET_MODE (v0);\n gcc_assert (GET_MODE_INNER (narrow_mode) == inner_mode\n \t\t && known_eq (GET_MODE_SIZE (mode),\n \t\t\t 2 * GET_MODE_SIZE (narrow_mode)));\n- emit_insn (gen_aarch64_vec_concat (narrow_mode, target,\n-\t\t\t\t\t XVECEXP (vals, 0, 0),\n-\t\t\t\t\t XVECEXP (vals, 0, 1)));\n- return;\n+ if (rtx_equal_p (v0, v1))\n+ aarch64_emit_move (target,\n+\t\t\t gen_vec_duplicate (mode,\n+\t\t\t\t\t force_reg (narrow_mode, v0)));\n+ else\n+ emit_insn (gen_aarch64_vec_concat (narrow_mode, target,\n+\t\t\t\t\t v0, v1));\n+ return;\n }\n \n /* Count the number of variable elements to initialise. */\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 1fc67d95bd4..eafb8f45a1b 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -234,6 +234,21 @@\n ;; All sub-64-bit vector modes.\n (define_mode_iterator VSUB64 [V2QI V4QI V2HI V2HF V2BF])\n \n+;; All sub-64-bit scalar modes.\n+(define_mode_iterator SSUB64 [QI HI HF BF SI SF])\n+\n+;; All sub-64-bit modes.\n+(define_mode_iterator VSSUB64 [VSUB64 SSUB64])\n+\n+;; All sub-32-bit integer modes.\n+(define_mode_iterator VSSUB32_I [V2QI QI HI])\n+\n+;; All sub-64-bit floating-point modes.\n+(define_mode_iterator VSSUB64_F [V2HF V2BF HF BF])\n+\n+;; All 32-bit integer and sub-64-bit floating point modes.\n+(define_mode_iterator VS32_I_SUB64_F [V4QI V2HI VSSUB64_F])\n+\n ;; All Advanced SIMD modes suitable for moving, loading, and storing.\n (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI\n \t\t\t\tV4HF V8HF V4BF V8BF V2SF V4SF V2DF])\n@@ -1471,7 +1486,13 @@\n (define_mode_attr bitsize [(V8QI \"64\") (V16QI \"128\")\n \t\t\t (V4HI \"64\") (V8HI \"128\")\n \t\t\t (V2SI \"64\") (V4SI \"128\")\n-\t\t\t (V1DI \"64\") (V2DI \"128\")])\n+\t\t\t (V1DI \"64\") (V2DI \"128\")\n+\t\t\t (QI \"8\") (V2QI \"16\")\n+\t\t\t (V4QI \"32\") (HI \"16\")\n+\t\t\t (HF \"16\") (BF \"16\")\n+\t\t\t (SI \"32\") (SF \"32\")\n+\t\t\t (V2HI \"32\") (V2HF \"32\")\n+\t\t\t (V2BF \"32\")])\n \n ;; Map a floating point or integer mode to the appropriate register name prefix\n (define_mode_attr s [(HF \"h\") (SF \"s\") (DF \"d\") (SI \"s\") (DI \"d\")])\n@@ -1970,10 +1991,16 @@\n (define_mode_attr V1half [(V2DI \"v1di\") (V2DF \"v1df\")])\n \n ;; Double modes of vector modes.\n-(define_mode_attr VDBL [(V8QI \"V16QI\") (V4HI \"V8HI\")\n+(define_mode_attr VDBL [(V8QI \"V16QI\") (V4QI \"V8QI\")\n+\t\t\t(V2QI \"V4QI\") (V4HI \"V8HI\")\n \t\t\t(V4HF \"V8HF\") (V4BF \"V8BF\")\n+\t\t\t(V2BF \"V4BF\")\n \t\t\t(V2SI \"V4SI\") (V2SF \"V4SF\")\n+\t\t\t(V2HI \"V4HI\") (V2HF \"V4HF\")\n+\t\t\t(BF \"V2BF\")\n \t\t\t(SI \"V2SI\") (SF \"V2SF\")\n+\t\t\t(QI \"V2QI\")\n+\t\t\t(HI \"V2HI\") (HF \"V2HF\")\n \t\t\t(DI \"V2DI\") (DF \"V2DF\")])\n \n ;; Load/store pair mode.\n@@ -2201,6 +2228,14 @@\n \t\t\t (V2SI \"x\") (V2SF \"x\")\n \t\t\t (DI \"x\") (DF \"x\")])\n \n+(define_mode_attr single_dwx [(SI \"x\") (SF \"x\")\n+\t\t\t (V2QI \"w\") (V4QI \"x\")\n+\t\t\t (V2HI \"x\") (V2HF \"x\")\n+\t\t\t (HF \"w\") (QI \"w\")\n+\t\t\t (V2BF \"x\") (BF \"w\")\n+\t\t\t (HI \"w\")])\n+\n+\n ;; Whether a mode fits in S or D registers (i.e. \"s\" for 32-bit modes\n ;; and \"d\" for 64-bit modes).\n (define_mode_attr single_type [(SI \"s\") (SF \"s\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/gather_load_10.c b/gcc/testsuite/gcc.target/aarch64/sve/gather_load_10.c\nindex 2a07c0be866..75283d355ae 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/gather_load_10.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/gather_load_10.c\n@@ -11,7 +11,8 @@ foo (uint64_t *restrict x, uint64_t *restrict y, uint64_t *restrict index)\n x[i] += y[index[i]];\n }\n \n-/* { dg-final { scan-assembler-times {\\tldr\\td[0-9]+, \\[x[0-9]+, x[0-9]+, lsl #?3\\]} 2 } } */\n+/* { dg-final { scan-assembler-times {\\tldr\\td[0-9]+, \\[x[0-9]+, x[0-9]+, lsl #?3\\]} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tld1\\t{v[0-9]+\\.d}\\[1\\], \\[x[0-9]+\\]} 1 } } */\n /* { dg-final { scan-assembler-not {\\tshl\\tv[0-9]+\\.2d,} } } */\n /* { dg-final { scan-assembler-not {\\tumov\\t} } } */\n /* { dg-final { scan-assembler {\\tadd\\tv[0-9]+\\.2d,} } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\nindex 2bb2c04fa20..1fbb08c7566 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_1.c\n@@ -30,12 +30,12 @@ vec_slp_##TYPE (TYPE *restrict a, TYPE b, TYPE c, int n)\t\\\n TEST_ALL (VEC_PERM)\n \n /* We should use one DUP for each of the 8-, 16- and 32-bit types,\n- (for now, insert both elements with ins for _Float16). We should use two\n+ (and we now use fmov + ins for _Float16). We should use two\n DUPs for each of the three 64-bit types. */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.h, [hw]} 2 } } */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.s, [sw]} 3 } } */\n /* { dg-final { scan-assembler-times {\\tmov\\tz[0-9]+\\.d, [dx]} 9 } } */\n-/* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[0\\], v[0-9]+\\.h\\[0\\]} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tfmov\\th[0-9]+, h} 1 } } */\n /* { dg-final { scan-assembler-times {\\tins\\tv[0-9]+\\.h\\[1\\], v[0-9]+\\.h\\[0\\]} 1 } } */\n /* { dg-final { scan-assembler-times {\\tzip1\\tz[0-9]+\\.d, z[0-9]+\\.d, z[0-9]+\\.d\\n} 3 } } */\n /* { dg-final { scan-assembler-not {\\tzip2\\t} } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-18.c b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c\nindex feeb181a0b5..394537c80d8 100644\n--- a/gcc/testsuite/gcc.target/aarch64/vec-init-18.c\n+++ b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c\n@@ -15,7 +15,6 @@ int16x8_t foo2(int16_t x)\n return v;\n }\n \n-/* { dg-final { scan-assembler-times {\\tdup\\tv[0-9]+\\.4s, w[0-9]+} 2 } } */\n-/* { dg-final { scan-assembler-times {\\tmov\\tw[0-9]+, 65537} 1 } } */\n-/* { dg-final { scan-assembler-times {\\tbfi\\tw[0-9]+, w[0-9]+, 0, 16} 1 } } */\n-/* { dg-final { scan-assembler-times {\\tbfi\\tw[0-9]+, w[0-9]+, 16, 16} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tmov\\tw1, 1} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tdup\\tv0+\\.4s, w0} 2 } } */\n+/* { dg-final { scan-assembler-times {\\tbfi\\tw0, w1, 16, 16} 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-23.c b/gcc/testsuite/gcc.target/aarch64/vec-init-23.c\nindex 595470b29fb..217838ea55a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/vec-init-23.c\n+++ b/gcc/testsuite/gcc.target/aarch64/vec-init-23.c\n@@ -111,9 +111,8 @@ TEST_64(int, int64_t, s)\n \n /*\n ** test_int8_5:\n-**\tmov\tw1, 0\n-**\tbfi\tw1, w0, 0, 8\n-**\tdup\tv0\\.8h, w1\n+**\tuxtb\tw0, w0\n+**\tdup\tv0\\.8h, w0\n **\tret\n */\n \n@@ -217,7 +216,7 @@ TEST_64(int, int64_t, s)\n ** test_float16_2:\n **\tfcvt\th1, s1\n **\tfcvt\th0, s0\n-**\tins\tv0\\.h\\[1\\], v1\\.h\\[0\\]\n+**\tuzp1\tv0\\.4h, v0\\.4h, v1\\.4h\n **\tdup\tv0\\.4s, v0\\.s\\[0\\]\n **\tret\n */\n@@ -227,55 +226,51 @@ TEST_64(int, int64_t, s)\n **\tuzp1\tv2\\.2s, v0\\.2s, v2\\.2s\n **\tuzp1\tv3\\.2s, v1\\.2s, v3\\.2s\n **\tzip1\tv3\\.4s, v2\\.4s, v3\\.4s\n-**\tfcvtn\tv0\\.4h, v3\\.4s\n-**\tuzp1\tv0\\.2d, v0\\.2d, v0\\.2d\n+**\tfcvtn\tv3\\.4h, v3\\.4s\n+**\tdup\tv0\\.2d, v3\\.d\\[0\\]\n **\tret\n */\n \n /*\n ** test_float16_4:\n **\tfcvt\th0, s0\n-**\tmovi\tv31\\.2d, #0\n-**\tins\tv31\\.h\\[0\\], v0\\.h\\[0\\]\n-**\tdup\tv0\\.4s, v31\\.s\\[0\\]\n+**\tfmov\th0, h0\n+**\tdup\tv0\\.4s, v0\\.s\\[0\\]\n **\tret\n */\n \n /*\n ** test_float16_5:\n+**\tmovi\tv31\\.4h, #0\n **\tfcvt\th0, s0\n-**\tmovi\tv31\\.2d, #0\n-**\tins\tv31\\.h\\[1\\], v0\\.h\\[0\\]\n-**\tdup\tv0\\.4s, v31\\.s\\[0\\]\n+**\tuzp1\tv0\\.4h, v31\\.4h, v0\\.4h\n+**\tdup\tv0\\.4s, v0\\.s\\[0\\]\n **\tret\n */\n \n /*\n ** test_float16_6:\n-**\tfcvt\th1, s1\n **\tfcvt\th0, s0\n-**\tmovi\tv31\\.2d, #0\n-**\tmov\tw0, 1006648320\n-**\tumov\tw1, v1\\.h\\[0\\]\n-**\tins\tv31\\.h\\[0\\], v0\\.h\\[0\\]\n-**\tbfi\tw0, w1, 0, 16\n-**\tdup\tv31\\.2s, v31\\.s\\[0\\]\n-**\tdup\tv0\\.2s, w0\n-**\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n+**\tfcvt\th1, s1\n+**\tfmov\th31, 1.0e\\+0\n+**\tfmov\th0, h0\n+**\tuzp1\tv1\\.4h, v1\\.4h, v31\\.4h\n+**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n+**\tdup\tv1\\.2s, v1\\.s\\[0\\]\n+**\tzip1\tv0\\.8h, v0\\.8h, v1\\.8h\n **\tret\n */\n \n /*\n ** test_float16_7:\n-**\tfcvt\th1, s1\n **\tfcvt\th0, s0\n-**\tmovi\tv31\\.2d, #0\n-**\tmov\tw0, 1006648320\n-**\tumov\tw1, v1\\.h\\[0\\]\n-**\tins\tv31\\.h\\[1\\], v0\\.h\\[0\\]\n-**\tbfi\tw0, w1, 16, 16\n+**\tmovi\tv31\\.4h, #0\n+**\tfcvt\th1, s1\n+**\tuzp1\tv31\\.4h, v31\\.4h, v0\\.4h\n+**\tfmov\th0, 1.0e\\+0\n+**\tuzp1\tv0\\.4h, v0\\.4h, v1\\.4h\n **\tdup\tv31\\.2s, v31\\.s\\[0\\]\n-**\tdup\tv0\\.2s, w0\n+**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n **\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n **\tret\n */\n@@ -285,7 +280,7 @@ TEST_64(int, int64_t, s)\n **\tfcvt\th1, s1\n **\tfcvt\th0, s0\n **\tmovi\tv31\\.2s, 0x3c, lsl 24\n-**\tins\tv0\\.h\\[1\\], v1\\.h\\[0\\]\n+**\tuzp1\tv0\\.4h, v0\\.4h, v1\\.4h\n **\tdup\tv0\\.2s, v0\\.s\\[0\\]\n **\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n **\tret\n@@ -316,9 +311,8 @@ TEST_64(int, int64_t, s)\n \n /*\n ** test_int16_4:\n-**\tmov\tw1, 0\n-**\tbfi\tw1, w0, 0, 16\n-**\tdup\tv0\\.4s, w1\n+**\tuxth\tw0, w0\n+**\tdup\tv0\\.4s, w0\n **\tret\n */\n \n@@ -332,12 +326,11 @@ TEST_64(int, int64_t, s)\n \n /*\n ** test_int16_6:\n-**\tmov\tw2, 0\n-**\tbfi\tw2, w0, 0, 16\n-**\tmov\tw0, 65537\n-**\tbfi\tw0, w1, 0, 16\n-**\tdup\tv31\\.2s, w2\n-**\tdup\tv0\\.2s, w0\n+**\tuxth\tw0, w0\n+**\tdup\tv31\\.2s, w0\n+**\tmov\tw0, 1\n+**\tbfi\tw1, w0, 16, 16\n+**\tdup\tv0\\.2s, w1\n **\tzip1\tv0\\.8h, v31\\.8h, v0\\.8h\n **\tret\n */\n@@ -378,17 +371,16 @@ TEST_64(int, int64_t, s)\n \n /*\n ** test_float32_3:\n-**\tmovi\tv31\\.2s, 0\n-**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n-**\tzip1\tv0\\.4s, v0\\.4s, v31\\.4s\n+**\tfmov\ts0, s0\n+**\tdup\tv0\\.2d, v0\\.d\\[0\\]\n **\tret\n */\n \n /*\n ** test_float32_4:\n-**\tmovi\tv31\\.2s, 0\n-**\tdup\tv0\\.2s, v0\\.s\\[0\\]\n-**\tzip1\tv0\\.4s, v31\\.4s, v0\\.4s\n+**\tmovi\tv31\\.2s, #0\n+**\tuzp1\tv0\\.2s, v31\\.2s, v0\\.2s\n+**\tdup\tv0\\.2d, v0\\.d\\[0\\]\n **\tret\n */\n \n@@ -408,9 +400,8 @@ TEST_64(int, int64_t, s)\n \n /*\n ** test_int32_3:\n-**\tdup\tv31\\.2s, w0\n-**\tmovi\tv0\\.2s, 0\n-**\tzip1\tv0\\.4s, v31\\.4s, v0\\.4s\n+**\tfmov\ts0, w0\n+**\tdup\tv0\\.2d, v0\\.d\\[0\\]\n **\tret\n */\n \ndiff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c\nindex 587b7ec0e3b..98f75336d86 100644\n--- a/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c\n+++ b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c\n@@ -47,8 +47,8 @@ int32x4_t f_s32(int32_t x)\n /*\n ** f_s64:\n **\tfmov\td0, x0\n-**\tmov\t(x[0-9]+), 1\n-**\tins\tv0\\.d\\[1\\], \\1\n+**\tmov\tx0, 1\n+**\tins\tv0\\.d\\[1\\], x0\n **\tret\n */\n \n","prefixes":["3/4"]}