{"id":2228030,"url":"http://patchwork.ozlabs.org/api/patches/2228030/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424230103.1579600-3-pierrick.bouvier@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424230103.1579600-3-pierrick.bouvier@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-24T23:01:03","name":"[2/2] target/arm: define stub library","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ae00b3086c2f67f48af3cafe27abd5dd8ab95b7e","submitter":{"id":93152,"url":"http://patchwork.ozlabs.org/api/people/93152/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424230103.1579600-3-pierrick.bouvier@oss.qualcomm.com/mbox/","series":[{"id":501408,"url":"http://patchwork.ozlabs.org/api/series/501408/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501408","date":"2026-04-24T23:01:01","name":"single-binary: add stubs for target/","version":1,"mbox":"http://patchwork.ozlabs.org/series/501408/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2228030/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2228030/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=I3vMco1/;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=TDevHutI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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With this, we are able to eliminate symbol conflicts when\nlinking arm and aarch64 targets, and get one step closer to having a\nsingle-binary.\n\nSigned-off-by: Pierrick Bouvier \n---\n target/arm/meson.build | 8 +++-----\n target/arm/tcg/meson.build | 2 +-\n 2 files changed, 4 insertions(+), 6 deletions(-)","diff":"diff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 192ac7c31ee..4723f9f170a 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -2,6 +2,7 @@ arm_ss = ss.source_set()\n arm_common_ss = ss.source_set()\n arm_common_system_ss = ss.source_set()\n arm_system_ss = ss.source_set()\n+arm_stubs_ss = ss.source_set()\n arm_user_ss = ss.source_set()\n \n arm_common_system_ss.add(files('gdbstub.c'))\n@@ -23,9 +24,7 @@ arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'))\n arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))\n \n arm_user_ss.add(files('cpu.c'))\n-arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files(\n- 'cpu32-stubs.c',\n-))\n+arm_stubs_ss.add(files('cpu32-stubs.c'))\n arm_user_ss.add(files(\n 'cpregs-gcs.c',\n 'cpregs-pmu.c',\n@@ -39,8 +38,6 @@ arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',\n \t\t if_true: files('common-semi-target.c'))\n \n arm_common_system_ss.add(files('cpu.c'))\n-arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files(\n- 'cpu32-stubs.c'))\n arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))\n arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',\n \t\t if_true: files('common-semi-target.c'))\n@@ -73,3 +70,4 @@ target_system_arch += {'arm': arm_system_ss}\n target_user_arch += {'arm': arm_user_ss}\n target_common_arch += {'arm': arm_common_ss}\n target_common_system_arch += {'arm': arm_common_system_ss}\n+target_stubs_arch += {'arm': arm_stubs_ss}\ndiff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build\nindex 506f031f1aa..80ec9f5b0f8 100644\n--- a/target/arm/tcg/meson.build\n+++ b/target/arm/tcg/meson.build\n@@ -28,7 +28,7 @@ translate32_d = [\n ]\n \n arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)\n-arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c'))\n+arm_stubs_ss.add(files('stubs32.c'))\n \n arm_ss.add(files(\n 'cpu32.c',\n","prefixes":["2/2"]}