{"id":2227823,"url":"http://patchwork.ozlabs.org/api/patches/2227823/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424102800.24022-4-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424102800.24022-4-frank.chang@sifive.com>","list_archive_url":null,"date":"2026-04-24T10:27:59","name":"[3/4] target/riscv: Support raising misaligned exceptions for vector loads/stores","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d3e946b3631cc2979c0efcded36d305c18a08cef","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424102800.24022-4-frank.chang@sifive.com/mbox/","series":[{"id":501338,"url":"http://patchwork.ozlabs.org/api/series/501338/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501338","date":"2026-04-24T10:27:56","name":"Support the true Zicclsm extension","version":1,"mbox":"http://patchwork.ozlabs.org/series/501338/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227823/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227823/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=mh6thZfy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x530.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nWhen the Zicclsm extension is not enabled, raise misaligned load/store\nexceptions for misaligned accesses from vector load/store instructions.\n\nWe will skip the host fast-path and fall back to the slow TLB-path to\nraise misaligned load/store exceptions for the misaligned accesses when\nZicclsm extension is disabled.\n\nSigned-off-by: Frank Chang \nReviewed-by: Max Chou \n---\n target/riscv/insn_trans/trans_rvv.c.inc | 3 +-\n target/riscv/vector_helper.c | 82 ++++++++++++++++++++-----\n 2 files changed, 69 insertions(+), 16 deletions(-)","diff":"diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 5b72926b3c1..c8f106c0bab 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -1190,9 +1190,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,\n * Update vstart with the number of processed elements.\n * Use the helper function if either:\n * - vstart is not 0.\n+ * - Zicclsm is disabled, so misaligned accesses could trap.\n */\n \n- bool use_helper_fn = !s->vstart_eq_zero;\n+ bool use_helper_fn = !s->vstart_eq_zero || !s->cfg_ptr->ext_zicclsm;\n \n if (!use_helper_fn) {\n uint32_t size = s->cfg_ptr->vlenb * nf;\ndiff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\nindex 538168efc9b..f74f73f046d 100644\n--- a/target/riscv/vector_helper.c\n+++ b/target/riscv/vector_helper.c\n@@ -200,20 +200,51 @@ static inline void vext_set_elem_mask(void *v0, int index,\n ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);\n }\n \n+static MemOpIdx vext_make_memop_idx(CPURISCVState *env, size_t size)\n+{\n+ int mmu_idx = riscv_env_mmu_index(env, false);\n+ MemOp memop;\n+\n+ switch (size) {\n+ case 1:\n+ memop = MO_UB;\n+ break;\n+ case 2:\n+ memop = MO_LEUW;\n+ break;\n+ case 4:\n+ memop = MO_LEUL;\n+ break;\n+ case 8:\n+ memop = MO_LEUQ;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ if (!riscv_cpu_cfg(env)->ext_zicclsm) {\n+ memop |= MO_ALIGN;\n+ }\n+\n+ return make_memop_idx(memop, mmu_idx);\n+}\n+\n /* elements operations for load and store */\n typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env, abi_ptr addr,\n uint32_t idx, void *vd, uintptr_t retaddr);\n typedef void vext_ldst_elem_fn_host(void *vd, uint32_t idx, void *host);\n \n-#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \\\n+#define GEN_VEXT_TLB_LD_ELEM(NAME, ETYPE, H, LDSUF) \\\n static inline QEMU_ALWAYS_INLINE \\\n void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \\\n uint32_t idx, void *vd, uintptr_t retaddr) \\\n { \\\n ETYPE *cur = ((ETYPE *)vd + H(idx)); \\\n- *cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \\\n+ MemOpIdx oi = vext_make_memop_idx(env, sizeof(ETYPE)); \\\n+ *cur = cpu_##LDSUF##_mmu(env, addr, oi, retaddr); \\\n } \\\n- \\\n+\n+#define GEN_VEXT_HOST_LD_ELEM(NAME, ETYPE, H, LDSUF) \\\n static inline QEMU_ALWAYS_INLINE \\\n void NAME##_host(void *vd, uint32_t idx, void *host) \\\n { \\\n@@ -221,20 +252,27 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \\\n *cur = (ETYPE)LDSUF##_p(host); \\\n }\n \n-GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub)\n-GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le)\n-GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le)\n-GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le)\n+GEN_VEXT_TLB_LD_ELEM(lde_b, uint8_t, H1, ldb)\n+GEN_VEXT_TLB_LD_ELEM(lde_h, uint16_t, H2, ldw)\n+GEN_VEXT_TLB_LD_ELEM(lde_w, uint32_t, H4, ldl)\n+GEN_VEXT_TLB_LD_ELEM(lde_d, uint64_t, H8, ldq)\n+\n+GEN_VEXT_HOST_LD_ELEM(lde_b, uint8_t, H1, ldub)\n+GEN_VEXT_HOST_LD_ELEM(lde_h, uint16_t, H2, lduw_le)\n+GEN_VEXT_HOST_LD_ELEM(lde_w, uint32_t, H4, ldl_le)\n+GEN_VEXT_HOST_LD_ELEM(lde_d, uint64_t, H8, ldq_le)\n \n-#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \\\n+#define GEN_VEXT_TLB_ST_ELEM(NAME, ETYPE, H, STSUF) \\\n static inline QEMU_ALWAYS_INLINE \\\n void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \\\n uint32_t idx, void *vd, uintptr_t retaddr) \\\n { \\\n ETYPE data = *((ETYPE *)vd + H(idx)); \\\n- cpu_##STSUF##_data_ra(env, addr, data, retaddr); \\\n+ MemOpIdx oi = vext_make_memop_idx(env, sizeof(ETYPE)); \\\n+ cpu_##STSUF##_mmu(env, addr, data, oi, retaddr); \\\n } \\\n- \\\n+\n+#define GEN_VEXT_HOST_ST_ELEM(NAME, ETYPE, H, STSUF) \\\n static inline QEMU_ALWAYS_INLINE \\\n void NAME##_host(void *vd, uint32_t idx, void *host) \\\n { \\\n@@ -242,10 +280,15 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \\\n STSUF##_p(host, data); \\\n }\n \n-GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb)\n-GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le)\n-GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le)\n-GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le)\n+GEN_VEXT_TLB_ST_ELEM(ste_b, uint8_t, H1, stb)\n+GEN_VEXT_TLB_ST_ELEM(ste_h, uint16_t, H2, stw)\n+GEN_VEXT_TLB_ST_ELEM(ste_w, uint32_t, H4, stl)\n+GEN_VEXT_TLB_ST_ELEM(ste_d, uint64_t, H8, stq)\n+\n+GEN_VEXT_HOST_ST_ELEM(ste_b, uint8_t, H1, stb)\n+GEN_VEXT_HOST_ST_ELEM(ste_h, uint16_t, H2, stw_le)\n+GEN_VEXT_HOST_ST_ELEM(ste_w, uint32_t, H4, stl_le)\n+GEN_VEXT_HOST_ST_ELEM(ste_d, uint64_t, H8, stq_le)\n \n static inline QEMU_ALWAYS_INLINE void\n vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,\n@@ -393,7 +436,16 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target_ulong addr,\n probe_pages(env, addr, size, ra, access_type, mmu_index, &host, &flags,\n true);\n \n- if (flags == 0) {\n+ bool misaligned = addr & (esz - 1);\n+\n+ /*\n+ * Allow the host fast-pash when:\n+ * 1. Page permission/pmp/watchpoint are checked and we have a contigous\n+ * host mapping.\n+ * 2. Zicclsm is enabled or load/store is not a misaligned access.\n+ * Otherwise, we will fall back to the slow TLB-path.\n+ */\n+ if (flags == 0 && (riscv_cpu_cfg(env)->ext_zicclsm || !misaligned)) {\n if (nf == 1) {\n vext_continuous_ldst_host(env, ldst_host, vd, evl, env->vstart,\n host, esz, is_load);\n","prefixes":["3/4"]}