{"id":2227812,"url":"http://patchwork.ozlabs.org/api/patches/2227812/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260424094913.522123-4-mahesh.vaidya@altera.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424094913.522123-4-mahesh.vaidya@altera.com>","list_archive_url":null,"date":"2026-04-24T09:49:13","name":"[3/3] PCI: altera: add Agilex 5 support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"aa046515893cefae1d4cc3661464b6fd47ea21f4","submitter":{"id":92067,"url":"http://patchwork.ozlabs.org/api/people/92067/?format=json","name":"Mahesh Vaidya","email":"mahesh.vaidya@altera.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260424094913.522123-4-mahesh.vaidya@altera.com/mbox/","series":[{"id":501332,"url":"http://patchwork.ozlabs.org/api/series/501332/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501332","date":"2026-04-24T09:49:10","name":"PCI: altera: Add Agilex 5 PCIe Root Port support","version":1,"mbox":"http://patchwork.ozlabs.org/series/501332/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227812/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227812/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=OmDvUrYW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53131-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=altera.com header.i=@altera.com\n header.b=\"OmDvUrYW\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.61.59","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=altera.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=altera.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=altera.com;"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g27XS2NJWz1yD5\n\tfor ; Fri, 24 Apr 2026 19:51:52 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 76191301E6E8\n\tfor ; Fri, 24 Apr 2026 09:49:53 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E555B3090C6;\n\tFri, 24 Apr 2026 09:49:52 +0000 (UTC)","from DM1PR04CU001.outbound.protection.outlook.com\n (mail-centralusazon11010059.outbound.protection.outlook.com [52.101.61.59])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E1912E7F2C;\n\tFri, 24 Apr 2026 09:49:50 +0000 (UTC)","from SA1PR03MB6498.namprd03.prod.outlook.com (2603:10b6:806:1c5::7)\n by DM4PR03MB5982.namprd03.prod.outlook.com (2603:10b6:5:389::21) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Fri, 24 Apr\n 2026 09:49:49 +0000","from SA1PR03MB6498.namprd03.prod.outlook.com\n ([fe80::feea:da58:faeb:9ebc]) by SA1PR03MB6498.namprd03.prod.outlook.com\n ([fe80::feea:da58:faeb:9ebc%4]) with mapi id 15.20.9846.021; Fri, 24 Apr 2026\n 09:49:49 +0000"],"ARC-Seal":["i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777024192; cv=fail;\n b=j90KP0z5wtfnFPr8Bs75OQSaUJbTGm6gJYzNLaFCalp6kNOQM33HGqJ1TOmD1SdYYZdhMsgcs+N2ycahxfovluszXLjqUwneEVI+IeGDNZt6dv1YB/vx8Rndd3R/OHNFTPs2UjzQ7zJ21B8ZEW+/yByWIPaueyQSQeuShFKuP6Q=","i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=ylWc+U7DWbcmvooQEyWrOjWkbfx7kx86rh9RwnpqyzvG/V41Awgb7n7n6mczQ5YAcZUjfwFcWK7FP4aXqQpOlqpxEflgGo6M3mQHibs7zRpNFh0Z8OCV21kwM9dJYpDfJeE53CbellnugS28pkCHTaK49Sr2mGoNdR5o0CGVLH+vg60DXoBx92nazZKKwDoniIwpNe9g0w5qr8Ame19FSHWenjZkEZbVdxehzqUGzeqxfu7cuHa6fGGu6kSDFxSGGRQIaznOEl+UViPjZSVUpEFQqk+6Km+Of4xXZEJIxd3pXvYWbghbMGhcEsQGFZG+DTJ+iItU6A/g+RQTG7DrOQ=="],"ARC-Message-Signature":["i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777024192; c=relaxed/simple;\n\tbh=Ng/s2NlM42ldA0DZEhSS1Of6ltzQ5H1taeBTpi17PSc=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t Content-Type:MIME-Version;\n b=udh58wSPyW7UkiyIhbF5ilD2R15sidsnGW9OknTKAdfmS4wO71b+XH0WSsyNZ45D633PztF5r+vUsyd6+p23iCYHdEEFFro9XbaO+gA1Nvk2NkXHOT0X6FYxyFQl/llebRZeOmgDyqTT4kKcs+vvlXy3phSJfRoJPys/AQbYipU=","i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=oYcZPuJUiUMn8O5FaaFRMfVOYqdut+Lo4+vloT2MdK4=;\n b=FpPsjmFOIabSne4jjcvh8ow+xAEEZymHkUDjuyeG41QPm9SlBQ8kiYYN/mAFRIn+GPjvdsgNu44JaQesW1Vbplj7EN8ph1GfjthXTipiDtRaUTzcppmb17ixkpDlBHW0fUWXiqq0pFiQ8WRAhYjcpsWhTa6NPfvYAQwf0Tscn1iFeRxPXmkKd+BhpeUvdhySY/rupLkW12K3wGxs+m804c4o8vou8ODsfwbPhdqmrg2SVRM+aaEY3HmKx8xIP5ScI6DexavT7ybu/9jJsedkjM6YR0uaRjsHd2INAjAyXARCZ9qFVQhQNfazlhKdMoIYB76n89WkQAqSt4V42RakqA=="],"ARC-Authentication-Results":["i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=altera.com;\n spf=pass smtp.mailfrom=altera.com;\n dkim=pass (2048-bit key) header.d=altera.com header.i=@altera.com\n header.b=OmDvUrYW; arc=fail smtp.client-ip=52.101.61.59","i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=altera.com; dmarc=pass action=none header.from=altera.com;\n dkim=pass header.d=altera.com; arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=oYcZPuJUiUMn8O5FaaFRMfVOYqdut+Lo4+vloT2MdK4=;\n b=OmDvUrYWf7REB1f0sea2/Pgui4eYd5YfDGZMsa2WFLI0DN9+jPiZUItDjfKMpeLRVo3RHBg9IHMxjloB0PYebxt/jPtDO5pVBxxV5ZMdOMqX/4WzLh4JNQsZ2uGsVQhDY3SAYA/WmbsemlPkfH3kdc9gWuJOSjvaUobNzT38qDgW94JzNtQKFl3hDlLBZBn+8zHtV7UYtAGhFXf90zA7XMUYv0D25LPrSBQtAuxTS0o222KkwwfIfl3CJVUYBHFtZfy59qlcno9GhW4Zu8XKPVAFGzOo/PrUXSMgOriPkkJKLVjdheOVA9TkJ9h7/cmAHzIPTrk4XZnjwxUfAe6xdQ==","From":"Mahesh Vaidya ","To":"joyce.ooi@intel.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org","Cc":"linux-pci@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tsubhransu.sekhar.prusty@altera.com,\n\tdinguyen@kernel.org,\n\tMahesh Vaidya ","Subject":"[PATCH 3/3] PCI: altera: add Agilex 5 support","Date":"Fri, 24 Apr 2026 02:49:13 -0700","Message-Id":"<20260424094913.522123-4-mahesh.vaidya@altera.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260424094913.522123-1-mahesh.vaidya@altera.com>","References":"<20260424094913.522123-1-mahesh.vaidya@altera.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"SI2PR02CA0014.apcprd02.prod.outlook.com\n (2603:1096:4:194::19) To SA1PR03MB6498.namprd03.prod.outlook.com\n (2603:10b6:806:1c5::7)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SA1PR03MB6498:EE_|DM4PR03MB5982:EE_","X-MS-Office365-Filtering-Correlation-Id":"495f5240-2992-4b9a-66ee-08dea1e6d319","X-MS-Exchange-AtpMessageProperties":"SA","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|376014|7416014|366016|1800799024|55112099003|56012099003|18002099003|22082099003;","X-Microsoft-Antispam-Message-Info":"\n\tzKt4Cn7eSxBSVmAH3MHxbIAh2kplcSZEo1cVY/IPeW1O5khTiCaxI6Oq5FLplALqBs+T3IHW5poIcTGAfGbR4/ZFGmy5gkK76PNtGPDxCgBiclc4uOZwC4v3wH6LlD9NaZhwT2Ap1j2FgmQlYNahaHJ2Alinzc2dLFMTpiSv48WT+2Io1qbruJOW3TknhyN6OmY87Qsmlucu6X/utZf0i5MTnWkAZKIMKdbOdBTuDcJA6Drlf/CykNdwugtiLPFvzhnfNO4bZYriGoeoSyeL2sRys8U4+U6HBO9TRe4FEucruvmwC/vtUe9KJXudRfuNUk0s5JrZiD/9L1zY825oVEHNAsVAJDIwiZN/RpLFcjEgEc74Vy2lCV8QuCUID3Ob6gfhkyrybs6YbvEkKBIW1iM4Rh6byA3D7Zl/56BsHRr0xGdynySjXTZmCMtDhO974vdVgHjtl8kNzXp6/Mlm9ZFno5QT3XEya8GEF+2BYS13sozhiCrqp+fK5+7nUy5xirUoW/td0WGgDZ67TiLPSh+SXfkC3l2eGlzaedR03K7BxEE7OourCHofU5LIOkKyBNvkgBtSKOMMJercOgeF7grF8HzpDuY4xmfSQESDAz10RvJmFcQ/kUeNVzvVjoIyuoBwRr88/+jWajOW3yrxotGTEfhNXRvDb0ljq+ACMWCBpIMyVAGnspHWy2h/0HvEHORIGf5eFj+ZpDVMExNNPNujdvvsA69t4ONqil+I9xE=","X-Forefront-Antispam-Report":"\n\tCIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SA1PR03MB6498.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(1800799024)(55112099003)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n xPqBxTHhyB2gn5HEdQkikKR7cVos82ul/CTAZvajxKg/KwMKEM8t53Bcvx8+bzQBazUokWuJQTdpjIsfav4jeiK+cXQFIOqETv4wWvoWbX91I1Ie7RBrNzmtY7rA9CdjCAXYZSHNvcl4I1HCmuWyqrJxEKKK6vdUh3gvhBR4MGKvPfrst9B1Fp/PNNkEZ82g7Gr6yyqcUjDG2KvRXj7s+iWfdVWK8sRMa2H5icFEkvrv8fmOWCeUPhMX9U8gjpBDDhnEoOQmyh/J6BWWoAN9LW8LwzK76jxPpLaH/KpOJyIrHbCgJm7YA9wdXcqDlna6cLfPj4g5hvXse0kvSnKgvdrQZH3JMOdz/v1VDoBbkGAuad049xOWaGcKL0q6tg3E7SA/a4yVnN8gizpY45r/WebcvTwt8HyVz8YSrfXuDrLCEYqaEvnBg0146oSJH/U2N+n8b3qfwNkce9uhwF4XB2WfK6+C3cCdYWk6uJ4Ksnz8mymE7Zc9Lj2pWUAh2EoX2RlHz/lRxJ08wXeeeWp86crqNfOXnXqSx934wTPxfUjL1z2LKN2kaW+8GnfO1UReT/IxP/S9IH3X1FLWI6o071JVXR4bRlLVKbSe5VM8HvnnEb5IdmKl8dnXhUPYTfHzffWClhTBJj3x7EoTehTm20238K15nYE5On0p785Ima/XAyZ3vA7dkHejpFUTBnWugPhdA22vL1cJqNpO5gYtvYnQCBanZSjALIs5h8uo5IvucpQXGy7PihyFIPdCismwAhlxV2YuLXCsbiYhrdDdKKqTKXnl544eWWmjYnKBV2lDJ8A3coVrrYAgbX5bgq2bDqo0xn66XwmOVLGQufYlMVphaRnPuOcPEDZsZQ8arhcpHQgz/lVB/DOXL5w2eeGraltAEVoemQ4VVcup1HYCr2XOgvvFZ4t7G4DQgQ/+B8P6Z+yEgHynyFkxXTr03stUELotPQj6hpagFe0l+tojkh8MwHrVHQLidyws5kXwe3rUp7gao9EwgRZejJ65oSxJTsjYZMVbf+ZIv8e5K76j5hCqc8WatVVACrIREBGlBwKGWfnuamHdSf6DrivSxTs9yzD326fqy3afCOgjeMiBhXnp0eYuyh6ngv5dXbcnKSvoTS+WViNKD/z5MQmyJ/XijyeVDn+FlFq3YcXINfjbNnh7l3FT+DvFFKas9ipDAzZRDke7kqNylIUfUIm84O98RgfLBqTTsW8S67p53AUeTns2Ho0uacb0H3QF8R+bzKxgRxu4kEcJj9BIWxINPH1zPQ0eNv0KMo/qpUgzjCIkSMWZ3s9wj5v9AdoQ+bX3feaTUxjZQASU625TOKaHJhUMTkcLforxGUwKO8nCflpSpvOnYbDcDWX8BaH4vFL2bOGQIQB0GNgILkaoN49SbECmDJng+Nq5oxIHOyIqyLsEyZR9GMdiiYIrAQz/GIaRUqc5i7bZf0ZWfnBvR8HUnRxFgmnBola5jCHYcxn8693V20U9FAuEE2Mhx2el8euwYIx5Wrsj7h2DVp6pkzDOlankuANfQeKSKhdme67QoILDa0NpCbGQWw2bOTKruwt28djZ8gC1D8GY8NwuGgrDKKdlq2gjWe5kBDHPVb9A/z82550kc8AdkWHn4W2R9A1dKaD4dnYgsq4ZFGGMDBkXBfx4N9FTlNmPCptPnB25IcFXXIGzI0UCGtwr6mOuIMST2/Z/Vxn8S+y1fUmntLwF49eFWvO1kUu+Dm7q72nZZA6uXg==","X-OriginatorOrg":"altera.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 495f5240-2992-4b9a-66ee-08dea1e6d319","X-MS-Exchange-CrossTenant-AuthSource":"SA1PR03MB6498.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"24 Apr 2026 09:49:49.2271\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"fbd72e03-d4a5-4110-adce-614d51f2077a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n EyjYr1LpDPtWXAO/Jn0tYur7U+uTCLPjSgbBQR7s7N1FwXZvoZ+nV72sk/Ks3YhDlJu7mGI1UBzWc7DlS8MoLOxCpLF70KSdJ9cm+3pXYSE=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM4PR03MB5982"},"content":"Add PCIe root port controller support for the Agilex 5 (V4) family\nof SoC FPGAs.\n\nThe Agilex 5 PCIe Hard IP reuses the same config-space access path\nas Agilex 7 (V3). Root port and endpoint configuration reads/writes\nuse direct MMIO to the HIP and CRA regions.\n\nThe difference is in the HIP port-level registers (IRQ status and IRQ\nenable). On V3 these are directly mapped through the HIP MMIO window.\nOn V4 these registers are only reachable through an indirect access\nmailbox (CFG REG IA CTRL) in the PCIe Subsystem AXI-Lite interface,\ndocumented in the GTS AXI Streaming IP for PCIe User Guide.\n\nThis adds:\n- ALTERA_PCIE_V4 version and platform data\n- Indirect register read/write helpers using readl_poll_timeout_atomic\n- Chained IRQ handler (aglx5_isr) for the V4 interrupt path\n- OF match for \"altr,pcie-root-port-4.0\"\n\nCo-developed-by: Matthew Gerlach \nSigned-off-by: Matthew Gerlach \nCo-developed-by: Peter Colberg \nSigned-off-by: Peter Colberg \nSigned-off-by: Mahesh Vaidya \n---\n drivers/pci/controller/pcie-altera.c | 156 ++++++++++++++++++++++++++-\n 1 file changed, 155 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c\nindex 025ba74d1ee2..db8149d84c96 100644\n--- a/drivers/pci/controller/pcie-altera.c\n+++ b/drivers/pci/controller/pcie-altera.c\n@@ -12,6 +12,8 @@\n #include \n #include \n #include \n+#include \n+#include \n #include \n #include \n #include \n@@ -93,16 +95,36 @@\n #define AGLX_CFG_TARGET_LOCAL_2000\t2\n #define AGLX_CFG_TARGET_LOCAL_3000\t3\n \n+/* PCIe subsystem indirect register access */\n+#define PCIE_SS_IA_CTL\t\t\t0xc8 /* control register */\n+#define PCIE_SS_IA_FN_NUM\t\t0xcc /* function number */\n+#define PCIE_SS_IA_FN_WRDATA\t\t0xd0 /* write data */\n+#define PCIE_SS_IA_FN_RDDATA\t\t0xd4 /* read data */\n+\n+/* PCIE_SS_IA_CTL bitfields */\n+#define PCIE_SS_IA_CTL_INITIATE\t\tBIT(0)\n+#define PCIE_SS_IA_CTL_WRITE\t\tBIT(1)\n+#define PCIE_SS_IA_CTL_BYTE_EN\t\tGENMASK(5, 2)\n+#define PCIE_SS_IA_CTL_ADDR\t\tGENMASK(31, 6)\n+\n+/* PCIE_SS_IA_FN_NUM function types */\n+#define PCIE_SS_IA_FN_TYPE_HIP\t\t2\n+\n+#define AGLX5_INDIRECT_SLEEP_US\t\t1\n+#define AGLX5_INDIRECT_TIMEOUT_US\t1000\n+\n enum altera_pcie_version {\n \tALTERA_PCIE_V1 = 0,\n \tALTERA_PCIE_V2,\n \tALTERA_PCIE_V3,\n+\tALTERA_PCIE_V4,\n };\n \n struct altera_pcie {\n \tstruct platform_device\t*pdev;\n \tvoid __iomem\t\t*cra_base;\n \tvoid __iomem\t\t*hip_base;\n+\tvoid __iomem\t\t*controller_base;\n \tint\t\t\tirq;\n \tu8\t\t\troot_bus_nr;\n \tstruct irq_domain\t*irq_domain;\n@@ -849,6 +871,98 @@ static void aglx_isr(struct irq_desc *desc)\n \tchained_irq_exit(chip, desc);\n }\n \n+/*\n+ * Indirect register access to HIP registers via the PCIe Subsystem\n+ * AXI-Lite mailbox, documented in the GTS AXI Streaming IP for PCIe\n+ * User Guide. Called from chained IRQ handler (hardirq) and probe\n+ * (before handler is installed), so no locking is required.\n+ */\n+static int aglx5_indirect_readl(const struct altera_pcie *pcie,\n+\t\t\t\tunsigned int addr, unsigned int *val)\n+{\n+\tunsigned int ctl;\n+\tint ret;\n+\n+\twritel(PCIE_SS_IA_FN_TYPE_HIP,\n+\t pcie->controller_base + PCIE_SS_IA_FN_NUM);\n+\n+\tctl = FIELD_PREP(PCIE_SS_IA_CTL_ADDR, addr >> 2) |\n+\t PCIE_SS_IA_CTL_BYTE_EN | PCIE_SS_IA_CTL_INITIATE;\n+\twritel(ctl, (pcie->controller_base + PCIE_SS_IA_CTL));\n+\n+\tret = readl_poll_timeout_atomic(pcie->controller_base + PCIE_SS_IA_CTL,\n+\t\t\t\t\tctl, !(ctl & PCIE_SS_IA_CTL_INITIATE),\n+\t\t\t\t\tAGLX5_INDIRECT_SLEEP_US,\n+\t\t\t\t\tAGLX5_INDIRECT_TIMEOUT_US);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = readl(pcie->controller_base + PCIE_SS_IA_FN_RDDATA);\n+\n+\treturn 0;\n+}\n+\n+static int aglx5_indirect_writel(const struct altera_pcie *pcie,\n+\t\t\t\t unsigned int addr, unsigned int val)\n+{\n+\tunsigned int ctl;\n+\tint ret;\n+\n+\twritel(PCIE_SS_IA_FN_TYPE_HIP,\n+\t pcie->controller_base + PCIE_SS_IA_FN_NUM);\n+\twritel(val, pcie->controller_base + PCIE_SS_IA_FN_WRDATA);\n+\n+\tctl = FIELD_PREP(PCIE_SS_IA_CTL_ADDR, addr >> 2) |\n+\t PCIE_SS_IA_CTL_BYTE_EN | PCIE_SS_IA_CTL_WRITE |\n+\t PCIE_SS_IA_CTL_INITIATE;\n+\twritel(ctl, pcie->controller_base + PCIE_SS_IA_CTL);\n+\n+\tret = readl_poll_timeout_atomic(pcie->controller_base + PCIE_SS_IA_CTL,\n+\t\t\t\t\tctl, !(ctl & PCIE_SS_IA_CTL_INITIATE),\n+\t\t\t\t\tAGLX5_INDIRECT_SLEEP_US,\n+\t\t\t\t\tAGLX5_INDIRECT_TIMEOUT_US);\n+\n+\treturn ret;\n+}\n+\n+static void aglx5_isr(struct irq_desc *desc)\n+{\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct altera_pcie *pcie;\n+\tstruct device *dev;\n+\tu32 status = 0;\n+\tint ret;\n+\n+\tchained_irq_enter(chip, desc);\n+\tpcie = irq_desc_get_handler_data(desc);\n+\tdev = &pcie->pdev->dev;\n+\n+\tret = aglx5_indirect_readl(pcie, pcie->pcie_data->port_irq_status_offset, &status);\n+\tif (ret) {\n+\t\tdev_err(dev, \"timeout reading IRQ status, masking IRQ\\n\");\n+\t\tdisable_irq_nosync(pcie->irq);\n+\t\tgoto out;\n+\t}\n+\n+\tif (status & CFG_AER) {\n+\t\tret = generic_handle_domain_irq(pcie->irq_domain, 0);\n+\t\tif (ret)\n+\t\t\tdev_err_ratelimited(dev, \"unexpected IRQ\\n\");\n+\n+\t\t/* W1C: clear the handled bit */\n+\t\tret = aglx5_indirect_writel(pcie,\n+\t\t\t\t\t pcie->pcie_data->port_irq_status_offset,\n+\t\t\t\t\t CFG_AER);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"timeout clearing IRQ status, masking IRQ\\n\");\n+\t\t\tdisable_irq_nosync(pcie->irq);\n+\t\t}\n+\t}\n+\n+out:\n+\tchained_irq_exit(chip, desc);\n+}\n+\n static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n@@ -880,12 +994,19 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)\n \t\treturn PTR_ERR(pcie->cra_base);\n \n \tif (pcie->pcie_data->version == ALTERA_PCIE_V2 ||\n-\t pcie->pcie_data->version == ALTERA_PCIE_V3) {\n+\t pcie->pcie_data->version == ALTERA_PCIE_V3 ||\n+\t pcie->pcie_data->version == ALTERA_PCIE_V4) {\n \t\tpcie->hip_base = devm_platform_ioremap_resource_byname(pdev, \"Hip\");\n \t\tif (IS_ERR(pcie->hip_base))\n \t\t\treturn PTR_ERR(pcie->hip_base);\n \t}\n \n+\tif (pcie->pcie_data->version == ALTERA_PCIE_V4) {\n+\t\tpcie->controller_base = devm_platform_ioremap_resource_byname(pdev, \"Txs\");\n+\t\tif (IS_ERR(pcie->controller_base))\n+\t\t\treturn PTR_ERR(pcie->controller_base);\n+\t}\n+\n \t/* setup IRQ */\n \tpcie->irq = platform_get_irq(pdev, 0);\n \tif (pcie->irq < 0)\n@@ -924,6 +1045,15 @@ static const struct altera_pcie_ops altera_pcie_ops_3_0 = {\n \t.rp_isr = aglx_isr,\n };\n \n+static const struct altera_pcie_ops altera_pcie_ops_4_0 = {\n+\t.rp_read_cfg = aglx_rp_read_cfg,\n+\t.rp_write_cfg = aglx_rp_write_cfg,\n+\t.get_link_status = aglx_altera_pcie_link_up,\n+\t.ep_read_cfg = aglx_ep_read_cfg,\n+\t.ep_write_cfg = aglx_ep_write_cfg,\n+\t.rp_isr = aglx5_isr,\n+};\n+\n static const struct altera_pcie_data altera_pcie_1_0_data = {\n \t.ops = &altera_pcie_ops_1_0,\n \t.cap_offset = 0x80,\n@@ -971,6 +1101,20 @@ static const struct altera_pcie_data altera_pcie_3_0_r_tile_data = {\n \t.port_irq_enable_offset = 0x4,\n };\n \n+static const struct altera_pcie_data altera_pcie_4_0_data = {\n+\t.ops = &altera_pcie_ops_4_0,\n+\t.version = ALTERA_PCIE_V4,\n+\t.cap_offset = 0x70,\n+\t.port_conf_offset = 0x14000,\n+\t/*\n+\t * Unlike V3 where IRQ offsets are relative to port_conf_offset,\n+\t * V4 IRQ offsets are absolute addresses in the HIP indirect access\n+\t * space documented in the GTS AXI Streaming IP for PCIe User Guide.\n+\t */\n+\t.port_irq_status_offset = 0x1414c,\n+\t.port_irq_enable_offset = 0x14150,\n+};\n+\n static const struct of_device_id altera_pcie_of_match[] = {\n \t{.compatible = \"altr,pcie-root-port-1.0\",\n \t .data = &altera_pcie_1_0_data },\n@@ -982,6 +1126,8 @@ static const struct of_device_id altera_pcie_of_match[] = {\n \t .data = &altera_pcie_3_0_p_tile_data },\n \t{.compatible = \"altr,pcie-root-port-3.0-r-tile\",\n \t .data = &altera_pcie_3_0_r_tile_data },\n+\t{.compatible = \"altr,pcie-root-port-4.0\",\n+\t .data = &altera_pcie_4_0_data },\n \t{},\n };\n \n@@ -1035,6 +1181,14 @@ static int altera_pcie_probe(struct platform_device *pdev)\n \t\twritel(CFG_AER,\n \t\t pcie->hip_base + pcie->pcie_data->port_conf_offset +\n \t\t pcie->pcie_data->port_irq_enable_offset);\n+\t} else if (pcie->pcie_data->version == ALTERA_PCIE_V4) {\n+\t\tret = aglx5_indirect_writel(pcie,\n+\t\t\t\t\t pcie->pcie_data->port_irq_enable_offset,\n+\t\t\t\t\t CFG_AER);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to enable AER IRQ\\n\");\n+\t\t\tgoto err_teardown_irq;\n+\t\t}\n \t}\n \n \tbridge->sysdata = pcie;\n","prefixes":["3/3"]}