{"id":2227700,"url":"http://patchwork.ozlabs.org/api/patches/2227700/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424050509.3935180-3-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424050509.3935180-3-frank.chang@sifive.com>","list_archive_url":null,"date":"2026-04-24T05:05:09","name":"[v4,2/2] target/riscv: Update MISA.X for non-standard extensions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"535580aa8170807f80aedc101f5bd5eb26869a43","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424050509.3935180-3-frank.chang@sifive.com/mbox/","series":[{"id":501301,"url":"http://patchwork.ozlabs.org/api/series/501301/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501301","date":"2026-04-24T05:05:08","name":"Set MISA.[C|X] based on the selected extensions","version":4,"mbox":"http://patchwork.ozlabs.org/series/501301/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227700/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227700/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=BWXO6yz9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g21C13gcyz1yHv\n\tfor ; Fri, 24 Apr 2026 15:06:21 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8jF-0003wO-Cx; Fri, 24 Apr 2026 01:05:25 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8jD-0003vb-V5\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 01:05:23 -0400","from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8jC-0005q7-9x\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 01:05:23 -0400","by mail-pf1-x433.google.com with SMTP id\n d2e1a72fcca58-82f8b60e485so3155462b3a.0\n for ; Thu, 23 Apr 2026 22:05:21 -0700 (PDT)","from hsinchu16.internal.sifive.com ([210.176.154.34])\n by smtp.gmail.com with ESMTPSA id\n d2e1a72fcca58-82f8e981992sm26698554b3a.7.2026.04.23.22.05.17\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 23 Apr 2026 22:05:19 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=sifive.com; s=google; t=1777007120; x=1777611920; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=vmZ0nGBImY+awhw0ANHTquhG/heSaRQBT3E52jWGxAE=;\n b=BWXO6yz9+OvMMuc+2BjIrSnPzTzN+cV+PRWbko7QT5oWU+vEsLXXDgMnzEMiy5J/dA\n Jv1IOWtBDor8JvOeQQGjOdyREEiKwZ+GYoSIGv9nFSdenIK710/f6cPEqos8cQrUr2hd\n kr24Kf9LM13W5xmIbshxV8dvreR4KHUx+5sSXVWZNzUqAMF75CCM3p0D7OKJzvlMoRkh\n QR9DmjJgoG5vw/IgKpkwtn2Yssp7HLN0ALVDcGkmZI7vBNmgf4NH+1tlQKLDSgz/7rfm\n e8q2tERlY/fuYc5Zwz+ywUn5nhwCwgk9M1CDIZdBc4GtbY67qmyxRZ2jY2GQkXXp85NY\n f6uQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777007120; x=1777611920;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=vmZ0nGBImY+awhw0ANHTquhG/heSaRQBT3E52jWGxAE=;\n b=cRJuUPCOrfQj16/EAIcRJn1xQVXcXywme8itktS2VXBTxmP8mjOrX2SUfNMxz+wBaO\n Es/lytm49JHglPewtVeNJk27FipPulisIznaAoCA9/8QaTzPLAyHzD4wEuV+ugce/Pvq\n 4JYdPPuO4c7+nkizHZ4BWR1/dxl8d6HPfAVSg+vUqaBvTbyGDwWf+Uw+qYN6K3OrIoFK\n aRH+S6o+Sc2rAyZZwyWYP56MxzkEPvTGRWMXHluEa8o/+jFIqnwEG8HwmDs/RxZJ/zUF\n +Xq9Hh66BYnHIudeeIqxk1Wlzg1LJvTOcjpHgnnnSQAk4nFGboYoYdGZi54oucbR4t/4\n q/5w==","X-Gm-Message-State":"AOJu0YyoUF8e08+1Gi3xzMzI1F/taETIkTnn6SaibkUAgiJ+lv8I3PnE\n RrLiH7qthGADj3MOzqbLOELldM6YZGW7D6CN8h8/mDfEP2IvmKJt146cWYHyUnrf45D14SFUl0T\n 1J7YP3HZEF38ldI2PqsMBCCjlvoPIBIh7iy1KroORiG3qrCE+tWJxctf9m4MDE+5NR8/YhhXRu2\n srutxdeehFNDkQomQ1thxso2rbO8rzXrWxJsUrrK9e0ZoJaPNg","X-Gm-Gg":"AeBDieuE9/5+Q/pCPyEzjZW6ZPEDwYHSNqzfFYkoOYMPwlb3+ok58K39Xh/LTVHJFVo\n Ys5YwhZYRgvrRgv+tpucjN8lDCl6yOC4C1bRIEqBxdIK8vIVGHAhYIPE3f6FgpTSrqbcWI2SSLY\n +x/KggKtntRoqASO+kvkALU5pV38+dgUixAPjQ/fF4VpVGbsvau04XQImywTX5Qv001I1TPnOcJ\n S4/FA8vRaOMrMrmWPK2EwBvvbDtONRfGnIrzhB+TNoxvoVkwTe48URagrcTclQ2nY1C+5LPF3MW\n jABPoKRLu7L2wkx7TgNuezkIFna1bZ1yytDKGfNjENUsi9VWM+WgF1+O1RzCmqjTHMHhkXSSdHo\n TSzw8NgcAnUjEL0oY7kDgffKYfFYkWuhq29yPsAvS1NaiBcfMjAE9XbouHKQBY/w15oBa6lHc9m\n +nN6GkjO1inl2H5BFKfK977i4rBYaDbsQRc9XsDvXMc8Tzu0LshtbZpbrKON1V","X-Received":"by 2002:a05:6a00:c8f:b0:82c:26a4:df02 with SMTP id\n d2e1a72fcca58-82f8c9bad60mr32888759b3a.42.1777007120169;\n Thu, 23 Apr 2026 22:05:20 -0700 (PDT)","From":"frank.chang@sifive.com","To":"qemu-devel@nongnu.org","Cc":"Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs),\n Frank Chang , Max Chou ,\n Daniel Henrique Barboza ","Subject":"[PATCH v4 2/2] target/riscv: Update MISA.X for non-standard\n extensions","Date":"Fri, 24 Apr 2026 13:05:09 +0800","Message-ID":"<20260424050509.3935180-3-frank.chang@sifive.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260424050509.3935180-1-frank.chang@sifive.com>","References":"<20260424050509.3935180-1-frank.chang@sifive.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::433;\n envelope-from=frank.chang@sifive.com; helo=mail-pf1-x433.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nMISA.X is set if there are any non-standard extensions.\nWe should set MISA.X when any of the vendor extensions is enabled.\n\nSigned-off-by: Frank Chang \nReviewed-by: Max Chou \nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Alistair Francis \n---\n target/riscv/cpu.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++\n 2 files changed, 16 insertions(+)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 4c0676ed53b..175e877f90a 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;\n #define RVH RV('H')\n #define RVG RV('G')\n #define RVB RV('B')\n+#define RVX RV('X')\n \n extern const uint32_t misa_bits[];\n const char *riscv_get_misa_ext_name(uint32_t bit);\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 5db166c01e9..42b40104806 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -1201,6 +1201,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)\n }\n }\n \n+/* MISA.X is set when any of the non-standard extensions is enabled. */\n+static void riscv_cpu_update_misa_x(RISCVCPU *cpu)\n+{\n+ CPURISCVState *env = &cpu->env;\n+ const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;\n+\n+ for (int i = 0; arr[i].name != NULL; i++) {\n+ if (isa_ext_is_enabled(cpu, arr[i].offset)) {\n+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);\n+ break;\n+ }\n+ }\n+}\n+\n void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n {\n CPURISCVState *env = &cpu->env;\n@@ -1209,6 +1223,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n riscv_cpu_init_implied_exts_rules();\n riscv_cpu_enable_implied_rules(cpu);\n riscv_cpu_update_misa_c(cpu);\n+ riscv_cpu_update_misa_x(cpu);\n \n riscv_cpu_validate_misa_priv(env, &local_err);\n if (local_err != NULL) {\n","prefixes":["v4","2/2"]}