{"id":2227697,"url":"http://patchwork.ozlabs.org/api/patches/2227697/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-24-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424043014.46305-24-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-24T04:29:57","name":"[v2,23/40] target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fa6a0709f4e7f7ab838908f0a27a8b79de98b024","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-24-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227697/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227697/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xr/0ad2s;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20Xm2fFnz1yD5\n\tfor ; Fri, 24 Apr 2026 14:36:40 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8DI-0001vq-5r; Fri, 24 Apr 2026 00:32:24 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Cy-0000fC-Da\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:05 -0400","from mail-oa1-x32.google.com ([2001:4860:4864:20::32])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Cw-0003F3-As\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:04 -0400","by mail-oa1-x32.google.com with SMTP id\n 586e51a60fabf-4243bf9be36so3461456fac.3\n for ; Thu, 23 Apr 2026 21:32:01 -0700 (PDT)","from stoup.. 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helo=mail-oa1-x32.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/helper-fp8.h | 14 ++++\n target/arm/tcg/helper-fp8-defs.h | 6 ++\n target/arm/tcg/translate-a64.h | 1 +\n target/arm/tcg/fp8_helper.c | 123 +++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 34 +++++++++\n target/arm/tcg/a64.decode | 3 +\n target/arm/tcg/meson.build | 1 +\n 7 files changed, 182 insertions(+)\n create mode 100644 target/arm/helper-fp8.h\n create mode 100644 target/arm/tcg/helper-fp8-defs.h\n create mode 100644 target/arm/tcg/fp8_helper.c","diff":"diff --git a/target/arm/helper-fp8.h b/target/arm/helper-fp8.h\nnew file mode 100644\nindex 0000000000..c45211ba22\n--- /dev/null\n+++ b/target/arm/helper-fp8.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#ifndef HELPER_FP8_H\n+#define HELPER_FP8_H\n+\n+#include \"exec/helper-proto-common.h\"\n+#include \"exec/helper-gen-common.h\"\n+\n+#define HELPER_H \"tcg/helper-fp8-defs.h\"\n+#include \"exec/helper-proto.h.inc\"\n+#include \"exec/helper-gen.h.inc\"\n+#undef HELPER_H\n+\n+#endif /* HELPER_FP8_H */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nnew file mode 100644\nindex 0000000000..0caaf63749\n--- /dev/null\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -0,0 +1,6 @@\n+/*\n+ * AArch64 FP8 helper definitions\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h\nindex 9c45f89305..35f8d4f82e 100644\n--- a/target/arm/tcg/translate-a64.h\n+++ b/target/arm/tcg/translate-a64.h\n@@ -25,6 +25,7 @@ TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);\n void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);\n bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,\n unsigned int imms, unsigned int immr);\n+bool fpmr_access_check(DisasContext *s);\n bool sve_access_check(DisasContext *s);\n bool sme_enabled_check(DisasContext *s);\n bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nnew file mode 100644\nindex 0000000000..a2efdd5cd7\n--- /dev/null\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -0,0 +1,123 @@\n+/*\n+ * AArch64 FP8 Operations\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"internals.h\"\n+#include \"tcg/tcg-gvec-desc.h\"\n+#include \"fpu/softfloat.h\"\n+#include \"helper-fp8.h\"\n+#include \"vec_internal.h\"\n+\n+#define HELPER_H \"tcg/helper-fp8-defs.h\"\n+#include \"exec/helper-info.c.inc\"\n+\n+typedef enum FPMRType {\n+ OFP8_E5M2 = 0,\n+ OFP8_E4M3 = 1,\n+ Unsupp2 = 2,\n+ Unsupp3 = 3,\n+ Unsupp4 = 4,\n+ Unsupp5 = 5,\n+ Unsupp6 = 6,\n+ Unsupp7 = 7,\n+} FPMRType;\n+\n+typedef struct FP8Context {\n+ float_status stat;\n+ ARMFPStatusFlavour fpst;\n+ FPMRType f8fmt;\n+ int scale;\n+ bool high;\n+} FP8Context;\n+\n+static FP8Context fp8_start(CPUARMState *env, uint32_t desc,\n+ FPMRType f8fmt, int scale)\n+{\n+ ARMFPStatusFlavour fpst = extract32(desc, SIMD_DATA_SHIFT + 2, 4);\n+\n+ FP8Context ret = {\n+ .stat = env->vfp.fp_status[fpst],\n+ .fpst = fpst,\n+ .f8fmt = f8fmt,\n+ .scale = scale,\n+ .high = extract32(desc, SIMD_DATA_SHIFT + 1, 1),\n+ };\n+\n+ set_flush_to_zero(0, &ret.stat);\n+ set_flush_inputs_to_zero(0, &ret.stat);\n+ set_default_nan_mode(true, &ret.stat);\n+ set_float_rounding_mode(float_round_nearest_even, &ret.stat);\n+\n+ return ret;\n+}\n+\n+static void fp8_finish(CPUARMState *env, FP8Context *c)\n+{\n+ int new_flags = get_float_exception_flags(&c->stat);\n+\n+ new_flags &= ~float_flag_input_denormal_used;\n+ float_raise(new_flags, &env->vfp.fp_status[c->fpst]);\n+}\n+\n+static FP8Context fp8_src_start(CPUARMState *env, uint32_t desc, int scale_mask)\n+{\n+ bool issrc2 = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType f8fmt = (issrc2\n+ ? FIELD_EX64(fpmr, FPMR, F8S2)\n+ : FIELD_EX64(fpmr, FPMR, F8S1));\n+ int scale;\n+\n+ scale = fpmr >> (issrc2 ? R_FPMR_LSCALE2_SHIFT : R_FPMR_LSCALE_SHIFT);\n+ scale = -(scale & scale_mask);\n+\n+ return fp8_start(env, desc, f8fmt, scale);\n+}\n+\n+/*\n+ * Invalid input format is treated as snan, then the conversion operation\n+ * converts to default nan and raises invalid.\n+ */\n+static void bfloat16_invalid_input(bfloat16 *d, size_t nelem, float_status *s)\n+{\n+ bfloat16 dnan = bfloat16_default_nan(s);\n+\n+ for (size_t i = 0; i < nelem; ++i) {\n+ d[i] = dnan;\n+ }\n+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n+}\n+\n+void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ uint8_t *n = vn, scratch[16];\n+ bfloat16 *d = vd;\n+\n+ if (vd == vn) {\n+ n = memcpy(scratch, vn, 16);\n+ }\n+ n += ctx.high * 8;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (int i = 0; i < 8; ++i) {\n+ d[H2(i)] = float8_e5m2_to_bfloat16(n[H1(i)], ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (int i = 0; i < 8; ++i) {\n+ d[H2(i)] = float8_e4m3_to_bfloat16(n[H1(i)], ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ bfloat16_invalid_input(d, 8, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+ clear_tail(vd, 16, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 515c0fb2e0..d23d1a0bf5 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -21,6 +21,7 @@\n #include \"helper-a64.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n+#include \"helper-fp8.h\"\n #include \"translate.h\"\n #include \"translate-a64.h\"\n #include \"qemu/log.h\"\n@@ -1456,6 +1457,24 @@ static bool fp_access_check(DisasContext *s)\n return fp_access_check_only(s) && nonstreaming_check(s);\n }\n \n+/*\n+ * Check that FPMR access is enabled, for an indirect reference by a\n+ * vector instruction. See CheckFPMREnabled().\n+ */\n+bool fpmr_access_check(DisasContext *s)\n+{\n+ if (s->fpmr_el) {\n+ /*\n+ * While denied direct access to the FPMR raises SystemRegisterTrap\n+ * and targets a specific EL, denied indirect access to the FPMR\n+ * results in a simple UNDEFINED to the default exception level.\n+ */\n+ unallocated_encoding(s);\n+ return false;\n+ }\n+ return true;\n+}\n+\n /*\n * Return <0 for non-supported element sizes, with MO_16 controlled by\n * FEAT_FP16; return 0 for fp disabled; otherwise return >0 for success.\n@@ -10611,6 +10630,21 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)\n return true;\n }\n \n+static bool do_f8cvt(DisasContext *s, arg_qrr_e *a,\n+ gen_helper_gvec_2_ptr *fn, bool issrc2)\n+{\n+ if (fpmr_access_check(s) && fp_access_check(s)) {\n+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ tcg_env, 16, vec_full_reg_size(s),\n+ issrc2 | (a->q << 1) | (FPST_A64 << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(BF1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, false)\n+TRANS_FEAT(BF2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, true)\n+\n static bool trans_OK(DisasContext *s, arg_OK *a)\n {\n return true;\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 02c7264cb9..b7aac148f2 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1910,6 +1910,9 @@ URSQRTE_v 0.10 1110 101 00001 11001 0 ..... ..... @qrr_s\n \n FCVTL_v 0.00 1110 0.1 00001 01111 0 ..... ..... @qrr_sd\n \n+BF1CVTL 0.10 1110 101 00001 01111 0 ..... ..... @qrr_h\n+BF2CVTL 0.10 1110 111 00001 01111 0 ..... ..... @qrr_h\n+\n &fcvt_q rd rn esz q shift\n @fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \\\n &fcvt_q esz=1 shift=%fcvt_f_sh_h\ndiff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build\nindex 5f59156055..0d715cfb87 100644\n--- a/target/arm/tcg/meson.build\n+++ b/target/arm/tcg/meson.build\n@@ -47,6 +47,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(\n 'sme_helper.c',\n 'sve_helper.c',\n 'vec_helper64.c',\n+ 'fp8_helper.c',\n ))\n \n arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))\n","prefixes":["v2","23/40"]}