{"id":2227696,"url":"http://patchwork.ozlabs.org/api/patches/2227696/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-28-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424043014.46305-28-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-24T04:30:01","name":"[v2,27/40] target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5ee9cca4abdcabb08646cd2c4df36c3ffeb377e1","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-28-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227696/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227696/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=MPHFMMej;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20XC3pLMz1yD5\n\tfor ; Fri, 24 Apr 2026 14:36:11 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8DM-0002Jg-3L; Fri, 24 Apr 2026 00:32:28 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8DD-0001NR-MC\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:19 -0400","from mail-oa1-x31.google.com ([2001:4860:4864:20::31])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8DB-0003Sy-J1\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:19 -0400","by mail-oa1-x31.google.com with SMTP id\n 586e51a60fabf-40427db1300so5595063fac.0\n for ; Thu, 23 Apr 2026 21:32:17 -0700 (PDT)","from stoup.. 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helo=mail-oa1-x31.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/tcg/helper-fp8-defs.h | 2 ++\n target/arm/tcg/fp8_helper.c | 42 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 3 +++\n target/arm/tcg/a64.decode | 3 +++\n 4 files changed, 50 insertions(+)","diff":"diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 966f83d796..718463422b 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -7,3 +7,5 @@ DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex daf9c35720..ed4923b1d5 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -91,6 +91,16 @@ static void bfloat16_invalid_input(bfloat16 *d, size_t nelem, float_status *s)\n float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n }\n \n+static void float16_invalid_input(float16 *d, size_t nelem, float_status *s)\n+{\n+ float16 dnan = float16_default_nan(s);\n+\n+ for (size_t i = 0; i < nelem; ++i) {\n+ d[i] = dnan;\n+ }\n+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n+}\n+\n void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n@@ -122,6 +132,38 @@ void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n clear_tail(vd, 16, simd_maxsz(desc));\n }\n \n+void HELPER(advsimd_fcvtl_hb)(void *vd, void *vn,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0xf);\n+ uint8_t *n = vn, scratch[16];\n+ float16 *d = vd;\n+\n+ if (vd == vn) {\n+ n = memcpy(scratch, vn, 16);\n+ }\n+ n += ctx.high * 8;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (int i = 0; i < 8; ++i) {\n+ d[H2(i)] = float8_e5m2_to_float16(n[H1(i)], ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (int i = 0; i < 8; ++i) {\n+ d[H2(i)] = float8_e4m3_to_float16(n[H1(i)], ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float16_invalid_input(d, 8, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+ clear_tail(vd, 16, simd_maxsz(desc));\n+}\n+\n void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex d23d1a0bf5..b3fbc5f193 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -10642,6 +10642,9 @@ static bool do_f8cvt(DisasContext *s, arg_qrr_e *a,\n return true;\n }\n \n+TRANS_FEAT(F1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_fcvtl_hb, false)\n+TRANS_FEAT(F2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_fcvtl_hb, true)\n+\n TRANS_FEAT(BF1CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, false)\n TRANS_FEAT(BF2CVTL, aa64_f8cvt, do_f8cvt, a, gen_helper_advsimd_bfcvtl, true)\n \ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex b7aac148f2..26d31d0a33 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1910,6 +1910,9 @@ URSQRTE_v 0.10 1110 101 00001 11001 0 ..... ..... @qrr_s\n \n FCVTL_v 0.00 1110 0.1 00001 01111 0 ..... ..... @qrr_sd\n \n+F1CVTL 0.10 1110 001 00001 01111 0 ..... ..... @qrr_h\n+F2CVTL 0.10 1110 011 00001 01111 0 ..... ..... @qrr_h\n+\n BF1CVTL 0.10 1110 101 00001 01111 0 ..... ..... @qrr_h\n BF2CVTL 0.10 1110 111 00001 01111 0 ..... ..... @qrr_h\n \n","prefixes":["v2","27/40"]}