{"id":2227683,"url":"http://patchwork.ozlabs.org/api/patches/2227683/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-7-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424043014.46305-7-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-24T04:29:40","name":"[v2,06/40] target/arm: Update SCR bits for Arm ARM M.a.a","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"80331f9d419d469f9b0646915f2742197f0c0380","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-7-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227683/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227683/checks/","tags":{},"related":[],"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=iV5P5hTm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20Vj34Swz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 14:34:53 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wG8Bt-00066B-JH; Fri, 24 Apr 2026 00:30:57 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8Bo-0005oV-D5\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:52 -0400","from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8Bm-0002bJ-O7\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:52 -0400","by mail-oa1-x2e.google.com with SMTP id\n 586e51a60fabf-40f1a1f77a6so5525303fac.2\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 21:30:50 -0700 (PDT)","from stoup.. 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helo=mail-oa1-x2e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu.h | 11 +++++++++++\n 1 file changed, 11 insertions(+)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 657ff4ab20..6ec3845edf 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1794,6 +1794,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)\n #define SCR_AIEN              (1ULL << 46)\n #define SCR_GPF               (1ULL << 48)\n #define SCR_MECEN             (1ULL << 49)\n+#define SCR_ENFPM             (1ULL << 50)\n+#define SCR_TMEA              (1ULL << 51)\n+#define SCR_TWERR             (1ULL << 52)\n+#define SCR_PFAREN            (1ULL << 53)\n+#define SCR_SRMASKEN          (1ULL << 54)\n+#define SCR_ENIDCP128         (1ULL << 55)\n+#define SCR_DSE               (1ULL << 57)\n+#define SCR_ENDSE             (1ULL << 58)\n+#define SCR_FGTEN2            (1ULL << 59)\n+#define SCR_HDBSSEN           (1ULL << 60)\n+#define SCR_HACEBSEN          (1ULL << 61)\n #define SCR_NSE               (1ULL << 62)\n \n /* GCSCR_ELx fields */\n","prefixes":["v2","06/40"]}