{"id":2227607,"url":"http://patchwork.ozlabs.org/api/patches/2227607/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424023606.2556830-8-brian.cain@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424023606.2556830-8-brian.cain@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-24T02:36:04","name":"[PULL,7/9] tests/tcg/hexagon: Add test for revision-gated instruction decoding","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6380895b496640db1cc93eae8c5e57e4993bf345","submitter":{"id":89839,"url":"http://patchwork.ozlabs.org/api/people/89839/?format=json","name":"Brian Cain","email":"brian.cain@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424023606.2556830-8-brian.cain@oss.qualcomm.com/mbox/","series":[{"id":501280,"url":"http://patchwork.ozlabs.org/api/series/501280/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501280","date":"2026-04-24T02:36:05","name":"[PULL,1/9] Hexagon (target/hexagon) Properly handle Hexagon CPU version","version":1,"mbox":"http://patchwork.ozlabs.org/series/501280/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227607/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227607/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=WF5DCmqZ;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=jCG5Ljda;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0a-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add check_rev_gating, a linux-user test that verifies the decoder\nrejects instructions from a newer CPU revision than the one selected\nby the ELF binary's e_flags.\n\nCo-authored-by: Taylor Simpson \nCo-authored-by: Matheus Tavares Bernardino \nReviewed-by: Marco Liebel \nSigned-off-by: Brian Cain \n---\n tests/tcg/hexagon/check_rev_gating.c | 141 +++++++++++++++++++++++++++\n tests/tcg/hexagon/Makefile.target | 6 ++\n 2 files changed, 147 insertions(+)\n create mode 100644 tests/tcg/hexagon/check_rev_gating.c","diff":"diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check_rev_gating.c\nnew file mode 100644\nindex 00000000000..26b66f54552\n--- /dev/null\n+++ b/tests/tcg/hexagon/check_rev_gating.c\n@@ -0,0 +1,141 @@\n+/*\n+ * Test that instructions from a newer revision than the running CPU\n+ * are rejected with SIGILL.\n+ *\n+ * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds\n+ * a v68 instruction (L2_loadw_aq: \"r0 = memw_aq(r0)\") via .word\n+ * encoding. The revision-gated decoder must reject it, and linux-user\n+ * must deliver SIGILL.\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+static void *resume_pc;\n+static int signals_handled;\n+static int expected_signals;\n+\n+static void handle_sigill(int sig, siginfo_t *info, void *puc)\n+{\n+ ucontext_t *uc = (ucontext_t *)puc;\n+\n+ if (sig != SIGILL) {\n+ _exit(EXIT_FAILURE);\n+ }\n+\n+ uc->uc_mcontext.r0 = SIGILL;\n+ uc->uc_mcontext.pc = (unsigned long)resume_pc;\n+ signals_handled++;\n+}\n+\n+/*\n+ * Try to execute an instruction introduced after v66\n+ * On a v66 CPU this must raise SIGILL.\n+ *\n+ * Since we are building for v66, the assembler will reject\n+ * the instructions, so introduce them with .word.\n+ */\n+#define TRY_FUNC(NAME, WORD) \\\n+static int try_##NAME(void) \\\n+{ \\\n+ int sig; \\\n+ expected_signals++; \\\n+ asm volatile( \\\n+ \"r0 = #0\\n\" \\\n+ \"r1 = ##1f\\n\" \\\n+ \"memw(%1) = r1\\n\" \\\n+ WORD \\\n+ \"1:\\n\" \\\n+ \"%0 = r0\\n\" \\\n+ : \"=r\"(sig) \\\n+ : \"r\"(&resume_pc) \\\n+ : \"r0\", \"r1\", \"memory\"); \\\n+ return sig; \\\n+}\n+\n+TRY_FUNC(v68_loadw_aq,\n+ \".word 0x9200c800 /* { r0 = memw_aq(r0) } */\\n\")\n+TRY_FUNC(v68_loadd_aq,\n+ \".word 0x9201d800 /* r1:0 = memd_aq(r1) */\\n\")\n+TRY_FUNC(v68_release_at,\n+ \".word 0xa0e0c00c /* release(r0):at */\\n\")\n+TRY_FUNC(v68_release_st,\n+ \".word 0xa0e0c02c /* release(r0):st */\\n\")\n+TRY_FUNC(v68_storew_rl_at,\n+ \".word 0xa0a0c108 /* memw_rl(r0):at = r1 */\\n\")\n+TRY_FUNC(v68_stored_rl_at,\n+ \".word 0xa0e2c008 /* memd_rl(r2):at = r1:0 */\\n\")\n+TRY_FUNC(v68_storew_rl_st,\n+ \".word 0xa0a0c128 /* memw_rl(r0):st = r1 */\\n\")\n+TRY_FUNC(v68_stored_rl_st,\n+ \".word 0xa0e2c028 /* memd_rl(r2):st = r1:0 */\\n\")\n+\n+TRY_FUNC(v68hvx_v6mpy,\n+ \".word 0x1f42e424 /* v5:4.w = v6mpy(v5:4.ub, v3:2.b, #1):v */\\n\")\n+\n+TRY_FUNC(v69hvx_vasrvuhubrndsat,\n+ \".word 0x1d06c465 /* v5.ub = vasr(v5:4.uh, v6.ub):rnd:sat */\\n\")\n+TRY_FUNC(v69hvx_vasrvuhubsat,\n+ \".word 0x1d06c445 /* v5.ub = vasr(v5:4.uh, v6.ub):sat */\\n\")\n+TRY_FUNC(v69hvx_vasrvwuhrndsat,\n+ \".word 0x1d06c425 /* v5.uh = vasr(v5:4.w, v6.uh):rnd:sat */\\n\")\n+TRY_FUNC(v69hvx_vasrvwuhsat,\n+ \".word 0x1d06c405 /* v5.uh = vasr(v5:4.w, v6.uh):sat */\\n\")\n+TRY_FUNC(v69hvx_vassign_tmp,\n+ \".word 0x1e014dcc /* { v12.tmp = v13 */\\n\"\n+ \".word 0x1c43cc04 /* v4.w = vadd(v12.w, v3.w) } */\\n\")\n+TRY_FUNC(v69hvx_vcombine_tmp,\n+ \".word 0x1eae4fec /* { v13:12.tmp = vcombine(v15, v14) */\\n\"\n+ \".word 0x1c434c04 /* v4.w = vadd(v12.w, v3.w) */\\n\"\n+ \".word 0x1e03edf0 /* v16 = v13 } */\\n\")\n+TRY_FUNC(v69hvx_vmpyuhvs,\n+ \".word 0x1fc5e4e4 /* v4.uh = vmpy(V4.uh, v5.uh):>>16 */\\n\")\n+\n+TRY_FUNC(v73_callrh,\n+ \".word 0x50c5c000 /* callrh r5 */\\n\")\n+TRY_FUNC(v73_jumprh,\n+ \".word 0x52c0c000 /* jumprh r0 */\\n\")\n+\n+int main(void)\n+{\n+ struct sigaction act;\n+\n+ memset(&act, 0, sizeof(act));\n+ act.sa_sigaction = handle_sigill;\n+ act.sa_flags = SA_SIGINFO;\n+ assert(sigaction(SIGILL, &act, NULL) == 0);\n+\n+ assert(try_v68_loadw_aq() == SIGILL);\n+ assert(try_v68_loadd_aq() == SIGILL);\n+ assert(try_v68_release_at() == SIGILL);\n+ assert(try_v68_release_st() == SIGILL);\n+ assert(try_v68_storew_rl_at() == SIGILL);\n+ assert(try_v68_stored_rl_at() == SIGILL);\n+ assert(try_v68_storew_rl_st() == SIGILL);\n+ assert(try_v68_stored_rl_st() == SIGILL);\n+\n+ assert(try_v68hvx_v6mpy() == SIGILL);\n+\n+ assert(try_v69hvx_vasrvuhubrndsat() == SIGILL);\n+ assert(try_v69hvx_vasrvuhubsat() == SIGILL);\n+ assert(try_v69hvx_vasrvwuhrndsat() == SIGILL);\n+ assert(try_v69hvx_vasrvwuhsat() == SIGILL);\n+ assert(try_v69hvx_vassign_tmp() == SIGILL);\n+ assert(try_v69hvx_vcombine_tmp() == SIGILL);\n+ assert(try_v69hvx_vmpyuhvs() == SIGILL);\n+\n+ assert(try_v73_callrh() == SIGILL);\n+ assert(try_v73_jumprh() == SIGILL);\n+\n+ assert(signals_handled == expected_signals);\n+\n+ puts(\"PASS\");\n+ return EXIT_SUCCESS;\n+}\ndiff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target\nindex 549c95082f6..09f0502abc5 100644\n--- a/tests/tcg/hexagon/Makefile.target\n+++ b/tests/tcg/hexagon/Makefile.target\n@@ -81,6 +81,7 @@ HEX_TESTS += test_vminh\n HEX_TESTS += test_vpmpyh\n HEX_TESTS += test_vspliceb\n \n+HEX_TESTS += check_rev_gating\n HEX_TESTS += test_pnew_jump_loads\n \n HEX_TESTS += v68_scalar\n@@ -109,6 +110,11 @@ reg_mut: reg_mut.c hex_test.h\n test_pnew_jump_loads: test_pnew_jump_loads.c hex_test.h\n unaligned_pc: unaligned_pc.c\n \n+# Compile for v66 so that the ELF selects a v66 CPU; the test then\n+# exercises revision gating by executing a v68 .word instruction.\n+check_rev_gating: check_rev_gating.c\n+\t$(CC) $(CFLAGS) -mv66 -O2 $< -o $@ $(LDFLAGS)\n+\n # This test has to be compiled for the -mv67t target\n usr: usr.c hex_test.h\n \t$(CC) $(CFLAGS) -mv67t -O2 -Wno-inline-asm -Wno-expansion-to-defined $< -o $@ $(LDFLAGS)\n","prefixes":["PULL","7/9"]}