{"id":2227603,"url":"http://patchwork.ozlabs.org/api/patches/2227603/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424023606.2556830-6-brian.cain@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260424023606.2556830-6-brian.cain@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-24T02:36:02","name":"[PULL,5/9] Hexagon (target/hexagon) Check each opcode against current CPU definition","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"96ae4a8d0b2d90a7ed0eead47ee187f4a79bdd8b","submitter":{"id":89839,"url":"http://patchwork.ozlabs.org/api/people/89839/?format=json","name":"Brian Cain","email":"brian.cain@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424023606.2556830-6-brian.cain@oss.qualcomm.com/mbox/","series":[{"id":501280,"url":"http://patchwork.ozlabs.org/api/series/501280/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501280","date":"2026-04-24T02:36:05","name":"[PULL,1/9] Hexagon (target/hexagon) Properly handle Hexagon CPU version","version":1,"mbox":"http://patchwork.ozlabs.org/series/501280/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227603/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227603/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=QH+fRniX;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=M8FVsxGL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0a-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Taylor Simpson \n\nDuring decoding, check that the opcode is supported in the current\nHexagon CPU definition\n\nCo-authored-by: Matheus Tavares Bernardino \nCo-authored-by: Brian Cain \nSigned-off-by: Taylor Simpson \nReviewed-by: Anton Johansson \nSigned-off-by: Brian Cain \n---\n target/hexagon/decode.h | 2 ++\n target/hexagon/decode.c | 27 +++++++++++++++++++++++++++\n 2 files changed, 29 insertions(+)","diff":"diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h\nindex 3f3012b978d..d4b049961ed 100644\n--- a/target/hexagon/decode.h\n+++ b/target/hexagon/decode.h\n@@ -30,4 +30,6 @@ void decode_send_insn_to(Packet *packet, int start, int newloc);\n int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,\n Packet *pkt, bool disas_only);\n \n+bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def);\n+\n #endif\ndiff --git a/target/hexagon/decode.c b/target/hexagon/decode.c\nindex dbc9c630e82..b8a1cd5b12b 100644\n--- a/target/hexagon/decode.c\n+++ b/target/hexagon/decode.c\n@@ -647,6 +647,22 @@ decode_set_slot_number(Packet *pkt)\n return has_valid_slot_assignment(pkt);\n }\n \n+bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def)\n+{\n+ HexagonVersion hex_version = hex_def->hex_version;\n+#include \"tag_rev_info.c.inc\"\n+\n+ struct tag_rev_info info = tag_rev_info[opcode];\n+ if (hex_version == HEX_VER_ANY) {\n+ return true;\n+ }\n+ if ((info.introduced != HEX_VER_NONE && hex_version < info.introduced) ||\n+ (info.removed != HEX_VER_NONE && hex_version >= info.removed)) {\n+ return false;\n+ }\n+ return true;\n+}\n+\n /*\n * Check for GPR write conflicts in the packet.\n * A conflict exists when a register is written by more than one instruction\n@@ -746,6 +762,17 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,\n /* Ran out of words! */\n return 0;\n }\n+\n+ /*\n+ * Check that all the opcodes are supported in this Hexagon definition\n+ * If not, return decode error\n+ */\n+ for (i = 0; i < num_insns; i++) {\n+ if (!opcode_supported(pkt->insn[i].opcode, ctx->hex_def)) {\n+ return 0;\n+ }\n+ }\n+\n pkt->encod_pkt_size_in_bytes = words_read * 4;\n pkt->pkt_has_hvx = false;\n for (i = 0; i < num_insns; i++) {\n","prefixes":["PULL","5/9"]}