{"id":2227357,"url":"http://patchwork.ozlabs.org/api/patches/2227357/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-7-0296bccb9f4e@oss.qualcomm.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260423-glymur-v2-7-0296bccb9f4e@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-23T13:29:36","name":"[v2,07/13] media: iris: Rename clock and power domain macros to use vcodec prefix","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"70c7b7f348c8b73c68c30de21235f24442a5e392","submitter":{"id":93161,"url":"http://patchwork.ozlabs.org/api/people/93161/?format=json","name":"Vishnu Reddy","email":"busanna.reddy@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423-glymur-v2-7-0296bccb9f4e@oss.qualcomm.com/mbox/","series":[{"id":501197,"url":"http://patchwork.ozlabs.org/api/series/501197/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501197","date":"2026-04-23T13:29:29","name":"media: iris: Add support for glymur platform","version":2,"mbox":"http://patchwork.ozlabs.org/series/501197/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227357/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227357/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=HhD3r7gE;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=d3mP9rfQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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Wysocki\" ,\n Danilo Krummrich ,\n Thierry Reding ,\n Mikko Perttunen ,\n David Airlie , Simona Vetter ,\n Jonathan Hunter ","Cc":"linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n iommu@lists.linux.dev, driver-core@lists.linux.dev,\n dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,\n Vishnu Reddy ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776950985; l=17094;\n i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id;\n bh=m5k//9k2AZqLBLTijFuX7klJ8v4jofc5QHXrTy9WJIk=;\n b=1Ygyh6Mhycy7NX/U8Ce0KIUOHTLFfBGTXVdgRPbkst+rOtOaW8mFgoRJ/0R8tsBXKiBpJKUH4\n 5tEAYWHFTlTBFQBnShzPMGCGC54yssp+2PbCe5Jf73uu52/MVqWSF+b","X-Developer-Key":"i=busanna.reddy@oss.qualcomm.com; a=ed25519;\n pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok=","X-Authority-Analysis":"v=2.4 cv=KPNqylFo c=1 sm=1 tr=0 ts=69ea1f16 cx=c_pps\n a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22\n a=EUspDBNiAAAA:8 a=kpNcZxiqwdVgWfiEekEA:9 a=QEXdDO2ut3YA:10\n a=uG9DUKGECoFWVXl0Dc02:22","X-Proofpoint-GUID":"KwmwSZRVc5rgnj2Y-hAiPb4nwGeoACyA","X-Proofpoint-ORIG-GUID":"KwmwSZRVc5rgnj2Y-hAiPb4nwGeoACyA","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIzMDEzNCBTYWx0ZWRfXyU1JC/2oonpB\n /0ElCV6X8YnBDGedapwleyfj9Y4r7637boJPy4UU/JXPwceKM+BkokRzTl3VwCD+lcmY6FePz7x\n XVVtAtCDp2ADFGx0z/G/GiZItF7YgrIQjH1qjsXev3mOVwQAAl+976qu6egJR1Rk6Xdvw7G5lv/\n laF+8QpUf2opDCLNY6WOepXD6gu/uIYYBIsdw23ECOKGGb3Cg2/cS6RQ50+s7+bmFuZ1OwSxhim\n L1KC0GZwlNEXbOH2jKChajnj9NTZ4gcATBRO20UkiFRBlU9I915CP3H1X57ik7NEz1qu7ItJVK+\n B2jXLgFNUSR1AF9t+w65PZLL3njWEBPaPjHDlLc+/XEgB1wbuxUslbVccsYxsLM6BfrUbQSEEfs\n PQOSTTRhWz3qIKEmJWfeD+Xkfuiqi1bezHn0vjwrGfr2MN6NtNY4hqNWnM8IXFXx2Aze7iRZrmh\n L1Yp5YSUPuNHGpwWcLQ==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 malwarescore=0 bulkscore=0\n priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 phishscore=0\n impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230134"},"content":"The current clock and power domain enum names are too generic. Rename\nthem with a vcodec prefix to make the names more meaningful and to easily\naccommodate vcodec1 enums for the secondary core for glymur platform.\n\nNo functional changes intended.\n\nSigned-off-by: Vishnu Reddy \n---\n .../platform/qcom/iris/iris_platform_common.h | 12 ++++----\n .../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++--\n .../media/platform/qcom/iris/iris_platform_gen2.c | 6 ++--\n .../platform/qcom/iris/iris_platform_sc7280.h | 10 +++----\n .../platform/qcom/iris/iris_platform_sm8750.h | 12 ++++----\n drivers/media/platform/qcom/iris/iris_vpu3x.c | 25 ++++++++--------\n drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 ++++++++++---------\n drivers/media/platform/qcom/iris/iris_vpu_common.c | 35 +++++++++++-----------\n 8 files changed, 70 insertions(+), 66 deletions(-)","diff":"diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h\nindex 55ff6137d9a9..30e9d4d288c6 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_common.h\n+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h\n@@ -49,14 +49,14 @@ extern const struct iris_platform_data sm8650_data;\n extern const struct iris_platform_data sm8750_data;\n \n enum platform_clk_type {\n-\tIRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */\n+\tIRIS_AXI_VCODEC_CLK,\n \tIRIS_CTRL_CLK,\n \tIRIS_AHB_CLK,\n-\tIRIS_HW_CLK,\n-\tIRIS_HW_AHB_CLK,\n-\tIRIS_AXI1_CLK,\n+\tIRIS_VCODEC_CLK,\n+\tIRIS_VCODEC_AHB_CLK,\n+\tIRIS_AXI_CTRL_CLK,\n \tIRIS_CTRL_FREERUN_CLK,\n-\tIRIS_HW_FREERUN_CLK,\n+\tIRIS_VCODEC_FREERUN_CLK,\n \tIRIS_BSE_HW_CLK,\n \tIRIS_VPP0_HW_CLK,\n \tIRIS_VPP1_HW_CLK,\n@@ -206,7 +206,7 @@ struct icc_vote_data {\n \n enum platform_pm_domain_type {\n \tIRIS_CTRL_POWER_DOMAIN,\n-\tIRIS_HW_POWER_DOMAIN,\n+\tIRIS_VCODEC_POWER_DOMAIN,\n \tIRIS_VPP0_HW_POWER_DOMAIN,\n \tIRIS_VPP1_HW_POWER_DOMAIN,\n \tIRIS_APV_HW_POWER_DOMAIN,\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c\nindex df8e6bf9430e..be6a631f8ede 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c\n+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c\n@@ -284,9 +284,9 @@ static const char * const sm8250_pmdomain_table[] = { \"venus\", \"vcodec0\" };\n static const char * const sm8250_opp_pd_table[] = { \"mx\" };\n \n static const struct platform_clk_data sm8250_clk_table[] = {\n-\t{IRIS_AXI_CLK, \"iface\" },\n-\t{IRIS_CTRL_CLK, \"core\" },\n-\t{IRIS_HW_CLK, \"vcodec0_core\" },\n+\t{IRIS_AXI_VCODEC_CLK,\t\"iface\"\t\t},\n+\t{IRIS_CTRL_CLK,\t\t\"core\"\t\t},\n+\t{IRIS_VCODEC_CLK,\t\"vcodec0_core\"\t},\n };\n \n static const char * const sm8250_opp_clk_table[] = {\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c\nindex 5da90d47f9c6..47c6b650f0b4 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c\n+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c\n@@ -780,9 +780,9 @@ static const char * const sm8550_pmdomain_table[] = { \"venus\", \"vcodec0\" };\n static const char * const sm8550_opp_pd_table[] = { \"mxc\", \"mmcx\" };\n \n static const struct platform_clk_data sm8550_clk_table[] = {\n-\t{IRIS_AXI_CLK, \"iface\" },\n-\t{IRIS_CTRL_CLK, \"core\" },\n-\t{IRIS_HW_CLK, \"vcodec0_core\" },\n+\t{IRIS_AXI_VCODEC_CLK,\t\"iface\"\t\t},\n+\t{IRIS_CTRL_CLK,\t\t\"core\"\t\t},\n+\t{IRIS_VCODEC_CLK,\t\"vcodec0_core\"\t},\n };\n \n static const char * const sm8550_opp_clk_table[] = {\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h\nindex 0ec8f334df67..6b783e524b81 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h\n+++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h\n@@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = {\n static const char * const sc7280_opp_pd_table[] = { \"cx\" };\n \n static const struct platform_clk_data sc7280_clk_table[] = {\n-\t{IRIS_CTRL_CLK, \"core\" },\n-\t{IRIS_AXI_CLK, \"iface\" },\n-\t{IRIS_AHB_CLK, \"bus\" },\n-\t{IRIS_HW_CLK, \"vcodec_core\" },\n-\t{IRIS_HW_AHB_CLK, \"vcodec_bus\" },\n+\t{IRIS_CTRL_CLK,\t\t\"core\"\t\t},\n+\t{IRIS_AXI_VCODEC_CLK,\t\"iface\"\t\t},\n+\t{IRIS_AHB_CLK,\t\t\"bus\"\t\t},\n+\t{IRIS_VCODEC_CLK,\t\"vcodec_core\"\t},\n+\t{IRIS_VCODEC_AHB_CLK,\t\"vcodec_bus\"\t},\n };\n \n static const char * const sc7280_opp_clk_table[] = {\ndiff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h\nindex 719056656a5b..f843f13251c5 100644\n--- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h\n+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h\n@@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = {\n };\n \n static const struct platform_clk_data sm8750_clk_table[] = {\n-\t{IRIS_AXI_CLK,\t\t\"iface\"\t\t\t},\n-\t{IRIS_CTRL_CLK,\t\t\"core\"\t\t\t},\n-\t{IRIS_HW_CLK,\t\t\"vcodec0_core\"\t\t},\n-\t{IRIS_AXI1_CLK,\t\t\"iface1\"\t\t},\n-\t{IRIS_CTRL_FREERUN_CLK,\t\"core_freerun\"\t\t},\n-\t{IRIS_HW_FREERUN_CLK,\t\"vcodec0_core_freerun\"\t},\n+\t{IRIS_AXI_VCODEC_CLK,\t\t\"iface\"\t\t\t},\n+\t{IRIS_CTRL_CLK,\t\t\t\"core\"\t\t\t},\n+\t{IRIS_VCODEC_CLK,\t\t\"vcodec0_core\"\t\t},\n+\t{IRIS_AXI_CTRL_CLK,\t\t\"iface1\"\t\t},\n+\t{IRIS_CTRL_FREERUN_CLK,\t\t\"core_freerun\"\t\t},\n+\t{IRIS_VCODEC_FREERUN_CLK,\t\"vcodec0_core_freerun\"\t},\n };\n \n #endif\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c\nindex fe4423b951b1..1f0a3a47d87f 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c\n@@ -209,7 +209,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core)\n \n disable_power:\n \tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n \n \treturn 0;\n }\n@@ -218,36 +218,37 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)\n {\n \tint ret;\n \n-\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core,\n+\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n \tif (ret)\n \t\treturn ret;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);\n \tif (ret)\n \t\tgoto err_disable_power;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK);\n \tif (ret)\n \t\tgoto err_disable_axi_clk;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_HW_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);\n \tif (ret)\n \t\tgoto err_disable_hw_free_clk;\n \n-\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);\n+\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);\n \tif (ret)\n \t\tgoto err_disable_hw_clk;\n \n \treturn 0;\n \n err_disable_hw_clk:\n-\tiris_disable_unprepare_clock(core, IRIS_HW_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n err_disable_hw_free_clk:\n-\tiris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);\n err_disable_axi_clk:\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n err_disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n \n \treturn ret;\n }\n@@ -256,8 +257,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)\n {\n \tiris_vpu33_power_off_hardware(core);\n \n-\tiris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n }\n \n const struct vpu_ops iris_vpu3_ops = {\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c\nindex a8db02ce5c5e..4082d331d2f3 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c\n@@ -27,7 +27,8 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32\n {\n \tint ret;\n \n-\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode);\n+\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN],\n+\t\t\t\t hw_mode);\n \tif (ret)\n \t\treturn ret;\n \n@@ -63,7 +64,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32\n \t\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],\n \t\t\t\t\t!hw_mode);\n restore_hw_domain_mode:\n-\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode);\n+\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode);\n \n \treturn ret;\n }\n@@ -162,15 +163,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v\n {\n \tint ret;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);\n \tif (ret)\n \t\treturn ret;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK);\n \tif (ret)\n \t\tgoto disable_axi_clock;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_HW_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);\n \tif (ret)\n \t\tgoto disable_hw_free_run_clock;\n \n@@ -198,11 +199,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v\n disable_bse_hw_clock:\n \tiris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);\n disable_hw_clock:\n-\tiris_disable_unprepare_clock(core, IRIS_HW_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n disable_hw_free_run_clock:\n-\tiris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);\n disable_axi_clock:\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n \n \treturn ret;\n }\n@@ -216,9 +217,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse\n \t\tiris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);\n \n \tiris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_HW_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n }\n \n static int iris_vpu4x_power_on_hardware(struct iris_core *core)\n@@ -226,7 +227,8 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)\n \tu32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);\n \tint ret;\n \n-\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core,\n+\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n \tif (ret)\n \t\treturn ret;\n \n@@ -278,7 +280,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)\n \t\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs\n \t\t\t\t\t\t[IRIS_VPP0_HW_POWER_DOMAIN]);\n disable_hw_power_domain:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n \n \treturn ret;\n }\n@@ -356,7 +358,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core)\n \t\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs\n \t\t\t\t\t [IRIS_VPP0_HW_POWER_DOMAIN]);\n \n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n }\n \n const struct vpu_ops iris_vpu4x_ops = {\ndiff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c\nindex bfd1e762c38e..006fd3ffc752 100644\n--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c\n+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c\n@@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *core)\n disable_power:\n \tiris_disable_unprepare_clock(core, IRIS_AHB_CLK);\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n \tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n \n \treturn 0;\n@@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *core)\n \n void iris_vpu_power_off_hw(struct iris_core *core)\n {\n-\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n-\tiris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_HW_CLK);\n+\tdev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false);\n+\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n }\n \n void iris_vpu_power_off(struct iris_core *core)\n@@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)\n \tif (ret)\n \t\tgoto err_disable_power;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);\n \tif (ret)\n \t\tgoto err_disable_power;\n \n@@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)\n err_disable_ctrl_clock:\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_CLK);\n err_disable_axi_clock:\n-\tiris_disable_unprepare_clock(core, IRIS_AXI_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);\n err_disable_power:\n \tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n \n@@ -279,30 +279,31 @@ int iris_vpu_power_on_hw(struct iris_core *core)\n {\n \tint ret;\n \n-\tret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tret = iris_enable_power_domains(core,\n+\t\t\t\t\tcore->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n \tif (ret)\n \t\treturn ret;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_HW_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);\n \tif (ret)\n \t\tgoto err_disable_power;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK);\n \tif (ret && ret != -ENOENT)\n \t\tgoto err_disable_hw_clock;\n \n-\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);\n+\tret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);\n \tif (ret)\n \t\tgoto err_disable_hw_ahb_clock;\n \n \treturn 0;\n \n err_disable_hw_ahb_clock:\n-\tiris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);\n err_disable_hw_clock:\n-\tiris_disable_unprepare_clock(core, IRIS_HW_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);\n err_disable_power:\n-\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);\n+\tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);\n \n \treturn ret;\n }\n@@ -362,7 +363,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)\n disable_power:\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_CLK);\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);\n-\tiris_disable_unprepare_clock(core, IRIS_AXI1_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);\n \n \tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n \n@@ -379,7 +380,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)\n \tif (ret)\n \t\treturn ret;\n \n-\tret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);\n+\tret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK);\n \tif (ret)\n \t\tgoto err_disable_power;\n \n@@ -396,7 +397,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)\n err_disable_ctrl_free_clk:\n \tiris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);\n err_disable_axi1_clk:\n-\tiris_disable_unprepare_clock(core, IRIS_AXI1_CLK);\n+\tiris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);\n err_disable_power:\n \tiris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);\n \n","prefixes":["v2","07/13"]}