{"id":2227110,"url":"http://patchwork.ozlabs.org/api/patches/2227110/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423085718.70762-10-akhilrajeev@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260423085718.70762-10-akhilrajeev@nvidia.com>","list_archive_url":null,"date":"2026-04-23T08:57:08","name":"[v3,09/13] i3c: dw-i3c-master: Add a quirk to skip clock and reset","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"371ab89c8e8ec2dbe6deed2ec91c9c7e8a10ac43","submitter":{"id":81965,"url":"http://patchwork.ozlabs.org/api/people/81965/?format=json","name":"Akhil R","email":"akhilrajeev@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260423085718.70762-10-akhilrajeev@nvidia.com/mbox/","series":[{"id":501164,"url":"http://patchwork.ozlabs.org/api/series/501164/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501164","date":"2026-04-23T08:56:59","name":"Support ACPI and SETAASA device discovery","version":3,"mbox":"http://patchwork.ozlabs.org/series/501164/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227110/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227110/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n 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sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C","From":"Akhil R ","To":"Alexandre Belloni , Frank Li\n\t, Rob Herring , Krzysztof Kozlowski\n\t, Conor Dooley , \"Rafael J .\n Wysocki\" , Saket Dumbre , \"Len\n Brown\" , Guenter Roeck , Philipp Zabel\n\t, Bjorn Andersson ,\n\tGeert Uytterhoeven , Dmitry Baryshkov\n\t, Arnd Bergmann , \"Eric\n Biggers\" , Wolfram Sang\n\t, Miquel Raynal\n\t, Jon Hunter , \"Thierry\n Reding\" , ,\n\t, ,\n\t, ,\n\t, ","CC":"Akhil R ","Subject":"[PATCH v3 09/13] i3c: dw-i3c-master: Add a quirk to skip clock and\n reset","Date":"Thu, 23 Apr 2026 14:27:08 +0530","Message-ID":"<20260423085718.70762-10-akhilrajeev@nvidia.com>","X-Mailer":"git-send-email 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Apr 2026 09:00:13.3907\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 4c8bca67-68a5-4e63-8388-08dea116bb35","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tCO1PEPF000075F2.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CH1PR12MB9670"},"content":"Some ACPI-enumerated devices like Tegra410 do not have clock and reset\nresources exposed via the clk/reset frameworks. Unlike device tree, ACPI\non Arm does not model such provider functions. The hardware is expected\nto be brought out of reset and have its clocks enabled by the firmware\nbefore the OS takes over. Any data to be shared with the OS is passed\nusing the _DSD property.\n\nAdd a match data for such devices to skip acquiring clock and reset\ncontrols during probe and read the clock rate from the \"clock-frequency\"\n_DSD property. Note that the \"clock-frequency\" here is the controller's\ncore clock and not the bus speed. I3C specifies the bus speed separately\nusing \"i3c-scl-hz\" and \"i2c-scl-hz\" and hence this should not cause any\nconflict.\n\nAlso, move match data parsing before clock/reset acquisition so the quirk\nis available early enough.\n\nSigned-off-by: Akhil R \n---\n drivers/i3c/master/dw-i3c-master.c | 57 ++++++++++++++++++++----------\n 1 file changed, 38 insertions(+), 19 deletions(-)","diff":"diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c\nindex edd42daf7553..b90756ade2db 100644\n--- a/drivers/i3c/master/dw-i3c-master.c\n+++ b/drivers/i3c/master/dw-i3c-master.c\n@@ -242,6 +242,7 @@\n /* List of quirks */\n #define AMD_I3C_OD_PP_TIMING\t\tBIT(1)\n #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK\tBIT(2)\n+#define DW_I3C_ACPI_SKIP_CLK_RST\t\tBIT(3)\n \n struct dw_i3c_cmd {\n \tu32 cmd_lo;\n@@ -556,13 +557,26 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master)\n \twritel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);\n }\n \n+static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *master)\n+{\n+\tunsigned int core_rate_prop;\n+\n+\tif (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST))\n+\t\treturn clk_get_rate(master->core_clk);\n+\n+\tif (device_property_read_u32(master->dev, \"clock-frequency\", &core_rate_prop))\n+\t\treturn 0;\n+\n+\treturn core_rate_prop;\n+}\n+\n static int dw_i3c_clk_cfg(struct dw_i3c_master *master)\n {\n \tunsigned long core_rate, core_period;\n \tu32 scl_timing;\n \tu8 hcnt, lcnt;\n \n-\tcore_rate = clk_get_rate(master->core_clk);\n+\tcore_rate = dw_i3c_master_get_core_rate(master);\n \tif (!core_rate)\n \t\treturn -EINVAL;\n \n@@ -615,7 +629,7 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *master)\n \tu16 hcnt, lcnt;\n \tu32 scl_timing;\n \n-\tcore_rate = clk_get_rate(master->core_clk);\n+\tcore_rate = dw_i3c_master_get_core_rate(master);\n \tif (!core_rate)\n \t\treturn -EINVAL;\n \n@@ -1580,19 +1594,33 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,\n \tif (IS_ERR(master->regs))\n \t\treturn PTR_ERR(master->regs);\n \n-\tmaster->core_clk = devm_clk_get_enabled(&pdev->dev, NULL);\n-\tif (IS_ERR(master->core_clk))\n-\t\treturn PTR_ERR(master->core_clk);\n+\tif (has_acpi_companion(&pdev->dev)) {\n+\t\tquirks = (unsigned long)device_get_match_data(&pdev->dev);\n+\t} else if (pdev->dev.of_node) {\n+\t\tdrvdata = device_get_match_data(&pdev->dev);\n+\t\tif (drvdata)\n+\t\t\tquirks = drvdata->flags;\n+\t}\n+\tmaster->quirks = quirks;\n+\n+\tif (master->quirks & DW_I3C_ACPI_SKIP_CLK_RST) {\n+\t\tmaster->core_clk = NULL;\n+\t\tmaster->core_rst = NULL;\n+\t} else {\n+\t\tmaster->core_clk = devm_clk_get_enabled(&pdev->dev, NULL);\n+\t\tif (IS_ERR(master->core_clk))\n+\t\t\treturn PTR_ERR(master->core_clk);\n+\n+\t\tmaster->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,\n+\t\t\t\t\t\t\t\t\t\t\t\"core_rst\");\n+\t\tif (IS_ERR(master->core_rst))\n+\t\t\treturn PTR_ERR(master->core_rst);\n+\t}\n \n \tmaster->pclk = devm_clk_get_optional_enabled(&pdev->dev, \"pclk\");\n \tif (IS_ERR(master->pclk))\n \t\treturn PTR_ERR(master->pclk);\n \n-\tmaster->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,\n-\t\t\t\t\t\t\t\t\t\t\"core_rst\");\n-\tif (IS_ERR(master->core_rst))\n-\t\treturn PTR_ERR(master->core_rst);\n-\n \tspin_lock_init(&master->xferqueue.lock);\n \tINIT_LIST_HEAD(&master->xferqueue.list);\n \n@@ -1625,15 +1653,6 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,\n \tmaster->maxdevs = ret >> 16;\n \tmaster->free_pos = GENMASK(master->maxdevs - 1, 0);\n \n-\tif (has_acpi_companion(&pdev->dev)) {\n-\t\tquirks = (unsigned long)device_get_match_data(&pdev->dev);\n-\t} else if (pdev->dev.of_node) {\n-\t\tdrvdata = device_get_match_data(&pdev->dev);\n-\t\tif (drvdata)\n-\t\t\tquirks = drvdata->flags;\n-\t}\n-\tmaster->quirks = quirks;\n-\n \t/* Keep controller enabled by preventing runtime suspend */\n \tif (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)\n \t\tpm_runtime_get_noresume(&pdev->dev);\n","prefixes":["v3","09/13"]}