{"id":2227059,"url":"http://patchwork.ozlabs.org/api/patches/2227059/?format=json","web_url":"http://patchwork.ozlabs.org/project/opensbi/patch/20260423052339.356900-7-anup.patel@oss.qualcomm.com/","project":{"id":67,"url":"http://patchwork.ozlabs.org/api/projects/67/?format=json","name":"OpenSBI development","link_name":"opensbi","list_id":"opensbi.lists.infradead.org","list_email":"opensbi@lists.infradead.org","web_url":"https://github.com/riscv/opensbi","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":"https://github.com/riscv/opensbi/commit/{}"},"msgid":"<20260423052339.356900-7-anup.patel@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-23T05:23:39","name":"[6/6] lib: sbi_irqchip: Add support for registering MSI handlers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2748ec97d8c6c2fef69290289f0cf02b8f83a041","submitter":{"id":92322,"url":"http://patchwork.ozlabs.org/api/people/92322/?format=json","name":"Anup Patel","email":"anup.patel@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/opensbi/patch/20260423052339.356900-7-anup.patel@oss.qualcomm.com/mbox/","series":[{"id":501146,"url":"http://patchwork.ozlabs.org/api/series/501146/?format=json","web_url":"http://patchwork.ozlabs.org/project/opensbi/list/?series=501146","date":"2026-04-23T05:23:35","name":"Extend irqchip framework for MSIs and line sensing","version":1,"mbox":"http://patchwork.ozlabs.org/series/501146/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227059/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227059/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=dFn1ryv+;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=AR243kdZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1PfF2MQRz1yGs\n\tfor ; Thu, 23 Apr 2026 15:24:21 +1000 (AEST)","from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wFmXw-0000000B3tP-0w3M;\n\tThu, 23 Apr 2026 05:24:16 +0000","from mx0b-0031df01.pphosted.com ([205.220.180.131])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wFmXs-0000000B3qT-1q4p\n\tfor opensbi@lists.infradead.org;\n\tThu, 23 Apr 2026 05:24:14 +0000","from pps.filterd (m0279868.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63N5B2ve2630173;\n\tThu, 23 Apr 2026 05:23:46 GMT","from apblrppmta01.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dq35r9vj3-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 23 Apr 2026 05:23:46 +0000 (GMT)","from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1])\n\tby APBLRPPMTA01.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id\n 63N5NgWC007147;\n\tThu, 23 Apr 2026 05:23:43 GMT","from pps.reinject (localhost [127.0.0.1])\n\tby APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4dm31jyv26-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 23 Apr 2026 05:23:43 +0000 (GMT)","from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com\n [127.0.0.1])\n\tby pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63N5NfNU007121;\n\tThu, 23 Apr 2026 05:23:42 GMT","from hu-devc-blr-u24-a.qualcomm.com (hu-anuppate-blr.qualcomm.com\n [10.131.36.165])\n\tby APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 63N5NgoO007161\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 23 Apr 2026 05:23:42 +0000 (GMT)","by hu-devc-blr-u24-a.qualcomm.com (Postfix, from userid 486687)\n\tid 0CD4422A6E; Thu, 23 Apr 2026 10:53:41 +0530 (+0530)"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=dX+OvaT9ct2mt/LLC26NAXlklZqOsdfrQrWAJCFLcWA=; b=dFn1ryv+MCI1m6\n\tRibC/Wos9eeTwrOE3ZcrqEjJ4ndN9RVARTWDzKxjjxqu0nX4BX2VODi7HXYUbIsw4uHbjnizJvYzt\n\tB7FOOaGbpbZ/DQlupdc52niTfCBfIg2uh+qqvcbclNfjFG7Pp4skF9+SEYWIPU9sXNzRpi6GCvw1n\n\tvcRwOwdM6Bqkfc+3YsDRSmSn/0VUx29f5NUuia0w7Af+7xqh0kI4dOtjJG+OvEmGT6jURbkNSv1xe\n\t1rFaC5snms4bSa203db4UZdWD5lNcPjWjW6rw46QgPz5PY/IuyMCxnCCl/Wcm9GFWvvlgnOQE/CWB\n\t4B0Kuyubg1QyMVDVI1UA==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:in-reply-to:message-id\n\t:mime-version:references:subject:to; s=qcppdkim1; bh=1jKuHKI5ZR4\n\t1JXbYW2guFj0HyROvlTy9Lx6TdPqxbyc=; b=AR243kdZigCMT05AxtD4LI5vaLz\n\t5GW44wp8cX7PNZF4WXh9qTYePYEYRll51RfchwQgV38ysYu2z328xHE6D5F4teZ5\n\tqu3/3A3T7te5rltXt8FKgCmjd1g4FHTM/OTpJh2Sz5giHrS/3CG3KBvshhFtXR/2\n\tL9uZfL3Lhy2UmATYlI2aeDQeUovt4r7hAk4OfSbIm5KcnjOdRcL1Kufmk0dT8UE5\n\tBmDAkvP+dZYpWKgBLdXWsWml54eGOfsJOAGMPZh5qdAH2dvXiBAeCaCqHU8Cdiyu\n\t5RNA/3wCwN+A0xF7KaJ4Y2So+D0UMKoWy8Tz8d4pjUAy/naDNOIsOvQmp4A=="],"From":"Anup Patel ","To":"Atish Patra ","Cc":"Andrew Jones ,\n Raymond Mao ,\n Dave Patel ,\n Evgeny Voevodin ,\n Samuel Holland ,\n Anup Patel , opensbi@lists.infradead.org,\n Anup Patel ","Subject":"[PATCH 6/6] lib: sbi_irqchip: Add support for registering MSI\n handlers","Date":"Thu, 23 Apr 2026 10:53:39 +0530","Message-ID":"<20260423052339.356900-7-anup.patel@oss.qualcomm.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260423052339.356900-1-anup.patel@oss.qualcomm.com>","References":"<20260423052339.356900-1-anup.patel@oss.qualcomm.com>","MIME-Version":"1.0","X-QCInternal":["smtphost","smtphost"],"X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIzMDA0NyBTYWx0ZWRfXwXvqYHC5QFeA\n 3YQGcbT6SGNTpG5T+FDRmvH1w7Zf18rNoQWSy1GRy4fUsab7kAGc3861S7F05XCHfQ57PBVLvaC\n Tjj7UdZKT0aCu1+3PexVK6JI9Imus1U+/pglT006oCJsVBWLv0MLpaFF+34DwWa/o7LHp07Zl/H\n h5Hv1ipXcobctovCFJqmIGq/EkdTlgZdYv8kN/XRREFyYVOAV+iVhX3S6+bowPC/BUINjvb8CSR\n hMV04RzgbhcS91TWsY2WEqHiFxVUW1dhZCT5A3/RMzNXdabOwPvlkwCJ02lUBwfiT8HOMY6y60m\n +01g9r1p1vqLd9AYhpv0+/6wg9JeYLKwLMUZ+/OdvgVf9aa/eyv0IUWCcdJ49YWOgI3SEq4fYec\n cSZjS6/62AdZQu2ubCaMFqkPXeyvEiCw99HUDJWeJ3wS8mm7lyg8aKD95lwkfeU/cMt5Z5SOGE7\n 8pIUVG7je92bPbXyXUg==","X-Proofpoint-ORIG-GUID":"tvjGY8tAAFChqWbrgrX7nFSGyy3Cjqmh","X-Proofpoint-GUID":"tvjGY8tAAFChqWbrgrX7nFSGyy3Cjqmh","X-Authority-Analysis":"v=2.4 cv=f5J4wuyM c=1 sm=1 tr=0 ts=69e9ace2 cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=ZpdpYltYx_vBUK5n70dp:22 a=W-_n0kkjAAAA:8 a=ZzP6kdRnfcf-SEE31FgA:9\n a=qeNa2pbTr82C0GpJEZFS:22","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_01,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 malwarescore=0\n spamscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230047","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20260422_222412_605984_48339A31 ","X-CRM114-Status":"GOOD ( 17.21 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Some of the drivers (such as APLIC) require capability to\n registers MSI handlers from the parent interrupt controller (such as IMSIC)\n so add sbi_irqchip_register_msi_handler() for this purpose. Signed-off-by:\n Anup Patel --- include/sbi/sbi_irqchip.h | 19\n +++++++++++\n lib/sbi/sbi_irqchip.c | 71 +++++++++++++++++++++++++++++++++++++-- 2 files\n changed, 88 insertions(+), 2 d [...]\n Content analysis details: (-2.7 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low\n trust\n [205.220.180.131 listed in list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]","X-BeenThere":"opensbi@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"opensbi\" ","Errors-To":"opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Some of the drivers (such as APLIC) require capability to registers\nMSI handlers from the parent interrupt controller (such as IMSIC)\nso add sbi_irqchip_register_msi_handler() for this purpose.\n\nSigned-off-by: Anup Patel \n---\n include/sbi/sbi_irqchip.h | 19 +++++++++++\n lib/sbi/sbi_irqchip.c | 71 +++++++++++++++++++++++++++++++++++++--\n 2 files changed, 88 insertions(+), 2 deletions(-)","diff":"diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h\nindex 03a01038..8e7ff573 100644\n--- a/include/sbi/sbi_irqchip.h\n+++ b/include/sbi/sbi_irqchip.h\n@@ -16,6 +16,13 @@\n \n struct sbi_scratch;\n \n+/** irqchip message signalled interrupt (MSI) */\n+struct sbi_irqchip_msi_msg {\n+\tu32 address_lo;\n+\tu32 address_hi;\n+\tu32 data;\n+};\n+\n /** irqchip hardware device */\n struct sbi_irqchip_device {\n \t/** Node in the list of irqchip devices (private) */\n@@ -109,6 +116,18 @@ int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,\n /** Set hardware interrupt affinity */\n int sbi_irqchip_set_affinity(struct sbi_irqchip_device *chip, u32 hwirq, u32 hart_index);\n \n+/** Write MSI message to the hardware interrupt handler */\n+int sbi_irqchip_write_msi(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t const struct sbi_irqchip_msi_msg *msg);\n+\n+/** Register a hardware MSI handler */\n+int sbi_irqchip_register_msi(struct sbi_irqchip_device *chip, u32 num_hwirq,\n+\t\t\t void (*write_msi)(u32 hwirq,\n+\t\t\t\t\t const struct sbi_irqchip_msi_msg *msg,\n+\t\t\t\t\t void *priv),\n+\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv,\n+\t\t\t u32 *out_first_hwirq);\n+\n /** Register a hardware interrupt handler */\n int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\ndiff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c\nindex 386dfd87..5880872c 100644\n--- a/lib/sbi/sbi_irqchip.c\n+++ b/lib/sbi/sbi_irqchip.c\n@@ -35,6 +35,9 @@ struct sbi_irqchip_handler {\n \t/** Number of consecutive hardware IRQs handled by this handler */\n \tu32 num_hwirq;\n \n+\t/** Write MSI function of this handler */\n+\tvoid (*write_msi)(u32 hwirq, const struct sbi_irqchip_msi_msg *msg, void *priv);\n+\n \t/** Callback function of this handler */\n \tint (*callback)(u32 hwirq, void *priv);\n \n@@ -141,6 +144,24 @@ int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,\n \treturn 0;\n }\n \n+int sbi_irqchip_write_msi(struct sbi_irqchip_device *chip, u32 hwirq,\n+\t\t\t const struct sbi_irqchip_msi_msg *msg)\n+{\n+\tstruct sbi_irqchip_handler *h;\n+\n+\tif (!chip || chip->num_hwirq <= hwirq || !msg)\n+\t\treturn SBI_EINVAL;\n+\n+\th = sbi_irqchip_find_handler(chip, hwirq);\n+\tif (!h)\n+\t\treturn SBI_EFAIL;\n+\tif (!h->write_msi)\n+\t\treturn SBI_ENOTSUPP;\n+\n+\th->write_msi(hwirq, msg, h->priv);\n+\treturn 0;\n+}\n+\n int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,\n \t\t\t u32 *out_hart_index)\n {\n@@ -215,6 +236,9 @@ static int __sbi_irqchip_handler_set_affinity(struct sbi_irqchip_device *chip,\n \n static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n+\t\t\t\t\t void (*write_msi)(u32 hwirq,\n+\t\t\t\t\t\t\t const struct sbi_irqchip_msi_msg *msg,\n+\t\t\t\t\t\t\t void *priv),\n \t\t\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv)\n {\n \tstruct sbi_irqchip_handler *h, *th, *nh;\n@@ -232,6 +256,7 @@ static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\treturn SBI_ENOMEM;\n \th->first_hwirq = first_hwirq;\n \th->num_hwirq = num_hwirq;\n+\th->write_msi = write_msi;\n \th->callback = callback;\n \th->priv = priv;\n \n@@ -281,6 +306,48 @@ static int __sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \treturn 0;\n }\n \n+int sbi_irqchip_register_msi(struct sbi_irqchip_device *chip, u32 num_hwirq,\n+\t\t\t void (*write_msi)(u32 hwirq,\n+\t\t\t\t\t const struct sbi_irqchip_msi_msg *msg,\n+\t\t\t\t\t void *priv),\n+\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv,\n+\t\t\t u32 *out_first_hwirq)\n+{\n+\tstruct sbi_irqchip_handler *h;\n+\tbool found;\n+\tu32 hwirq;\n+\n+\tif (!chip || !chip->hwirq_set_affinity || !num_hwirq ||\n+\t !write_msi || !callback || !out_first_hwirq)\n+\t\treturn SBI_EINVAL;\n+\tif (chip->num_hwirq < num_hwirq)\n+\t\treturn SBI_EBAD_RANGE;\n+\n+\thwirq = 0;\n+\tfound = false;\n+\tsbi_list_for_each_entry(h, &chip->handler_list, node) {\n+\t\tif (h->first_hwirq <= hwirq && hwirq < (h->first_hwirq + h->num_hwirq)) {\n+\t\t\thwirq = h->first_hwirq + h->num_hwirq;\n+\t\t} else if (hwirq < h->first_hwirq) {\n+\t\t\tif (h->first_hwirq - hwirq < num_hwirq) {\n+\t\t\t\tfound = true;\n+\t\t\t\tbreak;\n+\t\t\t} else {\n+\t\t\t\thwirq = h->first_hwirq + h->num_hwirq;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (!found && !hwirq)\n+\t\tfound = true;\n+\tif (!found)\n+\t\treturn SBI_ENOSPC;\n+\t*out_first_hwirq = hwirq;\n+\n+\treturn __sbi_irqchip_register_handler(chip, *out_first_hwirq,\n+\t\t\t\t\t num_hwirq, SBI_HWIRQ_FLAGS_NONE,\n+\t\t\t\t\t write_msi, callback, priv);\n+}\n+\n int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\t\t\t u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,\n \t\t\t\t int (*callback)(u32 hwirq, void *priv), void *priv)\n@@ -292,7 +359,7 @@ int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,\n \t\treturn SBI_EBAD_RANGE;\n \n \treturn __sbi_irqchip_register_handler(chip, first_hwirq, num_hwirq, hwirq_flags,\n-\t\t\t\t\t callback, priv);\n+\t\t\t\t\t NULL, callback, priv);\n }\n \n int sbi_irqchip_register_reserved(struct sbi_irqchip_device *chip,\n@@ -305,7 +372,7 @@ int sbi_irqchip_register_reserved(struct sbi_irqchip_device *chip,\n \t\treturn SBI_EBAD_RANGE;\n \n \treturn __sbi_irqchip_register_handler(chip, first_hwirq, num_hwirq,\n-\t\t\t\t\t SBI_HWIRQ_FLAGS_NONE, NULL, NULL);\n+\t\t\t\t\t SBI_HWIRQ_FLAGS_NONE, NULL, NULL, NULL);\n }\n \n int sbi_irqchip_unregister_handler(struct sbi_irqchip_device *chip,\n","prefixes":["6/6"]}