{"id":2227031,"url":"http://patchwork.ozlabs.org/api/patches/2227031/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260423-fix-eliza-pinctrl-v3-3-68b24893ae63@pm.me/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260423-fix-eliza-pinctrl-v3-3-68b24893ae63@pm.me>","list_archive_url":null,"date":"2026-04-23T04:43:37","name":"[v3,3/4] pinctrl: qcom: eliza: Split QUP lane mirror alternates","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3481b3293211a2d05cac55fa42f44135a1d737f2","submitter":{"id":93184,"url":"http://patchwork.ozlabs.org/api/people/93184/?format=json","name":"Alexander Koskovich","email":"akoskovich@pm.me"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260423-fix-eliza-pinctrl-v3-3-68b24893ae63@pm.me/mbox/","series":[{"id":501143,"url":"http://patchwork.ozlabs.org/api/series/501143/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501143","date":"2026-04-23T04:43:19","name":"pinctrl: qcom: eliza: Split up some QUP function groups","version":3,"mbox":"http://patchwork.ozlabs.org/series/501143/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227031/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227031/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=pm.me header.i=@pm.me header.a=rsa-sha256\n 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Message-ID:BIMI-Selector;\n\tb=qOE5wfgoZ6XkYiKUSLX1CSqbZCnXclaOfq8EXxgfrnEHPmtyLcYNhgFcrLx9eB2jq\n\t rbtacEaKCxgx9EffwDzey/Row9PGEVDZl8AecfGAexO17gnpU9dljgL2yi4Zxmh43n\n\t Ft1hnrIY6QKvIBNlQDNY2/s92AuiVPXSg9e+Z7UpcP5uFxOQ3sG/vlsYckczu55Jyi\n\t 6BH3NliK2h4klr+pKRMi3MZ6nhKl6zuCWemMUDCXaLqL7hR64MkdgvQBcOkF0is4Qn\n\t 6CHBqiWpXn0VnwFJZHamXHQ+2rwhWDxfDo56wy0o0eQwtXEjA62FCzTPlJP6W9HOqO\n\t w5wE1aIOC/H5g==","Date":"Thu, 23 Apr 2026 04:43:37 +0000","To":"Bjorn Andersson , Linus Walleij ,\n Rob Herring , Krzysztof Kozlowski ,\n Conor Dooley , Abel Vesa ,\n Konrad Dybcio ","From":"Alexander Koskovich ","Cc":"linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Alexander Koskovich ","Subject":"[PATCH v3 3/4] pinctrl: qcom: eliza: Split QUP lane mirror alternates","Message-ID":"<20260423-fix-eliza-pinctrl-v3-3-68b24893ae63@pm.me>","In-Reply-To":"<20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me>","References":"<20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me>","Feedback-ID":"37836894:user:proton","X-Pm-Message-ID":"ad38e37a1334c1dcecef455f2e4a7a67e19827f7","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable"},"content":"Several QUP lanes have MIRA/MIRB mirror routings which are collapsed\nunder a single function name (e.g. qup1_se6).\n\nThis is an issue because it means there are multiple functions defined\nfor a given pin that share the same name:\n\n[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6...\n\nSo when you select pin 42 and request function qup1_se6, it will select\nthe first instance of it in this group, which just happens to be\nQUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively\nunreachable.\n\nSplit each of these lanes that has an alternative GPIO into their own\nfunction so they can actually be selected, following the pattern seen\nin pinctrl-sm8550.c.\n\nSigned-off-by: Alexander Koskovich \n---\n drivers/pinctrl/qcom/pinctrl-eliza.c | 132 ++++++++++++++++++++++++++++++-----\n 1 file changed, 114 insertions(+), 18 deletions(-)","diff":"diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c\nindex c1f756cbcdeb..8f74756771b8 100644\n--- a/drivers/pinctrl/qcom/pinctrl-eliza.c\n+++ b/drivers/pinctrl/qcom/pinctrl-eliza.c\n@@ -563,15 +563,31 @@ enum eliza_functions {\n \tmsm_mux_qup1_se0,\n \tmsm_mux_qup1_se1,\n \tmsm_mux_qup1_se2,\n+\tmsm_mux_qup1_se2_l2_mira,\n+\tmsm_mux_qup1_se2_l2_mirb,\n+\tmsm_mux_qup1_se2_l3_mira,\n+\tmsm_mux_qup1_se2_l3_mirb,\n \tmsm_mux_qup1_se3,\n \tmsm_mux_qup1_se4,\n \tmsm_mux_qup1_se5,\n \tmsm_mux_qup1_se6,\n+\tmsm_mux_qup1_se6_l1_mira,\n+\tmsm_mux_qup1_se6_l1_mirb,\n+\tmsm_mux_qup1_se6_l3_mira,\n+\tmsm_mux_qup1_se6_l3_mirb,\n \tmsm_mux_qup1_se7,\n+\tmsm_mux_qup1_se7_l0_mira,\n+\tmsm_mux_qup1_se7_l0_mirb,\n+\tmsm_mux_qup1_se7_l1_mira,\n+\tmsm_mux_qup1_se7_l1_mirb,\n \tmsm_mux_qup2_se0,\n \tmsm_mux_qup2_se1,\n \tmsm_mux_qup2_se2,\n \tmsm_mux_qup2_se3,\n+\tmsm_mux_qup2_se3_l0_mira,\n+\tmsm_mux_qup2_se3_l0_mirb,\n+\tmsm_mux_qup2_se3_l1_mira,\n+\tmsm_mux_qup2_se3_l1_mirb,\n \tmsm_mux_qup2_se4,\n \tmsm_mux_qup2_se5,\n \tmsm_mux_qup2_se6,\n@@ -978,7 +994,23 @@ static const char *const qup1_se1_groups[] = {\n };\n \n static const char *const qup1_se2_groups[] = {\n-\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio52\", \"gpio55\", \"gpio53\", \"gpio40\", \"gpio42\", \"gpio30\",\n+\t\"gpio52\", \"gpio53\", \"gpio40\", \"gpio42\", \"gpio30\",\n+};\n+\n+static const char *const qup1_se2_l2_mira_groups[] = {\n+\t\"gpio54\",\n+};\n+\n+static const char *const qup1_se2_l2_mirb_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const qup1_se2_l3_mira_groups[] = {\n+\t\"gpio55\",\n+};\n+\n+static const char *const qup1_se2_l3_mirb_groups[] = {\n+\t\"gpio53\",\n };\n \n static const char *const qup1_se3_groups[] = {\n@@ -994,11 +1026,43 @@ static const char *const qup1_se5_groups[] = {\n };\n \n static const char *const qup1_se6_groups[] = {\n-\t\"gpio40\", \"gpio42\", \"gpio54\", \"gpio42\", \"gpio40\", \"gpio55\",\n+\t\"gpio40\", \"gpio42\",\n+};\n+\n+static const char *const qup1_se6_l1_mira_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const qup1_se6_l1_mirb_groups[] = {\n+\t\"gpio54\",\n+};\n+\n+static const char *const qup1_se6_l3_mira_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char *const qup1_se6_l3_mirb_groups[] = {\n+\t\"gpio55\",\n };\n \n static const char *const qup1_se7_groups[] = {\n-\t\"gpio81\", \"gpio78\", \"gpio80\", \"gpio114\", \"gpio114\", \"gpio78\",\n+\t\"gpio78\", \"gpio114\",\n+};\n+\n+static const char *const qup1_se7_l0_mira_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const char *const qup1_se7_l0_mirb_groups[] = {\n+\t\"gpio78\",\n+};\n+\n+static const char *const qup1_se7_l1_mira_groups[] = {\n+\t\"gpio80\",\n+};\n+\n+static const char *const qup1_se7_l1_mirb_groups[] = {\n+\t\"gpio114\",\n };\n \n static const char *const qup2_se0_groups[] = {\n@@ -1014,7 +1078,23 @@ static const char *const qup2_se2_groups[] = {\n };\n \n static const char *const qup2_se3_groups[] = {\n-\t\"gpio79\", \"gpio116\", \"gpio97\", \"gpio100\", \"gpio100\", \"gpio116\",\n+\t\"gpio100\", \"gpio116\",\n+};\n+\n+static const char *const qup2_se3_l0_mira_groups[] = {\n+\t\"gpio79\",\n+};\n+\n+static const char *const qup2_se3_l0_mirb_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const qup2_se3_l1_mira_groups[] = {\n+\t\"gpio97\",\n+};\n+\n+static const char *const qup2_se3_l1_mirb_groups[] = {\n+\t\"gpio100\",\n };\n \n static const char *const qup2_se4_groups[] = {\n@@ -1236,15 +1316,31 @@ static const struct pinfunction eliza_functions[] = {\n \tMSM_PIN_FUNCTION(qup1_se0),\n \tMSM_PIN_FUNCTION(qup1_se1),\n \tMSM_PIN_FUNCTION(qup1_se2),\n+\tMSM_PIN_FUNCTION(qup1_se2_l2_mira),\n+\tMSM_PIN_FUNCTION(qup1_se2_l2_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se2_l3_mira),\n+\tMSM_PIN_FUNCTION(qup1_se2_l3_mirb),\n \tMSM_PIN_FUNCTION(qup1_se3),\n \tMSM_PIN_FUNCTION(qup1_se4),\n \tMSM_PIN_FUNCTION(qup1_se5),\n \tMSM_PIN_FUNCTION(qup1_se6),\n+\tMSM_PIN_FUNCTION(qup1_se6_l1_mira),\n+\tMSM_PIN_FUNCTION(qup1_se6_l1_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se6_l3_mira),\n+\tMSM_PIN_FUNCTION(qup1_se6_l3_mirb),\n \tMSM_PIN_FUNCTION(qup1_se7),\n+\tMSM_PIN_FUNCTION(qup1_se7_l0_mira),\n+\tMSM_PIN_FUNCTION(qup1_se7_l0_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se7_l1_mira),\n+\tMSM_PIN_FUNCTION(qup1_se7_l1_mirb),\n \tMSM_PIN_FUNCTION(qup2_se0),\n \tMSM_PIN_FUNCTION(qup2_se1),\n \tMSM_PIN_FUNCTION(qup2_se2),\n \tMSM_PIN_FUNCTION(qup2_se3),\n+\tMSM_PIN_FUNCTION(qup2_se3_l0_mira),\n+\tMSM_PIN_FUNCTION(qup2_se3_l0_mirb),\n+\tMSM_PIN_FUNCTION(qup2_se3_l1_mira),\n+\tMSM_PIN_FUNCTION(qup2_se3_l1_mirb),\n \tMSM_PIN_FUNCTION(qup2_se4),\n \tMSM_PIN_FUNCTION(qup2_se5),\n \tMSM_PIN_FUNCTION(qup2_se6),\n@@ -1326,9 +1422,9 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),\n \t[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),\n \t[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),\n-\t[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),\n+\t[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),\n \t[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),\n-\t[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),\n+\t[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),\n \t[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),\n \t[44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),\n \t[45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),\n@@ -1338,10 +1434,10 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),\n \t[50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),\n \t[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),\n-\t[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),\n-\t[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),\n-\t[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),\n-\t[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),\n+\t[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),\n+\t[53] = PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),\n+\t[54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),\n+\t[55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),\n \t[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),\n \t[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),\n \t[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),\n@@ -1364,10 +1460,10 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),\n \t[76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),\n \t[77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),\n-\t[78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),\n-\t[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),\n-\t[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),\n-\t[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),\n+\t[78] = PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _),\n+\t[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _),\n+\t[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _),\n+\t[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _),\n \t[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),\n \t[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),\n \t[84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),\n@@ -1383,10 +1479,10 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),\n \t[95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),\n \t[96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),\n-\t[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),\n+\t[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _),\n \t[98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),\n \t[99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),\n-\t[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),\n+\t[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _),\n \t[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),\n \t[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),\n \t[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),\n@@ -1400,9 +1496,9 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),\n \t[112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),\n \t[113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),\n-\t[114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n+\t[114] = PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n \t[115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),\n-\t[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),\n+\t[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb, _, _, _, _, _, _, _),\n \t[117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),\n \t[118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),\n \t[119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),\n","prefixes":["v3","3/4"]}