{"id":2227015,"url":"http://patchwork.ozlabs.org/api/patches/2227015/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260423010851.46737-2-fengchengwen@huawei.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260423010851.46737-2-fengchengwen@huawei.com>","list_archive_url":null,"date":"2026-04-23T01:08:47","name":"[v3,1/5] PCI/TPH: Export pcie_tph_get_st_modes() for external use","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"aa2d02f7f456dd7a1bdeb3ea114f70044f6833e6","submitter":{"id":92756,"url":"http://patchwork.ozlabs.org/api/people/92756/?format=json","name":"fengchengwen","email":"fengchengwen@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260423010851.46737-2-fengchengwen@huawei.com/mbox/","series":[{"id":501135,"url":"http://patchwork.ozlabs.org/api/series/501135/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501135","date":"2026-04-23T01:08:48","name":"vfio/pci: Add PCIe TPH support","version":3,"mbox":"http://patchwork.ozlabs.org/series/501135/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227015/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227015/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=SMwNCJZz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=WgVWU6zoDpnq0ILk/hO0MLd7A+Ww9qyRKPHUW/8gbP8=;\n\tb=SMwNCJZz/6//HrEFhqfKfJPkbQgfjD0DNTbOIETPsKTUEMtI1AHBDmSR7453z/XOKFv3VPi4P\n\tyzdis+1M5qysYLUw+MnwTLO9Fneu3N+V4wL1jtHg0eENtewYB9P+TqHEy5LnQRK2yCpdWnku+3u\n\toQ43tVRs64jmybrSeJpoKeg=","From":"Chengwen Feng ","To":", ","CC":", ,\n\t, ,\n\t, , ","Subject":"[PATCH v3 1/5] PCI/TPH: Export pcie_tph_get_st_modes() for external\n use","Date":"Thu, 23 Apr 2026 09:08:47 +0800","Message-ID":"<20260423010851.46737-2-fengchengwen@huawei.com>","X-Mailer":"git-send-email 2.17.1","In-Reply-To":"<20260423010851.46737-1-fengchengwen@huawei.com>","References":"<20260423010851.46737-1-fengchengwen@huawei.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain","X-ClientProxiedBy":"kwepems500002.china.huawei.com (7.221.188.17) To\n kwepemk500009.china.huawei.com (7.202.194.94)"},"content":"Export the helper to retrieve supported PCIe TPH steering tag modes so\nthat drivers like VFIO can query and expose device capabilities to\nuserspace.\n\nAnd also add pcie_tph_get_st_table_size() and\npcie_tph_get_st_table_loc() stub implementation in the !CONFIG_PCI_TPH\ncase.\n\nSigned-off-by: Chengwen Feng \nAcked-by: Bjorn Helgaas \n---\n drivers/pci/tph.c | 13 +++++++++++--\n include/linux/pci-tph.h | 7 +++++++\n 2 files changed, 18 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c\nindex 91145e8d9d95..f8767bf6fee9 100644\n--- a/drivers/pci/tph.c\n+++ b/drivers/pci/tph.c\n@@ -145,7 +145,15 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type)\n \tpci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);\n }\n \n-static u8 get_st_modes(struct pci_dev *pdev)\n+/**\n+ * pcie_tph_get_st_modes - Get supported Steering Tag modes\n+ * @pdev: PCI device to query\n+ *\n+ * Return:\n+ * Bitmask of supported ST modes (PCI_TPH_CAP_ST_NS, PCI_TPH_CAP_ST_IV,\n+ * PCI_TPH_CAP_ST_DS)\n+ */\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n {\n \tu32 reg;\n \n@@ -154,6 +162,7 @@ static u8 get_st_modes(struct pci_dev *pdev)\n \n \treturn reg;\n }\n+EXPORT_SYMBOL(pcie_tph_get_st_modes);\n \n /**\n * pcie_tph_get_st_table_loc - Return the device's ST table location\n@@ -400,7 +409,7 @@ int pcie_enable_tph(struct pci_dev *pdev, int mode)\n \n \t/* Sanitize and check ST mode compatibility */\n \tmode &= PCI_TPH_CTRL_MODE_SEL_MASK;\n-\tdev_modes = get_st_modes(pdev);\n+\tdev_modes = pcie_tph_get_st_modes(pdev);\n \tif (!((1 << mode) & dev_modes))\n \t\treturn -EINVAL;\n \ndiff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h\nindex be68cd17f2f8..586c75b19e01 100644\n--- a/include/linux/pci-tph.h\n+++ b/include/linux/pci-tph.h\n@@ -30,6 +30,7 @@ void pcie_disable_tph(struct pci_dev *pdev);\n int pcie_enable_tph(struct pci_dev *pdev, int mode);\n u16 pcie_tph_get_st_table_size(struct pci_dev *pdev);\n u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev);\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev);\n #else\n static inline int pcie_tph_set_st_entry(struct pci_dev *pdev,\n \t\t\t\t\tunsigned int index, u16 tag)\n@@ -41,6 +42,12 @@ static inline int pcie_tph_get_cpu_st(struct pci_dev *dev,\n static inline void pcie_disable_tph(struct pci_dev *pdev) { }\n static inline int pcie_enable_tph(struct pci_dev *pdev, int mode)\n { return -EINVAL; }\n+static inline u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n+{ return 0; }\n+static inline u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n+{ return 0x7FF; /* Values that do not appear in normal case */ }\n+static inline u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n+{ return 0; }\n #endif\n \n #endif /* LINUX_PCI_TPH_H */\n","prefixes":["v3","1/5"]}