{"id":2226943,"url":"http://patchwork.ozlabs.org/api/patches/2226943/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-23-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422214225.2242-23-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-04-22T21:42:10","name":"[v3,22/37] whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c54b2d3bf5fb6f4cd4690f2dd11a34fd7afa47a8","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-23-mohamed@unpredictable.fr/mbox/","series":[{"id":501116,"url":"http://patchwork.ozlabs.org/api/series/501116/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501116","date":"2026-04-22T21:41:48","name":"[v3,01/37] target/i386: emulate: include name of unhandled instruction","version":3,"mbox":"http://patchwork.ozlabs.org/series/501116/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226943/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226943/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=dKcY0fb3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1CVg6BR5z1yD5\n\tfor ; Thu, 23 Apr 2026 07:47:07 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFfLs-0008Pp-Sp; Wed, 22 Apr 2026 17:43:20 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLp-0008Fu-6g\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:43:17 -0400","from p-east2-cluster1-host10-snip4-1.eps.apple.com ([57.103.76.114]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLn-0007PE-Fx\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:43:16 -0400","from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 481531800951; Wed, 22 Apr 2026 21:43:11 +0000 (UTC)","from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n 1F07C180021C; Wed, 22 Apr 2026 21:43:09 +0000 (UTC)"],"X-ICL-Out-Info":"\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAU1fDl4fBBdGGVUERx5dVkAZGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCC0oCWQVZB14LSgdfGlkBXVQXWwxaDlYwTBZDH1IPWxNNGVEBUkVUAgdYRxRHDg8TTAtHAlo0Vh9UGVoD","Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776894194; x=1779486194;\n bh=YHkuVnpzX5n//Dg7yBbo00rWen0/V/dFS7/fQ041cHE=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=dKcY0fb3KVSd0W5I0YxVNQXJI/bxpuVyi3/imm26XaPn98a81iRRw0dOUE4aBnMkIubANS28PSMqNyZrCBA0pM/JFpE4QXcpRIHAPLImx45Md8wjZzkjnoHGfBRQxPwX3qqdlnJD+TDhoVZ/2pEOYy9iC4JQw2uQM4ecXiIKZO9HB5DObg1gCKE2DQC6ARxv0Pr5toKU4Cwc9EKxWcA7NQ9n9Y42pOAAvEJn7OXevq93e4gL8NwAHSV/f8eiqP8ExRHAFnkfsvQAwKWl6hMJ49HJnucpsqpigUnRMXpVTF77Q/di0FYQ7VZSgPLOFpPgKkemLSSst95b5MdgmICWdg==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , qemu-arm@nongnu.org,\n Pierrick Bouvier ,\n Mohamed Mediouni ,\n Roman Bolshakov ,\n \"Michael S. Tsirkin\" , Wei Liu ,\n Phil Dennis-Jordan ,\n Peter Maydell , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v3 22/37] whpx: i386: add HV_X64_MSR_GUEST_IDLE when\n !kernel-irqchip","Date":"Wed, 22 Apr 2026 23:42:10 +0200","Message-ID":"<20260422214225.2242-23-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260422214225.2242-1-mohamed@unpredictable.fr>","References":"<20260422214225.2242-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-GUID":"m9g-lEtEjFVIUQr6zWpTvE6K5sgoJH9B","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIyMDIxMiBTYWx0ZWRfX3M+Y4peERC38\n 7TSnI8/XOW1AbsHICKYBKhc4uwQx/QURAOJWV1F2QoDjkKPgG0eitBMp9a1zhTavTEgSF47YcG2\n gbwue877SPgBfmfT3sE15jWi7Ru25yn29lD2J4YH+0x83tl1BNZfv72pBzPS3DMNgs3e9iXG8mV\n SZHfLkvdKlPSl91bp3OXvUjerc0qwbNr//Obp5fOdDeGjbibN4Fd5vm/BZOnlu0Rul0eshjq24F\n F6XSVbKC1m52KyLKyNgeHwlo6RUeIgRCWU7/2giN5qZp/PikdxTqdzcwQzUU+LVZOI/cvxNKelM\n zs3g5B9UF+iN4HphZ38RbxMbqwBEEJ/T/oIduYSVzqUlXAogMYJeOA+6tXrRUk=","X-Proofpoint-ORIG-GUID":"m9g-lEtEjFVIUQr6zWpTvE6K5sgoJH9B","X-Authority-Info-Out":"v=2.4 cv=VZL6/Vp9 c=1 sm=1 tr=0 ts=69e940f0\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=mSEN7FZ2dYRJNo9PPvgA:9","Received-SPF":"pass client-ip=57.103.76.114;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add support for an oddball HV_X64_MSR_GUEST_IDLE not-quite-an-HLT\nthat wakes the vCPU even if EFLAGS.IF is set.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 46 ++++++++++++++++++++++++++++++++++---\n 1 file changed, 43 insertions(+), 3 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex cafcbf8bbb..f03f5a5115 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -52,6 +52,7 @@\n /* for kernel-irqchip=off */\n #define HV_X64_MSR_APIC_FREQUENCY 0x40000023\n #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073\n+#define HV_X64_MSR_GUEST_IDLE 0x400000f0\n \n static bool is_modern_os = true;\n \n@@ -1628,13 +1629,16 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid)\n }\n }\n \n-static int whpx_handle_halt(CPUState *cpu)\n+static int whpx_handle_halt_generic(CPUState *cpu)\n {\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+\n int ret = 0;\n \n bql_lock();\n if (!(cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) &&\n- (cpu_env(cpu)->eflags & IF_MASK)) &&\n+ ((cpu_env(cpu)->eflags & IF_MASK) || env->hflags2 & HF2_HYPERV_HLT_MASK)) &&\n !cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) {\n cpu->exception_index = EXCP_HLT;\n cpu->halted = true;\n@@ -1645,6 +1649,27 @@ static int whpx_handle_halt(CPUState *cpu)\n return ret;\n }\n \n+static int whpx_handle_halt(CPUState *cpu)\n+{\n+ int ret = 0;\n+\n+ ret = whpx_handle_halt_generic(cpu);\n+\n+ return ret;\n+}\n+\n+static int whpx_handle_hyperv_guestidle(CPUState *cpu)\n+{\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+ int ret = 0;\n+\n+ env->hflags2 |= HF2_HYPERV_HLT_MASK;\n+ ret = whpx_handle_halt_generic(cpu);\n+\n+ return ret;\n+}\n+\n static void whpx_vcpu_kick_out_of_hlt(CPUState *cpu) \n {\n WHV_REGISTER_VALUE reg;\n@@ -1848,9 +1873,10 @@ static void whpx_vcpu_process_async_events(CPUState *cpu)\n }\n \n if ((cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) &&\n- (env->eflags & IF_MASK)) ||\n+ ((env->eflags & IF_MASK) || env->hflags2 & HF2_HYPERV_HLT_MASK)) ||\n cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) {\n cpu->halted = false;\n+ env->hflags2 &= ~HF2_HYPERV_HLT_MASK;\n }\n \n if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) {\n@@ -2120,6 +2146,20 @@ int whpx_vcpu_run(CPUState *cpu)\n }\n }\n \n+ /*\n+ * Windows and Linux both use this MSR.\n+ * Windows 11 25H2 uses it even when not advertised.\n+ */\n+ if (vcpu->exit_ctx.MsrAccess.MsrNumber == HV_X64_MSR_GUEST_IDLE\n+ && !vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite\n+ && !whpx_irqchip_in_kernel()\n+ && whpx->hyperv_enlightenments_enabled) {\n+ is_known_msr = 1;\n+ whpx_bump_rip(cpu, &vcpu->exit_ctx);\n+ ret = whpx_handle_hyperv_guestidle(cpu);\n+ break;\n+ }\n+\n /*\n * Linux tries to use it anyway even when not exposed.\n * Ignore the write as the VP assist page is not used.\n","prefixes":["v3","22/37"]}