{"id":2226941,"url":"http://patchwork.ozlabs.org/api/patches/2226941/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-22-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422214225.2242-22-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-04-22T21:42:09","name":"[v3,21/37] target: i386: HLT type that ignores EFLAGS.IF","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"84702bb1fae36d14aa22e6e9ab321ac3e80fd624","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-22-mohamed@unpredictable.fr/mbox/","series":[{"id":501116,"url":"http://patchwork.ozlabs.org/api/series/501116/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501116","date":"2026-04-22T21:41:48","name":"[v3,01/37] target/i386: emulate: include name of unhandled instruction","version":3,"mbox":"http://patchwork.ozlabs.org/series/501116/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226941/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226941/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=cXNqS4Md;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1CVb1zw2z1yHy\n\tfor ; Thu, 23 Apr 2026 07:47:03 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFfLr-0008NJ-Ol; Wed, 22 Apr 2026 17:43:19 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLm-00089m-B0\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:43:14 -0400","from p-east2-cluster1-host5-snip4-10.eps.apple.com ([57.103.76.93]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLk-0007NA-Lf\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:43:14 -0400","from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 6ED091800227; Wed, 22 Apr 2026 21:43:09 +0000 (UTC)","from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n 44DB518000B2; Wed, 22 Apr 2026 21:43:07 +0000 (UTC)"],"X-ICL-Out-Info":"\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAU1fDl4fBBdGGVUERx5dVkAZGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCC0oCWQVZB14LSgdfGlkAXVQXWwxaDlYwTBZDH1IPWxNNGVEBUkVUAgdYRxRHDg8TTAtHAlo0Vh9UGVoD","Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776894190; x=1779486190;\n bh=9nFB9fdsbicAKGT1x9988h90J9W4/Agy5ocP8yXnAyQ=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=cXNqS4MdcsEou5PVRW7KM2ojkkSWtXg4322MURyGlPBoln9XBjhn6w3qQXL5KWmrxRyCM9d2YSixdUnwcRShuilkQzVlm24x7gBIRFkNAh+AKvSqmJURvkKC+l0tN+CMZTWjt2YL0K9ZxQEJsDxWfZOr5l2wkZQA6oAXvja0jkz3zvs67slb2lG80cWhXtrsx2CthvuPOcnzgBa+9OOY3ikuRyESrgkbekxI9w61uUQzIwlKpPNeN/CsGlb5DSeY8RqffUSxCE1scGjmsErRp0SoLqUgaI7P30ypIzrtL1Ys6BMrDI04YtzLUOd/idMdLWW5pwxRUBC2kmK+tuF/oA==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , qemu-arm@nongnu.org,\n Pierrick Bouvier ,\n Mohamed Mediouni ,\n Roman Bolshakov ,\n \"Michael S. Tsirkin\" , Wei Liu ,\n Phil Dennis-Jordan ,\n Peter Maydell , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v3 21/37] target: i386: HLT type that ignores EFLAGS.IF","Date":"Wed, 22 Apr 2026 23:42:09 +0200","Message-ID":"<20260422214225.2242-22-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260422214225.2242-1-mohamed@unpredictable.fr>","References":"<20260422214225.2242-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-GUID":"BHPSpsv3qBW1sJYK9f2_SKrs0OeWjJne","X-Proofpoint-ORIG-GUID":"BHPSpsv3qBW1sJYK9f2_SKrs0OeWjJne","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIyMDIxMSBTYWx0ZWRfX4qudecbySQhS\n QxlYlP1JAKeIKhYUPwqKmAxp/CTEJVo3/IwOsHQkMQ6fy131oe3+/UalulsdRxxdVomaPv9p2jJ\n cWdPJg9yInlqDcUT8DXQ2SDUxv7mrOU2MXnwvk9B4AmYlTpdtcae2KiRzjzVI9Afki2//nfdg1R\n 10KeyxmEgq3evLucMBbFfwiGNo4zCNHxixTVgbS+kJLwOdHyLu0vWqm8OfJlL25MibrNEmIY/2t\n 1g2gnwH3FvulMYBqqLbqG5BNzNBeMchNTtotcY63XeQ4/TOu97nJTRIHJWMbUcT8rJ8gVND8QgJ\n TLBbdbnwTQi4TemNlIHP+i7WMWg91hVAMzM0QjWrU87LBEthxGh9Tup+tN5msM=","X-Authority-Info-Out":"v=2.4 cv=b7e/I9Gx c=1 sm=1 tr=0 ts=69e940ee\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=ZtXhj7NgbhMgH__AbsQA:9","Received-SPF":"pass client-ip=57.103.76.93;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The TLFS says:\n\n> A partition which possesses the AccessGuestIdleMsr privilege may trigger\n> entry into the virtual processor idle sleep state through a read to the\n> hypervisor-defined MSR HV_X64_MSR_GUEST_IDLE. The virtual processor will\n> be woken when an interrupt arrives, regardless of whether the interrupt\n> is enabled on the virtual processor or not.\n\nMeanwhile, Windows 24H2+ calls this MSR anyway without the privilege being set.\n\nAdd the infrastructure to support it on the generic QEMU side.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/cpu.c | 10 ++++++----\n target/i386/cpu.h | 2 ++\n 2 files changed, 8 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex a5f1a1a8fd..c9ed9b7580 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -10474,13 +10474,15 @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)\n (((env->hflags2 & HF2_VINTR_MASK) &&\n (env->hflags2 & HF2_HIF_MASK)) ||\n (!(env->hflags2 & HF2_VINTR_MASK) &&\n- (env->eflags & IF_MASK &&\n- !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {\n+ ((env->eflags & IF_MASK &&\n+ !(env->hflags & HF_INHIBIT_IRQ_MASK))\n+ || env->hflags2 & HF2_HYPERV_HLT_MASK)))) {\n return CPU_INTERRUPT_HARD;\n } else if (env->hflags2 & HF2_VGIF_MASK) {\n if((interrupt_request & CPU_INTERRUPT_VIRQ) &&\n- (env->eflags & IF_MASK) &&\n- !(env->hflags & HF_INHIBIT_IRQ_MASK)) {\n+ ((env->eflags & IF_MASK &&\n+ !(env->hflags & HF_INHIBIT_IRQ_MASK))\n+ || env->hflags2 & HF2_HYPERV_HLT_MASK)) {\n return CPU_INTERRUPT_VIRQ;\n }\n }\ndiff --git a/target/i386/cpu.h b/target/i386/cpu.h\nindex 0b539155c4..67f508dc10 100644\n--- a/target/i386/cpu.h\n+++ b/target/i386/cpu.h\n@@ -225,6 +225,7 @@ typedef enum X86Seg {\n #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */\n #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */\n #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/\n+#define HF2_HYPERV_HLT_SHIFT 9 /* Hyper-V HV_X64_MSR_GUEST_IDLE */\n \n #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)\n #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)\n@@ -235,6 +236,7 @@ typedef enum X86Seg {\n #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)\n #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)\n #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)\n+#define HF2_HYPERV_HLT_MASK (1 << HF2_HYPERV_HLT_SHIFT)\n \n #define CR0_PE_SHIFT 0\n #define CR0_MP_SHIFT 1\n","prefixes":["v3","21/37"]}