{"id":2226932,"url":"http://patchwork.ozlabs.org/api/patches/2226932/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-14-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422214225.2242-14-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-04-22T21:42:01","name":"[v3,13/37] whpx: i386: interrupt priority support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a8928d6db7320caa8f26526718c6a0a6a64b31e1","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-14-mohamed@unpredictable.fr/mbox/","series":[{"id":501116,"url":"http://patchwork.ozlabs.org/api/series/501116/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501116","date":"2026-04-22T21:41:48","name":"[v3,01/37] target/i386: emulate: include name of unhandled instruction","version":3,"mbox":"http://patchwork.ozlabs.org/series/501116/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226932/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226932/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=UBBbu64e;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1CTJ2Y5Dz1yD5\n\tfor ; Thu, 23 Apr 2026 07:45:56 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFfLf-00086D-1D; Wed, 22 Apr 2026 17:43:07 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLZ-00083v-Q0\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:43:01 -0400","from p-east2-cluster1-host4-snip4-10.eps.apple.com ([57.103.76.23]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLY-0007Hh-7a\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:43:01 -0400","from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 4D58218000A2; Wed, 22 Apr 2026 21:42:54 +0000 (UTC)","from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n 6250E1800216; Wed, 22 Apr 2026 21:42:52 +0000 (UTC)"],"X-ICL-Out-Info":"\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAU1fDl4fBBdGGVUERx5dVkAZGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCC0oCWQVZB14LSgdfGloGXVQXWwxaDlYwTBZDH1IPWxNNGVEBUkVUAgdYRxRHDg8TTAtHAlo0Vh9UGVoD","Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776894179; x=1779486179;\n bh=PTJ2O4Ojv4UoqiVrgxlmPkb95gxJ24lLpPPfWfj3pTE=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=UBBbu64ezrW4xm28OIPiijFWV/efay9SO+d/spZIe5hQ8qvIQmxiDbQu+uXaQ0U47tbeUfmVwr9zHnWrIHiYZ49DfWtTEE8T5B7fAYuFtYYIZMSYuiZCZfuQ0cK3+5VksYF/q7yxiDyf5VmlPQG+FHxV4yAx8S3Z4NpbSziPRRSx0CaRI7xIBKZ3yXw4wCXbum0oCVXSDUOGifCHinaBza1KR/UH9i2kw6Cjr9Jjxx9DJZ7vFQ27hS2s3KfGzQGro/WiCf+vK8NdSqG0WIxtt2Yp+vDjd1DYm9mwwxlCGlcQbyPv74Uj4cNPvJe/xdyr350LfWfAz50FlcWbPg2KPA==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , qemu-arm@nongnu.org,\n Pierrick Bouvier ,\n Mohamed Mediouni ,\n Roman Bolshakov ,\n \"Michael S. Tsirkin\" , Wei Liu ,\n Phil Dennis-Jordan ,\n Peter Maydell , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v3 13/37] whpx: i386: interrupt priority support","Date":"Wed, 22 Apr 2026 23:42:01 +0200","Message-ID":"<20260422214225.2242-14-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260422214225.2242-1-mohamed@unpredictable.fr>","References":"<20260422214225.2242-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-GUID":"LdGl3CKip8ZBmp7o0_q-RZmnF_WqXqNx","X-Proofpoint-ORIG-GUID":"LdGl3CKip8ZBmp7o0_q-RZmnF_WqXqNx","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIyMDIxMSBTYWx0ZWRfXz7fAEydlgM13\n ZZt1rvLa3t6qelWKBNTaKAhHFWUoxAO/reMnIJRReWwfcRt2w8D2ST+kXQHDAnbQNB754V6Gv/t\n Q2FTaIQE1ZuYKCH+JWktZEzy4uosHRvgW0YuQ+0MThacD9FslkKJfI9sBGz7t8pxqemP1O2vjRj\n VWvef4jFF6azCQK0igYH+SpOuqCkHMrXn4kpHTnY4BsHUiieAr7v1RQELb+iUZuoBsyHOAVgrkO\n jAQEyC+CPMwAr3RkJXOUVYaaERqFE36isfl5oFKolFe1PLif83QZ+zho5tAgviH/Bbw1jK+suID\n gLhwgP7fSKIjzIx6Je+BrhdIgFbN2vdP5DHM60bM3hwfmsJGRtmT/7paBrC7L8=","X-Authority-Info-Out":"v=2.4 cv=b7e/I9Gx c=1 sm=1 tr=0 ts=69e940e1\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=NuKELtICf0aykZwt-QIA:9","Received-SPF":"pass client-ip=57.103.76.23;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Implement APIC IRR interrupt priorities.\n\nEven with kernel-irqchip=off, Hyper-V is aware of interrupt priorities\nand implements CR8/TPR, with the InterruptPriority field being followed.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 24 ++++++++++++++++++++----\n 1 file changed, 20 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex cbcf1de7ae..012fa6d021 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -1673,6 +1673,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n UINT32 reg_count = 0;\n WHV_REGISTER_VALUE reg_values[3];\n WHV_REGISTER_NAME reg_names[3];\n+ int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);\n \n memset(&new_int, 0, sizeof(new_int));\n memset(reg_values, 0, sizeof(reg_values));\n@@ -1708,10 +1709,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n }\n \n+ if (irr == -1) {\n+ if (isa_pic != NULL && pic_get_output(isa_pic)) {\n+ /* In case it's a PIC interrupt */\n+ irr = 0;\n+ } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n+ abort();\n+ }\n+ }\n+\n /* Get pending hard interruption or replay one that was overwritten */\n if (!whpx_irqchip_in_kernel()) {\n if (!vcpu->interruption_pending &&\n- vcpu->interruptable && (env->eflags & IF_MASK)) {\n+ vcpu->interruptable && (env->eflags & IF_MASK)\n+ && (vcpu->tpr < irr || irr == 0)) {\n assert(!new_int.InterruptionPending);\n if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);\n@@ -1768,13 +1779,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Update the state of the interrupt delivery notification */\n- if (!vcpu->window_registered &&\n+ if ((!vcpu->window_registered ||\n+ (vcpu->window_priority < irr && vcpu->window_priority != 0) ||\n+ (irr == 0 && vcpu->window_priority != 0)) &&\n cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n reg_values[reg_count].DeliverabilityNotifications =\n (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {\n- .InterruptNotification = 1\n+ .InterruptNotification = 1,\n+ .InterruptPriority = irr >> 4\n };\n vcpu->window_registered = 1;\n+ vcpu->window_priority = irr;\n reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;\n reg_count += 1;\n }\n@@ -1788,7 +1803,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n reg_names, reg_count, reg_values);\n if (FAILED(hr)) {\n error_report(\"WHPX: Failed to set interrupt state registers,\"\n- \" hr=%08lx\", hr);\n+ \" hr=%08lx, InterruptPriority=%i\", hr, irr >> 4);\n }\n }\n }\n@@ -2004,6 +2019,7 @@ int whpx_vcpu_run(CPUState *cpu)\n case WHvRunVpExitReasonX64InterruptWindow:\n vcpu->ready_for_pic_interrupt = 1;\n vcpu->window_registered = 0;\n+ vcpu->window_priority = 0;\n ret = 0;\n break;\n \n","prefixes":["v3","13/37"]}