{"id":2226916,"url":"http://patchwork.ozlabs.org/api/patches/2226916/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-10-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422214225.2242-10-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-04-22T21:41:57","name":"[v3,09/37] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fdf8a7880917f8e1e26cefbbd6846b1aeb98968d","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422214225.2242-10-mohamed@unpredictable.fr/mbox/","series":[{"id":501116,"url":"http://patchwork.ozlabs.org/api/series/501116/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501116","date":"2026-04-22T21:41:48","name":"[v3,01/37] target/i386: emulate: include name of unhandled instruction","version":3,"mbox":"http://patchwork.ozlabs.org/series/501116/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226916/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226916/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=FX8zhnx9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1CRZ4g8gz1yDD\n\tfor ; Thu, 23 Apr 2026 07:44:26 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFfLU-00080z-Cq; Wed, 22 Apr 2026 17:42:56 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLP-0007xh-MM\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:42:51 -0400","from p-east2-cluster1-host3-snip4-4.eps.apple.com ([57.103.76.7]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFfLN-00073Z-JK\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 17:42:51 -0400","from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 3BA5018006EB; Wed, 22 Apr 2026 21:42:47 +0000 (UTC)","from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n F33FD18006EF; Wed, 22 Apr 2026 21:42:44 +0000 (UTC)"],"X-ICL-Out-Info":"\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAU1fDl4fBBdGGVUERx5dVkAZGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCC0oCWQVZB14LSgdfGloCXVQXWwxaDlYwTBZDH1IPWxNNGVEBUkVUAgdYRxRHDg8TTAtHAlo0Vh9UGVoD","Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776894168; x=1779486168;\n bh=xC+Bs3uetls1lV4cbRHxGlDX60WBtwmt4XZ2tgs35W4=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=FX8zhnx9un9lq+vPVZR/6suJow+FoEhwvsex4G9QGjBpFeRiLskhaGCAUdw/ZwvXWif0AnE7u93dv/0rywtMCnLuFyC1XC/sZmPPVx3kNFpW9n35aEBY2pHXxOXiNdqmhgsnHJy19layazFBqA2f4f4cgr9bNwvktKl/tW8j8BLLaPpVSqAq+aexhR392mc+8SrevRzly5d8/+EhWzgtf9BtmAMraaJx3u8x1SbH+0E8mhBwOnJM6RICwIKm0Ffykgu9mrkhH36tOnE7NKsi/SV7YnZjWUBBiKn5yXYgf93Bd/DEakHQfBT1O0U2r0CLBmahd+zdz+ewhr3+s7uALg==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , qemu-arm@nongnu.org,\n Pierrick Bouvier ,\n Mohamed Mediouni ,\n Roman Bolshakov ,\n \"Michael S. Tsirkin\" , Wei Liu ,\n Phil Dennis-Jordan ,\n Peter Maydell , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v3 09/37] whpx: i386: use WHvX64RegisterCr8 only when\n kernel-irqchip=off","Date":"Wed, 22 Apr 2026 23:41:57 +0200","Message-ID":"<20260422214225.2242-10-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260422214225.2242-1-mohamed@unpredictable.fr>","References":"<20260422214225.2242-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"Z5xbyGaJV_Pcac9j1vRLLqbhhM1-6Ptm","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIyMDIxMSBTYWx0ZWRfX1cBEdaCOIBYI\n eFHc9mYgGClgsMvCEs8kl8TlAmJrihicnPiqjpEf82VCBYRNEqWAcmjVfFcLpStA8Udm0kF6wvW\n WeRznUely+ou/1QLaeUabqA4T9t9aGYx0eZ7b7LY27WOsip/gZSM/9+x3Zns0eDs2eWljTXvwOB\n nfKpXOyqBvQBjNntsBjt7ObET6JRi8pjjt0az3d6fuo3p11eOr/pGFJu31yjIdXFcC3P7JtfJDS\n vu/ZV+eVp+FdWmno+Y2WITWiuWUgfpehT5w16BrvE/fPUPF9nBV3BuizdPMQ7bDH6ERoC9qsq+H\n +flNOQVWZk7CRG8w6ePvq6EpJrPEn+Zp2TaLoT8t+KCShfjkeKxVYlgSoCE3z0=","X-Authority-Info-Out":"v=2.4 cv=Kf/fcAYD c=1 sm=1 tr=0 ts=69e940d8\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=CtoYo02lv3ougeLbNZoA:9","X-Proofpoint-GUID":"Z5xbyGaJV_Pcac9j1vRLLqbhhM1-6Ptm","Received-SPF":"pass client-ip=57.103.76.7;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When kernel-irqchip=on, manage TPR as part of the APIC state instead entirely.\n\nThis fixes some failure to set state errors.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 15 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex d470c5b9d3..03c146dfb8 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -95,7 +95,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n WHvX64RegisterCr2,\n WHvX64RegisterCr3,\n WHvX64RegisterCr4,\n- WHvX64RegisterCr8,\n \n /* X64 Debug Registers */\n /*\n@@ -478,8 +477,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n vcxt.values[idx++].Reg64 = env->cr[3];\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n vcxt.values[idx++].Reg64 = env->cr[4];\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- vcxt.values[idx++].Reg64 = vcpu->tpr;\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ WHV_REGISTER_VALUE cr8 = {.Reg64 = vcpu->tpr};\n+ whpx_set_reg(cpu, WHvX64RegisterCr8, cr8);\n+ }\n \n /* 8 Debug Registers - Skipped */\n \n@@ -735,11 +737,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->cr[3] = vcxt.values[idx++].Reg64;\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n env->cr[4] = vcxt.values[idx++].Reg64;\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- tpr = vcxt.values[idx++].Reg64;\n- if (tpr != vcpu->tpr) {\n- vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (tpr != vcpu->tpr) {\n+ vcpu->tpr = tpr;\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+ }\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1745,7 +1750,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n- if (tpr != vcpu->tpr) {\n+ if (!whpx_irqchip_in_kernel() && tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n qatomic_set(&cpu->exit_request, true);\n@@ -1787,12 +1792,14 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n \n env->eflags = vcpu->exit_ctx.VpContext.Rflags;\n \n- uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n- if (vcpu->tpr != tpr) {\n- vcpu->tpr = tpr;\n- bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n- bql_unlock();\n+ if (!whpx_irqchip_in_kernel()) {\n+ uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (vcpu->tpr != tpr) {\n+ vcpu->tpr = tpr;\n+ bql_lock();\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n+ bql_unlock();\n+ }\n }\n \n vcpu->interruption_pending =\n","prefixes":["v3","09/37"]}