{"id":2226882,"url":"http://patchwork.ozlabs.org/api/patches/2226882/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.12@forge-stage.sourceware.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-22T19:01:46","name":"[v2,12/14] arm: [MVE intrinsics] rework sqrshr sqshl srshr uqrshl uqshl urshr","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ebd97e284dc8f9058705622b94db827c46cd8611","submitter":{"id":92734,"url":"http://patchwork.ozlabs.org/api/people/92734/?format=json","name":"Christophe Lyon via Sourceware Forge","email":"forge-bot+clyon@forge-stage.sourceware.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.12@forge-stage.sourceware.org/mbox/","series":[{"id":501104,"url":"http://patchwork.ozlabs.org/api/series/501104/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501104","date":"2026-04-22T19:01:35","name":"arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts","version":2,"mbox":"http://patchwork.ozlabs.org/series/501104/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226882/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226882/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org","sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org","server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Bbv05jdz1yD5\n\tfor ; Thu, 23 Apr 2026 07:06:35 +1000 (AEST)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id D2FCD4CCFF2C\n\tfor ; Wed, 22 Apr 2026 21:04:19 +0000 (GMT)","from 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b=XGwXVQwLin9X1LOmPlkrzWA/ifwNgiT1E1pF1bBRsdGdrDA7vsALP1cuC9rd4D2HqL78KXBWGzasezIvMwZT7BSGjWCm2OBC1vtiBnbT6zQ/6yN0vlTAFNR+7fbhqGQJ96ofSKs8/5FFtvKZgYv00Molm5MS0WcgG1tbIY/TI4U=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776884570; c=relaxed/simple;\n bh=yGtSEd8kZRlBh9CLe0cITXwjt4V7i0zwcKJwkbuce9E=;\n h=From:Date:Subject:To:Message-ID;\n b=gO7UL+LAegCbG8+S00z04tHS4utyBcw0tKA2+HoocJtSPCyIsbLmCOlQVug/CuwZEwdqnKAG13hYCb7BL50/j3HtNaxfSIapWbEL1Pb6T/tEqZVqBJGpyNZvNGeIlUwVHSf3FS0E+ddI6ibs4EPi+kD+jfFmcScvEbSctlsRlsU=","ARC-Authentication-Results":"i=1; server2.sourceware.org","From":"Christophe Lyon via Sourceware Forge\n ","Date":"Wed, 22 Apr 2026 19:01:46 +0000","Subject":"[PATCH v2 12/14] arm: [MVE intrinsics] rework sqrshr sqshl srshr\n uqrshl uqshl urshr","To":"gcc-patches mailing list ","Cc":"sloosemore@baylibre.com","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/121","References":"\n ","In-Reply-To":"\n ","X-Patch-URL":"\n https://forge.sourceware.org/clyon/gcc-TEST/commit/6232c033bf5572575994964663d10deda77b86f1","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"gcc-patches mailing list ,\n sloosemore@baylibre.com, clyon@gcc.gnu.org","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Christophe Lyon \n\nImplement sqrshr, sqshl, srshr, uqrshl, uqshl and urshr using the new\nMVE builtins framework.\n\nThe patch fixes a probable copy/paste typo in mve_sqshl_si and\nmve_srshr_si: operand 1 should have mode SI, and not DI.\n\ngcc/ChangeLog:\n\n\t* config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift):\n\tAdd ss_SQRSHR, ss_SQSHL, ss_SRSHR, ss_UQRSHL, ss_UQSHL, and\n\tss_URSHR.\n\t(mve_function_scalar_shift): Add support for ss_SQRSHR, ss_SQSHL,\n\tss_SRSHR, ss_UQRSHL, ss_UQSHL, and ss_URSHR.\n\t(sqrshr, sqshl, srshr, uqrshl, uqshl, urshr): New.\n\t* config/arm/arm-mve-builtins-base.def (sqrshr, sqshl, srshr)\n\t(uqrshl, uqshl, urshr): New.\n\t* config/arm/arm-mve-builtins-base.h (sqrshr, sqshl, srshr)\n\t(uqrshl, uqshl, urshr): New.\n\t* config/arm/arm-mve-builtins-shapes.cc (scalar_s32_shift): New.\n\t(scalar_s32_shift_imm): New.\n\t(scalar_u32_shift): New.\n\t(scalar_u32_shift_imm): New.\n\t* config/arm/arm-mve-builtins-shapes.h (scalar_s32_shift): New.\n\t(scalar_s32_shift_imm): New.\n\t(scalar_u32_shift): New.\n\t(scalar_u32_shift_imm): New.\n\t* config/arm/arm_mve.h (sqrshr): Delete.\n\t(sqshl): Delete.\n\t(srshr): Delete.\n\t(uqrshl): Delete.\n\t(uqshl): Delete.\n\t(urshr): Delete.\n\t(__arm_uqrshl): Delete.\n\t(__arm_sqrshr): Delete.\n\t(__arm_uqshl): Delete.\n\t(__arm_urshr): Delete.\n\t(__arm_sqshl): Delete.\n\t(__arm_srshr): Delete.\n\t* config/arm/mve.md (mve_sqshl_si, mve_srshr_si): Fix operand 1\n\tmode.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.target/arm/mve/intrinsics/sqshl_check_shift.c: New test.\n\t* gcc.target/arm/mve/intrinsics/srshr_check_shift.c: New test.\n\t* gcc.target/arm/mve/intrinsics/uqshl_check_shift.c: New test.\n\t* gcc.target/arm/mve/intrinsics/urshr_check_shift.c: New test.\n---\n gcc/config/arm/arm-mve-builtins-base.cc | 36 +++++++++\n gcc/config/arm/arm-mve-builtins-base.def | 6 ++\n gcc/config/arm/arm-mve-builtins-base.h | 6 ++\n gcc/config/arm/arm-mve-builtins-shapes.cc | 76 +++++++++++++++++++\n gcc/config/arm/arm-mve-builtins-shapes.h | 4 +\n gcc/config/arm/arm_mve.h | 48 ------------\n gcc/config/arm/mve.md | 4 +-\n .../arm/mve/intrinsics/sqshl_check_shift.c | 24 ++++++\n .../arm/mve/intrinsics/srshr_check_shift.c | 24 ++++++\n .../arm/mve/intrinsics/uqshl_check_shift.c | 24 ++++++\n .../arm/mve/intrinsics/urshr_check_shift.c | 24 ++++++\n 11 files changed, 226 insertions(+), 50 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl_check_shift.c\n create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr_check_shift.c","diff":"diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc\nindex bcb97108b594..c36c64a16d66 100644\n--- a/gcc/config/arm/arm-mve-builtins-base.cc\n+++ b/gcc/config/arm/arm-mve-builtins-base.cc\n@@ -1246,13 +1246,19 @@ public:\n enum which_scalar_shift {\n ss_ASRL,\n ss_LSLL,\n+ ss_SQRSHR,\n ss_SQRSHRL,\n ss_SQRSHRL_SAT48,\n+ ss_SQSHL,\n ss_SQSHLL,\n+ ss_SRSHR,\n ss_SRSHRL,\n+ ss_UQRSHL,\n ss_UQRSHLL,\n ss_UQRSHLL_SAT48,\n+ ss_UQSHL,\n ss_UQSHLL,\n+ ss_URSHR,\n ss_URSHRL\n };\n \n@@ -1283,6 +1289,10 @@ public:\n \tcode = CODE_FOR_mve_lsll;\n \tbreak;\n \n+ case ss_SQRSHR:\n+\tcode = CODE_FOR_mve_sqrshr_si;\n+\tbreak;\n+\n case ss_SQRSHRL:\n \tcode = code_for_mve_sqrshrl_sat_di (SQRSHRL_64);\n \tbreak;\n@@ -1291,6 +1301,18 @@ public:\n \tcode = code_for_mve_sqrshrl_sat_di (SQRSHRL_48);\n \tbreak;\n \n+ case ss_SQSHL:\n+\tcode = CODE_FOR_mve_sqshl_si;\n+\tbreak;\n+\n+ case ss_SRSHR:\n+\tcode = CODE_FOR_mve_srshr_si;\n+\tbreak;\n+\n+ case ss_UQRSHL:\n+\tcode = CODE_FOR_mve_uqrshl_si;\n+\tbreak;\n+\n case ss_SQSHLL:\n \tcode = CODE_FOR_mve_sqshll_di;\n \tbreak;\n@@ -1307,10 +1329,18 @@ public:\n \tcode = code_for_mve_uqrshll_sat_di (UQRSHLL_48);\n \tbreak;\n \n+ case ss_UQSHL:\n+\tcode = CODE_FOR_mve_uqshl_si;\n+\tbreak;\n+\n case ss_UQSHLL:\n \tcode = CODE_FOR_mve_uqshll_di;\n \tbreak;\n \n+ case ss_URSHR:\n+\tcode = CODE_FOR_mve_urshr_si;\n+\tbreak;\n+\n case ss_URSHRL:\n \tcode = CODE_FOR_mve_urshrl_di;\n \tbreak;\n@@ -1492,13 +1522,19 @@ namespace arm_mve {\n \n FUNCTION (asrl, mve_function_scalar_shift, (ss_ASRL))\n FUNCTION (lsll, mve_function_scalar_shift, (ss_LSLL))\n+FUNCTION (sqrshr, mve_function_scalar_shift, (ss_SQRSHR))\n FUNCTION (sqrshrl, mve_function_scalar_shift, (ss_SQRSHRL))\n FUNCTION (sqrshrl_sat48, mve_function_scalar_shift, (ss_SQRSHRL_SAT48))\n+FUNCTION (sqshl, mve_function_scalar_shift, (ss_SQSHL))\n FUNCTION (sqshll, mve_function_scalar_shift, (ss_SQSHLL))\n+FUNCTION (srshr, mve_function_scalar_shift, (ss_SRSHR))\n FUNCTION (srshrl, mve_function_scalar_shift, (ss_SRSHRL))\n+FUNCTION (uqrshl, mve_function_scalar_shift, (ss_UQRSHL))\n FUNCTION (uqrshll, mve_function_scalar_shift, (ss_UQRSHLL))\n FUNCTION (uqrshll_sat48, mve_function_scalar_shift, (ss_UQRSHLL_SAT48))\n+FUNCTION (uqshl, mve_function_scalar_shift, (ss_UQSHL))\n FUNCTION (uqshll, mve_function_scalar_shift, (ss_UQSHLL))\n+FUNCTION (urshr, mve_function_scalar_shift, (ss_URSHR))\n FUNCTION (urshrl, mve_function_scalar_shift, (ss_URSHRL))\n FUNCTION_PRED_P_S_U (vabavq, VABAVQ)\n FUNCTION_WITHOUT_N (vabdq, VABDQ)\ndiff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def\nindex f46ce835596c..9b9603e87b00 100644\n--- a/gcc/config/arm/arm-mve-builtins-base.def\n+++ b/gcc/config/arm/arm-mve-builtins-base.def\n@@ -20,13 +20,19 @@\n #define REQUIRES_FLOAT false\n DEF_MVE_FUNCTION (asrl, scalar_s64_shift, none, none)\n DEF_MVE_FUNCTION (lsll, scalar_u64_shift, none, none)\n+DEF_MVE_FUNCTION (sqrshr, scalar_s32_shift, none, none)\n DEF_MVE_FUNCTION (sqrshrl, scalar_s64_shift, none, none)\n DEF_MVE_FUNCTION (sqrshrl_sat48, scalar_s64_shift, none, none)\n+DEF_MVE_FUNCTION (sqshl, scalar_s32_shift_imm, none, none)\n DEF_MVE_FUNCTION (sqshll, scalar_s64_shift_imm, none, none)\n+DEF_MVE_FUNCTION (srshr, scalar_s32_shift_imm, none, none)\n DEF_MVE_FUNCTION (srshrl, scalar_s64_shift_imm, none, none)\n+DEF_MVE_FUNCTION (uqrshl, scalar_u32_shift, none, none)\n DEF_MVE_FUNCTION (uqrshll, scalar_u64_shift, none, none)\n DEF_MVE_FUNCTION (uqrshll_sat48, scalar_u64_shift, none, none)\n+DEF_MVE_FUNCTION (uqshl, scalar_u32_shift_imm, none, none)\n DEF_MVE_FUNCTION (uqshll, scalar_u64_shift_imm, none, none)\n+DEF_MVE_FUNCTION (urshr, scalar_u32_shift_imm, none, none)\n DEF_MVE_FUNCTION (urshrl, scalar_u64_shift_imm, none, none)\n DEF_MVE_FUNCTION (vabavq, binary_acca_int32, all_integer, p_or_none)\n DEF_MVE_FUNCTION (vabdq, binary, all_integer, mx_or_none)\ndiff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h\nindex 37302621d0b1..60bf51bb7521 100644\n--- a/gcc/config/arm/arm-mve-builtins-base.h\n+++ b/gcc/config/arm/arm-mve-builtins-base.h\n@@ -25,13 +25,19 @@ namespace functions {\n \n extern const function_base *const asrl;\n extern const function_base *const lsll;\n+extern const function_base *const sqrshr;\n extern const function_base *const sqrshrl;\n extern const function_base *const sqrshrl_sat48;\n+extern const function_base *const sqshl;\n extern const function_base *const sqshll;\n+extern const function_base *const srshr;\n extern const function_base *const srshrl;\n+extern const function_base *const uqrshl;\n extern const function_base *const uqrshll;\n extern const function_base *const uqrshll_sat48;\n+extern const function_base *const uqshl;\n extern const function_base *const uqshll;\n+extern const function_base *const urshr;\n extern const function_base *const urshrl;\n extern const function_base *const vabavq;\n extern const function_base *const vabdq;\ndiff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc\nindex f75c7095d949..741c582cef4d 100644\n--- a/gcc/config/arm/arm-mve-builtins-shapes.cc\n+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc\n@@ -1723,6 +1723,82 @@ struct mvn_def : public overloaded_base<0>\n };\n SHAPE (mvn)\n \n+/* int32_t foo(int32_t, int32_t)\n+\n+ Example: sqrshr.\n+ int32_t [__arm_]sqrshr(int32_t value, int32_t shift) */\n+struct scalar_s32_shift_def : public nonoverloaded_base\n+{\n+ void\n+ build (function_builder &b, const function_group_info &group,\n+\t bool preserve_user_namespace) const override\n+ {\n+ build_all (b, \"ss32,ss32,ss32\", group, MODE_none, preserve_user_namespace);\n+ }\n+};\n+SHAPE (scalar_s32_shift)\n+\n+/* int32_t foo(int32_t, const int)\n+\n+ Check that 'shift' is in the [1,32] range.\n+\n+ Example: sqshl.\n+ int32_t [__arm_]sqshl(int32_t value, const int shift) */\n+struct scalar_s32_shift_imm_def : public nonoverloaded_base\n+{\n+ void\n+ build (function_builder &b, const function_group_info &group,\n+\t bool preserve_user_namespace) const override\n+ {\n+ build_all (b, \"ss32,ss32,su64\", group, MODE_none, preserve_user_namespace);\n+ }\n+\n+ bool\n+ check (function_checker &c) const override\n+ {\n+ return c.require_immediate_range (1, 1, 32);\n+ }\n+};\n+SHAPE (scalar_s32_shift_imm)\n+\n+/* uint32_t foo(uint32_t, int32_t)\n+\n+ Example: uqrshl.\n+ uint32_t [__arm_]uqrshl(uint32_t value, int32_t shift) */\n+struct scalar_u32_shift_def : public nonoverloaded_base\n+{\n+ void\n+ build (function_builder &b, const function_group_info &group,\n+\t bool preserve_user_namespace) const override\n+ {\n+ build_all (b, \"su32,su32,ss32\", group, MODE_none, preserve_user_namespace);\n+ }\n+};\n+SHAPE (scalar_u32_shift)\n+\n+/* uint32_t foo(uint32_t, const int)\n+\n+ Check that 'shift' is in the [1,32] range.\n+\n+ Example: uqshl.\n+ uint32_t [__arm_]uqshl(uint32_t value, const int shift) */\n+struct scalar_u32_shift_imm_def : public nonoverloaded_base\n+{\n+ void\n+ build (function_builder &b, const function_group_info &group,\n+\t bool preserve_user_namespace) const override\n+ {\n+ build_all (b, \"su32,su32,su64\", group, MODE_none, preserve_user_namespace);\n+ }\n+\n+ bool\n+ check (function_checker &c) const override\n+ {\n+ return c.require_immediate_range (1, 1, 32);\n+ }\n+};\n+SHAPE (scalar_u32_shift_imm)\n+\n /* int64_t foo(int64_t, int32_t)\n \n Example: asrl\ndiff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h\nindex 1ab11615ba49..22d06ce0ebd3 100644\n--- a/gcc/config/arm/arm-mve-builtins-shapes.h\n+++ b/gcc/config/arm/arm-mve-builtins-shapes.h\n@@ -67,6 +67,10 @@ namespace arm_mve\n extern const function_shape *const load_ext_gather_offset;\n extern const function_shape *const load_gather_base;\n extern const function_shape *const mvn;\n+ extern const function_shape *const scalar_s32_shift;\n+ extern const function_shape *const scalar_s32_shift_imm;\n+ extern const function_shape *const scalar_u32_shift;\n+ extern const function_shape *const scalar_u32_shift_imm;\n extern const function_shape *const scalar_s64_shift;\n extern const function_shape *const scalar_s64_shift_imm;\n extern const function_shape *const scalar_u64_shift;\ndiff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h\nindex 3acb36a2a556..9710be53911a 100644\n--- a/gcc/config/arm/arm_mve.h\n+++ b/gcc/config/arm/arm_mve.h\n@@ -58,56 +58,8 @@\n #define vuninitializedq_s64(void) __arm_vuninitializedq_s64(void)\n #define vuninitializedq_f16(void) __arm_vuninitializedq_f16(void)\n #define vuninitializedq_f32(void) __arm_vuninitializedq_f32(void)\n-#define sqrshr(__p0, __p1) __arm_sqrshr(__p0, __p1)\n-#define sqshl(__p0, __p1) __arm_sqshl(__p0, __p1)\n-#define srshr(__p0, __p1) __arm_srshr(__p0, __p1)\n-#define uqrshl(__p0, __p1) __arm_uqrshl(__p0, __p1)\n-#define uqshl(__p0, __p1) __arm_uqshl(__p0, __p1)\n-#define urshr(__p0, __p1) __arm_urshr(__p0, __p1)\n #endif\n \n-__extension__ extern __inline uint32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_uqrshl (uint32_t value, int32_t shift)\n-{\n- return __builtin_mve_uqrshl_si (value, shift);\n-}\n-\n-__extension__ extern __inline int32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_sqrshr (int32_t value, int32_t shift)\n-{\n- return __builtin_mve_sqrshr_si (value, shift);\n-}\n-\n-__extension__ extern __inline uint32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_uqshl (uint32_t value, const int shift)\n-{\n- return __builtin_mve_uqshl_si (value, shift);\n-}\n-\n-__extension__ extern __inline uint32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_urshr (uint32_t value, const int shift)\n-{\n- return __builtin_mve_urshr_si (value, shift);\n-}\n-\n-__extension__ extern __inline int32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_sqshl (int32_t value, const int shift)\n-{\n- return __builtin_mve_sqshl_si (value, shift);\n-}\n-\n-__extension__ extern __inline int32_t\n-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))\n-__arm_srshr (int32_t value, const int shift)\n-{\n- return __builtin_mve_srshr_si (value, shift);\n-}\n-\n #ifdef __cplusplus\n \n __extension__ extern __inline uint8x16_t\ndiff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md\nindex 888837674ed3..2f2c2d4a868e 100644\n--- a/gcc/config/arm/mve.md\n+++ b/gcc/config/arm/mve.md\n@@ -4375,7 +4375,7 @@\n ;;\n (define_insn \"mve_sqshl_si\"\n [(set (match_operand:SI 0 \"arm_general_register_operand\" \"=r\")\n-\t(ss_ashift:SI (match_operand:DI 1 \"arm_general_register_operand\" \"0\")\n+\t(ss_ashift:SI (match_operand:SI 1 \"arm_general_register_operand\" \"0\")\n \t\t (match_operand:SI 2 \"immediate_operand\" \"Pg\")))]\n \"TARGET_HAVE_MVE\"\n \"sqshl%?\\\\t%1, %2\"\n@@ -4386,7 +4386,7 @@\n ;;\n (define_insn \"mve_srshr_si\"\n [(set (match_operand:SI 0 \"arm_general_register_operand\" \"=r\")\n-\t(unspec:SI [(match_operand:DI 1 \"arm_general_register_operand\" \"0\")\n+\t(unspec:SI [(match_operand:SI 1 \"arm_general_register_operand\" \"0\")\n \t\t (match_operand:SI 2 \"immediate_operand\" \"Pg\")]\n \t SRSHR))]\n \"TARGET_HAVE_MVE\"\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl_check_shift.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl_check_shift.c\nnew file mode 100644\nindex 000000000000..051916692854\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl_check_shift.c\n@@ -0,0 +1,24 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+int32_t\n+foo (int32_t value)\n+{\n+ return sqshl (value, 33); /* { dg-error {passing 33 to argument 2 of 'sqshl', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+int32_t\n+foo1 (int32_t value)\n+{\n+ return sqshl (value, -1); /* { dg-error {passing -1 to argument 2 of 'sqshl', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr_check_shift.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr_check_shift.c\nnew file mode 100644\nindex 000000000000..98c5e17a4266\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr_check_shift.c\n@@ -0,0 +1,24 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+int32_t\n+foo (int32_t value)\n+{\n+ return srshr (value, 33); /* { dg-error {passing 33 to argument 2 of 'srshr', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+int32_t\n+foo1 (int32_t value)\n+{\n+ return srshr (value, -1); /* { dg-error {passing -1 to argument 2 of 'srshr', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl_check_shift.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl_check_shift.c\nnew file mode 100644\nindex 000000000000..eef1bc03254b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl_check_shift.c\n@@ -0,0 +1,24 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+uint32_t\n+foo (uint32_t value)\n+{\n+ return uqshl (value, 33); /* { dg-error {passing 33 to argument 2 of 'uqshl', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+uint32_t\n+foo1 (uint32_t value)\n+{\n+ return uqshl (value, -1); /* { dg-error {passing -1 to argument 2 of 'uqshl', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\ndiff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr_check_shift.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr_check_shift.c\nnew file mode 100644\nindex 000000000000..744bf7ca7958\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr_check_shift.c\n@@ -0,0 +1,24 @@\n+/* { dg-require-effective-target arm_v8_1m_mve_ok } */\n+/* { dg-add-options arm_v8_1m_mve } */\n+\n+#include \"arm_mve.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+uint32_t\n+foo (uint32_t value)\n+{\n+ return urshr (value, 33); /* { dg-error {passing 33 to argument 2 of 'urshr', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+uint32_t\n+foo1 (uint32_t value)\n+{\n+ return urshr (value, -1); /* { dg-error {passing -1 to argument 2 of 'urshr', which expects a value in the range \\[1, 32\\]} } */\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n","prefixes":["v2","12/14"]}