{"id":2226869,"url":"http://patchwork.ozlabs.org/api/patches/2226869/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.5@forge-stage.sourceware.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-22T19:01:39","name":"[v2,05/14] arm: fix MVE asrl lsll lsrl patterns [PR122216]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4eaa070a4a53e949a5e0bcb7e77261eb7d85c15e","submitter":{"id":92734,"url":"http://patchwork.ozlabs.org/api/people/92734/?format=json","name":"Christophe Lyon via Sourceware Forge","email":"forge-bot+clyon@forge-stage.sourceware.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/bmm.hhuph3sz8c.gcc.gcc-TEST.clyon.121.2.5@forge-stage.sourceware.org/mbox/","series":[{"id":501104,"url":"http://patchwork.ozlabs.org/api/series/501104/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501104","date":"2026-04-22T19:01:35","name":"arm: [MVE intrinsics] rework vpnot, vgetq_lane, vsetq_lane, vuninitialized and scalar shifts","version":2,"mbox":"http://patchwork.ozlabs.org/series/501104/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226869/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226869/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org","From":"Christophe Lyon via Sourceware Forge\n ","Date":"Wed, 22 Apr 2026 19:01:39 +0000","Subject":"[PATCH v2 05/14] arm: fix MVE asrl lsll lsrl patterns [PR122216]","To":"gcc-patches mailing list ","Cc":"sloosemore@baylibre.com","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/121","References":"\n ","In-Reply-To":"\n ","X-Patch-URL":"\n https://forge.sourceware.org/clyon/gcc-TEST/commit/02e88f11462c0525dd88d5d95dc8447ae6c8f420","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"gcc-patches mailing list ,\n sloosemore@baylibre.com, clyon@gcc.gnu.org","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Christophe Lyon \n\nThe thumb2_asrl, thumb2_lsll and thumb2_lsrl patterns were incorrecly\nusing (match_dup 0) for the first argument of the shift operator.\n\nThis patch replaces that with (match_operand:DI 1\narm_general_register_operandarm_general_register_operand \"0\") and\nfixes the related expanders in arm.md to use that additional argument\nand get rid of the copy of operands[1] to operands[0].\n\nFinally, since these patterns are MVE-only, rename them into mve_XXX\nand move them to mve.md.\n\ngcc/ChangeLog:\n\n\tPR target/122216\n\t* config/arm/thumb2.md (thumb2_asrl, thumb2_lsll, thumb2_lsrl):\n\tMove to ...\n\t* config/arm/mve.md (mve_asrl, mve_lsll, mve_lsrl): ... here. Use\n\tmatch_operand instead of match_dup.\n\t* config/arm/arm.md (ashldi3, ashrdi3, lshrdi3): Remove useless\n\tcopy. Update for new prototype.\n---\n gcc/config/arm/arm.md | 15 +++------------\n gcc/config/arm/mve.md | 25 +++++++++++++++++++++++++\n gcc/config/arm/thumb2.md | 24 ------------------------\n 3 files changed, 28 insertions(+), 36 deletions(-)","diff":"diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md\nindex 422ae549b65b..58f8bde4bd92 100644\n--- a/gcc/config/arm/arm.md\n+++ b/gcc/config/arm/arm.md\n@@ -4588,10 +4588,7 @@\n if (arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2]))\n \t && (REG_P (operands[2]) || INTVAL(operands[2]) != 32))\n {\n-\t if (!reg_overlap_mentioned_p(operands[0], operands[1]))\n-\t emit_insn (gen_movdi (operands[0], operands[1]));\n-\n-\t emit_insn (gen_thumb2_lsll (operands[0], operands[2]));\n+\t emit_insn (gen_mve_lsll (operands[0], operands[1], operands[2]));\n \t DONE;\n \t}\n }\n@@ -4627,10 +4624,7 @@\n if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN\n && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2])))\n {\n- if (!reg_overlap_mentioned_p(operands[0], operands[1]))\n-\temit_insn (gen_movdi (operands[0], operands[1]));\n-\n- emit_insn (gen_thumb2_asrl (operands[0], operands[2]));\n+ emit_insn (gen_mve_asrl (operands[0], operands[1], operands[2]));\n DONE;\n }\n \n@@ -4662,10 +4656,7 @@\n if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN\n && long_shift_imm (operands[2], GET_MODE (operands[2])))\n {\n- if (!reg_overlap_mentioned_p(operands[0], operands[1]))\n- emit_insn (gen_movdi (operands[0], operands[1]));\n-\n- emit_insn (gen_thumb2_lsrl (operands[0], operands[2]));\n+ emit_insn (gen_mve_lsrl (operands[0], operands[1], operands[2]));\n DONE;\n }\n \ndiff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md\nindex 9da6684ab9b3..ccde93e5f344 100644\n--- a/gcc/config/arm/mve.md\n+++ b/gcc/config/arm/mve.md\n@@ -4715,3 +4715,28 @@\n \"TARGET_HAVE_MVE\"\n \"dlstp.\\t%|lr, %0\"\n [(set_attr \"type\" \"mve_misc\")])\n+\n+;; Scalar shifts\n+(define_insn \"mve_asrl\"\n+ [(set (match_operand:DI 0 \"arm_general_register_operand\" \"=r\")\n+\t(ashiftrt:DI (match_operand:DI 1 \"arm_general_register_operand\" \"0\")\n+\t\t (match_operand:SI 2 \"arm_reg_or_long_shift_imm\" \"rPg\")))]\n+ \"TARGET_HAVE_MVE\"\n+ \"asrl%?\\\\t%Q0, %R1, %2\"\n+ [(set_attr \"predicable\" \"yes\")])\n+\n+(define_insn \"mve_lsll\"\n+ [(set (match_operand:DI 0 \"arm_general_register_operand\" \"=r\")\n+\t(ashift:DI (match_operand:DI 1 \"arm_general_register_operand\" \"0\")\n+\t\t (match_operand:SI 2 \"arm_reg_or_long_shift_imm\" \"rPg\")))]\n+ \"TARGET_HAVE_MVE\"\n+ \"lsll%?\\\\t%Q0, %R1, %2\"\n+ [(set_attr \"predicable\" \"yes\")])\n+\n+(define_insn \"mve_lsrl\"\n+ [(set (match_operand:DI 0 \"arm_general_register_operand\" \"=r\")\n+\t(lshiftrt:DI (match_operand:DI 1 \"arm_general_register_operand\" \"0\")\n+\t\t (match_operand:SI 2 \"long_shift_imm\" \"Pg\")))]\n+ \"TARGET_HAVE_MVE\"\n+ \"lsrl%?\\\\t%Q0, %R1, %2\"\n+ [(set_attr \"predicable\" \"yes\")])\ndiff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md\nindex 2c2026b1e747..40c0e052946c 100644\n--- a/gcc/config/arm/thumb2.md\n+++ b/gcc/config/arm/thumb2.md\n@@ -1733,30 +1733,6 @@\n [(set_attr \"predicable\" \"yes\")]\n )\n \n-(define_insn \"thumb2_asrl\"\n- [(set (match_operand:DI 0 \"arm_general_register_operand\" \"+r\")\n-\t(ashiftrt:DI (match_dup 0)\n-\t\t (match_operand:SI 1 \"arm_reg_or_long_shift_imm\" \"rPg\")))]\n- \"TARGET_HAVE_MVE\"\n- \"asrl%?\\\\t%Q0, %R0, %1\"\n- [(set_attr \"predicable\" \"yes\")])\n-\n-(define_insn \"thumb2_lsll\"\n- [(set (match_operand:DI 0 \"arm_general_register_operand\" \"+r\")\n-\t(ashift:DI (match_dup 0)\n-\t\t (match_operand:SI 1 \"arm_reg_or_long_shift_imm\" \"rPg\")))]\n- \"TARGET_HAVE_MVE\"\n- \"lsll%?\\\\t%Q0, %R0, %1\"\n- [(set_attr \"predicable\" \"yes\")])\n-\n-(define_insn \"thumb2_lsrl\"\n- [(set (match_operand:DI 0 \"arm_general_register_operand\" \"+r\")\n-\t(lshiftrt:DI (match_dup 0)\n-\t\t (match_operand:SI 1 \"long_shift_imm\" \"Pg\")))]\n- \"TARGET_HAVE_MVE\"\n- \"lsrl%?\\\\t%Q0, %R0, %1\"\n- [(set_attr \"predicable\" \"yes\")])\n-\n ;; Originally expanded by 'doloop_end'.\n (define_insn \"*doloop_end_internal\"\n [(set (pc)\n","prefixes":["v2","05/14"]}