{"id":2226863,"url":"http://patchwork.ozlabs.org/api/patches/2226863/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-4-nathanc@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422204335.23116-4-nathanc@nvidia.com>","list_archive_url":null,"date":"2026-04-22T20:43:31","name":"[v2,3/7] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"91ed48eea37d416b3f21aa5a51d299b39f3587a4","submitter":{"id":92820,"url":"http://patchwork.ozlabs.org/api/people/92820/?format=json","name":"Nathan Chen","email":"nathanc@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422204335.23116-4-nathanc@nvidia.com/mbox/","series":[{"id":501105,"url":"http://patchwork.ozlabs.org/api/series/501105/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105","date":"2026-04-22T20:43:28","name":"hw/arm/smmuv3-accel: Resolve AUTO properties","version":2,"mbox":"http://patchwork.ozlabs.org/series/501105/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226863/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226863/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=TghO4neK;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Derive host values using\nIOMMU_GET_HW_INFO, retrieving RIL capability from IDR3.\n\nSigned-off-by: Nathan Chen \n---\n hw/arm/smmuv3-accel.c | 8 +++++++-\n hw/arm/smmuv3.c | 10 ++++------\n 2 files changed, 11 insertions(+), 7 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex b42d189d29..98c2cdcb5e 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -57,6 +57,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[0], IDR0, ATS));\n }\n \n+ if (s->ril == ON_OFF_AUTO_AUTO) {\n+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL,\n+ FIELD_EX32(info->idr[3], IDR3, RIL));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -968,7 +973,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n \n- if (s->ats == ON_OFF_AUTO_AUTO) {\n+ if (s->ats == ON_OFF_AUTO_AUTO ||\n+ s->ril == ON_OFF_AUTO_AUTO) {\n s->s_accel->auto_mode = true;\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 5671649fee..b7aa4122eb 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ril == ON_OFF_AUTO_AUTO) {\n- error_setg(errp, \"ril auto mode is not supported\");\n- return false;\n- }\n if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n error_setg(errp, \"ssidsize auto mode is not supported\");\n return false;\n@@ -2168,8 +2164,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Enable SMMUv3 accelerator support. Allows host SMMUv3 to be \"\n \"configured in nested mode for vfio-pci dev assignment\");\n object_class_property_set_description(klass, \"ril\",\n- \"Disable range invalidation support (for accel=on). ril=auto \"\n- \"is not supported.\");\n+ \"Enable/disable range invalidation support (for accel=on). \"\n+ \"Valid values are on, off, and auto. Defaults to on. \"\n+ \"Please enable if host platform supports RIL, and disable if \"\n+ \"host platform does not support RIL.\");\n object_class_property_set_description(klass, \"ats\",\n \"Enable/disable ATS support (for accel=on). \"\n \"Valid values are on, off, and auto. Defaults to off. \"\n","prefixes":["v2","3/7"]}