{"id":2226841,"url":"http://patchwork.ozlabs.org/api/patches/2226841/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422195746.88865-36-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422195746.88865-36-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-22T19:57:33","name":"[PULL,35/48] hw/arm/smmuv3: Have smmuv3_accel_init() take an Error* parameter","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"14c4963272321088fb372905f3ccfe443f4ff40a","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422195746.88865-36-philmd@linaro.org/mbox/","series":[{"id":501099,"url":"http://patchwork.ozlabs.org/api/series/501099/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501099","date":"2026-04-22T19:56:59","name":"[PULL,01/48] hw/avr: Build as common unit files","version":1,"mbox":"http://patchwork.ozlabs.org/series/501099/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226841/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226841/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Cfr+p2cS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"By giving smmuv3_accel_init() the ability to populate an error,\nwe can fail early in smmu_realize() when CONFIG_ARM_SMMUV3_ACCEL\nis not available, simplifying smmu_validate_property().\n\nSuggested-by: Shameer Kolothum Thodi \nCo-developed-by: Shameer Kolothum Thodi \nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Shameer Kolothum \nMessage-Id: <20260410200031.18572-2-philmd@linaro.org>\n---\n hw/arm/smmuv3-accel.h | 7 +++++--\n hw/arm/smmuv3-accel.c | 3 ++-\n hw/arm/smmuv3.c | 11 +++--------\n 3 files changed, 10 insertions(+), 11 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex dba6c71de52..1ca2c80a933 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -42,7 +42,7 @@ typedef struct SMMUv3AccelDevice {\n } SMMUv3AccelDevice;\n \n #ifdef CONFIG_ARM_SMMUV3_ACCEL\n-void smmuv3_accel_init(SMMUv3State *s);\n+bool smmuv3_accel_init(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid,\n Error **errp);\n bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range,\n@@ -54,8 +54,11 @@ void smmuv3_accel_idr_override(SMMUv3State *s);\n bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n #else\n-static inline void smmuv3_accel_init(SMMUv3State *s)\n+#include \"qapi/error.h\"\n+static inline bool smmuv3_accel_init(SMMUv3State *s, Error **errp)\n {\n+ error_setg(errp, \"accel=on support not compiled in\");\n+ return false;\n }\n static inline bool\n smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid,\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 65c2f44880a..ae031f1eccf 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -917,11 +917,12 @@ static void smmuv3_accel_as_init(SMMUv3State *s)\n address_space_init(shared_as_sysmem, &root, \"smmuv3-accel-as-sysmem\");\n }\n \n-void smmuv3_accel_init(SMMUv3State *s)\n+bool smmuv3_accel_init(SMMUv3State *s, Error **errp)\n {\n SMMUState *bs = ARM_SMMU(s);\n \n s->s_accel = g_new0(SMMUv3AccelState, 1);\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n+ return true;\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 5570a13c8a6..5c2855c3770 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1965,13 +1965,6 @@ static void smmu_reset_exit(Object *obj, ResetType type)\n \n static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n {\n-#ifndef CONFIG_ARM_SMMUV3_ACCEL\n- if (s->accel) {\n- error_setg(errp, \"accel=on support not compiled in\");\n- return false;\n- }\n-#endif\n-\n if (s->ats == ON_OFF_AUTO_AUTO) {\n error_setg(errp, \"ats auto mode is not supported\");\n return false;\n@@ -2033,7 +2026,9 @@ static void smmu_realize(DeviceState *d, Error **errp)\n }\n \n if (s->accel) {\n- smmuv3_accel_init(s);\n+ if (!smmuv3_accel_init(s, errp)) {\n+ return;\n+ }\n error_setg(&s->migration_blocker, \"Migration not supported with SMMUv3 \"\n \"accelerator mode enabled\");\n if (migrate_add_blocker(&s->migration_blocker, errp) < 0) {\n","prefixes":["PULL","35/48"]}