{"id":2226449,"url":"http://patchwork.ozlabs.org/api/patches/2226449/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422123306.286833-1-ankita@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422123306.286833-1-ankita@nvidia.com>","list_archive_url":null,"date":"2026-04-22T12:33:06","name":"[v5,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"eec38b9f97270b279ecaad83330696f7c9922ffd","submitter":{"id":86155,"url":"http://patchwork.ozlabs.org/api/people/86155/?format=json","name":"Ankit Agrawal","email":"ankita@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422123306.286833-1-ankita@nvidia.com/mbox/","series":[{"id":501007,"url":"http://patchwork.ozlabs.org/api/series/501007/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501007","date":"2026-04-22T12:33:06","name":"[v5,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC","version":5,"mbox":"http://patchwork.ozlabs.org/series/501007/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226449/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226449/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=jZCVog5t;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52968-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"jZCVog5t\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.209.27","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0zHz6rzlz1yD5\n\tfor ; Wed, 22 Apr 2026 22:37:03 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 5E6883044665\n\tfor ; Wed, 22 Apr 2026 12:33:44 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id AF0973D8121;\n\tWed, 22 Apr 2026 12:33:41 +0000 (UTC)","from PH8PR06CU001.outbound.protection.outlook.com\n (mail-westus3azon11012027.outbound.protection.outlook.com [40.107.209.27])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 10A013D8108;\n\tWed, 22 Apr 2026 12:33:31 +0000 (UTC)","from BL0PR02CA0001.namprd02.prod.outlook.com (2603:10b6:207:3c::14)\n by BY5PR12MB4244.namprd12.prod.outlook.com (2603:10b6:a03:204::8) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.20; Wed, 22 Apr\n 2026 12:33:26 +0000","from BL02EPF00029927.namprd02.prod.outlook.com\n (2603:10b6:207:3c:cafe::eb) by BL0PR02CA0001.outlook.office365.com\n (2603:10b6:207:3c::14) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9791.48 via Frontend Transport; Wed,\n 22 Apr 2026 12:33:26 +0000","from mail.nvidia.com (216.228.118.233) by\n BL02EPF00029927.mail.protection.outlook.com (10.167.249.52) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9846.18 via Frontend Transport; Wed, 22 Apr 2026 12:33:26 +0000","from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com\n (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 22 Apr\n 2026 05:33:06 -0700","from drhqmail202.nvidia.com (10.126.190.181) by\n drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.2562.20; Wed, 22 Apr 2026 05:33:06 -0700","from localhost.nvidia.com (10.127.8.12) by mail.nvidia.com\n (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend\n Transport; Wed, 22 Apr 2026 05:33:06 -0700"],"ARC-Seal":["i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776861217; cv=fail;\n b=ppTzIbUm9u5fqmTxsvjXYvgFRuGoh9eY4I0ZZSCjb6KzKJSq5phdySWFetdplGLhvQxzvVdOg2/ji8zv8Q25+f2w00ryq6EdgNDcnVI1WjdJ5EJmXAG2Qw0oqUsEhwSmbWGlvJWvR6Gk16+ufofxytPTkpkR0avdr+flIFiC85M=","i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=o34iNZsQqnxJZGSGc8w198OmpoY6YDz2ajOBv8Ui2dq/8f1MrkFq7qQ3OoM2nTPVZEhC1G5GhISy9EOED8sga22Nfi3p42Hipxgkc3a7HtG3G/EDRe2NDChHJpr8vInsA4hOrvBpSOzYEzVCFDekIGO8KVpjkqjsqHvoJeIWwFKk7CPgSPFB3AzTVlw40JXqzgeIXek1wRCPJ579WUKVmgQnPl+RPQaQScw8Fphz7XJL/4pgIgVkMsYM5DJcZImKCLcIxjzd6UIXJbeaKJk/IxULffEYgkAjdHSe9bRge92l/tXwd+3tAILJVnMbvQRWHj2bMuZdu2hCwVV4CRipIg=="],"ARC-Message-Signature":["i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776861217; c=relaxed/simple;\n\tbh=ARlL2lZWkT3ER0ERC1aMfJLVpZOGdhbKKTyr4xozUR0=;\n\th=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type;\n b=EfWBmpe35Vx0/EH4LmJ261EHMQ4qBFhxkYKXLMbOX2wNsKL+WcjQfJAH+Ps/7fs9kove7x4NjEIIvSQWkW4hxveA6RF5pIlejxLcJ8k78KPRbW4r3nwlB+/yhYDuW50sVYAdqEtJWEfRzhfi/hcm9jWaAPBBJNFzrMZv29oeZYk=","i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=1wWPDEdw5fdqchyaSimu5EbEks8IP6ya1LAsTYt4P2w=;\n b=F3JbbQ1uib5IJ1w5T5J7hbTUvpWhSPJsMP2pxb4K80btr9F7+M7uOT5VPEsYJ1JFXXjn4lcr/nVFPc5hfNJqcEMnI4UPqkWyQTvZs7tBmp7wWsCtDRrhtYJiLfeg9sL0/fJF5ClgPpgzqSWj07m50Y3SP+hPrj9WCrC2HdBK+URY5enxs9aXGIL2ugAijewtGhkDlUyHnUcGPp8xIrJdyF3KZmCa6VVB2tM24VLcQE6w8vqC692q90iuBceZPBFWC3a1o/KdLjgii/plaSdEH8V0IWYJ7/58j4pM7ueL9YhsGpoW1eHVD5a5bMy+mGin6+R2Rn6TLtjnhGVOFYrjCA=="],"ARC-Authentication-Results":["i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=jZCVog5t; arc=fail smtp.client-ip=40.107.209.27","i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.118.233) smtp.rcpttodomain=shazbot.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=1wWPDEdw5fdqchyaSimu5EbEks8IP6ya1LAsTYt4P2w=;\n b=jZCVog5tyhtuPr5+nPWpGjhzq19XgVeje4oPArB0QiPKh85wVWEZXP6U95Yvw9j9/W9PVXmv/gOzQ1UuRVSlOASqI+6fF2sApEX4wC4xigFBNxWKVG42PAd1pPyt3fJG1hwWCnhSqZAywWwWFaP7akbbC34MamrYeIkEmElKOshKJZdhxYiEFgteLlXofvNt5iMOau2M0v0pGlzIGci7qZVg7d19f+Xw7LC6PBRh/KHEUIGrMvxr6x9S6JEBcf6w4YWo1UpltU1KWuRAi//M1j3HgAhsDIfaS7/FKlv9ZTcUbGBaJzRcC7KQCrNS/zvtt77eVOI8X5k+pcAVaJsM7A==","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 216.228.118.233)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.118.233 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C","From":"Ankit Agrawal ","To":", ","CC":", , ,\n\t, , ,\n\t, ","Subject":"[PATCH v5 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC","Date":"Wed, 22 Apr 2026 12:33:06 +0000","Message-ID":"<20260422123306.286833-1-ankita@nvidia.com>","X-Mailer":"git-send-email 2.34.1","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"8bit","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL02EPF00029927:EE_|BY5PR12MB4244:EE_","X-MS-Office365-Filtering-Correlation-Id":"8d17ef20-5a84-40e8-3d68-08dea06b59d9","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|56012099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n\tkaJ9e11B/iIh+r+xxTqcHSJExwY4k/Y0upNdKRVuz3YCecxpqHIlSwlLimTQTh1aiRRiNrRTo7pPsSFj0CguTrUsaF2ID3Ijieb6dsH0Hg2zUhLR5c6EDnfpwKJ6i8FthD6Sh+6tQHhcJFTVD+o93jqVEthabmHCc28yEKhwLKGr30+xhXwncyVNW7+QIL/ZnnCwofcHy36zKjOpQmGVRbm+jthk+5yUWPDNnA0Iex1JYVUmMOrGX6Qo92LlTiFLdVRZi2lgNtYB6mXr4dIQwBD38af9+8haZPdsUNY6LEHYgkfZ3BoHcTO2garfzb3D0RjeUW4IRRAlbd06lRtwxY1lhGhqeKmiWf1ODcF34q+l0HfLSfYVXWf/Rn93VSKduTWF7XjQ5GB/12QvVkg2fMYZqH6bF4ILkKhyMZ2agAAGbcuV0BsOQAAenqji/did+vgO/al2OnPRImxaE+lUkPld2qyAIsYRWMiINJyO6O8+083MNrJK1Yyrrk8KeFaIfy8Hx8ONWJA5CveF//jABsvL+an/usRFUDsq9FAET0aaatG5EZIqTzSxTUYM8WdECTouOuDJSiP5LMZoozaptunioWHKG86s+nSpwZ/W43f6FKSTHFH/U4OJd3KGGuTQyXmP9mjuYFcPtE9sQl5+ATmE4hkp+UrHrkokMwGHkct5iMU/Rj4nRAGivNy1iGKVxb2GWl48pczaFEmpPqQhFX+awjt1Zn4pB44QBTZhwnO5X3k8tfqmyYmygD2ymi8B/AiwdjhUzFy4tpE+PYctWg==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(56012099003)(18002099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tjxfNWdVeboqT1woXvB2+9WlFZO3ael/JFp/xn6vuNg76fyPOrBOgZF9n+8JIdELd0XDMHVXTHJSecpezl8dWhFpTBs2U7Az/MeYuncTKlrTngYUEy81jsHqCe4cQekBtmCBdlcD4XlnkupwsKd2vIRZjd72jgaz0Pyq2Rj8CCgXxlGSbDka9dEyG2QKThfHqvXvfQHsoUSs4i2+OK/ewNQokN5eedigUQVD0Q4Ylyup/hbgtGGZ5ekFFg7CCA8ruLmRtQv6uxwVbW0E71x2aWF45oTo4Wtdxb5CogVx0Cm/fsMVbHpH4Tghzxjlve6scGPIekuq6xyDM48anJ0HKgrHRiB2vJT9kKLjooe4DpkKq3lIc0v/kWWEknctv1bFHN/lwVaFnK8XTT+MmkW8DXNqgpuSCVPMEdmTjNvajoGwZrdlI9okmmJqHjyCQMCWf","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"22 Apr 2026 12:33:26.0582\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 8d17ef20-5a84-40e8-3d68-08dea06b59d9","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tBL02EPF00029927.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BY5PR12MB4244"},"content":"Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside\nthe existing legacy BAR0 polling path. On probe and after reset, the\ndriver reads the CXL Device DVSEC capability to determine whether the\nGPU memory is ready. A static inline wrapper dispatches to the\nappropriate readiness check (legacy v/s blackwell-next) based on whether\nthe CXL DVSEC capability is present.\n\nThe memory readiness is checked by polling on the Memory_Active bit\nbased on the Memory_Active_Timeout. It also checks if MEM_INFO_VALID\nis set within 1 second. If not, return error. This is based on the\nCXL spec 4.0 Tables 8-13.\n\nAdd PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout\nfield encoding.\n\nCc: Ilpo Järvinen \nCc: Kevin Tian \nSuggested-by: Alex Williamson \nSigned-off-by: Ankit Agrawal \n---\n drivers/vfio/pci/nvgrace-gpu/main.c | 102 +++++++++++++++++++++++++---\n include/uapi/linux/pci_regs.h | 1 +\n 2 files changed, 95 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c\nindex fa056b69f899..81a725460112 100644\n--- a/drivers/vfio/pci/nvgrace-gpu/main.c\n+++ b/drivers/vfio/pci/nvgrace-gpu/main.c\n@@ -3,6 +3,7 @@\n * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved\n */\n \n+#include \n #include \n #include \n #include \n@@ -64,6 +65,8 @@ struct nvgrace_gpu_pci_core_device {\n \tbool has_mig_hw_bug;\n \t/* GPU has just been reset */\n \tbool reset_done;\n+\t/* CXL Device DVSEC offset; 0 if not present (legacy GB path) */\n+\tint cxl_dvsec;\n };\n \n static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev)\n@@ -242,7 +245,7 @@ static void nvgrace_gpu_close_device(struct vfio_device *core_vdev)\n \tvfio_pci_core_close_device(core_vdev);\n }\n \n-static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n+static int nvgrace_gpu_wait_device_ready_legacy(void __iomem *io)\n {\n \tunsigned long timeout = jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS);\n \n@@ -256,6 +259,81 @@ static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n \treturn -ETIME;\n }\n \n+/*\n+ * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n+ * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n+ * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n+ * 101b-111b = reserved (clamped to 256s).\n+ */\n+static inline unsigned long cxl_mem_active_timeout_ms(u8 timeout)\n+{\n+\treturn 1000UL << (2 * min_t(u8, timeout, 4));\n+}\n+\n+/*\n+ * Check if CXL DVSEC reports memory as valid and active.\n+ */\n+static inline bool cxl_dvsec_mem_is_active(u32 status)\n+{\n+\treturn (status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n+\t (status & PCI_DVSEC_CXL_MEM_ACTIVE);\n+}\n+\n+static int nvgrace_gpu_wait_device_ready_cxl(struct nvgrace_gpu_pci_core_device *nvdev)\n+{\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n+\tint cxl_dvsec = nvdev->cxl_dvsec;\n+\tunsigned long mem_info_valid_deadline;\n+\tunsigned long timeout = 0;\n+\tu32 dvsec_memory_status;\n+\n+\tmem_info_valid_deadline = jiffies + msecs_to_jiffies(POLL_QUANTUM_MS);\n+\n+\tdo {\n+\t\tpci_read_config_dword(pdev,\n+\t\t\t\t cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n+\t\t\t\t &dvsec_memory_status);\n+\n+\t\tif (dvsec_memory_status == ~0U)\n+\t\t\treturn -ENODEV;\n+\n+\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n+\t\t\treturn 0;\n+\n+\t\t/*\n+\t\t * Once MEM_INFO_VALID is set, derive the MEM_ACTIVE timeout\n+\t\t * from the register.\n+\t\t */\n+\t\tif (dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) {\n+\t\t\tif (!timeout) {\n+\t\t\t\tu8 mem_active_timeout =\n+\t\t\t\t\tFIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n+\t\t\t\t\t\t dvsec_memory_status);\n+\n+\t\t\t\ttimeout = jiffies +\n+\t\t\t\t\t msecs_to_jiffies(cxl_mem_active_timeout_ms(mem_active_timeout));\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Bail early if MEM_INFO_VALID is not set within 1 second */\n+\t\tif (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n+\t\t time_after(jiffies, mem_info_valid_deadline))\n+\t\t\treturn -ETIME;\n+\n+\t\tmsleep(POLL_QUANTUM_MS);\n+\t} while (!timeout || !time_after(jiffies, timeout));\n+\n+\treturn -ETIME;\n+}\n+\n+static inline int nvgrace_gpu_wait_device_ready(struct nvgrace_gpu_pci_core_device *nvdev,\n+\t\t\t\t\t\tvoid __iomem *io)\n+{\n+\treturn nvdev->cxl_dvsec ?\n+\t\tnvgrace_gpu_wait_device_ready_cxl(nvdev) :\n+\t\tnvgrace_gpu_wait_device_ready_legacy(io);\n+}\n+\n /*\n * If the GPU memory is accessed by the CPU while the GPU is not ready\n * after reset, it can cause harmless corrected RAS events to be logged.\n@@ -275,7 +353,7 @@ nvgrace_gpu_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n \tif (!__vfio_pci_memory_enabled(vdev))\n \t\treturn -EIO;\n \n-\tret = nvgrace_gpu_wait_device_ready(vdev->barmap[0]);\n+\tret = nvgrace_gpu_wait_device_ready(nvdev, vdev->barmap[0]);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1146,11 +1224,16 @@ static bool nvgrace_gpu_has_mig_hw_bug(struct pci_dev *pdev)\n * Ensure that the BAR0 region is enabled before accessing the\n * registers.\n */\n-static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n+static int nvgrace_gpu_probe_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n {\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n \tvoid __iomem *io;\n \tint ret;\n \n+\t/* CXL path only reads PCI config space; no need to map BAR0. */\n+\tif (nvdev->cxl_dvsec)\n+\t\treturn nvgrace_gpu_wait_device_ready_cxl(nvdev);\n+\n \tret = pci_enable_device(pdev);\n \tif (ret)\n \t\treturn ret;\n@@ -1165,7 +1248,7 @@ static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n \t\tgoto iomap_exit;\n \t}\n \n-\tret = nvgrace_gpu_wait_device_ready(io);\n+\tret = nvgrace_gpu_wait_device_ready_legacy(io);\n \n \tpci_iounmap(pdev, io);\n iomap_exit:\n@@ -1183,10 +1266,6 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \tu64 memphys, memlength;\n \tint ret;\n \n-\tret = nvgrace_gpu_probe_check_device_ready(pdev);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tret = nvgrace_gpu_fetch_memory_property(pdev, &memphys, &memlength);\n \tif (!ret)\n \t\tops = &nvgrace_gpu_pci_ops;\n@@ -1198,6 +1277,13 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \n \tdev_set_drvdata(&pdev->dev, &nvdev->core_device);\n \n+\tnvdev->cxl_dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n+\t\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n+\n+\tret = nvgrace_gpu_probe_check_device_ready(nvdev);\n+\tif (ret)\n+\t\tgoto out_put_vdev;\n+\n \tif (ops == &nvgrace_gpu_pci_ops) {\n \t\tnvdev->has_mig_hw_bug = nvgrace_gpu_has_mig_hw_bug(pdev);\n \ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 14f634ab9350..718fb630f5bb 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1357,6 +1357,7 @@\n #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i)\t\t(0x1C + (i * 0x10))\n #define PCI_DVSEC_CXL_MEM_INFO_VALID\t\t\t_BITUL(0)\n #define PCI_DVSEC_CXL_MEM_ACTIVE\t\t\t_BITUL(1)\n+#define PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT\t\t__GENMASK(15, 13)\n #define PCI_DVSEC_CXL_MEM_SIZE_LOW\t\t\t__GENMASK(31, 28)\n #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i)\t\t(0x20 + (i * 0x10))\n #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i)\t\t(0x24 + (i * 0x10))\n","prefixes":["v5","1/1"]}