{"id":2226444,"url":"http://patchwork.ozlabs.org/api/patches/2226444/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260422094649.57611-4-brian.ruley@gehealthcare.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422094649.57611-4-brian.ruley@gehealthcare.com>","list_archive_url":null,"date":"2026-04-22T09:46:42","name":"[4/5] clk: imx6q: configure ldb clock selectors","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0e1afc4dd16c6e50934180b137d61c54bbb306ee","submitter":{"id":89422,"url":"http://patchwork.ozlabs.org/api/people/89422/?format=json","name":"Brian Ruley","email":"brian.ruley@gehealthcare.com"},"delegate":{"id":151988,"url":"http://patchwork.ozlabs.org/api/users/151988/?format=json","username":"festevam","first_name":"Fabio","last_name":"Estevam","email":"festevam@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260422094649.57611-4-brian.ruley@gehealthcare.com/mbox/","series":[{"id":501004,"url":"http://patchwork.ozlabs.org/api/series/501004/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501004","date":"2026-04-22T09:46:40","name":"[1/5] clk: imx6q: cosmetic: keep pll definitions together","version":1,"mbox":"http://patchwork.ozlabs.org/series/501004/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226444/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226444/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 header.b=xau2QndM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Ip=[165.85.157.49];\n Helo=[atlrelay2.compute.ge-healthcare.net]","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"\n TreatMessagesAsInternal-CH1PEPF0000A34B.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR22MB4722","X-Mailman-Approved-At":"Wed, 22 Apr 2026 14:34:21 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"A hardware bug prevents LDB clock selectors from being configured later\non non-plus i.MX6QD variants, so let's set the desired configuration in\nthe probe before we register them.\n\nSigned-off-by: Brian Ruley \n---\n drivers/clk/imx/clk-imx6q.c | 121 +++++++++++++++++++++++++++++++++++-\n 1 file changed, 119 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c\nindex eadb44749a0..11da6991905 100644\n--- a/drivers/clk/imx/clk-imx6q.c\n+++ b/drivers/clk/imx/clk-imx6q.c\n@@ -9,6 +9,7 @@\n #include \n #include \n #include \n+#include \n #include \n \n #include \"clk.h\"\n@@ -148,6 +149,121 @@ static const char *pll7_bypass_sels[] = {\n \n static unsigned int share_count_mipi_core_cfg;\n \n+static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel,\n+\t\t\t\t int *ldb_di1_sel)\n+{\n+\tstruct ofnode_phandle_args clk_args, parent_args;\n+\tofnode node = dev_ofnode(dev);\n+\tint count, err;\n+\n+\tcount = dev_count_phandle_with_args(dev, \"assigned-clocks\",\n+\t\t\t\t\t \"#clock-cells\", 0);\n+\tif (count <= 0) {\n+\t\tif (count == 0)\n+\t\t\tdebug(\"%s: no assigned_clocks found\\n\", dev->name);\n+\t\telse\n+\t\t\tpr_err(\"%s: failed to get phandle count (%d)\\n\",\n+\t\t\t dev->name, count);\n+\t\treturn;\n+\t}\n+\n+\tfor (int i = 0; i < count; i++) {\n+\t\terr = dev_read_phandle_with_args(dev, \"assigned-clocks\",\n+\t\t\t\t\t\t \"#clock-cells\", 0, i,\n+\t\t\t\t\t\t &clk_args);\n+\t\tif (err == -ENOENT)\n+\t\t\t/* Skip empty handles */\n+\t\t\tcontinue;\n+\t\telse if (err < 0)\n+\t\t\treturn;\n+\n+\t\tif (!ofnode_equal(clk_args.node, node) ||\n+\t\t clk_args.args[0] >= IMX6QDL_CLK_END) {\n+\t\t\tpr_err(\"%s: clock %d not in ccm\\n\", dev->name, i);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\terr = dev_read_phandle_with_args(dev, \"assigned-clock-parents\",\n+\t\t\t\t\t\t \"#clock-cells\", 0, i,\n+\t\t\t\t\t\t &parent_args);\n+\t\tif (err < 0)\n+\t\t\treturn;\n+\n+\t\tif (!ofnode_equal(parent_args.node, node) ||\n+\t\t parent_args.args[0] >= IMX6QDL_CLK_END) {\n+\t\t\tpr_err(\"%s: parent clock %d not in ccm\\n\", dev->name,\n+\t\t\t i);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tif (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL)\n+\t\t\t*ldb_di0_sel = parent_args.args[0];\n+\t\telse if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL)\n+\t\t\t*ldb_di1_sel = parent_args.args[0];\n+\t}\n+}\n+\n+static void imx6q_init_ldb_clks(struct udevice *dev)\n+{\n+\tint ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END };\n+\tenum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK };\n+\n+\tof_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]);\n+\tfor (int i = 0; i < 2; i++) {\n+\t\tswitch (ldb_di_sel[i]) {\n+\t\tcase IMX6QDL_CLK_PLL5_VIDEO_DIV:\n+\t\t\tldb_di_clk[i] = MXC_PLL5_CLK;\n+\t\t\tbreak;\n+\t\tcase IMX6QDL_CLK_PLL2_PFD0_352M:\n+\t\t\tldb_di_clk[i] = MXC_PLL2_PFD0_CLK;\n+\t\t\tbreak;\n+\t\tcase IMX6QDL_CLK_PLL2_PFD2_396M: {\n+\t\t\tstruct clk *clk, *parent;\n+\n+\t\t\tint err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk);\n+\n+\t\t\tif (err) {\n+\t\t\t\tpr_err(\"%s: failed to get periph_pre clock \"\n+\t\t\t\t \"(%d)\\n\",\n+\t\t\t\t dev->name, err);\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\terr = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M,\n+\t\t\t\t\t &parent);\n+\t\t\tif (err) {\n+\t\t\t\tpr_err(\"%s: failed to get pll2_pfd2_396m clock\"\n+\t\t\t\t \" (%d)\\n\",\n+\t\t\t\t dev->name, err);\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tif (parent == clk) {\n+\t\t\t\tpr_err(\"%s: ldb_di%d_sel: couldn't disable \"\n+\t\t\t\t \"pll2_pfd2_396m clock\\n\",\n+\t\t\t\t dev->name, i);\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tldb_di_clk[i] = MXC_PLL2_PFD2_CLK;\n+\t\t\tbreak;\n+\t\t}\n+\t\tcase IMX6QDL_CLK_MMDC_CH1_AXI:\n+\t\tcase IMX6QDL_CLK_END:\n+\t\t\t/* use the default clock */\n+\t\t\tbreak;\n+\t\tcase IMX6QDL_CLK_PLL3_USB_OTG:\n+\t\t\tldb_di_clk[i] = MXC_PLL3_SW_CLK;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tpr_err(\"%s: invalid LDB clock parent\\n\", dev->name);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tselect_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]);\n+}\n+\n static int imx6q_clk_probe(struct udevice *dev)\n {\n \tvoid *base;\n@@ -358,9 +474,10 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t\t\t\t ldb_di_sels, ARRAY_SIZE(ldb_di_sels)));\n \t} else {\n \t\t/*\n-\t\t * Need to set these as read-only due to a hardware bug.\n-\t\t * Keeping default mux values. Fixed on the i.MX6 QuadPlus\n+\t\t * Need to set the clocks now and make them read-only due to a\n+\t\t * hardware bug. Fixed on the i.MX6 QuadPlus\n \t\t */\n+\t\timx6q_init_ldb_clks(dev);\n \t\tclk_dm(IMX6QDL_CLK_LDB_DI0_SEL,\n \t\t imx_clk_mux_flags(dev, \"ldb_di0_sel\", base + 0x2c, 9, 3,\n \t\t\t\t\t ldb_di_sels, ARRAY_SIZE(ldb_di_sels),\n","prefixes":["4/5"]}