{"id":2226149,"url":"http://patchwork.ozlabs.org/api/patches/2226149/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-9-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422101043.1234229-9-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-22T10:10:19","name":"[v2,08/31] target/arm: migrate BXJ trap syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b175ebe1e1c665fca6405766c53974843f1103e6","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-9-alex.bennee@linaro.org/mbox/","series":[{"id":500957,"url":"http://patchwork.ozlabs.org/api/series/500957/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957","date":"2026-04-22T10:10:11","name":"target/arm: fully model WFxT instructions for A-profile","version":2,"mbox":"http://patchwork.ozlabs.org/series/500957/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226149/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226149/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HrCAWMlC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This is an Armv7 specific syndrome for chips with Jazelle\nfunctionality.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n---\n target/arm/syndrome.h | 20 ++++++++++++++++++--\n 1 file changed, 18 insertions(+), 2 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 52a6745cb23..6fcf0ac7572 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -440,10 +440,26 @@ static inline uint32_t syn_btitrap(int btype)\n return res;\n }\n \n+/*\n+ * ISS encoding for trapped BXJ execution\n+ *\n+ * This is an Armv7 encoding.\n+ */\n+FIELD(BXJ_ISS, RM, 0, 4)\n+/* bits 4:19 are Reserved, UNK/SBZP */\n+FIELD(BXJ_ISS, COND, 20, 4)\n+FIELD(BXJ_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)\n {\n- return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |\n- (cv << 24) | (cond << 20) | rm;\n+ uint32_t res = syn_set_ec(0, EC_BXJTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, BXJ_ISS, CV, cv);\n+ res = FIELD_DP32(res, BXJ_ISS, COND, cond);\n+ res = FIELD_DP32(res, BXJ_ISS, RM, rm);\n+\n+ return res;\n }\n \n static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr,\n","prefixes":["v2","08/31"]}