{"id":2226143,"url":"http://patchwork.ozlabs.org/api/patches/2226143/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-14-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422101043.1234229-14-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-22T10:10:24","name":"[v2,13/31] target/arm: migrate gcs syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f40a18f8542727191050f191479d9a4c8ff86d67","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-14-alex.bennee@linaro.org/mbox/","series":[{"id":500957,"url":"http://patchwork.ozlabs.org/api/series/500957/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957","date":"2026-04-22T10:10:11","name":"target/arm: fully model WFxT instructions for A-profile","version":2,"mbox":"http://patchwork.ozlabs.org/series/500957/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226143/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226143/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KjbfbogY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42c;\n envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Tweak arg names to make it clear raddr is the data address register\nnumber.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n\n---\nv2\n - rename ra->raddr to document things.\n---\n target/arm/syndrome.h | 39 +++++++++++++++++++++++++++++++++------\n 1 file changed, 33 insertions(+), 6 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 65d0de63a83..7ff8c30e2bb 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -690,21 +690,48 @@ static inline uint32_t syn_pcalignment(void)\n return res;\n }\n \n+/*\n+ * ISS encoding for a GCS exception\n+ *\n+ * Field validity depends on EXTYPE\n+ */\n+FIELD(GCS_ISS, IT, 0, 5)\n+FIELD(GCS_ISS, RN, 5, 5) /* only for non EXLOCK exceptions */\n+FIELD(GCS_ISS, RADDR, 10, 5) /* only for GCSSTR/GCSSTTR traps */\n+FIELD(GCS_ISS, EXTYPE, 20, 4)\n+\n static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn)\n {\n- return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL |\n- (GCS_ET_DataCheck << 20) | (rn << 5) | it);\n+ uint32_t res = syn_set_ec(0, EC_GCS);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_DataCheck);\n+ res = FIELD_DP32(res, GCS_ISS, RN, rn);\n+ res = FIELD_DP32(res, GCS_ISS, IT, it);\n+\n+ return res;\n }\n \n static inline uint32_t syn_gcs_exlock(void)\n {\n- return (EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | (GCS_ET_EXLOCK << 20);\n+ uint32_t res = syn_set_ec(0, EC_GCS);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_EXLOCK);\n+\n+ return res;\n }\n \n-static inline uint32_t syn_gcs_gcsstr(int ra, int rn)\n+static inline uint32_t syn_gcs_gcsstr(int raddr, int rn)\n {\n- return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL |\n- (GCS_ET_GCSSTR_GCSSTTR << 20) | (ra << 10) | (rn << 5));\n+ uint32_t res = syn_set_ec(0, EC_GCS);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_GCSSTR_GCSSTTR);\n+ res = FIELD_DP32(res, GCS_ISS, RADDR, raddr);\n+ res = FIELD_DP32(res, GCS_ISS, RN, rn);\n+\n+ return res;\n }\n \n static inline uint32_t syn_serror(uint32_t extra)\n","prefixes":["v2","13/31"]}