{"id":2226134,"url":"http://patchwork.ozlabs.org/api/patches/2226134/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-11-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422101043.1234229-11-alex.bennee@linaro.org>","list_archive_url":null,"date":"2026-04-22T10:10:21","name":"[v2,10/31] target/arm: migrate fault syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e0389f1c3b0ddb7b98bb95311946f799fe56b2e4","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422101043.1234229-11-alex.bennee@linaro.org/mbox/","series":[{"id":500957,"url":"http://patchwork.ozlabs.org/api/series/500957/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500957","date":"2026-04-22T10:10:11","name":"target/arm: fully model WFxT instructions for A-profile","version":2,"mbox":"http://patchwork.ozlabs.org/series/500957/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226134/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226134/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google 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5b1f17b1804b1-48919270787mr135668195e9.0.1776852650190;\n Wed, 22 Apr 2026 03:10:50 -0700 (PDT)","From":"=?utf-8?q?Alex_Benn=C3=A9e?= ","To":"qemu-devel@nongnu.org","Cc":"Alexander Graf , qemu-arm@nongnu.org,\n Peter Maydell ,\n Paolo Bonzini ,\n Mohamed Mediouni , kvm@vger.kernel.org,\n Pedro Barbuda ,\n =?utf-8?q?Alex_Benn=C3=A9e?= ,\n Richard Henderson ","Subject":"[PATCH v2 10/31] target/arm: migrate fault syndromes to\n registerfields","Date":"Wed, 22 Apr 2026 11:10:21 +0100","Message-ID":"<20260422101043.1234229-11-alex.bennee@linaro.org>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260422101043.1234229-1-alex.bennee@linaro.org>","References":"<20260422101043.1234229-1-alex.bennee@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::332;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Migrate syn_insn_abort and syn_data_abort_* to the registerfields API.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n\n---\nv2\n - use !is_16bit directly\n---\n target/arm/syndrome.h | 87 ++++++++++++++++++++++++++++++++++++-------\n 1 file changed, 74 insertions(+), 13 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex bc65106c61a..2031b3704fb 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -494,20 +494,64 @@ static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr,\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an Instruction Abort\n+ *\n+ * (aka instruction abort)\n+ */\n+FIELD(IABORT_ISS, IFSC, 0, 6)\n+FIELD(IABORT_ISS, S1PTW, 7, 1)\n+FIELD(IABORT_ISS, EA, 9, 1)\n+FIELD(IABORT_ISS, FnV, 10, 1) /* FAR not Valid */\n+FIELD(IABORT_ISS, SET, 11, 2)\n+FIELD(IABORT_ISS, PFV, 14, 1)\n+FIELD(IABORT_ISS, TopLevel, 21, 1) /* FEAT_THE */\n+\n static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)\n {\n- return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_INSNABORT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, IABORT_ISS, EA, ea);\n+ res = FIELD_DP32(res, IABORT_ISS, S1PTW, s1ptw);\n+ res = FIELD_DP32(res, IABORT_ISS, IFSC, fsc);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from a Data Abort\n+ */\n+FIELD(DABORT_ISS, DFSC, 0, 6)\n+FIELD(DABORT_ISS, WNR, 6, 1)\n+FIELD(DABORT_ISS, S1PTW, 7, 1)\n+FIELD(DABORT_ISS, CM, 8, 1)\n+FIELD(DABORT_ISS, EA, 9, 1)\n+FIELD(DABORT_ISS, FnV, 10, 1)\n+FIELD(DABORT_ISS, LST, 11, 2)\n+FIELD(DABORT_ISS, VNCR, 13, 1)\n+FIELD(DABORT_ISS, AR, 14, 1)\n+FIELD(DABORT_ISS, SF, 15, 1)\n+FIELD(DABORT_ISS, SRT, 16, 5)\n+FIELD(DABORT_ISS, SSE, 21, 1)\n+FIELD(DABORT_ISS, SAS, 22, 2)\n+FIELD(DABORT_ISS, ISV, 24, 1)\n+\n static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv,\n int ea, int cm, int s1ptw,\n int wnr, int fsc)\n {\n- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL\n- | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7)\n- | (wnr << 6) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_DATAABORT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, DABORT_ISS, FnV, fnv);\n+ res = FIELD_DP32(res, DABORT_ISS, EA, ea);\n+ res = FIELD_DP32(res, DABORT_ISS, CM, cm);\n+ res = FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw);\n+ res = FIELD_DP32(res, DABORT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, DABORT_ISS, DFSC, fsc);\n+\n+ return res;\n }\n \n static inline uint32_t syn_data_abort_with_iss(int same_el,\n@@ -517,11 +561,22 @@ static inline uint32_t syn_data_abort_with_iss(int same_el,\n int wnr, int fsc,\n bool is_16bit)\n {\n- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)\n- | (sf << 15) | (ar << 14)\n- | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_DATAABORT + same_el);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, DABORT_ISS, ISV, 1);\n+ res = FIELD_DP32(res, DABORT_ISS, SAS, sas);\n+ res = FIELD_DP32(res, DABORT_ISS, SSE, sse);\n+ res = FIELD_DP32(res, DABORT_ISS, SRT, srt);\n+ res = FIELD_DP32(res, DABORT_ISS, SF, sf);\n+ res = FIELD_DP32(res, DABORT_ISS, AR, ar);\n+ res = FIELD_DP32(res, DABORT_ISS, EA, ea);\n+ res = FIELD_DP32(res, DABORT_ISS, CM, cm);\n+ res = FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw);\n+ res = FIELD_DP32(res, DABORT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, DABORT_ISS, DFSC, fsc);\n+\n+ return res;\n }\n \n /*\n@@ -530,8 +585,14 @@ static inline uint32_t syn_data_abort_with_iss(int same_el,\n */\n static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc)\n {\n- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT)\n- | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc;\n+ uint32_t res = syn_set_ec(0, EC_DATAABORT_SAME_EL);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, DABORT_ISS, VNCR, 1);\n+ res = FIELD_DP32(res, DABORT_ISS, WNR, wnr);\n+ res = FIELD_DP32(res, DABORT_ISS, DFSC, fsc);\n+\n+ return res;\n }\n \n static inline uint32_t syn_swstep(int same_el, int isv, int ex)\n","prefixes":["v2","10/31"]}