{"id":2226124,"url":"http://patchwork.ozlabs.org/api/patches/2226124/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422093549.407022-12-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422093549.407022-12-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-22T09:35:48","name":"[V14,11/12] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"abba5f1ba9856206e772e59eeef6d23581b4ea95","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422093549.407022-12-sherry.sun@nxp.com/mbox/","series":[{"id":500954,"url":"http://patchwork.ozlabs.org/api/series/500954/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500954","date":"2026-04-22T09:35:40","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":14,"mbox":"http://patchwork.ozlabs.org/series/500954/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226124/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226124/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V14 11/12] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and\n PERST property","Date":"Wed, 22 Apr 2026 17:35:48 +0800","Message-Id":"<20260422093549.407022-12-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260422093549.407022-1-sherry.sun@nxp.com>","References":"<20260422093549.407022-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"SG2PR01CA0140.apcprd01.prod.exchangelabs.com\n (2603:1096:4:8f::20) To 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mqIkVHU3JtEzq5VFdbEZg5Vk5M6wOTU3FC8qfMdgK61ilAhwGUTqh6ACISpgAdmK9Z6/zXnA8xSEgrZWcTao6By14DFbugrKlrOPiNWSJ12AS26XTUMcjW0Dtp9HKTLDwMsSZlnlXAVEmAIGF2sgL/GhtVsyFsWOwmU0VepHkleRTLjGGcVO0D7On9Ar+sRVQWH6l92jrgi2KgCJiZyGI0mkrO0L2HXw6WCvTbyHoRyXM1oqOsA3APTiUsBIUv4wDBHNiXDiI0g8zZOeIfVxQVSLsF97+AEuM6d/TEX1Qo0lhLMjpS8YqCCk9stwmwTLLlg7+dUKo/r6M7E87a1VXuCYAJyGHHbACTemhWOONm3g/klmP1Ejmxn7lg0mpqOUxq8fY1X8Oic3AdALtSbKic8ijy8vimNNjQmANYwk1l1aoMQvoeYk0u0dU5YEFd7oRaUdHwSO4sRdtZr1uly3KFXjsJyfj28L43fGe7Qw8cUeYfbBhHLLTp0e1AnwsgLyshvNYfvsVvgzYI2veWvBDqs4GtCRpmfa8NguCWQ7qXEkWI8WWkZZZePpAWT0O5W0dnUZ2bdd1rhEeVLukLPgVI6LRf/9zlwpZ1eZbEenHPBUGs5eyc3OFp+F06lM7bh134oZUFy8V4Y71gCxb5L3dTjiDqFPPGY/ruyJabRxL7tQN3HMbL8WiHgQk8sLuepVdEj66ARMoh1R9xzRKgsB8oWn+O7xeDfVsYTEter93+pfrylvRNiQZSxz0ppmrLtdaIwPLOkjAcTMb4iuH2doG0w8cs9VeNFZurmfNMBBIdmqUPh3oiPVuZmAaD2p48vQ+iMFvf9QF/0uklui4Dkt7kd9HvbPYbSaLnwjx+bMToS+n4wP9DAIX8z1JrBU8PZcGNIAz3ZmaoBMrtmVzlJUaWcMMxlQtvVE80xAQl/R+WYCTp2BfaGmgAmK/vBflWqX4dkBe2GetmqPBT9615ZdkT5DJByxEqzPv2PA2vTwyim36dHWSocaFMy8vLDmPizb0bOtyiNO5H9D+4FvTkflFsi/d+98zcv4YGxRk6OjJ8/Zo7To/S01FFkm9GuTnLYtEttTWlUS0QinlsjyJNswwqA4k6E493NIUMo3Y3rEw3D5lcf7tiW6nIooGrFBl/WmIDKFXgImFIQ0aXmLGTVGWYyTcTlEJ2FjQ5PRgiGViGvEIBCZ0+WE8MkqdV30g6lzBczCsGtaEekDlVRprNKvqvbvawNFvO72XyblnabtCAHbDPyP19jnqKpliGxltfH3jJoSts6e4lMB3cLEvvGuj38/+WfdMwoJD8nj1k03Ee69WMGAv0/3Fzu7BQCPaHfXF3xGt/K4tJ3ZxkYES2llcXjZlpzS4Af4/qc22GWIavoKII64sNP9/+1OrPLP2e5M2ygpPxeF61LXPCcf78n4AgcjKWeqRfOUph+w+jaWd8gkz6jPznHFS92U8V7bdHyiS/+CRH4n04LkidGKhsayFoF8fAoYsHvgUpJT6bhXPUFkpf1rChFcJ5yld3TA+CjcXlEPVl7tesObfJsXg38/5pWGiWCcwWuC+2eBc3Po7UHvB/NJbnyk5fI9SfLNuXCOywWB6iWeqGRvLNf0+bsi2Y7EBnSjRUk4Bmrs/VIjtde1GNiq+7heImOWsM+6U8iBgastsJCd9Td9emepMnzxydBlk6SFKFehxmXm1x9jhsuisIWMYHrLwjuvZY1Xo1nl6VBP+cy261aQJ/vDWEIWbA==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n afd03521-27e5-4eed-56ee-08dea0527956","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"22 Apr 2026 09:35:21.7704\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n f7cq0XgDVa45icwRkU5noL6Wzq9wZj+q9pUErse1VeqLFjcLcK5etmARrGL0GRaAt3ydkMMad6hc1o4Rl5Ai0A==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"GV4PR04MB11428"},"content":"Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun \n---\n .../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++\n arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +++++\n arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++\n .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++\n arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +++++\n 5 files changed, 53 insertions(+)","diff":"diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\nindex 469de8b536b5..009990b2e559 100644\n--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcieb_ep: pcie-ep@5f010000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\nindex bc62ae5ca812..39108a915f96 100644\n--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n@@ -675,6 +675,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -691,6 +692,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &sai0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_sai0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\nindex 011a89d85961..f706c86137c0 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n@@ -810,6 +810,7 @@ &pciea {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pciea>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pciea>;\n \tvpcie3v3aux-supply = <®_pciea>;\n@@ -817,15 +818,24 @@ &pciea {\n \tstatus = \"okay\";\n };\n \n+&pciea_port0 {\n+\treset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcieb {\n \tphys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &qm_pwm_lvds0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pwm_lvds0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\nindex f2c94cdb682b..2e4fbfe0ca16 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n@@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_A>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpciea_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcie0_ep: pciea_ep: pcie-ep@5f000000 {\n@@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tsata: sata@5f020000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\nindex 623169f7ddb5..489e174df4c4 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n@@ -730,6 +730,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -746,6 +747,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &scu_key {\n \tstatus = \"okay\";\n };\n","prefixes":["V14","11/12"]}