{"id":2226117,"url":"http://patchwork.ozlabs.org/api/patches/2226117/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422093549.407022-2-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422093549.407022-2-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-22T09:35:38","name":"[V14,01/12] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3251068ee9e53f63b745075ba6ef7f82383237bb","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260422093549.407022-2-sherry.sun@nxp.com/mbox/","series":[{"id":500954,"url":"http://patchwork.ozlabs.org/api/series/500954/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500954","date":"2026-04-22T09:35:40","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":14,"mbox":"http://patchwork.ozlabs.org/series/500954/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226117/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226117/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V14 01/12] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in\n Root Port node","Date":"Wed, 22 Apr 2026 17:35:38 +0800","Message-Id":"<20260422093549.407022-2-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260422093549.407022-1-sherry.sun@nxp.com>","References":"<20260422093549.407022-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"SG2PR01CA0140.apcprd01.prod.exchangelabs.com\n (2603:1096:4:8f::20) To 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HoeFgCxxoBNbaYe72PVbsNz+yoDExGE8r7mFrl7ny2bwwQ887L1N/rmyNMauVqlkNLb4omYojMqDWE8WkTah80zy/X9rm+Iqx8BprHt8dOkyNK7k/sTCpUuAzcbxtogg3RY+J+uDM6f4naV+gXUHxVwg9m3GRUgCxaTzEXz32catB79T5Dpsb6FoZLje3OUvp2u76b0T10a0/yrPtIVxzLBR2LoGu3J1hMvh1GdxKa0Dr4uYreYgRqmpaibwp7YwDlrHPPAndihU+CYVSUL0DDCxoLy8DhjS5bnZ+kpWuJfmxPABR6y3Za2pQY7PXhmtJou+G4nEYN5dzcKqkYZVxytWjhcnNsHpkuOVdpM/yMH85vCuRRdO1pD3Viot7jDMqSPMptOmW5eHCQm3dIw1vULkQC7WhRBF8OMS0aTmyuirpvTR7eMJ2yORnu1WVW+XWcUIjZhMFYSrTZNx2l2NeP68tdyFGUKvwb/LgAaow/sSbdNibIFcA1L8yXv3pMWd4uYeCSleuwU8N4f7pBVv0NgOtLz/AqW5jPt34M941SSeGfWnfYNP7IapiXHG9Z+5sXHLNtFzI2di3bs1aqFF7x19klxOc4EXiU79frHKgGL11dWCp0TCl1TrjHB5UYRBgbnVVPNRnP5Nn/l1Fs/j0g6YV1HgRS5dhIuNznShbyu5BONgZV86bypZF2RP2fyidKopYZY6koJueXc+7KePQunpN0/ss9tOr+F941XWbwU4Nx6b1sBgfcfhxAc/0T2i2Fqm/r7M6OytrzokrfBs4s/Z/w0cbioe0YF0CurhXZVw98+KakO60qONazhFjtyGHunbfkMDC4fMLOrRVsvIxlTNE45ON/X8jWk2iAC3ajGq8OkjfgTSb+slAuNglgGkUR6Qa/nuk7f2thYT/r2n/x6nvgUNilw78Lp+QVa+TB7A1Fcbf4wPBmDRr38dYIWMcYdTOu3YFCi0LtZaB3EoDRpFFH9iadCN4oVI7wzR5ygH+yamzi5HuXdb8BToKR2QZsxwpqS6z81a5ze6mAAnyX6goAp6qFSHYPywzmOsbmzFAbvdjZDwbylo6y815YOFZkZWUnZzJTBhGbyi/Bv3pfRzVqqu+29a4V7qCBYTV7/4HA0MSZgfaLdIaDC3W1LcVTq2ZAEDyeOrEeAE/YpSRRJsXOckuX5gvZJPBJDCP60oe9DNmz2dVkSKfdLvceb9QNgnOV+ClkD02pY7xjJ78HVC7yfUDBz+DNSDM5Xl6a8+XDPM/PB0XtI2gwNf577gAxf5q9BQGWdsjLdKU9z4TeYkDxU8UkVyv5ZSAzabfsou/GvdqQuYIIcJZOtkCM8PpUFYXpMTbIhwFgMvxM2PYQjAGUUTqMotkF1/KxTM2REPvp/Ogvg5qqKWDPpepozl5UuUG5Z6yKrJIKijIhHxnQk10YvDhmyf0Ea6UbOnxXzySTunZZGr/ZQof07MoFTu/PIP/S32jxgYtqAZtAvBESmHz2TGBlXHnL7r6xOOT2tnh03zvlqjd+KwfdN3U2PCpQ6RmzGhzTrIE2DhOMuvrvENhQKn6XolnkuONoqu1JENVSg8oALyclHB7jDQGmq8vrmGzutpfBuVFNkB5gErhnlUgEAeWMk+YAMGRtX0VGHuVY94/xLJdM3GtMns8g0ofBCQ0NnthPkDMwb5r+iKEpdEw8xLDyld+sT+vKO9QUhIDsrPYLsrXRhCitIoVA1gVcKVL12Idwo1NMyDpCP3Vw==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 2d7c4ab1-a822-4294-ae90-08dea0524eb1","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"22 Apr 2026 09:34:10.2421\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n Q9iAXVh+rD0IhwUVXMX6F9gg5mO4TPZc1jeK7yOQ3ON/LWcZP4kWRk8ghVoCt/+batqywUc3Xl05ILZWI0bv1g==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"GV4PR04MB11428"},"content":"Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property\nfor the Root Port node.\n\nThe reset-gpios property is already defined in pci-bus-common.yaml for\nPERST#, so use it instead of the local reset-gpio property. Keep the\nexisting reset-gpio property in the bridge node for backward\ncompatibility, but mark it as deprecated.\n\nSigned-off-by: Sherry Sun \nReviewed-by: Rob Herring (Arm) \n---\n .../bindings/pci/fsl,imx6q-pcie.yaml | 32 +++++++++++++++++++\n 1 file changed, 32 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\nindex 9d1349855b42..e8b8131f5f23 100644\n--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n@@ -66,16 +66,34 @@ properties:\n - const: dma\n \n reset-gpio:\n+ deprecated: true\n description: Should specify the GPIO for controlling the PCI bus device\n reset signal. It's not polarity aware and defaults to active-low reset\n sequence (L=reset state, H=operation state) (optional required).\n+ This property is deprecated, instead of referencing this property from the\n+ host bridge node, use the reset-gpios property from the root port node.\n \n reset-gpio-active-high:\n+ deprecated: true\n description: If present then the reset sequence using the GPIO\n specified in the \"reset-gpio\" property is reversed (H=reset state,\n L=operation state) (optional required).\n+ This property is deprecated along with the reset-gpio property above, use\n+ the reset-gpios property from the root port node.\n type: boolean\n \n+ pcie@0:\n+ description:\n+ Describe the i.MX6 PCIe Root Port.\n+ type: object\n+ $ref: /schemas/pci/pci-pci-bridge.yaml#\n+\n+ properties:\n+ reg:\n+ maxItems: 1\n+\n+ unevaluatedProperties: false\n+\n required:\n - compatible\n - reg\n@@ -236,6 +254,7 @@ unevaluatedProperties: false\n examples:\n - |\n #include \n+ #include \n #include \n \n pcie: pcie@1ffc000 {\n@@ -262,5 +281,18 @@ examples:\n <&clks IMX6QDL_CLK_LVDS1_GATE>,\n <&clks IMX6QDL_CLK_PCIE_REF_125M>;\n clock-names = \"pcie\", \"pcie_bus\", \"pcie_phy\";\n+\n+ pcie_port0: pcie@0 {\n+ compatible = \"pciclass,0604\";\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;\n+ };\n };\n ...\n","prefixes":["V14","01/12"]}