{"id":2226058,"url":"http://patchwork.ozlabs.org/api/patches/2226058/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260422064134.1323610-1-kkartik@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260422064134.1323610-1-kkartik@nvidia.com>","list_archive_url":null,"date":"2026-04-22T06:41:34","name":"[RESEND] dmaengine: tegra: Fix burst size calculation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8ecd143e4c2e5618742e27adb99ac60580c498fb","submitter":{"id":83016,"url":"http://patchwork.ozlabs.org/api/people/83016/?format=json","name":"Kartik Rajput","email":"kkartik@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260422064134.1323610-1-kkartik@nvidia.com/mbox/","series":[{"id":500928,"url":"http://patchwork.ozlabs.org/api/series/500928/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500928","date":"2026-04-22T06:41:34","name":"[RESEND] dmaengine: tegra: Fix burst size calculation","version":1,"mbox":"http://patchwork.ozlabs.org/series/500928/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226058/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226058/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YQi7OiZd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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When a\nclient requests a transfer where the length is not evenly divisible by\nthe configured max burst size, the DMA hangs with partial burst at\nthe end.\n\nFix this by reducing the burst size to the largest power-of-2 value\nthat evenly divides the transfer length. For example, a 40-byte\ntransfer with a 16-byte max burst will now use an 8-byte burst\n(40 / 8 = 5 complete bursts) instead of causing a hang.\n\nThis issue was observed with the PL011 UART driver where TX DMA\ntransfers of arbitrary lengths were stuck.\n\nFixes: ee17028009d4 (\"dmaengine: tegra: Add tegra gpcdma driver\")\nCc: stable@vger.kernel.org\nSigned-off-by: Kartik Rajput \nReviewed-by: Frank Li \n---\n drivers/dma/tegra186-gpc-dma.c | 7 +++++++\n 1 file changed, 7 insertions(+)","diff":"diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 5948fbf32c21..0aa3a02b2277 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -825,6 +825,13 @@ static unsigned int get_burst_size(struct tegra_dma_channel *tdc,\n \t * len to calculate the optimum burst size\n \t */\n \tburst_byte = burst_size ? burst_size * slave_bw : len;\n+\n+\t/*\n+\t * Find the largest burst size that evenly divides the transfer length.\n+\t * The hardware requires the transfer length to be a multiple of the\n+\t * burst size - partial bursts are not supported.\n+\t */\n+\tburst_byte = min(burst_byte, 1U << __ffs(len));\n \tburst_mmio_width = burst_byte / 4;\n \n \tif (burst_mmio_width < TEGRA_GPCDMA_MMIOSEQ_BURST_MIN)\n","prefixes":["RESEND"]}