{"id":2226047,"url":"http://patchwork.ozlabs.org/api/patches/2226047/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260422041846.2035118-1-kuba@kernel.org/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<20260422041846.2035118-1-kuba@kernel.org>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/20260422041846.2035118-1-kuba@kernel.org/","date":"2026-04-22T04:18:44","name":"[net-deletions,v2] net: remove unused ATM protocols and legacy ATM device drivers","commit_ref":null,"pull_url":null,"state":"handled-elsewhere","archived":false,"hash":"d0daa544e800b4c1201a30572328da708f880016","submitter":{"id":77159,"url":"http://patchwork.ozlabs.org/api/people/77159/?format=json","name":"Jakub Kicinski","email":"kuba@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260422041846.2035118-1-kuba@kernel.org/mbox/","series":[{"id":500919,"url":"http://patchwork.ozlabs.org/api/series/500919/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=500919","date":"2026-04-22T04:18:44","name":"[net-deletions,v2] net: remove unused ATM protocols and legacy ATM device drivers","version":2,"mbox":"http://patchwork.ozlabs.org/series/500919/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226047/comments/","check":"success","checks":"http://patchwork.ozlabs.org/api/patches/2226047/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n 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d=kernel.org;\n\ts=k20201202; t=1776831532;\n\tbh=fA41cJ+obcn3U+YwhP4f0bQZw8YCu5MM621lrRLrpOg=;\n\th=From:To:Cc:Subject:Date:From;\n\tb=RLCNNIayLuSLQikPsSTPuwPvoL803somGPJkdVMnIzDRsG30GslpbBg7gg7hXBxyL\n\t 30aRGuXOjnwXErqE3DaJ6ZynCVKP68fZ83Ri2KRuHQs10UOmHjd/QEwZvMdeV019aP\n\t +6YZnhlB+6BVBnztn1E9XyfLFOQniQL5sWedaPBNbMb4rPR6sXpW1irTffqtvqSHRX\n\t 3dVOXC1upDSSB+u7PWTuYlsYghEoKvn8jlaLAltqIcwYpqAWBKmPrx4OJLGXR0lWEh\n\t 4VQwgUh0iml2M4ij0Gj95prDbp67plC8+3shgvhE6zvNbLHcfTfWC8iWJ6MFxtTc3f\n\t 9W1ewrNJmsBvg==","From":"Jakub Kicinski ","To":"davem@davemloft.net","Cc":"netdev@vger.kernel.org,\n\tedumazet@google.com,\n\tpabeni@redhat.com,\n\tandrew+netdev@lunn.ch,\n\thorms@kernel.org,\n\tJakub Kicinski ,\n\tcorbet@lwn.net,\n\tskhan@linuxfoundation.org,\n\tlinux@armlinux.org.uk,\n\ttsbogend@alpha.franken.de,\n\tmaddy@linux.ibm.com,\n\tmpe@ellerman.id.au,\n\tnpiggin@gmail.com,\n\tchleroy@kernel.org,\n\t3chas3@gmail.com,\n\trazor@blackwall.org,\n\tidosch@nvidia.com,\n\tjani.nikula@intel.com,\n\tmchehab+huawei@kernel.org,\n\ttytso@mit.edu,\n\therbert@gondor.apana.org.au,\n\tgeert@linux-m68k.org,\n\tebiggers@kernel.org,\n\tjohannes.berg@intel.com,\n\tjonathan.cameron@huawei.com,\n\tkees@kernel.org,\n\tkuniyu@google.com,\n\tfourier.thomas@gmail.com,\n\tandriy.shevchenko@intel.com,\n\trdunlap@infradead.org,\n\takpm@linux-foundation.org,\n\tlinux-doc@vger.kernel.org,\n\tlinux-mips@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tbridge@lists.linux.dev,\n\tdwmw2@infradead.org","Subject":"[PATCH net-deletions v2] net: remove unused ATM protocols and legacy\n ATM device drivers","Date":"Tue, 21 Apr 2026 21:18:44 -0700","Message-ID":"<20260422041846.2035118-1-kuba@kernel.org>","X-Mailer":"git-send-email 2.53.0","X-Mailing-List":"linuxppc-dev@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n ","List-Unsubscribe":"","Precedence":"list","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-Spam-Status":"No, score=-0.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,\n\tDKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,\n\tT_FILL_THIS_FORM_SHORT autolearn=disabled version=4.0.1 OzLabs 8","X-Spam-Checker-Version":"SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org"},"content":"Remove the ATM protocol modules and PCI/SBUS ATM device drivers\nthat are no longer in active use.\n\nThe ATM core protocol stack, PPPoATM, BR2684, and USB DSL modem\ndrivers (drivers/usb/atm/) are retained in-tree to maintain PPP\nover ATM (PPPoA) and PPPoE-over-BR2684 support for DSL connections.\n\nRemoved ATM protocol modules:\n - net/atm/clip.c - Classical IP over ATM (RFC 2225)\n - net/atm/lec.c - LAN Emulation Client (LANE)\n - net/atm/mpc.c, mpoa_caches.c, mpoa_proc.c - Multi-Protocol Over ATM\n\nRemoved PCI/SBUS ATM device drivers (drivers/atm/):\n - adummy, atmtcp - software/testing ATM devices\n - eni - Efficient Networks ENI155P (OC-3, ~1995)\n - fore200e - FORE Systems 200E PCI/SBUS (OC-3, ~1999)\n - he - ForeRunner HE (OC-3/OC-12, ~2000)\n - idt77105 - IDT 77105 25 Mbps ATM PHY\n - idt77252 - IDT 77252 NICStAR II (OC-3, ~2000)\n - iphase - Interphase ATM PCI (OC-3/DS3/E3)\n - lanai - Efficient Networks Speedstream 3010\n - nicstar - IDT 77201 NICStAR (155/25 Mbps, ~1999)\n - solos-pci - Traverse Technologies ADSL2+ PCI\n - suni - PMC S/UNI SONET PHY library\n\nAlso clean up references in:\n - net/bridge/ - remove ATM LANE hook (br_fdb_test_addr_hook,\n br_fdb_test_addr)\n - net/core/dev.c - remove br_fdb_test_addr_hook export\n - defconfig files - remove ATM driver config options\n\nThe removed code is moved to an out-of-tree module package (mod-orphan).\n\nSigned-off-by: Jakub Kicinski \n---\nv2:\n - keep BR2684\n - correct the claim that Traverse Technologies is defunct,\n I'm still deleting the solos driver, chances are nobody uses it.\n Easy enough to revert back in since core is still around.\n The guiding principle is to keep USB modems and delete\n the rest as USB ADSL2+ CPEs were most popular historically.\nv1: https://lore.kernel.org/20260421021943.1295109-1-kuba@kernel.org\n\nCC: corbet@lwn.net\nCC: skhan@linuxfoundation.org\nCC: linux@armlinux.org.uk\nCC: tsbogend@alpha.franken.de\nCC: maddy@linux.ibm.com\nCC: mpe@ellerman.id.au\nCC: npiggin@gmail.com\nCC: chleroy@kernel.org\nCC: 3chas3@gmail.com\nCC: razor@blackwall.org\nCC: idosch@nvidia.com\nCC: jani.nikula@intel.com\nCC: mchehab+huawei@kernel.org\nCC: tytso@mit.edu\nCC: herbert@gondor.apana.org.au\nCC: geert@linux-m68k.org\nCC: ebiggers@kernel.org\nCC: johannes.berg@intel.com\nCC: jonathan.cameron@huawei.com\nCC: kees@kernel.org\nCC: kuniyu@google.com\nCC: fourier.thomas@gmail.com\nCC: andriy.shevchenko@intel.com\nCC: rdunlap@infradead.org\nCC: akpm@linux-foundation.org\nCC: linux-doc@vger.kernel.org\nCC: linux-mips@vger.kernel.org\nCC: linuxppc-dev@lists.ozlabs.org\nCC: bridge@lists.linux.dev\nCC: dwmw2@infradead.org\nCC: herbert@gondor.apana.org.au\n---\n MAINTAINERS | 3 +-\n Documentation/.renames.txt | 2 -\n .../device_drivers/atm/fore200e.rst | 66 -\n .../networking/device_drivers/atm/index.rst | 2 -\n .../networking/device_drivers/atm/iphase.rst | 193 -\n drivers/atm/Kconfig | 325 --\n drivers/net/Kconfig | 2 -\n net/atm/Kconfig | 37 -\n drivers/Makefile | 1 -\n drivers/atm/Makefile | 32 -\n net/atm/Makefile | 4 -\n drivers/atm/eni.h | 136 -\n drivers/atm/fore200e.h | 973 -----\n drivers/atm/he.h | 845 ----\n drivers/atm/idt77105.h | 92 -\n drivers/atm/idt77252.h | 816 ----\n drivers/atm/idt77252_tables.h | 781 ----\n drivers/atm/iphase.h | 1452 -------\n drivers/atm/midway.h | 266 --\n drivers/atm/nicstar.h | 759 ----\n drivers/atm/suni.h | 242 --\n drivers/atm/tonga.h | 21 -\n drivers/atm/zeprom.h | 35 -\n net/atm/lec.h | 155 -\n net/atm/lec_arpc.h | 97 -\n net/atm/mpc.h | 65 -\n net/atm/mpoa_caches.h | 99 -\n net/bridge/br_private.h | 4 -\n drivers/atm/adummy.c | 202 -\n drivers/atm/atmtcp.c | 513 ---\n drivers/atm/eni.c | 2321 ----------\n drivers/atm/fore200e.c | 3012 -------------\n drivers/atm/he.c | 2861 -------------\n drivers/atm/idt77105.c | 376 --\n drivers/atm/idt77252.c | 3797 -----------------\n drivers/atm/iphase.c | 3283 --------------\n drivers/atm/lanai.c | 2603 -----------\n drivers/atm/nicstar.c | 2759 ------------\n drivers/atm/nicstarmac.c | 244 --\n drivers/atm/solos-attrlist.c | 83 -\n drivers/atm/solos-pci.c | 1496 -------\n drivers/atm/suni.c | 391 --\n net/atm/clip.c | 960 -----\n net/atm/lec.c | 2274 ----------\n net/atm/mpc.c | 1538 -------\n net/atm/mpoa_caches.c | 565 ---\n net/atm/mpoa_proc.c | 307 --\n net/bridge/br.c | 7 -\n net/bridge/br_fdb.c | 29 -\n net/core/dev.c | 7 -\n arch/arm/configs/ixp4xx_defconfig | 5 -\n arch/mips/configs/gpr_defconfig | 13 -\n arch/mips/configs/mtx1_defconfig | 13 -\n arch/powerpc/configs/ppc6xx_defconfig | 9 -\n drivers/atm/.gitignore | 5 -\n drivers/atm/nicstarmac.copyright | 61 -\n 56 files changed, 2 insertions(+), 37237 deletions(-)\n delete mode 100644 Documentation/networking/device_drivers/atm/fore200e.rst\n delete mode 100644 Documentation/networking/device_drivers/atm/iphase.rst\n delete mode 100644 drivers/atm/Kconfig\n delete mode 100644 drivers/atm/Makefile\n delete mode 100644 drivers/atm/eni.h\n delete mode 100644 drivers/atm/fore200e.h\n delete mode 100644 drivers/atm/he.h\n delete mode 100644 drivers/atm/idt77105.h\n delete mode 100644 drivers/atm/idt77252.h\n delete mode 100644 drivers/atm/idt77252_tables.h\n delete mode 100644 drivers/atm/iphase.h\n delete mode 100644 drivers/atm/midway.h\n delete mode 100644 drivers/atm/nicstar.h\n delete mode 100644 drivers/atm/suni.h\n delete mode 100644 drivers/atm/tonga.h\n delete mode 100644 drivers/atm/zeprom.h\n delete mode 100644 net/atm/lec.h\n delete mode 100644 net/atm/lec_arpc.h\n delete mode 100644 net/atm/mpc.h\n delete mode 100644 net/atm/mpoa_caches.h\n delete mode 100644 drivers/atm/adummy.c\n delete mode 100644 drivers/atm/atmtcp.c\n delete mode 100644 drivers/atm/eni.c\n delete mode 100644 drivers/atm/fore200e.c\n delete mode 100644 drivers/atm/he.c\n delete mode 100644 drivers/atm/idt77105.c\n delete mode 100644 drivers/atm/idt77252.c\n delete mode 100644 drivers/atm/iphase.c\n delete mode 100644 drivers/atm/lanai.c\n delete mode 100644 drivers/atm/nicstar.c\n delete mode 100644 drivers/atm/nicstarmac.c\n delete mode 100644 drivers/atm/solos-attrlist.c\n delete mode 100644 drivers/atm/solos-pci.c\n delete mode 100644 drivers/atm/suni.c\n delete mode 100644 net/atm/clip.c\n delete mode 100644 net/atm/lec.c\n delete mode 100644 net/atm/mpc.c\n delete mode 100644 net/atm/mpoa_caches.c\n delete mode 100644 net/atm/mpoa_proc.c\n delete mode 100644 drivers/atm/.gitignore\n delete mode 100644 drivers/atm/nicstarmac.copyright","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex e7dc9e6fad2e..e51c85a2fa87 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -4156,11 +4156,12 @@ L:\tlinux-atm-general@lists.sourceforge.net (moderated for non-subscribers)\n L:\tnetdev@vger.kernel.org\n S:\tMaintained\n W:\thttp://linux-atm.sourceforge.net\n-F:\tdrivers/atm/\n+F:\tdrivers/usb/atm/\n F:\tinclude/linux/atm*\n F:\tinclude/linux/sonet.h\n F:\tinclude/uapi/linux/atm*\n F:\tinclude/uapi/linux/sonet.h\n+F:\tnet/atm/\n \n ATMEL MACB ETHERNET DRIVER\n M:\tNicolas Ferre \ndiff --git a/Documentation/.renames.txt b/Documentation/.renames.txt\nindex a37d68471d50..c4de5200abdb 100644\n--- a/Documentation/.renames.txt\n+++ b/Documentation/.renames.txt\n@@ -836,14 +836,12 @@ networking/e100 networking/device_drivers/ethernet/intel/e100\n networking/e1000 networking/device_drivers/ethernet/intel/e1000\n networking/e1000e networking/device_drivers/ethernet/intel/e1000e\n networking/fm10k networking/device_drivers/ethernet/intel/fm10k\n-networking/fore200e networking/device_drivers/atm/fore200e\n networking/hinic networking/device_drivers/ethernet/huawei/hinic\n networking/i40e networking/device_drivers/ethernet/intel/i40e\n networking/iavf networking/device_drivers/ethernet/intel/iavf\n networking/ice networking/device_drivers/ethernet/intel/ice\n networking/igb networking/device_drivers/ethernet/intel/igb\n networking/igbvf networking/device_drivers/ethernet/intel/igbvf\n-networking/iphase networking/device_drivers/atm/iphase\n networking/ixgbe networking/device_drivers/ethernet/intel/ixgbe\n networking/ixgbevf networking/device_drivers/ethernet/intel/ixgbevf\n networking/netdev-FAQ process/maintainer-netdev\ndiff --git a/Documentation/networking/device_drivers/atm/fore200e.rst b/Documentation/networking/device_drivers/atm/fore200e.rst\ndeleted file mode 100644\nindex 55df9ec09ac8..000000000000\n--- a/Documentation/networking/device_drivers/atm/fore200e.rst\n+++ /dev/null\n@@ -1,66 +0,0 @@\n-.. SPDX-License-Identifier: GPL-2.0\n-\n-=============================================\n-FORE Systems PCA-200E/SBA-200E ATM NIC driver\n-=============================================\n-\n-This driver adds support for the FORE Systems 200E-series ATM adapters\n-to the Linux operating system. It is based on the earlier PCA-200E driver\n-written by Uwe Dannowski.\n-\n-The driver simultaneously supports PCA-200E and SBA-200E adapters on\n-i386, alpha (untested), powerpc, sparc and sparc64 archs.\n-\n-The intent is to enable the use of different models of FORE adapters at the\n-same time, by hosts that have several bus interfaces (such as PCI+SBUS,\n-or PCI+EISA).\n-\n-Only PCI and SBUS devices are currently supported by the driver, but support\n-for other bus interfaces such as EISA should not be too hard to add.\n-\n-\n-Firmware Copyright Notice\n--------------------------\n-\n-Please read the fore200e_firmware_copyright file present\n-in the linux/drivers/atm directory for details and restrictions.\n-\n-\n-Firmware Updates\n-----------------\n-\n-The FORE Systems 200E-series driver is shipped with firmware data being\n-uploaded to the ATM adapters at system boot time or at module loading time.\n-The supplied firmware images should work with all adapters.\n-\n-However, if you encounter problems (the firmware doesn't start or the driver\n-is unable to read the PROM data), you may consider trying another firmware\n-version. Alternative binary firmware images can be found somewhere on the\n-ForeThought CD-ROM supplied with your adapter by FORE Systems.\n-\n-You can also get the latest firmware images from FORE Systems at\n-https://en.wikipedia.org/wiki/FORE_Systems. Register TACTics Online and go to\n-the 'software updates' pages. The firmware binaries are part of\n-the various ForeThought software distributions.\n-\n-Notice that different versions of the PCA-200E firmware exist, depending\n-on the endianness of the host architecture. The driver is shipped with\n-both little and big endian PCA firmware images.\n-\n-Name and location of the new firmware images can be set at kernel\n-configuration time:\n-\n-1. Copy the new firmware binary files (with .bin, .bin1 or .bin2 suffix)\n- to some directory, such as linux/drivers/atm.\n-\n-2. Reconfigure your kernel to set the new firmware name and location.\n- Expected pathnames are absolute or relative to the drivers/atm directory.\n-\n-3. Rebuild and re-install your kernel or your module.\n-\n-\n-Feedback\n---------\n-\n-Feedback is welcome. Please send success stories/bug reports/\n-patches/improvement/comments/flames to .\ndiff --git a/Documentation/networking/device_drivers/atm/index.rst b/Documentation/networking/device_drivers/atm/index.rst\nindex 724552ca0be4..9392c86f48bc 100644\n--- a/Documentation/networking/device_drivers/atm/index.rst\n+++ b/Documentation/networking/device_drivers/atm/index.rst\n@@ -9,5 +9,3 @@ Asynchronous Transfer Mode (ATM) Device Drivers\n :maxdepth: 2\n \n cxacru\n- fore200e\n- iphase\ndiff --git a/Documentation/networking/device_drivers/atm/iphase.rst b/Documentation/networking/device_drivers/atm/iphase.rst\ndeleted file mode 100644\nindex 388c7101e2cb..000000000000\n--- a/Documentation/networking/device_drivers/atm/iphase.rst\n+++ /dev/null\n@@ -1,193 +0,0 @@\n-.. SPDX-License-Identifier: GPL-2.0\n-\n-==================================\n-ATM (i)Chip IA Linux Driver Source\n-==================================\n-\n-\t\t\t READ ME FIRST\n-\n---------------------------------------------------------------------------------\n-\n-\t\t Read This Before You Begin!\n-\n---------------------------------------------------------------------------------\n-\n-Description\n-===========\n-\n-This is the README file for the Interphase PCI ATM (i)Chip IA Linux driver\n-source release.\n-\n-The features and limitations of this driver are as follows:\n-\n- - A single VPI (VPI value of 0) is supported.\n- - Supports 4K VCs for the server board (with 512K control memory) and 1K\n- VCs for the client board (with 128K control memory).\n- - UBR, ABR and CBR service categories are supported.\n- - Only AAL5 is supported.\n- - Supports setting of PCR on the VCs.\n- - Multiple adapters in a system are supported.\n- - All variants of Interphase ATM PCI (i)Chip adapter cards are supported,\n- including x575 (OC3, control memory 128K , 512K and packet memory 128K,\n- 512K and 1M), x525 (UTP25) and x531 (DS3 and E3). See\n- http://www.iphase.com/\n- for details.\n- - Only x86 platforms are supported.\n- - SMP is supported.\n-\n-\n-Before You Start\n-================\n-\n-\n-Installation\n-------------\n-\n-1. Installing the adapters in the system\n-\n- To install the ATM adapters in the system, follow the steps below.\n-\n- a. Login as root.\n- b. Shut down the system and power off the system.\n- c. Install one or more ATM adapters in the system.\n- d. Connect each adapter to a port on an ATM switch. The green 'Link'\n-\t LED on the front panel of the adapter will be on if the adapter is\n-\t connected to the switch properly when the system is powered up.\n- e. Power on and boot the system.\n-\n-2. [ Removed ]\n-\n-3. Rebuild kernel with ABR support\n-\n- [ a. and b. removed ]\n-\n- c. Reconfigure the kernel, choose the Interphase ia driver through \"make\n- menuconfig\" or \"make xconfig\".\n- d. Rebuild the kernel, loadable modules and the atm tools.\n- e. Install the new built kernel and modules and reboot.\n-\n-4. Load the adapter hardware driver (ia driver) if it is built as a module\n-\n- a. Login as root.\n- b. Change directory to /lib/modules//atm.\n- c. Run \"insmod suni.o;insmod iphase.o\"\n-\t The yellow 'status' LED on the front panel of the adapter will blink\n-\t while the driver is loaded in the system.\n- d. To verify that the 'ia' driver is loaded successfully, run the\n-\t following command::\n-\n-\t cat /proc/atm/devices\n-\n-\t If the driver is loaded successfully, the output of the command will\n-\t be similar to the following lines::\n-\n-\t Itf Type ESI/\"MAC\"addr AAL(TX,err,RX,err,drop) ...\n-\t 0 ia xxxxxxxxx 0 ( 0 0 0 0 0 ) 5 ( 0 0 0 0 0 )\n-\n-\t You can also check the system log file /var/log/messages for messages\n-\t related to the ATM driver.\n-\n-5. Ia Driver Configuration\n-\n-5.1 Configuration of adapter buffers\n- The (i)Chip boards have 3 different packet RAM size variants: 128K, 512K and\n- 1M. The RAM size decides the number of buffers and buffer size. The default\n- size and number of buffers are set as following:\n-\n-\t========= ======= ====== ====== ====== ====== ======\n-\t Total Rx RAM Tx RAM Rx Buf Tx Buf Rx buf Tx buf\n-\t RAM size size size size size cnt cnt\n-\t========= ======= ====== ====== ====== ====== ======\n-\t 128K 64K 64K 10K 10K 6 6\n-\t 512K 256K 256K 10K 10K 25 25\n-\t 1M 512K 512K 10K 10K 51 51\n-\t========= ======= ====== ====== ====== ====== ======\n-\n- These setting should work well in most environments, but can be\n- changed by typing the following command::\n-\n-\t insmod /ia.o IA_RX_BUF= IA_RX_BUF_SZ= \\\n-\t\t IA_TX_BUF= IA_TX_BUF_SZ=\n-\n- Where:\n-\n-\t - RX_CNT = number of receive buffers in the range (1-128)\n-\t - RX_SIZE = size of receive buffers in the range (48-64K)\n-\t - TX_CNT = number of transmit buffers in the range (1-128)\n-\t - TX_SIZE = size of transmit buffers in the range (48-64K)\n-\n-\t 1. Transmit and receive buffer size must be a multiple of 4.\n-\t 2. Care should be taken so that the memory required for the\n-\t transmit and receive buffers is less than or equal to the\n-\t total adapter packet memory.\n-\n-5.2 Turn on ia debug trace\n-\n- When the ia driver is built with the CONFIG_ATM_IA_DEBUG flag, the driver\n- can provide more debug trace if needed. There is a bit mask variable,\n- IADebugFlag, which controls the output of the traces. You can find the bit\n- map of the IADebugFlag in iphase.h.\n- The debug trace can be turn on through the insmod command line option, for\n- example, \"insmod iphase.o IADebugFlag=0xffffffff\" can turn on all the debug\n- traces together with loading the driver.\n-\n-6. Ia Driver Test Using ttcp_atm and PVC\n-\n- For the PVC setup, the test machines can either be connected back-to-back or\n- through a switch. If connected through the switch, the switch must be\n- configured for the PVC(s).\n-\n- a. For UBR test:\n-\n- At the test machine intended to receive data, type::\n-\n-\t ttcp_atm -r -a -s 0.100\n-\n- At the other test machine, type::\n-\n-\t ttcp_atm -t -a -s 0.100 -n 10000\n-\n- Run \"ttcp_atm -h\" to display more options of the ttcp_atm tool.\n- b. For ABR test:\n-\n- It is the same as the UBR testing, but with an extra command option::\n-\n-\t -Pabr:max_pcr=\n-\n- where:\n-\n-\t xxx = the maximum peak cell rate, from 170 - 353207.\n-\n- This option must be set on both the machines.\n-\n- c. For CBR test:\n-\n- It is the same as the UBR testing, but with an extra command option::\n-\n-\t -Pcbr:max_pcr=\n-\n- where:\n-\n-\t xxx = the maximum peak cell rate, from 170 - 353207.\n-\n- This option may only be set on the transmit machine.\n-\n-\n-Outstanding Issues\n-==================\n-\n-\n-\n-Contact Information\n--------------------\n-\n-::\n-\n- Customer Support:\n-\t United States:\tTelephone:\t(214) 654-5555\n-\t\t\tFax:\t\t(214) 654-5500\n-\t\t\tE-Mail:\t\tintouch@iphase.com\n-\t Europe:\tTelephone:\t33 (0)1 41 15 44 00\n-\t\t\tFax:\t\t33 (0)1 41 15 12 13\n- World Wide Web:\thttp://www.iphase.com\n- Anonymous FTP:\tftp.iphase.com\ndiff --git a/drivers/atm/Kconfig b/drivers/atm/Kconfig\ndeleted file mode 100644\nindex 63cdb46a3439..000000000000\n--- a/drivers/atm/Kconfig\n+++ /dev/null\n@@ -1,325 +0,0 @@\n-# SPDX-License-Identifier: GPL-2.0\n-#\n-# ATM device configuration\n-#\n-\n-menuconfig ATM_DRIVERS\n-\tbool \"ATM drivers\"\n-\tdepends on NETDEVICES && ATM\n-\tdefault y\n-\thelp\n-\t Say Y here to get to see options for Asynchronous Transfer Mode\n-\t device drivers. This option alone does not add any kernel code.\n-\n-\t If you say N, all options in this submenu will be skipped and disabled.\n-\n-if ATM_DRIVERS && NETDEVICES && ATM\n-\n-config ATM_DUMMY\n-\ttristate \"Dummy ATM driver\"\n-\thelp\n-\t Dummy ATM driver. Useful for proxy signalling, testing,\n-\t and development. If unsure, say N.\n-\n-config ATM_TCP\n-\ttristate \"ATM over TCP\"\n-\tdepends on INET\n-\thelp\n-\t ATM over TCP driver. Useful mainly for development and for\n-\t experiments. If unsure, say N.\n-\n-config ATM_LANAI\n-\ttristate \"Efficient Networks Speedstream 3010\"\n-\tdepends on PCI && ATM\n-\thelp\n-\t Supports ATM cards based on the Efficient Networks \"Lanai\"\n-\t chipset such as the Speedstream 3010 and the ENI-25p. The\n-\t Speedstream 3060 is currently not supported since we don't\n-\t have the code to drive the on-board Alcatel DSL chipset (yet).\n-\n-config ATM_ENI\n-\ttristate \"Efficient Networks ENI155P\"\n-\tdepends on PCI\n-\thelp\n-\t Driver for the Efficient Networks ENI155p series and SMC ATM\n-\t Power155 155 Mbps ATM adapters. Both, the versions with 512KB and\n-\t 2MB on-board RAM (Efficient calls them \"C\" and \"S\", respectively),\n-\t and the FPGA and the ASIC Tonga versions of the board are supported.\n-\t The driver works with MMF (-MF or ...F) and UTP-5 (-U5 or ...D)\n-\t adapters.\n-\n-\t To compile this driver as a module, choose M here: the module will\n-\t be called eni.\n-\n-config ATM_ENI_DEBUG\n-\tbool \"Enable extended debugging\"\n-\tdepends on ATM_ENI\n-\thelp\n-\t Extended debugging records various events and displays that list\n-\t when an inconsistency is detected. This mechanism is faster than\n-\t generally using printks, but still has some impact on performance.\n-\t Note that extended debugging may create certain race conditions\n-\t itself. Enable this ONLY if you suspect problems with the driver.\n-\n-config ATM_ENI_TUNE_BURST\n-\tbool \"Fine-tune burst settings\"\n-\tdepends on ATM_ENI\n-\thelp\n-\t In order to obtain good throughput, the ENI NIC can transfer\n-\t multiple words of data per PCI bus access cycle. Such a multi-word\n-\t transfer is called a burst.\n-\n-\t The default settings for the burst sizes are suitable for most PCI\n-\t chipsets. However, in some cases, large bursts may overrun buffers\n-\t in the PCI chipset and cause data corruption. In such cases, large\n-\t bursts must be disabled and only (slower) small bursts can be used.\n-\t The burst sizes can be set independently in the send (TX) and\n-\t receive (RX) direction.\n-\n-\t Note that enabling many different burst sizes in the same direction\n-\t may increase the cost of setting up a transfer such that the\n-\t resulting throughput is lower than when using only the largest\n-\t available burst size.\n-\n-\t Also, sometimes larger bursts lead to lower throughput, e.g. on an\n-\t Intel 440FX board, a drop from 135 Mbps to 103 Mbps was observed\n-\t when going from 8W to 16W bursts.\n-\n-config ATM_ENI_BURST_TX_16W\n-\tbool \"Enable 16W TX bursts (discouraged)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst sixteen words at once in the send direction. This may work\n-\t with recent PCI chipsets, but is known to fail with older chipsets.\n-\n-config ATM_ENI_BURST_TX_8W\n-\tbool \"Enable 8W TX bursts (recommended)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst eight words at once in the send direction. This is the default\n-\t setting.\n-\n-config ATM_ENI_BURST_TX_4W\n-\tbool \"Enable 4W TX bursts (optional)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst four words at once in the send direction. You may want to try\n-\t this if you have disabled 8W bursts. Enabling 4W if 8W is also set\n-\t may or may not improve throughput.\n-\n-config ATM_ENI_BURST_TX_2W\n-\tbool \"Enable 2W TX bursts (optional)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst two words at once in the send direction. You may want to try\n-\t this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or 8W\n-\t are also set may or may not improve throughput.\n-\n-config ATM_ENI_BURST_RX_16W\n-\tbool \"Enable 16W RX bursts (discouraged)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst sixteen words at once in the receive direction. This may work\n-\t with recent PCI chipsets, but is known to fail with older chipsets.\n-\n-config ATM_ENI_BURST_RX_8W\n-\tbool \"Enable 8W RX bursts (discouraged)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst eight words at once in the receive direction. This may work\n-\t with recent PCI chipsets, but is known to fail with older chipsets,\n-\t such as the Intel Neptune series.\n-\n-config ATM_ENI_BURST_RX_4W\n-\tbool \"Enable 4W RX bursts (recommended)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst four words at once in the receive direction. This is the\n-\t default setting. Enabling 4W if 8W is also set may or may not\n-\t improve throughput.\n-\n-config ATM_ENI_BURST_RX_2W\n-\tbool \"Enable 2W RX bursts (optional)\"\n-\tdepends on ATM_ENI_TUNE_BURST\n-\thelp\n-\t Burst two words at once in the receive direction. You may want to\n-\t try this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or\n-\t 8W are also set may or may not improve throughput.\n-\n-config ATM_NICSTAR\n-\ttristate \"IDT 77201 (NICStAR) (ForeRunnerLE)\"\n-\tdepends on PCI\n-\thelp\n-\t The NICStAR chipset family is used in a large number of ATM NICs for\n-\t 25 and for 155 Mbps, including IDT cards and the Fore ForeRunnerLE\n-\t series. Say Y if you have one of those.\n-\n-\t To compile this driver as a module, choose M here: the module will\n-\t be called nicstar.\n-\n-config ATM_NICSTAR_USE_SUNI\n-\tbool \"Use suni PHY driver (155Mbps)\"\n-\tdepends on ATM_NICSTAR\n-\thelp\n-\t Support for the S-UNI and compatible PHYsical layer chips. These are\n-\t found in most 155Mbps NICStAR based ATM cards, namely in the\n-\t ForeRunner LE155 cards. This driver provides detection of cable~\n-\t removal and reinsertion and provides some statistics. This driver\n-\t doesn't have removal capability when compiled as a module, so if you\n-\t need that capability don't include S-UNI support (it's not needed to\n-\t make the card work).\n-\n-config ATM_NICSTAR_USE_IDT77105\n-\tbool \"Use IDT77105 PHY driver (25Mbps)\"\n-\tdepends on ATM_NICSTAR\n-\thelp\n-\t Support for the PHYsical layer chip in ForeRunner LE25 cards. In\n-\t addition to cable removal/reinsertion detection, this driver allows\n-\t you to control the loopback mode of the chip via a dedicated IOCTL.\n-\t This driver is required for proper handling of temporary carrier\n-\t loss, so if you have a 25Mbps NICStAR based ATM card you must say Y.\n-\n-config ATM_IDT77252\n-\ttristate \"IDT 77252 (NICStAR II)\"\n-\tdepends on PCI\n-\thelp\n-\t Driver for the IDT 77252 ATM PCI chips.\n-\n-\t To compile this driver as a module, choose M here: the module will\n-\t be called idt77252.\n-\n-config ATM_IDT77252_DEBUG\n-\tbool \"Enable debugging messages\"\n-\tdepends on ATM_IDT77252\n-\thelp\n-\t Somewhat useful debugging messages are available. The choice of\n-\t messages is controlled by a bitmap. This may be specified as a\n-\t module argument. See the file for\n-\t the meanings of the bits in the mask.\n-\n-\t When active, these messages can have a significant impact on the\n-\t speed of the driver, and the size of your syslog files! When\n-\t inactive, they will have only a modest impact on performance.\n-\n-config ATM_IDT77252_RCV_ALL\n-\tbool \"Receive ALL cells in raw queue\"\n-\tdepends on ATM_IDT77252\n-\thelp\n-\t Enable receiving of all cells on the ATM link, that do not match\n-\t an open connection in the raw cell queue of the driver. Useful\n-\t for debugging or special applications only, so the safe answer is N.\n-\n-config ATM_IDT77252_USE_SUNI\n-\tbool\n-\tdepends on ATM_IDT77252\n-\tdefault y\n-\n-config ATM_IA\n-\ttristate \"Interphase ATM PCI x575/x525/x531\"\n-\tdepends on PCI\n-\thelp\n-\t This is a driver for the Interphase (i)ChipSAR adapter cards\n-\t which include a variety of variants in term of the size of the\n-\t control memory (128K-1KVC, 512K-4KVC), the size of the packet\n-\t memory (128K, 512K, 1M), and the PHY type (Single/Multi mode OC3,\n-\t UTP155, UTP25, DS3 and E3). Go to:\n-\t \t\n-\t for more info about the cards. Say Y (or M to compile as a module\n-\t named iphase) here if you have one of these cards.\n-\n-\t See the file\n-\t \n-\t for further details.\n-\n-config ATM_IA_DEBUG\n-\tbool \"Enable debugging messages\"\n-\tdepends on ATM_IA\n-\thelp\n-\t Somewhat useful debugging messages are available. The choice of\n-\t messages is controlled by a bitmap. This may be specified as a\n-\t module argument (kernel command line argument as well?), changed\n-\t dynamically using an ioctl (Get the debug utility, iadbg, from\n-\t ).\n-\n-\t See the file for the meanings of the\n-\t bits in the mask.\n-\n-\t When active, these messages can have a significant impact on the\n-\t speed of the driver, and the size of your syslog files! When\n-\t inactive, they will have only a modest impact on performance.\n-\n-config ATM_FORE200E\n-\ttristate \"FORE Systems 200E-series\"\n-\tdepends on (PCI || SBUS)\n-\tselect FW_LOADER\n-\thelp\n-\t This is a driver for the FORE Systems 200E-series ATM adapter\n-\t cards. It simultaneously supports PCA-200E and SBA-200E models\n-\t on PCI and SBUS hosts. Say Y (or M to compile as a module\n-\t named fore_200e) here if you have one of these ATM adapters.\n-\n-\t See the file\n-\t for\n-\t further details.\n-\n-config ATM_FORE200E_USE_TASKLET\n-\tbool \"Defer interrupt work to a tasklet\"\n-\tdepends on ATM_FORE200E\n-\tdefault n\n-\thelp\n-\t This defers work to be done by the interrupt handler to a\n-\t tasklet instead of handling everything at interrupt time. This\n-\t may improve the responsive of the host.\n-\n-config ATM_FORE200E_TX_RETRY\n-\tint \"Maximum number of tx retries\"\n-\tdepends on ATM_FORE200E\n-\tdefault \"16\"\n-\thelp\n-\t Specifies the number of times the driver attempts to transmit\n-\t a message before giving up, if the transmit queue of the ATM card\n-\t is transiently saturated.\n-\n-\t Saturation of the transmit queue may occur only under extreme\n-\t conditions, e.g. when a fast host continuously submits very small\n-\t frames (<64 bytes) or raw AAL0 cells (48 bytes) to the ATM adapter.\n-\n-\t Note that under common conditions, it is unlikely that you encounter\n-\t a saturation of the transmit queue, so the retry mechanism never\n-\t comes into play.\n-\n-config ATM_FORE200E_DEBUG\n-\tint \"Debugging level (0-3)\"\n-\tdepends on ATM_FORE200E\n-\tdefault \"0\"\n-\thelp\n-\t Specifies the level of debugging messages issued by the driver.\n-\t The verbosity of the driver increases with the value of this\n-\t parameter.\n-\n-\t When active, these messages can have a significant impact on\n-\t the performances of the driver, and the size of your syslog files!\n-\t Keep the debugging level to 0 during normal operations.\n-\n-config ATM_HE\n-\ttristate \"ForeRunner HE Series\"\n-\tdepends on PCI\n-\thelp\n-\t This is a driver for the Marconi ForeRunner HE-series ATM adapter\n-\t cards. It simultaneously supports the 155 and 622 versions.\n-\n-config ATM_HE_USE_SUNI\n-\tbool \"Use S/UNI PHY driver\"\n-\tdepends on ATM_HE\n-\thelp\n-\t Support for the S/UNI-Ultra and S/UNI-622 found in the ForeRunner\n-\t HE cards. This driver provides carrier detection some statistics.\n-\n-config ATM_SOLOS\n-\ttristate \"Solos ADSL2+ PCI Multiport card driver\"\n-\tdepends on PCI\n-\tselect FW_LOADER\n-\thelp\n-\t Support for the Solos multiport ADSL2+ card.\n-\n-endif # ATM\ndiff --git a/drivers/net/Kconfig b/drivers/net/Kconfig\nindex edaab759dc50..f3764818b68a 100644\n--- a/drivers/net/Kconfig\n+++ b/drivers/net/Kconfig\n@@ -501,8 +501,6 @@ config SUNGEM_PHY\n \n source \"drivers/net/arcnet/Kconfig\"\n \n-source \"drivers/atm/Kconfig\"\n-\n source \"drivers/net/caif/Kconfig\"\n \n source \"drivers/net/dsa/Kconfig\"\ndiff --git a/net/atm/Kconfig b/net/atm/Kconfig\nindex 77343d57ff2a..dfdc3a8553ba 100644\n--- a/net/atm/Kconfig\n+++ b/net/atm/Kconfig\n@@ -19,43 +19,6 @@ config ATM\n \t of ATM. See the file for\n \t further details.\n \n-config ATM_CLIP\n-\ttristate \"Classical IP over ATM\"\n-\tdepends on ATM && INET\n-\thelp\n-\t Classical IP over ATM for PVCs and SVCs, supporting InARP and\n-\t ATMARP. If you want to communication with other IP hosts on your ATM\n-\t network, you will typically either say Y here or to \"LAN Emulation\n-\t (LANE)\" below.\n-\n-config ATM_CLIP_NO_ICMP\n-\tbool \"Do NOT send ICMP if no neighbour\"\n-\tdepends on ATM_CLIP\n-\thelp\n-\t Normally, an \"ICMP host unreachable\" message is sent if a neighbour\n-\t cannot be reached because there is no VC to it in the kernel's\n-\t ATMARP table. This may cause problems when ATMARP table entries are\n-\t briefly removed during revalidation. If you say Y here, packets to\n-\t such neighbours are silently discarded instead.\n-\n-config ATM_LANE\n-\ttristate \"LAN Emulation (LANE) support\"\n-\tdepends on ATM\n-\thelp\n-\t LAN Emulation emulates services of existing LANs across an ATM\n-\t network. Besides operating as a normal ATM end station client, Linux\n-\t LANE client can also act as an proxy client bridging packets between\n-\t ELAN and Ethernet segments. You need LANE if you want to try MPOA.\n-\n-config ATM_MPOA\n-\ttristate \"Multi-Protocol Over ATM (MPOA) support\"\n-\tdepends on ATM && INET && ATM_LANE!=n\n-\thelp\n-\t Multi-Protocol Over ATM allows ATM edge devices such as routers,\n-\t bridges and ATM attached hosts establish direct ATM VCs across\n-\t subnetwork boundaries. These shortcut connections bypass routers\n-\t enhancing overall network performance.\n-\n config ATM_BR2684\n \ttristate \"RFC1483/2684 Bridged protocols\"\n \tdepends on ATM && INET\ndiff --git a/drivers/Makefile b/drivers/Makefile\nindex 53fbd2e0acdd..c902fe94f6e8 100644\n--- a/drivers/Makefile\n+++ b/drivers/Makefile\n@@ -90,7 +90,6 @@ obj-$(CONFIG_SPMI)\t\t+= spmi/\n obj-$(CONFIG_HSI)\t\t+= hsi/\n obj-$(CONFIG_SLIMBUS)\t\t+= slimbus/\n obj-y\t\t\t\t+= net/\n-obj-$(CONFIG_ATM)\t\t+= atm/\n obj-$(CONFIG_FUSION)\t\t+= message/\n obj-y\t\t\t\t+= firewire/\n obj-$(CONFIG_UIO)\t\t+= uio/\ndiff --git a/drivers/atm/Makefile b/drivers/atm/Makefile\ndeleted file mode 100644\nindex c9eade92019b..000000000000\n--- a/drivers/atm/Makefile\n+++ /dev/null\n@@ -1,32 +0,0 @@\n-# SPDX-License-Identifier: GPL-2.0\n-#\n-# Makefile for the Linux network (ATM) device drivers.\n-#\n-\n-fore_200e-y\t:= fore200e.o\n-\n-obj-$(CONFIG_ATM_NICSTAR)\t+= nicstar.o\n-obj-$(CONFIG_ATM_IA)\t\t+= iphase.o suni.o\n-obj-$(CONFIG_ATM_FORE200E)\t+= fore_200e.o\n-obj-$(CONFIG_ATM_ENI)\t\t+= eni.o suni.o\n-obj-$(CONFIG_ATM_IDT77252)\t+= idt77252.o\n-obj-$(CONFIG_ATM_SOLOS)\t\t+= solos-pci.o\n-\n-ifeq ($(CONFIG_ATM_NICSTAR_USE_SUNI),y)\n- obj-$(CONFIG_ATM_NICSTAR)\t+= suni.o\n-endif\n-ifeq ($(CONFIG_ATM_NICSTAR_USE_IDT77105),y)\n- obj-$(CONFIG_ATM_NICSTAR)\t+= idt77105.o\n-endif\n-ifeq ($(CONFIG_ATM_IDT77252_USE_SUNI),y)\n- obj-$(CONFIG_ATM_IDT77252)\t+= suni.o\n-endif\n-\n-obj-$(CONFIG_ATM_DUMMY)\t\t+= adummy.o\n-obj-$(CONFIG_ATM_TCP)\t\t+= atmtcp.o\n-obj-$(CONFIG_ATM_LANAI)\t\t+= lanai.o\n-\n-obj-$(CONFIG_ATM_HE)\t\t+= he.o\n-ifeq ($(CONFIG_ATM_HE_USE_SUNI),y)\n- obj-$(CONFIG_ATM_HE)\t\t+= suni.o\n-endif\ndiff --git a/net/atm/Makefile b/net/atm/Makefile\nindex bfec0f2d83b5..484a1b1552cc 100644\n--- a/net/atm/Makefile\n+++ b/net/atm/Makefile\n@@ -4,13 +4,9 @@\n #\n \n atm-y\t\t:= addr.o pvc.o signaling.o svc.o ioctl.o common.o atm_misc.o raw.o resources.o atm_sysfs.o\n-mpoa-objs\t:= mpc.o mpoa_caches.o mpoa_proc.o\n \n obj-$(CONFIG_ATM) += atm.o\n-obj-$(CONFIG_ATM_CLIP) += clip.o\n obj-$(CONFIG_ATM_BR2684) += br2684.o\n atm-$(CONFIG_PROC_FS) += proc.o\n \n-obj-$(CONFIG_ATM_LANE) += lec.o\n-obj-$(CONFIG_ATM_MPOA) += mpoa.o\n obj-$(CONFIG_PPPOATM) += pppoatm.o\ndiff --git a/drivers/atm/eni.h b/drivers/atm/eni.h\ndeleted file mode 100644\nindex de1ed802cbf8..000000000000\n--- a/drivers/atm/eni.h\n+++ /dev/null\n@@ -1,136 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */\n- \n-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */\n- \n- \n-#ifndef DRIVER_ATM_ENI_H\n-#define DRIVER_ATM_ENI_H\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \"midway.h\"\n-\n-\n-#define DEV_LABEL\t\"eni\"\n-\n-#define UBR_BUFFER\t(128*1024)\t/* UBR buffer size */\n-\n-#define RX_DMA_BUF\t 8\t\t/* burst and skip a few things */\n-#define TX_DMA_BUF\t100\t\t/* should be enough for 64 kB */\n-\n-#define DEFAULT_RX_MULT\t300\t\t/* max_sdu*3 */\n-#define DEFAULT_TX_MULT\t300\t\t/* max_sdu*3 */\n-\n-#define ENI_ZEROES_SIZE\t 4\t\t/* need that many DMA-able zero bytes */\n-\n-\n-struct eni_free {\n-\tvoid __iomem *start;\t\t/* counting in bytes */\n-\tint order;\n-};\n-\n-struct eni_tx {\n-\tvoid __iomem *send;\t\t/* base, 0 if unused */\n-\tint prescaler;\t\t\t/* shaping prescaler */\n-\tint resolution;\t\t\t/* shaping divider */\n-\tunsigned long tx_pos;\t\t/* current TX write position */\n-\tunsigned long words;\t\t/* size of TX queue */\n-\tint index;\t\t\t/* TX channel number */\n-\tint reserved;\t\t\t/* reserved peak cell rate */\n-\tint shaping;\t\t\t/* shaped peak cell rate */\n-\tstruct sk_buff_head backlog;\t/* queue of waiting TX buffers */\n-};\n-\n-struct eni_vcc {\n-\tint (*rx)(struct atm_vcc *vcc);\t/* RX function, NULL if none */\n-\tvoid __iomem *recv;\t\t/* receive buffer */\n-\tunsigned long words;\t\t/* its size in words */\n-\tunsigned long descr;\t\t/* next descriptor (RX) */\n-\tunsigned long rx_pos;\t\t/* current RX descriptor pos */\n-\tstruct eni_tx *tx;\t\t/* TXer, NULL if none */\n-\tint rxing;\t\t\t/* number of pending PDUs */\n-\tint servicing;\t\t\t/* number of waiting VCs (0 or 1) */\n-\tint txing;\t\t\t/* number of pending TX bytes */\n-\tktime_t timestamp;\t\t/* for RX timing */\n-\tstruct atm_vcc *next;\t\t/* next pending RX */\n-\tstruct sk_buff *last;\t\t/* last PDU being DMAed (used to carry\n-\t\t\t\t\t discard information) */\n-};\n-\n-struct eni_dev {\n-\t/*-------------------------------- spinlock */\n-\tspinlock_t lock;\t\t/* sync with interrupt */\n-\tstruct tasklet_struct task;\t/* tasklet for interrupt work */\n-\tu32 events;\t\t\t/* pending events */\n-\t/*-------------------------------- base pointers into Midway address\n-\t\t\t\t\t space */\n-\tvoid __iomem *ioaddr;\n-\tvoid __iomem *phy;\t\t/* PHY interface chip registers */\n-\tvoid __iomem *reg;\t\t/* register base */\n-\tvoid __iomem *ram;\t\t/* RAM base */\n-\tvoid __iomem *vci;\t\t/* VCI table */\n-\tvoid __iomem *rx_dma;\t\t/* RX DMA queue */\n-\tvoid __iomem *tx_dma;\t\t/* TX DMA queue */\n-\tvoid __iomem *service;\t\t/* service list */\n-\t/*-------------------------------- TX part */\n-\tstruct eni_tx tx[NR_CHAN];\t/* TX channels */\n-\tstruct eni_tx *ubr;\t\t/* UBR channel */\n-\tstruct sk_buff_head tx_queue;\t/* PDUs currently being TX DMAed*/\n-\twait_queue_head_t tx_wait;\t/* for close */\n-\tint tx_bw;\t\t\t/* remaining bandwidth */\n-\tu32 dma[TX_DMA_BUF*2];\t\t/* DMA request scratch area */\n-\tstruct eni_zero {\t\t/* aligned \"magic\" zeroes */\n-\t\tu32 *addr;\n-\t\tdma_addr_t dma;\n-\t} zero;\n-\tint tx_mult;\t\t\t/* buffer size multiplier (percent) */\n-\t/*-------------------------------- RX part */\n-\tu32 serv_read;\t\t\t/* host service read index */\n-\tstruct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */\n-\tstruct atm_vcc *slow,*last_slow;\n-\tstruct atm_vcc **rx_map;\t/* for fast lookups */\n-\tstruct sk_buff_head rx_queue;\t/* PDUs currently being RX-DMAed */\n-\twait_queue_head_t rx_wait;\t/* for close */\n-\tint rx_mult;\t\t\t/* buffer size multiplier (percent) */\n-\t/*-------------------------------- statistics */\n-\tunsigned long lost;\t\t/* number of lost cells (RX) */\n-\t/*-------------------------------- memory management */\n-\tunsigned long base_diff;\t/* virtual-real base address */\n-\tint free_len;\t\t\t/* free list length */\n-\tstruct eni_free *free_list;\t/* free list */\n-\tint free_list_size;\t\t/* maximum size of free list */\n-\t/*-------------------------------- ENI links */\n-\tstruct atm_dev *more;\t\t/* other ENI devices */\n-\t/*-------------------------------- general information */\n-\tint mem;\t\t\t/* RAM on board (in bytes) */\n-\tint asic;\t\t\t/* PCI interface type, 0 for FPGA */\n-\tunsigned int irq;\t\t/* IRQ */\n-\tstruct pci_dev *pci_dev;\t/* PCI stuff */\n-};\n-\n-\n-#define ENI_DEV(d) ((struct eni_dev *) (d)->dev_data)\n-#define ENI_VCC(d) ((struct eni_vcc *) (d)->dev_data)\n-\n-\n-struct eni_skb_prv {\n-\tstruct atm_skb_data _;\t\t/* reserved */\n-\tunsigned long pos;\t\t/* position of next descriptor */\n-\tint size;\t\t\t/* PDU size in reassembly buffer */\n-\tdma_addr_t paddr;\t\t/* DMA handle */\n-};\n-\n-#define ENI_PRV_SIZE(skb) (((struct eni_skb_prv *) (skb)->cb)->size)\n-#define ENI_PRV_POS(skb) (((struct eni_skb_prv *) (skb)->cb)->pos)\n-#define ENI_PRV_PADDR(skb) (((struct eni_skb_prv *) (skb)->cb)->paddr)\n-\n-#endif\ndiff --git a/drivers/atm/fore200e.h b/drivers/atm/fore200e.h\ndeleted file mode 100644\nindex 5d95fe9fd836..000000000000\n--- a/drivers/atm/fore200e.h\n+++ /dev/null\n@@ -1,973 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-#ifndef _FORE200E_H\n-#define _FORE200E_H\n-\n-#ifdef __KERNEL__\n-\n-/* rx buffer sizes */\n-\n-#define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */\n-#define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */\n-\n-\n-#define RBD_BLK_SIZE\t 32 /* nbr of supplied rx buffers per rbd */\n-\n-\n-#define MAX_PDU_SIZE\t 65535 /* maximum PDU size supported by AALs */\n-\n-\n-#define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */\n-#define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */\n-\n-#define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */\n-#define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */\n-\n-#define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)\n-#define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)\n-\n-#define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)\n-#define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)\n-\n-\n-#define QUEUE_SIZE_CMD 16\t /* command queue capacity */\n-#define QUEUE_SIZE_RX\t 64\t /* receive queue capacity */\n-#define QUEUE_SIZE_TX\t 256 /* transmit queue capacity */\n-#define QUEUE_SIZE_BS 32\t /* buffer supply queue capacity */\n-\n-#define FORE200E_VPI_BITS 0\n-#define FORE200E_VCI_BITS 10\n-#define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */\n-\n-\n-#define TSD_FIXED 2\n-#define TSD_EXTENSION 0\n-#define TSD_NBR (TSD_FIXED + TSD_EXTENSION)\n-\n-\n-/* the cp starts putting a received PDU into one *small* buffer,\n- then it uses a number of *large* buffers for the trailing data. \n- we compute here the total number of receive segment descriptors \n- required to hold the largest possible PDU */\n-\n-#define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)\n-\n-#define RSD_FIXED 3\n-\n-/* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,\n- but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,\n- so we add one extra RSD to RSD_EXTENSION \n- (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */\n-\n-#define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)\n-#define RSD_NBR (RSD_FIXED + RSD_EXTENSION)\n-\n-\n-#define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))\n-#define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))\n-\n-/* bitfields endian games */\n-\n-#if defined(__LITTLE_ENDIAN_BITFIELD)\n-#define BITFIELD2(b1, b2) b1; b2;\n-#define BITFIELD3(b1, b2, b3) b1; b2; b3;\n-#define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;\n-#define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;\n-#define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;\n-#elif defined(__BIG_ENDIAN_BITFIELD)\n-#define BITFIELD2(b1, b2) b2; b1;\n-#define BITFIELD3(b1, b2, b3) b3; b2; b1;\n-#define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;\n-#define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;\n-#define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;\n-#else\n-#error unknown bitfield endianess\n-#endif\n-\n- \n-/* ATM cell header (minus HEC byte) */\n-\n-typedef struct atm_header {\n- BITFIELD5( \n- u32 clp : 1, /* cell loss priority */\n- u32 plt : 3, /* payload type */\n- u32 vci : 16, /* virtual channel identifier */\n- u32 vpi : 8, /* virtual path identifier */\n- u32 gfc : 4 /* generic flow control */\n- )\n-} atm_header_t;\n-\n-\n-/* ATM adaptation layer id */\n-\n-typedef enum fore200e_aal {\n- FORE200E_AAL0 = 0,\n- FORE200E_AAL34 = 4,\n- FORE200E_AAL5 = 5,\n-} fore200e_aal_t;\n-\n-\n-/* transmit PDU descriptor specification */\n-\n-typedef struct tpd_spec {\n- BITFIELD4(\n- u32 length : 16, /* total PDU length */\n- u32 nseg : 8, /* number of transmit segments */\n- enum fore200e_aal aal : 4, /* adaptation layer */\n- u32 intr : 4 /* interrupt requested */\n- )\n-} tpd_spec_t;\n-\n-\n-/* transmit PDU rate control */\n-\n-typedef struct tpd_rate\n-{\n- BITFIELD2( \n- u32 idle_cells : 16, /* number of idle cells to insert */\n- u32 data_cells : 16 /* number of data cells to transmit */\n- )\n-} tpd_rate_t;\n-\n-\n-/* transmit segment descriptor */\n-\n-typedef struct tsd {\n- u32 buffer; /* transmit buffer DMA address */\n- u32 length; /* number of bytes in buffer */\n-} tsd_t;\n-\n-\n-/* transmit PDU descriptor */\n-\n-typedef struct tpd {\n- struct atm_header atm_header; /* ATM header minus HEC byte */\n- struct tpd_spec spec; /* tpd specification */\n- struct tpd_rate rate; /* tpd rate control */\n- u32 pad; /* reserved */\n- struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */\n-} tpd_t;\n-\n-\n-/* receive segment descriptor */\n-\n-typedef struct rsd {\n- u32 handle; /* host supplied receive buffer handle */\n- u32 length; /* number of bytes in buffer */\n-} rsd_t;\n-\n-\n-/* receive PDU descriptor */\n-\n-typedef struct rpd {\n- struct atm_header atm_header; /* ATM header minus HEC byte */\n- u32 nseg; /* number of receive segments */\n- struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */\n-} rpd_t;\n-\n-\n-/* buffer scheme */\n-\n-typedef enum buffer_scheme {\n- BUFFER_SCHEME_ONE,\n- BUFFER_SCHEME_TWO,\n- BUFFER_SCHEME_NBR /* always last */\n-} buffer_scheme_t;\n-\n-\n-/* buffer magnitude */\n-\n-typedef enum buffer_magn {\n- BUFFER_MAGN_SMALL,\n- BUFFER_MAGN_LARGE,\n- BUFFER_MAGN_NBR /* always last */\n-} buffer_magn_t;\n-\n-\n-/* receive buffer descriptor */\n-\n-typedef struct rbd {\n- u32 handle; /* host supplied handle */\n- u32 buffer_haddr; /* host DMA address of host buffer */\n-} rbd_t;\n-\n-\n-/* receive buffer descriptor block */\n-\n-typedef struct rbd_block {\n- struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */\n-} rbd_block_t;\n-\n-\n-/* tpd DMA address */\n-\n-typedef struct tpd_haddr {\n- BITFIELD3( \n- u32 size : 4, /* tpd size expressed in 32 byte blocks */\n- u32 pad : 1, /* reserved */\n- u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */\n- )\n-} tpd_haddr_t;\n-\n-#define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */\n-\n-/* cp resident transmit queue entry */\n-\n-typedef struct cp_txq_entry {\n- struct tpd_haddr tpd_haddr; /* host DMA address of tpd */\n- u32 status_haddr; /* host DMA address of completion status */\n-} cp_txq_entry_t;\n-\n-\n-/* cp resident receive queue entry */\n-\n-typedef struct cp_rxq_entry {\n- u32 rpd_haddr; /* host DMA address of rpd */\n- u32 status_haddr; /* host DMA address of completion status */\n-} cp_rxq_entry_t;\n-\n-\n-/* cp resident buffer supply queue entry */\n-\n-typedef struct cp_bsq_entry {\n- u32 rbd_block_haddr; /* host DMA address of rbd block */\n- u32 status_haddr; /* host DMA address of completion status */\n-} cp_bsq_entry_t;\n-\n-\n-/* completion status */\n-\n-typedef volatile enum status {\n- STATUS_PENDING = (1<<0), /* initial status (written by host) */\n- STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */\n- STATUS_FREE = (1<<2), /* initial status (written by host) */\n- STATUS_ERROR = (1<<3) /* completion status (written by cp) */\n-} status_t;\n-\n-\n-/* cp operation code */\n-\n-typedef enum opcode {\n- OPCODE_INITIALIZE = 1, /* initialize board */\n- OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */\n- OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */\n- OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */\n- OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */\n- OPCODE_GET_STATS, /* get board statistics */\n- OPCODE_SET_OC3, /* set OC-3 registers */\n- OPCODE_GET_OC3, /* get OC-3 registers */\n- OPCODE_RESET_STATS, /* reset board statistics */\n- OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */\n- OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the\n-\t\t\t\t firmware to be low order bits from\n-\t\t\t\t the VPI field of the ATM cell header */\n- OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */\n-} opcode_t;\n-\n-\n-/* virtual path / virtual channel identifiers */\n-\n-typedef struct vpvc {\n- BITFIELD3(\n- u32 vci : 16, /* virtual channel identifier */\n- u32 vpi : 8, /* virtual path identifier */\n- u32 pad : 8 /* reserved */\n- )\n-} vpvc_t;\n-\n-\n-/* activate VC command opcode */\n-\n-typedef struct activate_opcode {\n- BITFIELD4( \n- enum opcode opcode : 8, /* cp opcode */\n- enum fore200e_aal aal : 8, /* adaptation layer */\n- enum buffer_scheme scheme : 8, /* buffer scheme */\n- u32 pad : 8 /* reserved */\n- )\n-} activate_opcode_t;\n-\n-\n-/* activate VC command block */\n-\n-typedef struct activate_block {\n- struct activate_opcode opcode; /* activate VC command opcode */\n- struct vpvc vpvc; /* VPI/VCI */\n- u32 mtu; /* for AAL0 only */\n-\n-} activate_block_t;\n-\n-\n-/* deactivate VC command opcode */\n-\n-typedef struct deactivate_opcode {\n- BITFIELD2(\n- enum opcode opcode : 8, /* cp opcode */\n- u32 pad : 24 /* reserved */\n- )\n-} deactivate_opcode_t;\n-\n-\n-/* deactivate VC command block */\n-\n-typedef struct deactivate_block {\n- struct deactivate_opcode opcode; /* deactivate VC command opcode */\n- struct vpvc vpvc; /* VPI/VCI */\n-} deactivate_block_t;\n-\n-\n-/* OC-3 registers */\n-\n-typedef struct oc3_regs {\n- u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite\n-\t\t\t Saturn User Network Interface documentation\n-\t\t\t for a description of the OC-3 chip registers */\n-} oc3_regs_t;\n-\n-\n-/* set/get OC-3 regs command opcode */\n-\n-typedef struct oc3_opcode {\n- BITFIELD4(\n- enum opcode opcode : 8, /* cp opcode */\n-\tu32 reg : 8, /* register index */\n-\tu32 value : 8, /* register value */\n-\tu32 mask : 8 /* register mask that specifies which\n-\t\t\t\t bits of the register value field\n-\t\t\t\t are significant */\n- )\n-} oc3_opcode_t;\n-\n-\n-/* set/get OC-3 regs command block */\n-\n-typedef struct oc3_block {\n- struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */\n- u32 regs_haddr; /* host DMA address of OC-3 regs buffer */\n-} oc3_block_t;\n-\n-\n-/* physical encoding statistics */\n-\n-typedef struct stats_phy {\n- __be32 crc_header_errors; /* cells received with bad header CRC */\n- __be32 framing_errors; /* cells received with bad framing */\n- __be32 pad[ 2 ]; /* i960 padding */\n-} stats_phy_t;\n-\n-\n-/* OC-3 statistics */\n-\n-typedef struct stats_oc3 {\n- __be32 section_bip8_errors; /* section 8 bit interleaved parity */\n- __be32 path_bip8_errors; /* path 8 bit interleaved parity */\n- __be32 line_bip24_errors; /* line 24 bit interleaved parity */\n- __be32 line_febe_errors; /* line far end block errors */\n- __be32 path_febe_errors; /* path far end block errors */\n- __be32 corr_hcs_errors; /* correctable header check sequence */\n- __be32 ucorr_hcs_errors; /* uncorrectable header check sequence */\n- __be32 pad[ 1 ]; /* i960 padding */\n-} stats_oc3_t;\n-\n-\n-/* ATM statistics */\n-\n-typedef struct stats_atm {\n- __be32\tcells_transmitted; /* cells transmitted */\n- __be32\tcells_received; /* cells received */\n- __be32\tvpi_bad_range; /* cell drops: VPI out of range */\n- __be32\tvpi_no_conn; /* cell drops: no connection for VPI */\n- __be32\tvci_bad_range; /* cell drops: VCI out of range */\n- __be32\tvci_no_conn; /* cell drops: no connection for VCI */\n- __be32\tpad[ 2 ]; /* i960 padding */\n-} stats_atm_t;\n-\n-/* AAL0 statistics */\n-\n-typedef struct stats_aal0 {\n- __be32\tcells_transmitted; /* cells transmitted */\n- __be32\tcells_received; /* cells received */\n- __be32\tcells_dropped; /* cells dropped */\n- __be32\tpad[ 1 ]; /* i960 padding */\n-} stats_aal0_t;\n-\n-\n-/* AAL3/4 statistics */\n-\n-typedef struct stats_aal34 {\n- __be32\tcells_transmitted; /* cells transmitted from segmented PDUs */\n- __be32\tcells_received; /* cells reassembled into PDUs */\n- __be32\tcells_crc_errors; /* payload CRC error count */\n- __be32\tcells_protocol_errors; /* SAR or CS layer protocol errors */\n- __be32\tcells_dropped; /* cells dropped: partial reassembly */\n- __be32\tcspdus_transmitted; /* CS PDUs transmitted */\n- __be32\tcspdus_received; /* CS PDUs received */\n- __be32\tcspdus_protocol_errors; /* CS layer protocol errors */\n- __be32\tcspdus_dropped; /* reassembled PDUs drop'd (in cells) */\n- __be32\tpad[ 3 ]; /* i960 padding */\n-} stats_aal34_t;\n-\n-\n-/* AAL5 statistics */\n-\n-typedef struct stats_aal5 {\n- __be32\tcells_transmitted; /* cells transmitted from segmented SDUs */\n- __be32\tcells_received;\t\t /* cells reassembled into SDUs */\n- __be32\tcells_dropped;\t\t /* reassembled PDUs dropped (in cells) */\n- __be32\tcongestion_experienced; /* CRC error and length wrong */\n- __be32\tcspdus_transmitted; /* CS PDUs transmitted */\n- __be32\tcspdus_received; /* CS PDUs received */\n- __be32\tcspdus_crc_errors; /* CS PDUs CRC errors */\n- __be32\tcspdus_protocol_errors; /* CS layer protocol errors */\n- __be32\tcspdus_dropped; /* reassembled PDUs dropped */\n- __be32\tpad[ 3 ]; /* i960 padding */\n-} stats_aal5_t;\n-\n-\n-/* auxiliary statistics */\n-\n-typedef struct stats_aux {\n- __be32\tsmall_b1_failed; /* receive BD allocation failures */\n- __be32\tlarge_b1_failed; /* receive BD allocation failures */\n- __be32\tsmall_b2_failed; /* receive BD allocation failures */\n- __be32\tlarge_b2_failed; /* receive BD allocation failures */\n- __be32\trpd_alloc_failed; /* receive PDU allocation failures */\n- __be32\treceive_carrier; /* no carrier = 0, carrier = 1 */\n- __be32\tpad[ 2 ]; /* i960 padding */\n-} stats_aux_t;\n-\n-\n-/* whole statistics buffer */\n-\n-typedef struct stats {\n- struct stats_phy phy; /* physical encoding statistics */\n- struct stats_oc3 oc3; /* OC-3 statistics */\n- struct stats_atm atm; /* ATM statistics */\n- struct stats_aal0 aal0; /* AAL0 statistics */\n- struct stats_aal34 aal34; /* AAL3/4 statistics */\n- struct stats_aal5 aal5; /* AAL5 statistics */\n- struct stats_aux aux; /* auxiliary statistics */\n-} stats_t;\n-\n-\n-/* get statistics command opcode */\n-\n-typedef struct stats_opcode {\n- BITFIELD2(\n- enum opcode opcode : 8, /* cp opcode */\n- u32 pad : 24 /* reserved */\n- )\n-} stats_opcode_t;\n-\n-\n-/* get statistics command block */\n-\n-typedef struct stats_block {\n- struct stats_opcode opcode; /* get statistics command opcode */\n- u32 stats_haddr; /* host DMA address of stats buffer */\n-} stats_block_t;\n-\n-\n-/* expansion PROM data (PCI specific) */\n-\n-typedef struct prom_data {\n- u32 hw_revision; /* hardware revision */\n- u32 serial_number; /* board serial number */\n- u8 mac_addr[ 8 ]; /* board MAC address */\n-} prom_data_t;\n-\n-\n-/* get expansion PROM data command opcode */\n-\n-typedef struct prom_opcode {\n- BITFIELD2(\n- enum opcode opcode : 8, /* cp opcode */\n- u32 pad : 24 /* reserved */\n- )\n-} prom_opcode_t;\n-\n-\n-/* get expansion PROM data command block */\n-\n-typedef struct prom_block {\n- struct prom_opcode opcode; /* get PROM data command opcode */\n- u32 prom_haddr; /* host DMA address of PROM buffer */\n-} prom_block_t;\n-\n-\n-/* cp command */\n-\n-typedef union cmd {\n- enum opcode opcode; /* operation code */\n- struct activate_block activate_block; /* activate VC */\n- struct deactivate_block deactivate_block; /* deactivate VC */\n- struct stats_block stats_block; /* get statistics */\n- struct prom_block prom_block; /* get expansion PROM data */\n- struct oc3_block oc3_block; /* get/set OC-3 registers */\n- u32 pad[ 4 ]; /* i960 padding */\n-} cmd_t;\n-\n-\n-/* cp resident command queue */\n-\n-typedef struct cp_cmdq_entry {\n- union cmd cmd; /* command */\n- u32 status_haddr; /* host DMA address of completion status */\n- u32 pad[ 3 ]; /* i960 padding */\n-} cp_cmdq_entry_t;\n-\n-\n-/* host resident transmit queue entry */\n-\n-typedef struct host_txq_entry {\n- struct cp_txq_entry __iomem *cp_entry; /* addr of cp resident tx queue entry */\n- enum status* status; /* addr of host resident status */\n- struct tpd* tpd; /* addr of transmit PDU descriptor */\n- u32 tpd_dma; /* DMA address of tpd */\n- struct sk_buff* skb; /* related skb */\n- void* data; /* copy of misaligned data */\n- unsigned long incarn; /* vc_map incarnation when submitted for tx */\n- struct fore200e_vc_map* vc_map;\n-\n-} host_txq_entry_t;\n-\n-\n-/* host resident receive queue entry */\n-\n-typedef struct host_rxq_entry {\n- struct cp_rxq_entry __iomem *cp_entry; /* addr of cp resident rx queue entry */\n- enum status* status; /* addr of host resident status */\n- struct rpd* rpd; /* addr of receive PDU descriptor */\n- u32 rpd_dma; /* DMA address of rpd */\n-} host_rxq_entry_t;\n-\n-\n-/* host resident buffer supply queue entry */\n-\n-typedef struct host_bsq_entry {\n- struct cp_bsq_entry __iomem *cp_entry; /* addr of cp resident buffer supply queue entry */\n- enum status* status; /* addr of host resident status */\n- struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */\n- u32 rbd_block_dma; /* DMA address od rdb */\n-} host_bsq_entry_t;\n-\n-\n-/* host resident command queue entry */\n-\n-typedef struct host_cmdq_entry {\n- struct cp_cmdq_entry __iomem *cp_entry; /* addr of cp resident cmd queue entry */\n- enum status *status;\t /* addr of host resident status */\n-} host_cmdq_entry_t;\n-\n-\n-/* chunk of memory */\n-\n-typedef struct chunk {\n- void* alloc_addr; /* base address of allocated chunk */\n- void* align_addr; /* base address of aligned chunk */\n- dma_addr_t dma_addr; /* DMA address of aligned chunk */\n- int direction; /* direction of DMA mapping */\n- u32 alloc_size; /* length of allocated chunk */\n- u32 align_size; /* length of aligned chunk */\n-} chunk_t;\n-\n-#define dma_size align_size /* DMA useable size */\n-\n-\n-/* host resident receive buffer */\n-\n-typedef struct buffer {\n- struct buffer* next; /* next receive buffer */\n- enum buffer_scheme scheme; /* buffer scheme */\n- enum buffer_magn magn; /* buffer magnitude */\n- struct chunk data; /* data buffer */\n-#ifdef FORE200E_BSQ_DEBUG\n- unsigned long index; /* buffer # in queue */\n- int supplied; /* 'buffer supplied' flag */\n-#endif\n-} buffer_t;\n-\n-\n-#if (BITS_PER_LONG == 32)\n-#define FORE200E_BUF2HDL(buffer) ((u32)(buffer))\n-#define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))\n-#else /* deal with 64 bit pointers */\n-#define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))\n-#define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))\n-#endif\n-\n-\n-/* host resident command queue */\n-\n-typedef struct host_cmdq {\n- struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */\n- int head; /* head of cmd queue */\n- struct chunk status; /* array of completion status */\n-} host_cmdq_t;\n-\n-\n-/* host resident transmit queue */\n-\n-typedef struct host_txq {\n- struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */\n- int head; /* head of tx queue */\n- int tail; /* tail of tx queue */\n- struct chunk tpd; /* array of tpds */\n- struct chunk status; /* arry of completion status */\n- int txing; /* number of pending PDUs in tx queue */\n-} host_txq_t;\n-\n-\n-/* host resident receive queue */\n-\n-typedef struct host_rxq {\n- struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */\n- int head; /* head of rx queue */\n- struct chunk rpd; /* array of rpds */\n- struct chunk status; /* array of completion status */\n-} host_rxq_t;\n-\n-\n-/* host resident buffer supply queues */\n-\n-typedef struct host_bsq {\n- struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */\n- int head; /* head of buffer supply queue */\n- struct chunk rbd_block; /* array of rbds */\n- struct chunk status; /* array of completion status */\n- struct buffer* buffer; /* array of rx buffers */\n- struct buffer* freebuf; /* list of free rx buffers */\n- volatile int freebuf_count; /* count of free rx buffers */\n-} host_bsq_t;\n-\n-\n-/* header of the firmware image */\n-\n-typedef struct fw_header {\n- __le32 magic; /* magic number */\n- __le32 version; /* firmware version id */\n- __le32 load_offset; /* fw load offset in board memory */\n- __le32 start_offset; /* fw execution start address in board memory */\n-} fw_header_t;\n-\n-#define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */\n-\n-\n-/* receive buffer supply queues scheme specification */\n-\n-typedef struct bs_spec {\n- u32\tqueue_length; /* queue capacity */\n- u32\tbuffer_size;\t /* host buffer size\t\t\t */\n- u32\tpool_size;\t /* number of rbds\t\t\t */\n- u32\tsupply_blksize; /* num of rbds in I/O block (multiple\n-\t\t\t of 4 between 4 and 124 inclusive)\t */\n-} bs_spec_t;\n-\n-\n-/* initialization command block (one-time command, not in cmd queue) */\n-\n-typedef struct init_block {\n- enum opcode opcode; /* initialize command */\n- enum status\t status;\t /* related status word */\n- u32 receive_threshold; /* not used */\n- u32 num_connect; /* ATM connections */\n- u32 cmd_queue_len; /* length of command queue */\n- u32 tx_queue_len; /* length of transmit queue */\n- u32 rx_queue_len; /* length of receive queue */\n- u32 rsd_extension; /* number of extra 32 byte blocks */\n- u32 tsd_extension; /* number of extra 32 byte blocks */\n- u32 conless_vpvc; /* not used */\n- u32 pad[ 2 ]; /* force quad alignment */\n- struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */\n-} init_block_t;\n-\n-\n-typedef enum media_type {\n- MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */\n- MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */\n- MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */\n- MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */\n- MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */\n-} media_type_t;\n-\n-#define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)\n-\n-\n-/* cp resident queues */\n-\n-typedef struct cp_queues {\n- u32\t cp_cmdq; /* command queue */\n- u32\t cp_txq; /* transmit queue */\n- u32\t cp_rxq; /* receive queue */\n- u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */\n- u32\t imask; /* 1 enables cp to host interrupts */\n- u32\t istat; /* 1 for interrupt posted */\n- u32\t heap_base; /* offset form beginning of ram */\n- u32\t heap_size; /* space available for queues */\n- u32\t hlogger; /* non zero for host logging */\n- u32 heartbeat; /* cp heartbeat */\n- u32\t fw_release; /* firmware version */\n- u32\t mon960_release; /* i960 monitor version */\n- u32\t tq_plen; /* transmit throughput measurements */\n- /* make sure the init block remains on a quad word boundary */\n- struct init_block init; /* one time cmd, not in cmd queue */\n- enum media_type media_type; /* media type id */\n- u32 oc3_revision; /* OC-3 revision number */\n-} cp_queues_t;\n-\n-\n-/* boot status */\n-\n-typedef enum boot_status {\n- BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */\n- BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */\n- BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */\n- BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */\n- BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */\n-} boot_status_t;\n-\n-\n-/* software UART */\n-\n-typedef struct soft_uart {\n- u32 send; /* write register */\n- u32 recv; /* read register */\n-} soft_uart_t;\n-\n-#define FORE200E_CP_MONITOR_UART_FREE 0x00000000\n-#define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000\n-\n-\n-/* i960 monitor */\n-\n-typedef struct cp_monitor {\n- struct soft_uart soft_uart; /* software UART */\n- enum boot_status\tbstat; /* boot status */\n- u32\t\t\tapp_base; /* application base offset */\n- u32\t\t\tmon_version; /* i960 monitor version */\n-} cp_monitor_t;\n-\n-\n-/* device state */\n-\n-typedef enum fore200e_state {\n- FORE200E_STATE_BLANK, /* initial state */\n- FORE200E_STATE_REGISTER, /* device registered */\n- FORE200E_STATE_CONFIGURE, /* bus interface configured */\n- FORE200E_STATE_MAP, /* board space mapped in host memory */\n- FORE200E_STATE_RESET, /* board resetted */\n- FORE200E_STATE_START_FW, /* firmware started */\n- FORE200E_STATE_INITIALIZE, /* initialize command successful */\n- FORE200E_STATE_INIT_CMDQ, /* command queue initialized */\n- FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */\n- FORE200E_STATE_INIT_RXQ, /* receive queue initialized */\n- FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */\n- FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */\n- FORE200E_STATE_IRQ, /* host interrupt requested */\n- FORE200E_STATE_COMPLETE /* initialization completed */\n-} fore200e_state;\n-\n-\n-/* PCA-200E registers */\n-\n-typedef struct fore200e_pca_regs {\n- volatile u32 __iomem * hcr; /* address of host control register */\n- volatile u32 __iomem * imr; /* address of host interrupt mask register */\n- volatile u32 __iomem * psr; /* address of PCI specific register */\n-} fore200e_pca_regs_t;\n-\n-\n-/* SBA-200E registers */\n-\n-typedef struct fore200e_sba_regs {\n- u32 __iomem *hcr; /* address of host control register */\n- u32 __iomem *bsr; /* address of burst transfer size register */\n- u32 __iomem *isr; /* address of interrupt level selection register */\n-} fore200e_sba_regs_t;\n-\n-\n-/* model-specific registers */\n-\n-typedef union fore200e_regs {\n- struct fore200e_pca_regs pca; /* PCA-200E registers */\n- struct fore200e_sba_regs sba; /* SBA-200E registers */\n-} fore200e_regs;\n-\n-\n-struct fore200e;\n-\n-/* bus-dependent data */\n-\n-typedef struct fore200e_bus {\n- char* model_name; /* board model name */\n- char* proc_name; /* board name under /proc/atm */\n- int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */\n- int buffer_alignment; /* rx buffers DMA alignment requirement */\n- int status_alignment; /* status words DMA alignment requirement */\n- u32 (*read)(volatile u32 __iomem *);\n- void (*write)(u32, volatile u32 __iomem *);\n- int (*configure)(struct fore200e*); \n- int (*map)(struct fore200e*); \n- void (*reset)(struct fore200e*);\n- int (*prom_read)(struct fore200e*, struct prom_data*);\n- void (*unmap)(struct fore200e*);\n- void (*irq_enable)(struct fore200e*);\n- int (*irq_check)(struct fore200e*);\n- void (*irq_ack)(struct fore200e*);\n- int (*proc_read)(struct fore200e*, char*);\n-} fore200e_bus_t;\n-\n-/* vc mapping */\n-\n-typedef struct fore200e_vc_map {\n- struct atm_vcc* vcc; /* vcc entry */\n- unsigned long incarn; /* vcc incarnation number */\n-} fore200e_vc_map_t;\n-\n-#define FORE200E_VC_MAP(fore200e, vpi, vci) \\\n- (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])\n-\n-\n-/* per-device data */\n-\n-typedef struct fore200e {\n- const struct fore200e_bus* bus; /* bus-dependent code and data */\n- union fore200e_regs regs; /* bus-dependent registers */\n- struct atm_dev* atm_dev; /* ATM device */\n-\n- enum fore200e_state state; /* device state */\n-\n- char name[16]; /* device name */\n- struct device\t *dev;\n- int irq; /* irq number */\n- unsigned long phys_base; /* physical base address */\n- void __iomem * virt_base; /* virtual base address */\n- \n- unsigned char esi[ ESI_LEN ]; /* end system identifier */\n-\n- struct cp_monitor __iomem * cp_monitor; /* i960 monitor address */\n- struct cp_queues __iomem * cp_queues; /* cp resident queues */\n- struct host_cmdq host_cmdq; /* host resident cmd queue */\n- struct host_txq host_txq; /* host resident tx queue */\n- struct host_rxq host_rxq; /* host resident rx queue */\n- /* host resident buffer supply queues */\n- struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; \n-\n- u32 available_cell_rate; /* remaining pseudo-CBR bw on link */\n-\n- int loop_mode; /* S/UNI loopback mode */\n-\n- struct stats* stats; /* last snapshot of the stats */\n- \n- struct mutex rate_mtx; /* protects rate reservation ops */\n- spinlock_t q_lock; /* protects queue ops */\n-#ifdef FORE200E_USE_TASKLET\n- struct tasklet_struct tx_tasklet; /* performs tx interrupt work */\n- struct tasklet_struct rx_tasklet; /* performs rx interrupt work */\n-#endif\n- unsigned long tx_sat; /* tx queue saturation count */\n-\n- unsigned long incarn_count;\n- struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */\n-} fore200e_t;\n-\n-\n-/* per-vcc data */\n-\n-typedef struct fore200e_vcc {\n- enum buffer_scheme scheme; /* rx buffer scheme */\n- struct tpd_rate rate; /* tx rate control data */\n- int rx_min_pdu; /* size of smallest PDU received */\n- int rx_max_pdu; /* size of largest PDU received */\n- int tx_min_pdu; /* size of smallest PDU transmitted */\n- int tx_max_pdu; /* size of largest PDU transmitted */\n- unsigned long tx_pdu; /* nbr of tx pdus */\n- unsigned long rx_pdu; /* nbr of rx pdus */\n-} fore200e_vcc_t;\n-\n-\n-\n-/* 200E-series common memory layout */\n-\n-#define FORE200E_CP_MONITOR_OFFSET\t0x00000400 /* i960 monitor interface */\n-#define FORE200E_CP_QUEUES_OFFSET\t0x00004d40 /* cp resident queues */\n-\n-\n-/* PCA-200E memory layout */\n-\n-#define PCA200E_IOSPACE_LENGTH\t 0x00200000\n-\n-#define PCA200E_HCR_OFFSET\t\t0x00100000 /* board control register */\n-#define PCA200E_IMR_OFFSET\t\t0x00100004 /* host IRQ mask register */\n-#define PCA200E_PSR_OFFSET\t\t0x00100008 /* PCI specific register */\n-\n-\n-/* PCA-200E host control register */\n-\n-#define PCA200E_HCR_RESET (1<<0) /* read / write */\n-#define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */\n-#define PCA200E_HCR_I960FAIL (1<<2) /* read */\n-#define PCA200E_HCR_INTRB (1<<2) /* write */\n-#define PCA200E_HCR_HOLD_ACK (1<<3) /* read */\n-#define PCA200E_HCR_INTRA (1<<3) /* write */\n-#define PCA200E_HCR_OUTFULL (1<<4) /* read */\n-#define PCA200E_HCR_CLRINTR (1<<4) /* write */\n-#define PCA200E_HCR_ESPHOLD (1<<5) /* read */\n-#define PCA200E_HCR_INFULL (1<<6) /* read */\n-#define PCA200E_HCR_TESTMODE (1<<7) /* read */\n-\n-\n-/* PCA-200E PCI bus interface regs (offsets in PCI config space) */\n-\n-#define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */\n-#define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */\n-#define PCA200E_PCI_THRESHOLD 0x42 /* burst / continuous req threshold */\n-\n-/* PBI master control register */\n-\n-#define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */\n-#define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */\n-#define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */\n-#define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */\n-#define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */\n-#define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */\n-#define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */\n-\n-\n-\n-#define SBA200E_PROM_NAME \"FORE,sba-200e\" /* device name in openprom tree */\n-\n-\n-/* size of SBA-200E registers */\n-\n-#define SBA200E_HCR_LENGTH 4\n-#define SBA200E_BSR_LENGTH 4\n-#define SBA200E_ISR_LENGTH 4\n-#define SBA200E_RAM_LENGTH 0x40000\n-\n-\n-/* SBA-200E SBUS burst transfer size register */\n-\n-#define SBA200E_BSR_BURST4 0x04\n-#define SBA200E_BSR_BURST8 0x08\n-#define SBA200E_BSR_BURST16 0x10\n-\n-\n-/* SBA-200E host control register */\n-\n-#define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */\n-#define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */\n-#define SBA200E_HCR_I960FAIL (1<<2) /* read */\n-#define SBA200E_HCR_I960SETINTR (1<<2) /* write */\n-#define SBA200E_HCR_OUTFULL (1<<3) /* read */\n-#define SBA200E_HCR_INTR_CLR (1<<3) /* write */\n-#define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */\n-#define SBA200E_HCR_ESPHOLD (1<<5) /* read */\n-#define SBA200E_HCR_INFULL (1<<6) /* read */\n-#define SBA200E_HCR_TESTMODE (1<<7) /* read */\n-#define SBA200E_HCR_INTR_REQ (1<<8) /* read */\n-\n-#define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)\n-\n-\n-#endif /* __KERNEL__ */\n-#endif /* _FORE200E_H */\ndiff --git a/drivers/atm/he.h b/drivers/atm/he.h\ndeleted file mode 100644\nindex f3f53674ef3f..000000000000\n--- a/drivers/atm/he.h\n+++ /dev/null\n@@ -1,845 +0,0 @@\n-/*\n-\n- he.h\n-\n- ForeRunnerHE ATM Adapter driver for ATM on Linux\n- Copyright (C) 1999-2001 Naval Research Laboratory\n-\n- This library is free software; you can redistribute it and/or\n- modify it under the terms of the GNU Lesser General Public\n- License as published by the Free Software Foundation; either\n- version 2.1 of the License, or (at your option) any later version.\n-\n- This library is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n- Lesser General Public License for more details.\n-\n- You should have received a copy of the GNU Lesser General Public\n- License along with this library; if not, write to the Free Software\n- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n-\n-*/\n-\n-/*\n-\n- he.h\n-\n- ForeRunnerHE ATM Adapter driver for ATM on Linux\n- Copyright (C) 1999-2000 Naval Research Laboratory\n-\n- Permission to use, copy, modify and distribute this software and its\n- documentation is hereby granted, provided that both the copyright\n- notice and this permission notice appear in all copies of the software,\n- derivative works or modified versions, and any portions thereof, and\n- that both notices appear in supporting documentation.\n-\n- NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS \"AS IS\" CONDITION AND\n- DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER\n- RESULTING FROM THE USE OF THIS SOFTWARE.\n-\n- */\n-\n-#ifndef _HE_H_\n-#define _HE_H_\n-\n-#define DEV_LABEL \"he\"\n-\n-#define CONFIG_DEFAULT_VCIBITS\t12\n-#define CONFIG_DEFAULT_VPIBITS\t0\n-\n-#define CONFIG_IRQ_SIZE\t\t128\n-#define CONFIG_IRQ_THRESH\t(CONFIG_IRQ_SIZE/2)\n-\n-#define CONFIG_TPDRQ_SIZE\t512\n-#define TPDRQ_MASK(x)\t\t(((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1))\n-\n-#define CONFIG_RBRQ_SIZE\t512\n-#define CONFIG_RBRQ_THRESH\t400\n-#define RBRQ_MASK(x)\t\t(((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1))\n-\n-#define CONFIG_TBRQ_SIZE\t512\n-#define CONFIG_TBRQ_THRESH\t400\n-#define TBRQ_MASK(x)\t\t(((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1))\n-\n-#define CONFIG_RBPL_SIZE\t512\n-#define CONFIG_RBPL_THRESH\t64\n-#define CONFIG_RBPL_BUFSIZE\t4096\n-#define RBPL_MASK(x)\t\t(((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1))\n-\n-/* 5.1.3 initialize connection memory */\n-\n-#define CONFIG_RSRA\t\t0x00000\n-#define CONFIG_RCMLBM\t\t0x08000\n-#define CONFIG_RCMABR\t\t0x0d800\n-#define CONFIG_RSRB\t\t0x0e000\n-\n-#define CONFIG_TSRA\t\t0x00000\n-#define CONFIG_TSRB\t\t0x08000\n-#define CONFIG_TSRC\t\t0x0c000\n-#define CONFIG_TSRD\t\t0x0e000\n-#define CONFIG_TMABR\t\t0x0f000\n-#define CONFIG_TPDBA\t\t0x10000\n-\n-#define HE_MAXCIDBITS\t\t12\n-\n-/* 2.9.3.3 interrupt encodings */\n-\n-struct he_irq {\n-\tvolatile u32 isw;\n-};\n-\n-#define IRQ_ALIGNMENT\t\t0x1000\n-\n-#define NEXT_ENTRY(base, tail, mask) \\\n-\t\t\t\t(((unsigned long)base)|(((unsigned long)(tail+1))&mask))\n-\n-#define ITYPE_INVALID\t\t0xffffffff\n-#define ITYPE_TBRQ_THRESH\t(0<<3)\n-#define ITYPE_TPD_COMPLETE\t(1<<3)\n-#define ITYPE_RBPS_THRESH\t(2<<3)\n-#define ITYPE_RBPL_THRESH\t(3<<3)\n-#define ITYPE_RBRQ_THRESH\t(4<<3)\n-#define ITYPE_RBRQ_TIMER\t(5<<3)\n-#define ITYPE_PHY\t\t(6<<3)\n-#define ITYPE_OTHER\t\t0x80\n-#define ITYPE_PARITY\t\t0x81\n-#define ITYPE_ABORT\t\t0x82\n-\n-#define ITYPE_GROUP(x)\t\t(x & 0x7)\n-#define ITYPE_TYPE(x)\t\t(x & 0xf8)\n-\n-#define HE_NUM_GROUPS 8\n-\n-/* 2.1.4 transmit packet descriptor */\n-\n-struct he_tpd {\n-\n-\t/* read by the adapter */\n-\n-\tvolatile u32 status;\n-\tvolatile u32 reserved;\n-\n-#define TPD_MAXIOV\t3\n-\tstruct {\n-\t\tu32 addr, len;\n-\t} iovec[TPD_MAXIOV];\n-\n-#define address0 iovec[0].addr\n-#define length0 iovec[0].len\n-\n-\t/* linux-atm extensions */\n-\n-\tstruct sk_buff *skb;\n-\tstruct atm_vcc *vcc;\n-\n-\tstruct list_head entry;\n-};\n-\n-#define TPD_ALIGNMENT\t64\n-#define TPD_LEN_MASK\t0xffff\n-\n-#define TPD_ADDR_SHIFT 6\n-#define TPD_MASK\t0xffffffc0\n-#define TPD_ADDR(x)\t((x) & TPD_MASK)\n-#define TPD_INDEX(x)\t(TPD_ADDR(x) >> TPD_ADDR_SHIFT)\n-\n-\n-/* table 2.3 transmit buffer return elements */\n-\n-struct he_tbrq {\n-\tvolatile u32 tbre;\n-};\n-\n-#define TBRQ_ALIGNMENT\tCONFIG_TBRQ_SIZE\n-\n-#define TBRQ_TPD(tbrq)\t\t((tbrq)->tbre & 0xffffffc0)\n-#define TBRQ_EOS(tbrq)\t\t((tbrq)->tbre & (1<<3))\n-#define TBRQ_MULTIPLE(tbrq)\t((tbrq)->tbre & (1))\n-\n-/* table 2.21 receive buffer return queue element field organization */\n-\n-struct he_rbrq {\n-\tvolatile u32 addr;\n-\tvolatile u32 cidlen;\n-};\n-\n-#define RBRQ_ALIGNMENT\tCONFIG_RBRQ_SIZE\n-\n-#define RBRQ_ADDR(rbrq)\t\t((rbrq)->addr & 0xffffffc0)\n-#define RBRQ_CRC_ERR(rbrq)\t((rbrq)->addr & (1<<5))\n-#define RBRQ_LEN_ERR(rbrq)\t((rbrq)->addr & (1<<4))\n-#define RBRQ_END_PDU(rbrq)\t((rbrq)->addr & (1<<3))\n-#define RBRQ_AAL5_PROT(rbrq)\t((rbrq)->addr & (1<<2))\n-#define RBRQ_CON_CLOSED(rbrq)\t((rbrq)->addr & (1<<1))\n-#define RBRQ_HBUF_ERR(rbrq)\t((rbrq)->addr & 1)\n-#define RBRQ_CID(rbrq)\t\t(((rbrq)->cidlen >> 16) & 0x1fff)\n-#define RBRQ_BUFLEN(rbrq)\t((rbrq)->cidlen & 0xffff)\n-\n-/* figure 2.3 transmit packet descriptor ready queue */\n-\n-struct he_tpdrq {\n-\tvolatile u32 tpd;\n-\tvolatile u32 cid;\n-};\n-\n-#define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE\n-\n-/* table 2.30 host status page detail */\n-\n-#define HSP_ALIGNMENT\t0x400\t\t/* must align on 1k boundary */\n-\n-struct he_hsp {\n-\tstruct he_hsp_entry {\n-\t\tvolatile u32 tbrq_tail; \n-\t\tvolatile u32 reserved1[15];\n-\t\tvolatile u32 rbrq_tail; \n-\t\tvolatile u32 reserved2[15];\n-\t} group[HE_NUM_GROUPS];\n-};\n-\n-/*\n- * figure 2.9 receive buffer pools\n- *\n- * since a virtual address might be more than 32 bits, we store an index\n- * in the virt member of he_rbp. NOTE: the lower six bits in the rbrq\n- * addr member are used for buffer status further limiting us to 26 bits.\n- */\n-\n-struct he_rbp {\n-\tvolatile u32 phys;\n-\tvolatile u32 idx;\t/* virt */\n-};\n-\n-#define RBP_IDX_OFFSET 6\n-\n-/*\n- * the he dma engine will try to hold an extra 16 buffers in its local\n- * caches. and add a couple buffers for safety.\n- */\n-\n-#define RBPL_TABLE_SIZE (CONFIG_RBPL_SIZE + 16 + 2)\n-\n-struct he_buff {\n-\tstruct list_head entry;\n-\tdma_addr_t mapping;\n-\tunsigned long len;\n-\tu8 data[];\n-};\n-\n-#ifdef notyet\n-struct he_group {\n-\tu32 rpbl_size, rpbl_qsize;\n-\tstruct he_rpb_entry *rbpl_ba;\n-};\n-#endif\n-\n-#define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc)\n-\n-struct he_vcc_table \n-{\n-\tstruct atm_vcc *vcc;\n-};\n-\n-struct he_cs_stper\n-{\n-\tlong pcr;\n-\tint inuse;\n-};\n-\n-#define HE_NUM_CS_STPER\t\t16\n-\n-struct he_dev {\n-\tunsigned int number;\n-\tunsigned int irq;\n-\tvoid __iomem *membase;\n-\n-\tchar prod_id[30];\n-\tchar mac_addr[6];\n-\tint media;\n-\n-\tunsigned int vcibits, vpibits;\n-\tunsigned int cells_per_row;\n-\tunsigned int bytes_per_row;\n-\tunsigned int cells_per_lbuf;\n-\tunsigned int r0_numrows, r0_startrow, r0_numbuffs;\n-\tunsigned int r1_numrows, r1_startrow, r1_numbuffs;\n-\tunsigned int tx_numrows, tx_startrow, tx_numbuffs;\n-\tunsigned int buffer_limit;\n-\n-\tstruct he_vcc_table *he_vcc_table;\n-\n-#ifdef notyet\n-\tstruct he_group group[HE_NUM_GROUPS];\n-#endif\n-\tstruct he_cs_stper cs_stper[HE_NUM_CS_STPER];\n-\tunsigned total_bw;\n-\n-\tdma_addr_t irq_phys;\n-\tstruct he_irq *irq_base, *irq_head, *irq_tail;\n-\tvolatile unsigned *irq_tailoffset;\n-\tint irq_peak;\n-\n-\tstruct tasklet_struct tasklet;\n-\tstruct dma_pool *tpd_pool;\n-\tstruct list_head outstanding_tpds;\n-\n-\tdma_addr_t tpdrq_phys;\n-\tstruct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head;\n-\n-\tspinlock_t global_lock;\t\t/* 8.1.5 pci transaction ordering\n-\t\t\t\t\t error problem */\n-\tdma_addr_t rbrq_phys;\n-\tstruct he_rbrq *rbrq_base, *rbrq_head;\n-\tint rbrq_peak;\n-\n-\tstruct he_buff **rbpl_virt;\n-\tunsigned long *rbpl_table;\n-\tunsigned long rbpl_hint;\n-\tstruct dma_pool *rbpl_pool;\n-\tdma_addr_t rbpl_phys;\n-\tstruct he_rbp *rbpl_base, *rbpl_tail;\n-\tstruct list_head rbpl_outstanding;\n-\tint rbpl_peak;\n-\n-\tdma_addr_t tbrq_phys;\n-\tstruct he_tbrq *tbrq_base, *tbrq_head;\n-\tint tbrq_peak;\n-\n-\tdma_addr_t hsp_phys;\n-\tstruct he_hsp *hsp;\n-\n-\tstruct pci_dev *pci_dev;\n-\tstruct atm_dev *atm_dev;\n-\tstruct he_dev *next;\n-};\n-\n-#define HE_MAXIOV 20\n-\n-struct he_vcc\n-{\n-\tstruct list_head buffers;\n-\tint pdu_len;\n-\tint rc_index;\n-\n-\twait_queue_head_t rx_waitq;\n-\twait_queue_head_t tx_waitq;\n-};\n-\n-#define HE_VCC(vcc)\t((struct he_vcc *)(vcc->dev_data))\n-\n-#define PCI_VENDOR_ID_FORE\t0x1127\n-#define PCI_DEVICE_ID_FORE_HE\t0x400\n-\n-#define GEN_CNTL_0\t\t\t\t0x40\n-#define INT_PROC_ENBL\t\t(1<<25)\n-#define SLAVE_ENDIAN_MODE\t(1<<16)\n-#define MRL_ENB\t\t(1<<5)\n-#define MRM_ENB\t\t(1<<4)\n-#define INIT_ENB\t\t(1<<2)\n-#define IGNORE_TIMEOUT\t\t(1<<1)\n-#define ENBL_64\t\t(1<<0)\n-\n-#define MIN_PCI_LATENCY\t\t32\t/* errata 8.1.3 */\n-\n-#define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data)\n-\n-#define he_is622(dev)\t((dev)->media & 0x1)\n-#define he_isMM(dev)\t((dev)->media & 0x20)\n-\n-#define HE_REGMAP_SIZE\t0x100000\n-\n-#define RESET_CNTL\t0x80000\n-#define BOARD_RST_STATUS\t(1<<6)\n-\n-#define HOST_CNTL\t0x80004\n-#define PCI_BUS_SIZE64\t\t\t(1<<27)\n-#define DESC_RD_STATIC_64\t\t(1<<26)\n-#define DATA_RD_STATIC_64\t\t(1<<25)\n-#define DATA_WR_STATIC_64\t\t(1<<24)\n-#define ID_CS\t\t\t\t(1<<12)\n-#define ID_WREN\t\t\t(1<<11)\n-#define ID_DOUT\t\t\t(1<<10)\n-#define ID_DOFFSET\t\t\t10\n-#define ID_DIN\t\t\t\t(1<<9)\n-#define ID_CLOCK\t\t\t(1<<8)\n-#define QUICK_RD_RETRY\t\t\t(1<<7)\n-#define QUICK_WR_RETRY\t\t\t(1<<6)\n-#define OUTFF_ENB\t\t\t(1<<5)\n-#define CMDFF_ENB\t\t\t(1<<4)\n-#define PERR_INT_ENB\t\t\t(1<<2)\n-#define IGNORE_INTR\t\t\t(1<<0)\n-\n-#define LB_SWAP\t\t0x80008\n-#define SWAP_RNUM_MAX(x)\t(x<<27)\n-#define DATA_WR_SWAP\t\t(1<<20)\n-#define DESC_RD_SWAP\t\t(1<<19)\n-#define DATA_RD_SWAP\t\t(1<<18)\n-#define INTR_SWAP\t\t(1<<17)\n-#define DESC_WR_SWAP\t\t(1<<16)\n-#define SDRAM_INIT\t\t(1<<15)\n-#define BIG_ENDIAN_HOST\t(1<<14)\n-#define XFER_SIZE\t\t(1<<7)\n-\n-#define LB_MEM_ADDR\t0x8000c\n-#define LB_MEM_DATA\t0x80010\n-\n-#define LB_MEM_ACCESS\t0x80014\n-#define LB_MEM_HNDSHK\t\t(1<<30)\n-#define LM_MEM_WRITE\t\t(0x7)\n-#define LM_MEM_READ\t\t(0x3)\n-\n-#define SDRAM_CTL\t0x80018\n-#define LB_64_ENB\t\t(1<<3)\n-#define LB_TWR\t\t\t(1<<2)\n-#define LB_TRP\t\t\t(1<<1)\n-#define LB_TRAS\t\t(1<<0)\n-\n-#define INT_FIFO\t0x8001c\n-#define INT_MASK_D\t\t(1<<15)\n-#define INT_MASK_C\t\t(1<<14)\n-#define INT_MASK_B\t\t(1<<13)\n-#define INT_MASK_A\t\t(1<<12)\n-#define INT_CLEAR_D\t\t(1<<11)\n-#define INT_CLEAR_C\t\t(1<<10)\n-#define INT_CLEAR_B\t\t(1<<9)\n-#define INT_CLEAR_A\t\t(1<<8)\n-\n-#define ABORT_ADDR\t0x80020\n-\n-#define IRQ0_BASE\t0x80080\n-#define IRQ_BASE(x)\t\t(x<<12)\n-#define IRQ_MASK\t\t((CONFIG_IRQ_SIZE<<2)-1)\t/* was 0x3ff */\n-#define IRQ_TAIL(x)\t\t(((unsigned long)(x)) & IRQ_MASK)\n-#define IRQ0_HEAD\t0x80084\n-#define IRQ_SIZE(x)\t\t(x<<22)\n-#define IRQ_THRESH(x)\t\t(x<<12)\n-#define IRQ_HEAD(x)\t\t(x<<2)\n-/* #define IRQ_PENDING\t\t(1) \t\tconflict with linux/irq.h */\n-#define IRQ0_CNTL\t0x80088\n-#define IRQ_ADDRSEL(x)\t\t(x<<2)\n-#define IRQ_INT_A\t\t(0<<2)\n-#define IRQ_INT_B\t\t(1<<2)\n-#define IRQ_INT_C\t\t(2<<2)\n-#define IRQ_INT_D\t\t(3<<2)\n-#define IRQ_TYPE_ADDR\t\t0x1\n-#define IRQ_TYPE_LINE\t\t0x0\n-#define IRQ0_DATA\t0x8008c\n-\n-#define IRQ1_BASE\t0x80090\n-#define IRQ1_HEAD\t0x80094\n-#define IRQ1_CNTL\t0x80098\n-#define IRQ1_DATA\t0x8009c\n-\n-#define IRQ2_BASE\t0x800a0\n-#define IRQ2_HEAD\t0x800a4\n-#define IRQ2_CNTL\t0x800a8\n-#define IRQ2_DATA\t0x800ac\n-\n-#define IRQ3_BASE\t0x800b0\n-#define IRQ3_HEAD\t0x800b4\n-#define IRQ3_CNTL\t0x800b8\n-#define IRQ3_DATA\t0x800bc\n-\n-#define GRP_10_MAP\t0x800c0\n-#define GRP_32_MAP\t0x800c4\n-#define GRP_54_MAP\t0x800c8\n-#define GRP_76_MAP\t0x800cc\n-\n-#define\tG0_RBPS_S\t0x80400\n-#define G0_RBPS_T\t0x80404\n-#define RBP_TAIL(x)\t\t((x)<<3)\n-#define RBP_MASK(x)\t\t((x)|0x1fff)\n-#define G0_RBPS_QI\t0x80408\n-#define RBP_QSIZE(x)\t\t((x)<<14)\n-#define RBP_INT_ENB\t\t(1<<13)\n-#define RBP_THRESH(x)\t\t(x)\n-#define G0_RBPS_BS\t0x8040c\n-#define G0_RBPL_S\t0x80410\n-#define G0_RBPL_T\t0x80414\n-#define G0_RBPL_QI\t0x80418 \n-#define G0_RBPL_BS\t0x8041c\n-\n-#define\tG1_RBPS_S\t0x80420\n-#define G1_RBPS_T\t0x80424\n-#define G1_RBPS_QI\t0x80428\n-#define G1_RBPS_BS\t0x8042c\n-#define G1_RBPL_S\t0x80430\n-#define G1_RBPL_T\t0x80434\n-#define G1_RBPL_QI\t0x80438\n-#define G1_RBPL_BS\t0x8043c\n-\n-#define\tG2_RBPS_S\t0x80440\n-#define G2_RBPS_T\t0x80444\n-#define G2_RBPS_QI\t0x80448\n-#define G2_RBPS_BS\t0x8044c\n-#define G2_RBPL_S\t0x80450\n-#define G2_RBPL_T\t0x80454\n-#define G2_RBPL_QI\t0x80458\n-#define G2_RBPL_BS\t0x8045c\n-\n-#define\tG3_RBPS_S\t0x80460\n-#define G3_RBPS_T\t0x80464\n-#define G3_RBPS_QI\t0x80468\n-#define G3_RBPS_BS\t0x8046c\n-#define G3_RBPL_S\t0x80470\n-#define G3_RBPL_T\t0x80474\n-#define G3_RBPL_QI\t0x80478\n-#define G3_RBPL_BS\t0x8047c\n-\n-#define\tG4_RBPS_S\t0x80480\n-#define G4_RBPS_T\t0x80484\n-#define G4_RBPS_QI\t0x80488\n-#define G4_RBPS_BS\t0x8048c\n-#define G4_RBPL_S\t0x80490\n-#define G4_RBPL_T\t0x80494\n-#define G4_RBPL_QI\t0x80498\n-#define G4_RBPL_BS\t0x8049c\n-\n-#define\tG5_RBPS_S\t0x804a0\n-#define G5_RBPS_T\t0x804a4\n-#define G5_RBPS_QI\t0x804a8\n-#define G5_RBPS_BS\t0x804ac\n-#define G5_RBPL_S\t0x804b0\n-#define G5_RBPL_T\t0x804b4\n-#define G5_RBPL_QI\t0x804b8\n-#define G5_RBPL_BS\t0x804bc\n-\n-#define\tG6_RBPS_S\t0x804c0\n-#define G6_RBPS_T\t0x804c4\n-#define G6_RBPS_QI\t0x804c8\n-#define G6_RBPS_BS\t0x804cc\n-#define G6_RBPL_S\t0x804d0\n-#define G6_RBPL_T\t0x804d4\n-#define G6_RBPL_QI\t0x804d8\n-#define G6_RBPL_BS\t0x804dc\n-\n-#define\tG7_RBPS_S\t0x804e0\n-#define G7_RBPS_T\t0x804e4\n-#define G7_RBPS_QI\t0x804e8\n-#define G7_RBPS_BS\t0x804ec\n-\n-#define G7_RBPL_S\t0x804f0\n-#define G7_RBPL_T\t0x804f4\n-#define G7_RBPL_QI\t0x804f8\n-#define G7_RBPL_BS\t0x804fc\n-\n-#define G0_RBRQ_ST\t0x80500\n-#define G0_RBRQ_H\t0x80504\n-#define G0_RBRQ_Q\t0x80508\n-#define RBRQ_THRESH(x)\t\t((x)<<13)\n-#define RBRQ_SIZE(x)\t\t(x)\n-#define G0_RBRQ_I\t0x8050c\n-#define RBRQ_TIME(x)\t\t((x)<<8)\n-#define RBRQ_COUNT(x)\t\t(x)\n-\n-/* fill in 1 ... 7 later */\n-\n-#define G0_TBRQ_B_T\t0x80600\n-#define G0_TBRQ_H\t0x80604\n-#define G0_TBRQ_S\t0x80608\n-#define G0_TBRQ_THRESH\t0x8060c\n-#define TBRQ_THRESH(x)\t\t(x)\n-\n-/* fill in 1 ... 7 later */\n-\n-#define RH_CONFIG\t0x805c0\n-#define PHY_INT_ENB\t(1<<10)\n-#define OAM_GID(x)\t(x<<7)\n-#define PTMR_PRE(x)\t(x)\n-\n-#define G0_INMQ_S\t0x80580\n-#define G0_INMQ_L\t0x80584\n-#define G1_INMQ_S\t0x80588\n-#define G1_INMQ_L\t0x8058c\n-#define G2_INMQ_S\t0x80590\n-#define G2_INMQ_L\t0x80594\n-#define G3_INMQ_S\t0x80598\n-#define G3_INMQ_L\t0x8059c\n-#define G4_INMQ_S\t0x805a0\n-#define G4_INMQ_L\t0x805a4\n-#define G5_INMQ_S\t0x805a8\n-#define G5_INMQ_L\t0x805ac\n-#define G6_INMQ_S\t0x805b0\n-#define G6_INMQ_L\t0x805b4\n-#define G7_INMQ_S\t0x805b8\n-#define G7_INMQ_L\t0x805bc\n-\n-#define TPDRQ_B_H\t0x80680\n-#define TPDRQ_T\t\t0x80684\n-#define TPDRQ_S\t\t0x80688\n-\n-#define UBUFF_BA\t0x8068c\n-\n-#define RLBF0_H\t\t0x806c0\n-#define RLBF0_T\t\t0x806c4\n-#define RLBF1_H\t\t0x806c8\n-#define RLBF1_T\t\t0x806cc\n-#define RLBC_H\t\t0x806d0\n-#define RLBC_T\t\t0x806d4\n-#define RLBC_H2\t\t0x806d8\n-#define TLBF_H\t\t0x806e0\n-#define TLBF_T\t\t0x806e4\n-#define RLBF0_C\t\t0x806e8\n-#define RLBF1_C\t\t0x806ec\n-#define RXTHRSH\t\t0x806f0\n-#define LITHRSH\t\t0x806f4\n-\n-#define LBARB\t\t0x80700\n-#define SLICE_X(x)\t\t (x<<28)\n-#define ARB_RNUM_MAX(x)\t (x<<23)\n-#define TH_PRTY(x)\t\t (x<<21)\n-#define RH_PRTY(x)\t\t (x<<19)\n-#define TL_PRTY(x)\t\t (x<<17)\n-#define RL_PRTY(x)\t\t (x<<15)\n-#define BUS_MULTI(x)\t\t (x<<8)\n-#define NET_PREF(x)\t\t (x)\n-\n-#define SDRAMCON\t0x80704\n-#define\t BANK_ON\t\t(1<<14)\n-#define\t WIDE_DATA\t\t(1<<13)\n-#define\t TWR_WAIT\t\t(1<<12)\n-#define\t TRP_WAIT\t\t(1<<11)\n-#define\t TRAS_WAIT\t\t(1<<10)\n-#define\t REF_RATE(x)\t\t(x)\n-\n-#define LBSTAT\t\t0x80708\n-\n-#define RCC_STAT\t0x8070c\n-#define RCC_BUSY\t\t(1)\n-\n-#define TCMCONFIG\t0x80740\n-#define TM_DESL2\t\t(1<<10)\n-#define\t TM_BANK_WAIT(x)\t(x<<6)\n-#define\t TM_ADD_BANK4(x)\t(x<<4)\n-#define TM_PAR_CHECK(x)\t(x<<3)\n-#define TM_RW_WAIT(x)\t\t(x<<2)\n-#define TM_SRAM_TYPE(x)\t(x)\n-\n-#define TSRB_BA\t\t0x80744\t\n-#define TSRC_BA\t\t0x80748\t\n-#define TMABR_BA\t0x8074c\t\n-#define TPD_BA\t\t0x80750\t\n-#define TSRD_BA\t\t0x80758\t\n-\n-#define TX_CONFIG\t0x80760\n-#define DRF_THRESH(x)\t\t(x<<22)\n-#define TX_UT_MODE(x)\t\t(x<<21)\n-#define TX_VCI_MASK(x)\t\t(x<<17)\n-#define LBFREE_CNT(x)\t\t(x)\n-\n-#define TXAAL5_PROTO\t0x80764\n-#define CPCS_UU(x)\t\t(x<<8)\n-#define CPI(x)\t\t\t(x)\n-\n-#define RCMCONFIG\t0x80780\n-#define RM_DESL2(x)\t\t(x<<10)\n-#define RM_BANK_WAIT(x)\t(x<<6)\n-#define RM_ADD_BANK(x)\t\t(x<<4)\n-#define RM_PAR_CHECK(x)\t(x<<3)\n-#define RM_RW_WAIT(x)\t\t(x<<2)\n-#define RM_SRAM_TYPE(x)\t(x)\n-\n-#define RCMRSRB_BA\t0x80784\n-#define RCMLBM_BA\t0x80788\n-#define RCMABR_BA\t0x8078c\n-\n-#define RC_CONFIG\t0x807c0\n-#define UT_RD_DELAY(x)\t\t(x<<11)\n-#define WRAP_MODE(x)\t\t(x<<10)\n-#define RC_UT_MODE(x)\t\t(x<<9)\n-#define RX_ENABLE\t\t(1<<8)\n-#define RX_VALVP(x)\t\t(x<<4)\n-#define RX_VALVC(x)\t\t(x)\n-\n-#define MCC\t\t0x807c4\n-#define OEC\t\t0x807c8\n-#define DCC\t\t0x807cc\n-#define CEC\t\t0x807d0\n-\n-#define HSP_BA\t\t0x807f0\n-\n-#define LB_CONFIG\t0x807f4\n-#define LB_SIZE(x)\t\t(x)\n-\n-#define CON_DAT\t\t0x807f8\n-#define CON_CTL\t\t0x807fc\n-#define CON_CTL_MBOX\t\t(2<<30)\n-#define CON_CTL_TCM\t\t(1<<30)\n-#define CON_CTL_RCM\t\t(0<<30)\n-#define CON_CTL_WRITE\t\t(1<<29)\n-#define CON_CTL_READ\t\t(0<<29)\n-#define CON_CTL_BUSY\t\t(1<<28)\n-#define CON_BYTE_DISABLE_3\t(1<<22)\t\t/* 24..31 */\n-#define CON_BYTE_DISABLE_2\t(1<<21)\t\t/* 16..23 */\n-#define CON_BYTE_DISABLE_1\t(1<<20)\t\t/* 8..15 */\n-#define CON_BYTE_DISABLE_0\t(1<<19)\t\t/* 0..7 */\n-#define CON_CTL_ADDR(x)\t(x)\n-\n-#define FRAMER\t\t0x80800\t\t/* to 0x80bfc */\n-\n-/* 3.3 network controller (internal) mailbox registers */\n-\n-#define CS_STPER0\t0x0\n-\t/* ... */\n-#define CS_STPER31\t0x01f\n-\n-#define CS_STTIM0\t0x020\n-\t/* ... */\n-#define CS_STTIM31\t0x03f\n-\n-#define CS_TGRLD0\t0x040\n-\t/* ... */\n-#define CS_TGRLD15\t0x04f\n-\n-#define CS_ERTHR0\t0x050\n-#define CS_ERTHR1\t0x051\n-#define CS_ERTHR2\t0x052\n-#define CS_ERTHR3\t0x053\n-#define CS_ERTHR4\t0x054\n-#define CS_ERCTL0\t0x055\n-#define TX_ENABLE\t\t(1<<28)\n-#define ER_ENABLE\t\t(1<<27)\n-#define CS_ERCTL1\t0x056\n-#define CS_ERCTL2\t0x057\n-#define CS_ERSTAT0\t0x058\n-#define CS_ERSTAT1\t0x059\n-\n-#define CS_RTCCT\t0x060\n-#define CS_RTFWC\t0x061\n-#define CS_RTFWR\t0x062\n-#define CS_RTFTC\t0x063\n-#define CS_RTATR\t0x064\n-\n-#define CS_TFBSET\t0x070\n-#define CS_TFBADD\t0x071\n-#define CS_TFBSUB\t0x072\n-#define CS_WCRMAX\t0x073\n-#define CS_WCRMIN\t0x074\n-#define CS_WCRINC\t0x075\n-#define CS_WCRDEC\t0x076\n-#define CS_WCRCEIL\t0x077\n-#define CS_BWDCNT\t0x078\n-\n-#define CS_OTPPER\t0x080\n-#define CS_OTWPER\t0x081\n-#define CS_OTTLIM\t0x082\n-#define CS_OTTCNT\t0x083\n-\n-#define CS_HGRRT0\t0x090\n-\t/* ... */\n-#define CS_HGRRT7\t0x097\n-\n-#define CS_ORPTRS\t0x0a0\n-\n-#define RXCON_CLOSE\t0x100\n-\n-\n-#define RCM_MEM_SIZE\t0x10000\t\t/* 1M of 32-bit registers */\n-#define TCM_MEM_SIZE\t0x20000\t\t/* 2M of 32-bit registers */\n-\n-/* 2.5 transmit connection memory registers */\n-\n-#define TSR0_CONN_STATE(x)\t((x>>28) & 0x7)\n-#define TSR0_USE_WMIN\t\t(1<<23)\n-#define TSR0_GROUP(x)\t\t((x & 0x7)<<18)\n-#define TSR0_ABR\t\t(2<<16)\n-#define TSR0_UBR\t\t(1<<16)\n-#define TSR0_CBR\t\t(0<<16)\n-#define TSR0_PROT\t\t(1<<15)\n-#define TSR0_AAL0_SDU\t\t(2<<12)\n-#define TSR0_AAL0\t\t(1<<12)\n-#define TSR0_AAL5\t\t(0<<12)\n-#define TSR0_HALT_ER\t\t(1<<11)\n-#define TSR0_MARK_CI\t\t(1<<10)\n-#define TSR0_MARK_ER\t\t(1<<9)\n-#define TSR0_UPDATE_GER\t\t(1<<8)\n-#define TSR0_RC_INDEX(x)\t(x & 0x1F)\n-\n-#define TSR1_PCR(x)\t\t((x & 0x7FFF)<<16)\n-#define TSR1_MCR(x)\t\t(x & 0x7FFF)\n-\n-#define TSR2_ACR(x)\t\t((x & 0x7FFF)<<16)\n-\n-#define TSR3_NRM_CNT(x)\t\t((x & 0xFF)<<24)\n-#define TSR3_CRM_CNT(x)\t\t(x & 0xFFFF)\n-\n-#define TSR4_FLUSH_CONN\t\t(1<<31)\n-#define TSR4_SESSION_ENDED\t(1<<30)\n-#define TSR4_CRC10\t\t(1<<28)\n-#define TSR4_NULL_CRC10\t\t(1<<27)\n-#define TSR4_PROT\t\t(1<<26)\n-#define TSR4_AAL0_SDU\t\t(2<<23)\n-#define TSR4_AAL0\t\t(1<<23)\n-#define TSR4_AAL5\t\t(0<<23)\n-\n-#define TSR9_OPEN_CONN\t\t(1<<20)\n-\n-#define TSR11_ICR(x)\t\t((x & 0x7FFF)<<16)\n-#define TSR11_TRM(x)\t\t((x & 0x7)<<13)\n-#define TSR11_NRM(x)\t\t((x & 0x7)<<10)\n-#define TSR11_ADTF(x)\t\t(x & 0x3FF)\n-\n-#define TSR13_RDF(x)\t\t((x & 0xF)<<23)\n-#define TSR13_RIF(x)\t\t((x & 0xF)<<19)\n-#define TSR13_CDF(x)\t\t((x & 0x7)<<16)\n-#define TSR13_CRM(x)\t\t(x & 0xFFFF)\n-\n-#define TSR14_DELETE\t\t(1<<31)\n-#define TSR14_ABR_CLOSE\t\t(1<<16)\n-\n-/* 2.7.1 per connection receieve state registers */\n-\n-#define RSR0_START_PDU\t(1<<10)\n-#define RSR0_OPEN_CONN\t(1<<6)\n-#define RSR0_CLOSE_CONN\t(0<<6)\n-#define RSR0_PPD_ENABLE\t(1<<5)\n-#define RSR0_EPD_ENABLE\t(1<<4)\n-#define RSR0_TCP_CKSUM\t(1<<3)\n-#define RSR0_AAL5\t\t(0)\n-#define RSR0_AAL0\t\t(1)\n-#define RSR0_AAL0_SDU\t\t(2)\n-#define RSR0_RAWCELL\t\t(3)\n-#define RSR0_RAWCELL_CRC10\t(4)\n-\n-#define RSR1_AQI_ENABLE\t(1<<20)\n-#define RSR1_RBPL_ONLY\t(1<<19)\n-#define RSR1_GROUP(x)\t((x)<<16)\n-\n-#define RSR4_AQI_ENABLE (1<<30)\n-#define RSR4_GROUP(x)\t((x)<<27)\n-#define RSR4_RBPL_ONLY\t(1<<26)\n-\n-/* 2.1.4 transmit packet descriptor */\n-\n-#define\tTPD_USERCELL\t\t0x0\n-#define\tTPD_SEGMENT_OAMF5\t0x4\n-#define\tTPD_END2END_OAMF5\t0x5\n-#define\tTPD_RMCELL\t\t0x6\n-#define TPD_CELLTYPE(x)\t\t(x<<3)\n-#define TPD_EOS\t\t\t(1<<2)\n-#define TPD_CLP\t\t\t(1<<1)\n-#define TPD_INT\t\t\t(1<<0)\n-#define TPD_LST\t\t(1<<31)\n-\n-/* table 4.3 serial eeprom information */\n-\n-#define PROD_ID\t\t0x08\t/* char[] */\n-#define PROD_ID_LEN\t30\n-#define HW_REV\t\t0x26\t/* char[] */\n-#define M_SN\t\t0x3a\t/* integer */\n-#define MEDIA\t\t0x3e\t/* integer */\n-#define HE155MM\t0x26\n-#define HE622MM\t0x27\n-#define HE155SM\t0x46\n-#define HE622SM\t0x47\n-#define MAC_ADDR\t0x42\t/* char[] */\n-\n-#define CS_LOW\t\t0x0\n-#define CS_HIGH\t\tID_CS /* HOST_CNTL_ID_PROM_SEL */\n-#define CLK_LOW\t\t0x0\n-#define CLK_HIGH\tID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */\n-#define SI_HIGH\t\tID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */\n-#define EEPROM_DELAY\t400 /* microseconds */\n-\n-#endif /* _HE_H_ */\ndiff --git a/drivers/atm/idt77105.h b/drivers/atm/idt77105.h\ndeleted file mode 100644\nindex 8dfea9e361de..000000000000\n--- a/drivers/atm/idt77105.h\n+++ /dev/null\n@@ -1,92 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */\n- \n-/* Written 1999 by Greg Banks, NEC Australia . Based on suni.h */\n- \n-\n-#ifndef DRIVER_ATM_IDT77105_H\n-#define DRIVER_ATM_IDT77105_H\n-\n-#include \n-#include \n-\n-\n-/* IDT77105 registers */\n-\n-#define IDT77105_MCR\t\t0x0\t/* Master Control Register */\n-#define IDT77105_ISTAT\t 0x1\t/* Interrupt Status */\n-#define IDT77105_DIAG \t0x2\t/* Diagnostic Control */\n-#define IDT77105_LEDHEC\t\t0x3\t/* LED Driver & HEC Status/Control */\n-#define IDT77105_CTRLO\t\t0x4\t/* Low Byte Counter Register */\n-#define IDT77105_CTRHI\t\t0x5\t/* High Byte Counter Register */\n-#define IDT77105_CTRSEL\t\t0x6\t/* Counter Register Read Select */\n-\n-/* IDT77105 register values */\n-\n-/* MCR */\n-#define IDT77105_MCR_UPLO\t0x80\t/* R/W, User Prog'le Output Latch */\n-#define IDT77105_MCR_DREC\t0x40\t/* R/W, Discard Receive Error Cells */\n-#define IDT77105_MCR_ECEIO\t0x20\t/* R/W, Enable Cell Error Interrupts\n- * Only */\n-#define IDT77105_MCR_TDPC\t0x10\t/* R/W, Transmit Data Parity Check */\n-#define IDT77105_MCR_DRIC\t0x08\t/* R/W, Discard Received Idle Cells */\n-#define IDT77105_MCR_HALTTX\t0x04\t/* R/W, Halt Tx */\n-#define IDT77105_MCR_UMODE\t0x02\t/* R/W, Utopia (cell/byte) Mode */\n-#define IDT77105_MCR_EIP\t0x01\t/* R/W, Enable Interrupt Pin */\n-\n-/* ISTAT */\n-#define IDT77105_ISTAT_GOODSIG\t0x40\t/* R, Good Signal Bit */\n-#define IDT77105_ISTAT_HECERR\t0x20\t/* sticky, HEC Error*/\n-#define IDT77105_ISTAT_SCR\t0x10\t/* sticky, Short Cell Received */\n-#define IDT77105_ISTAT_TPE\t0x08\t/* sticky, Transmit Parity Error */\n-#define IDT77105_ISTAT_RSCC\t0x04\t/* sticky, Rx Signal Condition Change */\n-#define IDT77105_ISTAT_RSE\t0x02\t/* sticky, Rx Symbol Error */\n-#define IDT77105_ISTAT_RFO\t0x01\t/* sticky, Rx FIFO Overrun */\n-\n-/* DIAG */\n-#define IDT77105_DIAG_FTD\t0x80\t/* R/W, Force TxClav deassert */\n-#define IDT77105_DIAG_ROS\t0x40\t/* R/W, RxClav operation select */\n-#define IDT77105_DIAG_MPCS\t0x20\t/* R/W, Multi-PHY config'n select */\n-#define IDT77105_DIAG_RFLUSH\t0x10\t/* R/W, clear receive FIFO */\n-#define IDT77105_DIAG_ITPE\t0x08\t/* R/W, Insert Tx payload error */\n-#define IDT77105_DIAG_ITHE\t0x04\t/* R/W, Insert Tx HEC error */\n-#define IDT77105_DIAG_UMODE\t0x02\t/* R/W, Utopia (cell/byte) Mode */\n-#define IDT77105_DIAG_LCMASK\t0x03\t/* R/W, Loopback Control */\n-\n-#define IDT77105_DIAG_LC_NORMAL 0x00\t/* Receive from network */\n-#define IDT77105_DIAG_LC_PHY_LOOPBACK\t0x02\n-#define IDT77105_DIAG_LC_LINE_LOOPBACK\t0x03\n-\n-/* LEDHEC */\n-#define IDT77105_LEDHEC_DRHC\t0x40\t/* R/W, Disable Rx HEC check */\n-#define IDT77105_LEDHEC_DTHC\t0x20\t/* R/W, Disable Tx HEC calculation */\n-#define IDT77105_LEDHEC_RPWMASK\t0x18\t/* R/W, RxRef pulse width select */\n-#define IDT77105_LEDHEC_TFS\t0x04\t/* R, Tx FIFO Status (1=empty) */\n-#define IDT77105_LEDHEC_TLS\t0x02\t/* R, Tx LED Status (1=lit) */\n-#define IDT77105_LEDHEC_RLS\t0x01\t/* R, Rx LED Status (1=lit) */\n-\n-#define IDT77105_LEDHEC_RPW_1\t0x00\t/* RxRef active for 1 RxClk cycle */\n-#define IDT77105_LEDHEC_RPW_2\t0x08\t/* RxRef active for 2 RxClk cycle */\n-#define IDT77105_LEDHEC_RPW_4\t0x10\t/* RxRef active for 4 RxClk cycle */\n-#define IDT77105_LEDHEC_RPW_8\t0x18\t/* RxRef active for 8 RxClk cycle */\n-\n-/* CTRSEL */\n-#define IDT77105_CTRSEL_SEC\t0x08\t/* W, Symbol Error Counter */\n-#define IDT77105_CTRSEL_TCC\t0x04\t/* W, Tx Cell Counter */\n-#define IDT77105_CTRSEL_RCC\t0x02\t/* W, Rx Cell Counter */\n-#define IDT77105_CTRSEL_RHEC\t0x01\t/* W, Rx HEC Error Counter */\n-\n-#ifdef __KERNEL__\n-int idt77105_init(struct atm_dev *dev);\n-#endif\n-\n-/*\n- * Tunable parameters\n- */\n- \n-/* Time between samples of the hardware cell counters. Should be <= 1 sec */\n-#define IDT77105_STATS_TIMER_PERIOD (HZ) \n-/* Time between checks to see if the signal has been found again */\n-#define IDT77105_RESTART_TIMER_PERIOD (5 * HZ)\n-\n-#endif\ndiff --git a/drivers/atm/idt77252.h b/drivers/atm/idt77252.h\ndeleted file mode 100644\nindex b059d31364dd..000000000000\n--- a/drivers/atm/idt77252.h\n+++ /dev/null\n@@ -1,816 +0,0 @@\n-/******************************************************************* \n- *\n- * Copyright (c) 2000 ATecoM GmbH \n- *\n- * The author may be reached at ecd@atecom.com.\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; either version 2 of the License, or (at your\n- * option) any later version.\n- *\n- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED\n- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN\n- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF\n- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- *\n- * You should have received a copy of the GNU General Public License along\n- * with this program; if not, write to the Free Software Foundation, Inc.,\n- * 675 Mass Ave, Cambridge, MA 02139, USA.\n- *\n- *******************************************************************/\n-\n-#ifndef _IDT77252_H\n-#define _IDT77252_H 1\n-\n-\n-#include \n-#include \n-#include \n-#include \n-\n-/*****************************************************************************/\n-/* */\n-/* Makros */\n-/* */\n-/*****************************************************************************/\n-#define VPCI2VC(card, vpi, vci) \\\n- (((vpi) << card->vcibits) | ((vci) & card->vcimask))\n-\n-/*****************************************************************************/\n-/* */\n-/* DEBUGGING definitions */\n-/* */\n-/*****************************************************************************/\n-\n-#define DBG_RAW_CELL\t0x00000400\n-#define DBG_TINY\t0x00000200\n-#define DBG_GENERAL 0x00000100\n-#define DBG_XGENERAL 0x00000080\n-#define DBG_INIT 0x00000040\n-#define DBG_DEINIT 0x00000020\n-#define DBG_INTERRUPT 0x00000010\n-#define DBG_OPEN_CONN 0x00000008\n-#define DBG_CLOSE_CONN 0x00000004\n-#define DBG_RX_DATA 0x00000002\n-#define DBG_TX_DATA 0x00000001\n-\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-\n-#define CPRINTK(args...) do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0)\n-#define OPRINTK(args...) do { if (debug & DBG_OPEN_CONN) printk(args); } while(0)\n-#define IPRINTK(args...) do { if (debug & DBG_INIT) printk(args); } while(0)\n-#define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT) printk(args); } while(0)\n-#define DIPRINTK(args...) do { if (debug & DBG_DEINIT) printk(args); } while(0)\n-#define TXPRINTK(args...) do { if (debug & DBG_TX_DATA) printk(args); } while(0)\n-#define RXPRINTK(args...) do { if (debug & DBG_RX_DATA) printk(args); } while(0)\n-#define XPRINTK(args...) do { if (debug & DBG_XGENERAL) printk(args); } while(0)\n-#define DPRINTK(args...) do { if (debug & DBG_GENERAL) printk(args); } while(0)\n-#define NPRINTK(args...) do { if (debug & DBG_TINY)\t printk(args); } while(0)\n-#define RPRINTK(args...) do { if (debug & DBG_RAW_CELL) printk(args); } while(0)\n-\n-#else\n-\n-#define CPRINTK(args...)\tdo { } while(0)\n-#define OPRINTK(args...)\tdo { } while(0)\n-#define IPRINTK(args...)\tdo { } while(0)\n-#define INTPRINTK(args...)\tdo { } while(0)\n-#define DIPRINTK(args...)\tdo { } while(0)\n-#define TXPRINTK(args...)\tdo { } while(0)\n-#define RXPRINTK(args...)\tdo { } while(0)\n-#define XPRINTK(args...)\tdo { } while(0)\n-#define DPRINTK(args...)\tdo { } while(0)\n-#define NPRINTK(args...)\tdo { } while(0)\n-#define RPRINTK(args...)\tdo { } while(0)\n-\n-#endif\n-\n-#define SCHED_UBR0\t\t0\n-#define SCHED_UBR\t\t1\n-#define SCHED_VBR\t\t2\n-#define SCHED_ABR\t\t3\n-#define SCHED_CBR\t\t4\n-\n-#define SCQFULL_TIMEOUT\t\tHZ\n-\n-/*****************************************************************************/\n-/* */\n-/* Free Buffer Queue Layout */\n-/* */\n-/*****************************************************************************/\n-#define SAR_FB_SIZE_0\t\t(2048 - 256)\n-#define SAR_FB_SIZE_1\t\t(4096 - 256)\n-#define SAR_FB_SIZE_2\t\t(8192 - 256)\n-#define SAR_FB_SIZE_3\t\t(16384 - 256)\n-\n-#define SAR_FBQ0_LOW\t\t4\n-#define SAR_FBQ0_HIGH\t\t8\n-#define SAR_FBQ1_LOW\t\t2\n-#define SAR_FBQ1_HIGH\t\t4\n-#define SAR_FBQ2_LOW\t\t1\n-#define SAR_FBQ2_HIGH\t\t2\n-#define SAR_FBQ3_LOW\t\t1\n-#define SAR_FBQ3_HIGH\t\t2\n-\n-#if 0\n-#define SAR_TST_RESERVED\t44\t/* Num TST reserved for UBR/ABR/VBR */\n-#else\n-#define SAR_TST_RESERVED\t0\t/* Num TST reserved for UBR/ABR/VBR */\n-#endif\n-\n-#define TCT_CBR\t\t\t0x00000000\n-#define TCT_UBR\t\t\t0x00000000\n-#define TCT_VBR\t\t\t0x40000000\n-#define TCT_ABR\t\t\t0x80000000\n-#define TCT_TYPE\t\t0xc0000000\n-\n-#define TCT_RR\t\t\t0x20000000\n-#define TCT_LMCR\t\t0x08000000\n-#define TCT_SCD_MASK\t\t0x0007ffff\n-\n-#define TCT_TSIF\t\t0x00004000\n-#define TCT_HALT\t\t0x80000000\n-#define TCT_IDLE\t\t0x40000000\n-#define TCT_FLAG_UBR\t\t0x80000000\n-\n-/*****************************************************************************/\n-/* */\n-/* Structure describing an IDT77252 */\n-/* */\n-/*****************************************************************************/\n-\n-struct scqe\n-{\n-\tu32\t\tword_1;\n-\tu32\t\tword_2;\n-\tu32\t\tword_3;\n-\tu32\t\tword_4;\n-};\n-\n-#define SCQ_ENTRIES\t64\n-#define SCQ_SIZE\t(SCQ_ENTRIES * sizeof(struct scqe))\n-#define SCQ_MASK\t(SCQ_SIZE - 1)\n-\n-struct scq_info\n-{\n-\tstruct scqe\t\t*base;\n-\tstruct scqe\t\t*next;\n-\tstruct scqe\t\t*last;\n-\tdma_addr_t\t\tpaddr;\n-\tspinlock_t\t\tlock;\n-\tatomic_t\t\tused;\n-\tunsigned long\t\ttrans_start;\n- unsigned long\t\tscd;\n-\tspinlock_t\t\tskblock;\n-\tstruct sk_buff_head\ttransmit;\n-\tstruct sk_buff_head\tpending;\n-};\n-\n-struct rx_pool {\n-\tstruct sk_buff_head\tqueue;\n-\tunsigned int\t\tlen;\n-};\n-\n-struct aal1 {\n-\tunsigned int\t\ttotal;\n-\tunsigned int\t\tcount;\n-\tstruct sk_buff\t\t*data;\n-\tunsigned char\t\tsequence;\n-};\n-\n-struct vc_map;\n-\n-struct rate_estimator {\n-\tstruct timer_list\ttimer;\n-\tunsigned int\t\tinterval;\n-\tunsigned int\t\tewma_log;\n-\tu64\t\t\tcells;\n-\tu64\t\t\tlast_cells;\n-\tlong\t\t\tavcps;\n-\tu32\t\t\tcps;\n-\tu32\t\t\tmaxcps;\n-\tstruct vc_map\t\t*vc;\n-};\n-\n-struct vc_map {\n-\tunsigned int\t\tindex;\n-\tunsigned long\t\tflags;\n-#define VCF_TX\t\t0\n-#define VCF_RX\t\t1\n-#define VCF_IDLE\t2\n-#define VCF_RSV\t\t3\n-\tunsigned int\t\tclass;\n-\tu8\t\t\tinit_er;\n-\tu8\t\t\tlacr;\n-\tu8\t\t\tmax_er;\n-\tunsigned int\t\tntste;\n-\tspinlock_t\t\tlock;\n-\tstruct atm_vcc\t\t*tx_vcc;\n-\tstruct atm_vcc\t\t*rx_vcc;\n-\tstruct idt77252_dev\t*card;\n-\tstruct scq_info\t\t*scq;\t\t/* To keep track of the SCQ */\n-\tstruct rate_estimator\t*estimator;\n-\tint\t\t\tscd_index;\n-\tunion {\n-\t\tstruct rx_pool\trx_pool;\n-\t\tstruct aal1\taal1;\n-\t} rcv;\n-};\n-\n-/*****************************************************************************/\n-/* */\n-/* RCTE - Receive Connection Table Entry */\n-/* */\n-/*****************************************************************************/\n-\n-struct rct_entry\n-{\n-\tu32\t\tword_1;\n-\tu32\t\tbuffer_handle;\n-\tu32\t\tdma_address;\n-\tu32\t\taal5_crc32;\n-};\n-\n-/*****************************************************************************/\n-/* */\n-/* RSQ - Receive Status Queue */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_RSQE_VALID 0x80000000\n-#define SAR_RSQE_IDLE 0x40000000\n-#define SAR_RSQE_BUF_MASK 0x00030000\n-#define SAR_RSQE_BUF_ASGN 0x00008000\n-#define SAR_RSQE_NZGFC 0x00004000\n-#define SAR_RSQE_EPDU 0x00002000\n-#define SAR_RSQE_BUF_CONT 0x00001000\n-#define SAR_RSQE_EFCIE 0x00000800\n-#define SAR_RSQE_CLP 0x00000400\n-#define SAR_RSQE_CRC 0x00000200\n-#define SAR_RSQE_CELLCNT 0x000001FF\n-\n-\n-#define RSQSIZE 8192\n-#define RSQ_NUM_ENTRIES (RSQSIZE / 16)\n-#define RSQ_ALIGNMENT 8192\n-\n-struct rsq_entry {\n-\tu32\t\t\tword_1;\n-\tu32\t\t\tword_2;\n-\tu32\t\t\tword_3;\n-\tu32\t\t\tword_4;\n-};\n-\n-struct rsq_info {\n-\tstruct rsq_entry\t*base;\n-\tstruct rsq_entry\t*next;\n-\tstruct rsq_entry\t*last;\n-\tdma_addr_t\t\tpaddr;\n-};\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* TSQ - Transmit Status Queue */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_TSQE_INVALID 0x80000000\n-#define SAR_TSQE_TIMESTAMP 0x00FFFFFF\n-#define SAR_TSQE_TYPE\t\t 0x60000000\n-#define SAR_TSQE_TYPE_TIMER 0x00000000\n-#define SAR_TSQE_TYPE_TSR 0x20000000\n-#define SAR_TSQE_TYPE_IDLE 0x40000000\n-#define SAR_TSQE_TYPE_TBD_COMP 0x60000000\n-\n-#define SAR_TSQE_TAG(stat)\t(((stat) >> 24) & 0x1f)\n-\n-#define TSQSIZE 8192\n-#define TSQ_NUM_ENTRIES 1024\n-#define TSQ_ALIGNMENT 8192\n-\n-struct tsq_entry\n-{\n-\tu32\t\t\tword_1;\n-\tu32\t\t\tword_2;\n-};\n-\n-struct tsq_info\n-{\n-\tstruct tsq_entry\t*base;\n-\tstruct tsq_entry\t*next;\n-\tstruct tsq_entry\t*last;\n-\tdma_addr_t\t\tpaddr;\n-};\n-\n-struct tst_info\n-{\n-\tstruct vc_map\t\t*vc;\n-\tu32\t\t\ttste;\n-};\n-\n-#define TSTE_MASK\t\t0x601fffff\n-\n-#define TSTE_OPC_MASK\t\t0x60000000\n-#define TSTE_OPC_NULL\t\t0x00000000\n-#define TSTE_OPC_CBR\t\t0x20000000\n-#define TSTE_OPC_VAR\t\t0x40000000\n-#define TSTE_OPC_JMP\t\t0x60000000\n-\n-#define TSTE_PUSH_IDLE\t\t0x01000000\n-#define TSTE_PUSH_ACTIVE\t0x02000000\n-\n-#define TST_SWITCH_DONE\t\t0\n-#define TST_SWITCH_PENDING\t1\n-#define TST_SWITCH_WAIT\t\t2\n-\n-#define FBQ_SHIFT\t\t9\n-#define FBQ_SIZE\t\t(1 << FBQ_SHIFT)\n-#define FBQ_MASK\t\t(FBQ_SIZE - 1)\n-\n-struct sb_pool\n-{\n-\tunsigned int\t\tindex;\n-\tstruct sk_buff\t\t*skb[FBQ_SIZE];\n-};\n-\n-#define POOL_HANDLE(queue, index)\t(((queue + 1) << 16) | (index))\n-#define POOL_QUEUE(handle)\t\t(((handle) >> 16) - 1)\n-#define POOL_INDEX(handle)\t\t((handle) & 0xffff)\n-\n-struct idt77252_dev\n-{\n- struct tsq_info\t\ttsq;\t\t/* Transmit Status Queue */\n- struct rsq_info\t\trsq;\t\t/* Receive Status Queue */\n-\n-\tstruct pci_dev\t\t*pcidev;\t/* PCI handle (desriptor) */\n-\tstruct atm_dev\t\t*atmdev;\t/* ATM device desriptor */\n-\n-\tvoid __iomem\t\t*membase;\t/* SAR's memory base address */\n-\tunsigned long\t\tsrambase;\t/* SAR's sram base address */\n-\tvoid __iomem\t\t*fbq[4];\t/* FBQ fill addresses */\n-\n-\tstruct mutex\t\tmutex;\n-\tspinlock_t\t\tcmd_lock;\t/* for r/w utility/sram */\n-\n-\tunsigned long\t\tsoftstat;\n-\tunsigned long\t\tflags;\t\t/* see blow */\n-\n-\tstruct work_struct\ttqueue;\n-\n-\tunsigned long\t\ttct_base;\t/* TCT base address in SRAM */\n- unsigned long\t\trct_base;\t/* RCT base address in SRAM */\n- unsigned long\t\trt_base;\t/* Rate Table base in SRAM */\n- unsigned long\t\tscd_base;\t/* SCD base address in SRAM */\n- unsigned long\t\ttst[2];\t\t/* TST base address in SRAM */\n-\tunsigned long\t\tabrst_base;\t/* ABRST base address in SRAM */\n- unsigned long\t\tfifo_base;\t/* RX FIFO base in SRAM */\n-\n-\tunsigned long\t\tirqstat[16];\n-\n-\tunsigned int\t\tsramsize;\t/* SAR's sram size */\n-\n- unsigned int\t\ttct_size;\t/* total TCT entries */\n- unsigned int\t\trct_size;\t/* total RCT entries */\n- unsigned int\t\tscd_size;\t/* length of SCD */\n- unsigned int\t\ttst_size;\t/* total TST entries */\n- unsigned int\t\ttst_free;\t/* free TSTEs in TST */\n- unsigned int\t\tabrst_size;\t/* size of ABRST in words */\n- unsigned int\t\tfifo_size;\t/* size of RX FIFO in words */\n-\n- unsigned int\t\tvpibits;\t/* Bits used for VPI index */\n- unsigned int\t\tvcibits;\t/* Bits used for VCI index */\n- unsigned int\t\tvcimask;\t/* Mask for VCI index */\n-\n-\tunsigned int\t\tutopia_pcr;\t/* Utopia Itf's Cell Rate */\n-\tunsigned int\t\tlink_pcr;\t/* PHY's Peek Cell Rate */\n-\n-\tstruct vc_map\t\t**vcs;\t\t/* Open Connections */\n-\tstruct vc_map\t\t**scd2vc;\t/* SCD to Connection map */\n-\n-\tstruct tst_info\t\t*soft_tst;\t/* TST to Connection map */\n-\tunsigned int\t\ttst_index;\t/* Current TST in use */\n-\tstruct timer_list\ttst_timer;\n-\tspinlock_t\t\ttst_lock;\n-\tunsigned long\t\ttst_state;\n-\n-\tstruct sb_pool\t\tsbpool[4];\t/* Pool of RX skbuffs */\n-\tstruct sk_buff\t\t*raw_cell_head; /* Pointer to raw cell queue */\n-\tu32\t\t\t*raw_cell_hnd;\t/* Pointer to RCQ handle */\n-\tdma_addr_t\t\traw_cell_paddr;\n-\n-\tint\t\t\tindex;\t\t/* SAR's ID */\n-\tint\t\t\trevision;\t/* chip revision */\n-\n-\tchar\t\t\tname[16];\t/* Device name */\n-\n-\tstruct idt77252_dev\t*next;\n-};\n-\n-\n-/* definition for flag field above */\n-#define IDT77252_BIT_INIT\t\t1\n-#define IDT77252_BIT_INTERRUPT\t\t2\n-\n-\n-#define ATM_CELL_PAYLOAD 48\n-\n-#define FREEBUF_ALIGNMENT 16\n-\n-/*****************************************************************************/\n-/* */\n-/* Makros */\n-/* */\n-/*****************************************************************************/\n-#define ALIGN_ADDRESS(addr, alignment) \\\n- ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* ABR SAR Network operation Register */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_REG_DR0\t(card->membase + 0x00)\n-#define SAR_REG_DR1\t(card->membase + 0x04)\n-#define SAR_REG_DR2\t(card->membase + 0x08)\n-#define SAR_REG_DR3\t(card->membase + 0x0C)\n-#define SAR_REG_CMD\t(card->membase + 0x10)\n-#define SAR_REG_CFG\t(card->membase + 0x14)\n-#define SAR_REG_STAT\t(card->membase + 0x18)\n-#define SAR_REG_RSQB\t(card->membase + 0x1C)\n-#define SAR_REG_RSQT\t(card->membase + 0x20)\n-#define SAR_REG_RSQH\t(card->membase + 0x24)\n-#define SAR_REG_CDC\t(card->membase + 0x28)\n-#define SAR_REG_VPEC\t(card->membase + 0x2C)\n-#define SAR_REG_ICC\t(card->membase + 0x30)\n-#define SAR_REG_RAWCT\t(card->membase + 0x34)\n-#define SAR_REG_TMR\t(card->membase + 0x38)\n-#define SAR_REG_TSTB\t(card->membase + 0x3C)\n-#define SAR_REG_TSQB\t(card->membase + 0x40)\n-#define SAR_REG_TSQT\t(card->membase + 0x44)\n-#define SAR_REG_TSQH\t(card->membase + 0x48)\n-#define SAR_REG_GP\t(card->membase + 0x4C)\n-#define SAR_REG_VPM\t(card->membase + 0x50)\n-#define SAR_REG_RXFD\t(card->membase + 0x54)\n-#define SAR_REG_RXFT\t(card->membase + 0x58)\n-#define SAR_REG_RXFH\t(card->membase + 0x5C)\n-#define SAR_REG_RAWHND\t(card->membase + 0x60)\n-#define SAR_REG_RXSTAT\t(card->membase + 0x64)\n-#define SAR_REG_ABRSTD\t(card->membase + 0x68)\n-#define SAR_REG_ABRRQ\t(card->membase + 0x6C)\n-#define SAR_REG_VBRRQ\t(card->membase + 0x70)\n-#define SAR_REG_RTBL\t(card->membase + 0x74)\n-#define SAR_REG_MDFCT\t(card->membase + 0x78)\n-#define SAR_REG_TXSTAT\t(card->membase + 0x7C)\n-#define SAR_REG_TCMDQ\t(card->membase + 0x80)\n-#define SAR_REG_IRCP\t(card->membase + 0x84)\n-#define SAR_REG_FBQP0\t(card->membase + 0x88)\n-#define SAR_REG_FBQP1\t(card->membase + 0x8C)\n-#define SAR_REG_FBQP2\t(card->membase + 0x90)\n-#define SAR_REG_FBQP3\t(card->membase + 0x94)\n-#define SAR_REG_FBQS0\t(card->membase + 0x98)\n-#define SAR_REG_FBQS1\t(card->membase + 0x9C)\n-#define SAR_REG_FBQS2\t(card->membase + 0xA0)\n-#define SAR_REG_FBQS3\t(card->membase + 0xA4)\n-#define SAR_REG_FBQWP0\t(card->membase + 0xA8)\n-#define SAR_REG_FBQWP1\t(card->membase + 0xAC)\n-#define SAR_REG_FBQWP2\t(card->membase + 0xB0)\n-#define SAR_REG_FBQWP3\t(card->membase + 0xB4)\n-#define SAR_REG_NOW\t(card->membase + 0xB8)\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* Commands */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_CMD_NO_OPERATION 0x00000000\n-#define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000\n-#define SAR_CMD_WRITE_SRAM 0x40000000\n-#define SAR_CMD_READ_SRAM 0x50000000\n-#define SAR_CMD_READ_UTILITY 0x80000000\n-#define SAR_CMD_WRITE_UTILITY 0x90000000\n-\n-#define SAR_CMD_OPEN_CONNECTION (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)\n-#define SAR_CMD_CLOSE_CONNECTION SAR_CMD_OPENCLOSE_CONNECTION\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* Configuration Register bits */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_CFG_SWRST 0x80000000 /* Software reset */\n-#define SAR_CFG_LOOP 0x40000000 /* Internal Loopback */\n-#define SAR_CFG_RXPTH 0x20000000 /* Receive Path Enable */\n-#define SAR_CFG_IDLE_CLP 0x10000000 /* SAR set CLP Bits of Null Cells */\n-#define SAR_CFG_TX_FIFO_SIZE_1 0x04000000 /* TX FIFO Size = 1 cell */\n-#define SAR_CFG_TX_FIFO_SIZE_2 0x08000000 /* TX FIFO Size = 2 cells */\n-#define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000 /* TX FIFO Size = 4 cells */\n-#define SAR_CFG_TX_FIFO_SIZE_9 0x00000000 /* TX FIFO Size = 9 cells (full) */\n-#define SAR_CFG_NO_IDLE 0x02000000 /* SAR sends no Null Cells */\n-#define SAR_CFG_RSVD1 0x01000000 /* Reserved */\n-#define SAR_CFG_RXSTQ_SIZE_2k 0x00000000 /* RX Stat Queue Size = 2048 byte */\n-#define SAR_CFG_RXSTQ_SIZE_4k 0x00400000 /* RX Stat Queue Size = 4096 byte */\n-#define SAR_CFG_RXSTQ_SIZE_8k 0x00800000 /* RX Stat Queue Size = 8192 byte */\n-#define SAR_CFG_RXSTQ_SIZE_R 0x00C00000 /* RX Stat Queue Size = reserved */\n-#define SAR_CFG_ICAPT 0x00200000 /* accept Invalid Cells */\n-#define SAR_CFG_IGGFC 0x00100000 /* Ignore GFC */\n-#define SAR_CFG_VPVCS_0 0x00000000 /* VPI/VCI Select bit range */\n-#define SAR_CFG_VPVCS_1 0x00040000 /* VPI/VCI Select bit range */\n-#define SAR_CFG_VPVCS_2 0x00080000 /* VPI/VCI Select bit range */\n-#define SAR_CFG_VPVCS_8 0x000C0000 /* VPI/VCI Select bit range */\n-#define SAR_CFG_CNTBL_1k 0x00000000 /* Connection Table Size */\n-#define SAR_CFG_CNTBL_4k 0x00010000 /* Connection Table Size */\n-#define SAR_CFG_CNTBL_16k 0x00020000 /* Connection Table Size */\n-#define SAR_CFG_CNTBL_512 0x00030000 /* Connection Table Size */\n-#define SAR_CFG_VPECA 0x00008000 /* VPI/VCI Error Cell Accept */\n-#define SAR_CFG_RXINT_NOINT 0x00000000 /* No Interrupt on PDU received */\n-#define SAR_CFG_RXINT_NODELAY 0x00001000 /* Interrupt without delay to host*/\n-#define SAR_CFG_RXINT_256US 0x00002000 /* Interrupt with delay 256 usec */\n-#define SAR_CFG_RXINT_505US 0x00003000 /* Interrupt with delay 505 usec */\n-#define SAR_CFG_RXINT_742US 0x00004000 /* Interrupt with delay 742 usec */\n-#define SAR_CFG_RAWIE 0x00000800 /* Raw Cell Queue Interrupt Enable*/\n-#define SAR_CFG_RQFIE 0x00000400 /* RSQ Almost Full Int Enable */\n-#define SAR_CFG_RSVD2 0x00000200 /* Reserved */\n-#define SAR_CFG_CACHE 0x00000100 /* DMA on Cache Line Boundary */\n-#define SAR_CFG_TMOIE 0x00000080 /* Timer Roll Over Int Enable */\n-#define SAR_CFG_FBIE 0x00000040 /* Free Buffer Queue Int Enable */\n-#define SAR_CFG_TXEN 0x00000020 /* Transmit Operation Enable */\n-#define SAR_CFG_TXINT 0x00000010 /* Transmit status Int Enable */\n-#define SAR_CFG_TXUIE 0x00000008 /* Transmit underrun Int Enable */\n-#define SAR_CFG_UMODE 0x00000004 /* Utopia Mode Select */\n-#define SAR_CFG_TXSFI 0x00000002 /* Transmit status Full Int Enable*/\n-#define SAR_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */\n-\n-#define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000 /* TX FIFO Size Mask */\n-#define SAR_CFG_RXSTQSIZE_MASK 0x00C00000\n-#define SAR_CFG_CNTBL_MASK 0x00030000\n-#define SAR_CFG_RXINT_MASK 0x00007000\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* Status Register bits */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_STAT_FRAC_3 0xF0000000 /* Fraction of Free Buffer Queue 3 */\n-#define SAR_STAT_FRAC_2 0x0F000000 /* Fraction of Free Buffer Queue 2 */\n-#define SAR_STAT_FRAC_1 0x00F00000 /* Fraction of Free Buffer Queue 1 */\n-#define SAR_STAT_FRAC_0 0x000F0000 /* Fraction of Free Buffer Queue 0 */\n-#define SAR_STAT_TSIF 0x00008000 /* Transmit Status Indicator */\n-#define SAR_STAT_TXICP 0x00004000 /* Transmit Status Indicator */\n-#define SAR_STAT_RSVD1 0x00002000 /* Reserved */\n-#define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */\n-#define SAR_STAT_TMROF 0x00000800 /* Timer overflow */\n-#define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */\n-#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Command Busy Flag */\n-#define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */\n-#define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */\n-#define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */\n-#define SAR_STAT_EPDU 0x00000020 /* End Of PDU Flag */\n-#define SAR_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ \n-#define SAR_STAT_FBQ1A 0x00000008 /* Free Buffer Queue 1 Attention */\n-#define SAR_STAT_FBQ0A 0x00000004 /* Free Buffer Queue 0 Attention */\n-#define SAR_STAT_RSQAF 0x00000002 /* Receive Status Queue almost full*/ \n-#define SAR_STAT_RSVD2 0x00000001 /* Reserved */\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* General Purpose Register bits */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_GP_TXNCC_MASK 0xff000000 /* Transmit Negative Credit Count */\n-#define SAR_GP_EEDI 0x00010000 /* EEPROM Data In */\n-#define SAR_GP_BIGE 0x00008000 /* Big Endian Operation */\n-#define SAR_GP_RM_NORMAL 0x00000000 /* Normal handling of RM cells */\n-#define SAR_GP_RM_TO_RCQ 0x00002000 /* put RM cells into Raw Cell Queue */\n-#define SAR_GP_RM_RSVD 0x00004000 /* Reserved */\n-#define SAR_GP_RM_INHIBIT 0x00006000 /* Inhibit update of Connection tab */\n-#define SAR_GP_PHY_RESET 0x00000008 /* PHY Reset */\n-#define SAR_GP_EESCLK\t 0x00000004\t/* EEPROM SCLK\t\t\t */\n-#define SAR_GP_EECS\t 0x00000002\t/* EEPROM Chip Select\t\t */\n-#define SAR_GP_EEDO\t 0x00000001\t/* EEPROM Data Out\t\t */\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* SAR local SRAM layout for 128k work SRAM */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_SRAM_SCD_SIZE 12\n-#define SAR_SRAM_TCT_SIZE 8\n-#define SAR_SRAM_RCT_SIZE 4\n-\n-#define SAR_SRAM_TCT_128_BASE 0x00000\n-#define SAR_SRAM_TCT_128_TOP 0x01fff\n-#define SAR_SRAM_RCT_128_BASE 0x02000\n-#define SAR_SRAM_RCT_128_TOP 0x02fff\n-#define SAR_SRAM_FB0_128_BASE 0x03000\n-#define SAR_SRAM_FB0_128_TOP 0x033ff\n-#define SAR_SRAM_FB1_128_BASE 0x03400\n-#define SAR_SRAM_FB1_128_TOP 0x037ff\n-#define SAR_SRAM_FB2_128_BASE 0x03800\n-#define SAR_SRAM_FB2_128_TOP 0x03bff\n-#define SAR_SRAM_FB3_128_BASE 0x03c00\n-#define SAR_SRAM_FB3_128_TOP 0x03fff\n-#define SAR_SRAM_SCD_128_BASE 0x04000\n-#define SAR_SRAM_SCD_128_TOP 0x07fff\n-#define SAR_SRAM_TST1_128_BASE 0x08000\n-#define SAR_SRAM_TST1_128_TOP 0x0bfff\n-#define SAR_SRAM_TST2_128_BASE 0x0c000\n-#define SAR_SRAM_TST2_128_TOP 0x0ffff\n-#define SAR_SRAM_ABRSTD_128_BASE 0x10000\n-#define SAR_SRAM_ABRSTD_128_TOP 0x13fff\n-#define SAR_SRAM_RT_128_BASE 0x14000\n-#define SAR_SRAM_RT_128_TOP 0x15fff\n-\n-#define SAR_SRAM_FIFO_128_BASE 0x18000\n-#define SAR_SRAM_FIFO_128_TOP 0x1ffff\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* SAR local SRAM layout for 32k work SRAM */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_SRAM_TCT_32_BASE 0x00000\n-#define SAR_SRAM_TCT_32_TOP 0x00fff\n-#define SAR_SRAM_RCT_32_BASE 0x01000\n-#define SAR_SRAM_RCT_32_TOP 0x017ff\n-#define SAR_SRAM_FB0_32_BASE 0x01800\n-#define SAR_SRAM_FB0_32_TOP 0x01bff\n-#define SAR_SRAM_FB1_32_BASE 0x01c00\n-#define SAR_SRAM_FB1_32_TOP 0x01fff\n-#define SAR_SRAM_FB2_32_BASE 0x02000\n-#define SAR_SRAM_FB2_32_TOP 0x023ff\n-#define SAR_SRAM_FB3_32_BASE 0x02400\n-#define SAR_SRAM_FB3_32_TOP 0x027ff\n-#define SAR_SRAM_SCD_32_BASE 0x02800\n-#define SAR_SRAM_SCD_32_TOP 0x03fff\n-#define SAR_SRAM_TST1_32_BASE 0x04000\n-#define SAR_SRAM_TST1_32_TOP 0x04fff\n-#define SAR_SRAM_TST2_32_BASE 0x05000\n-#define SAR_SRAM_TST2_32_TOP 0x05fff\n-#define SAR_SRAM_ABRSTD_32_BASE 0x06000\n-#define SAR_SRAM_ABRSTD_32_TOP 0x067ff\n-#define SAR_SRAM_RT_32_BASE 0x06800\n-#define SAR_SRAM_RT_32_TOP 0x06fff\n-#define SAR_SRAM_FIFO_32_BASE 0x07000\n-#define SAR_SRAM_FIFO_32_TOP 0x07fff\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* TSR - Transmit Status Request */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_TSR_TYPE_TSR 0x80000000\n-#define SAR_TSR_TYPE_TBD 0x00000000\n-#define SAR_TSR_TSIF 0x20000000\n-#define SAR_TSR_TAG_MASK 0x01F00000\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* TBD - Transmit Buffer Descriptor */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_TBD_EPDU 0x40000000\n-#define SAR_TBD_TSIF 0x20000000\n-#define SAR_TBD_OAM 0x10000000\n-#define SAR_TBD_AAL0 0x00000000\n-#define SAR_TBD_AAL34 0x04000000\n-#define SAR_TBD_AAL5 0x08000000\n-#define SAR_TBD_GTSI 0x02000000\n-#define SAR_TBD_TAG_MASK 0x01F00000\n-\n-#define SAR_TBD_VPI_MASK 0x0FF00000\n-#define SAR_TBD_VCI_MASK 0x000FFFF0\n-#define SAR_TBD_VC_MASK (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)\n-\n-#define SAR_TBD_VPI_SHIFT 20\n-#define SAR_TBD_VCI_SHIFT 4\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* RXFD - Receive FIFO Descriptor */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_RXFD_SIZE_MASK 0x0F000000\n-#define SAR_RXFD_SIZE_512 0x00000000 /* 512 words */\n-#define SAR_RXFD_SIZE_1K 0x01000000 /* 1k words */\n-#define SAR_RXFD_SIZE_2K 0x02000000 /* 2k words */\n-#define SAR_RXFD_SIZE_4K 0x03000000 /* 4k words */\n-#define SAR_RXFD_SIZE_8K 0x04000000 /* 8k words */\n-#define SAR_RXFD_SIZE_16K 0x05000000 /* 16k words */\n-#define SAR_RXFD_SIZE_32K 0x06000000 /* 32k words */\n-#define SAR_RXFD_SIZE_64K 0x07000000 /* 64k words */\n-#define SAR_RXFD_SIZE_128K 0x08000000 /* 128k words */\n-#define SAR_RXFD_SIZE_256K 0x09000000 /* 256k words */\n-#define SAR_RXFD_ADDR_MASK 0x001ffc00\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* ABRSTD - ABR + VBR Schedule Tables */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_ABRSTD_SIZE_MASK 0x07000000\n-#define SAR_ABRSTD_SIZE_512 0x00000000 /* 512 words */\n-#define SAR_ABRSTD_SIZE_1K 0x01000000 /* 1k words */\n-#define SAR_ABRSTD_SIZE_2K 0x02000000 /* 2k words */\n-#define SAR_ABRSTD_SIZE_4K 0x03000000 /* 4k words */\n-#define SAR_ABRSTD_SIZE_8K 0x04000000 /* 8k words */\n-#define SAR_ABRSTD_SIZE_16K 0x05000000 /* 16k words */\n-#define SAR_ABRSTD_ADDR_MASK 0x001ffc00\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* RCTE - Receive Connection Table Entry */\n-/* */\n-/*****************************************************************************/\n-\n-#define SAR_RCTE_IL_MASK 0xE0000000 /* inactivity limit */\n-#define SAR_RCTE_IC_MASK 0x1C000000 /* inactivity count */\n-#define SAR_RCTE_RSVD 0x02000000 /* reserved */\n-#define SAR_RCTE_LCD 0x01000000 /* last cell data */\n-#define SAR_RCTE_CI_VC 0x00800000 /* EFCI in previous cell of VC */\n-#define SAR_RCTE_FBP_01 0x00000000 /* 1. cell->FBQ0, others->FBQ1 */\n-#define SAR_RCTE_FBP_1 0x00200000 /* use FBQ 1 for all cells */\n-#define SAR_RCTE_FBP_2 0x00400000 /* use FBQ 2 for all cells */\n-#define SAR_RCTE_FBP_3 0x00600000 /* use FBQ 3 for all cells */\n-#define SAR_RCTE_NZ_GFC 0x00100000 /* non zero GFC in all cell of VC */\n-#define SAR_RCTE_CONNECTOPEN 0x00080000 /* VC is open */\n-#define SAR_RCTE_AAL_MASK 0x00070000 /* mask for AAL type field s.b. */\n-#define SAR_RCTE_RAWCELLINTEN 0x00008000 /* raw cell interrupt enable */\n-#define SAR_RCTE_RXCONCELLADDR 0x00004000 /* RX constant cell address */\n-#define SAR_RCTE_BUFFSTAT_MASK 0x00003000 /* buffer status */\n-#define SAR_RCTE_EFCI 0x00000800 /* EFCI Congestion flag */\n-#define SAR_RCTE_CLP 0x00000400 /* Cell Loss Priority flag */\n-#define SAR_RCTE_CRC 0x00000200 /* Received CRC Error */\n-#define SAR_RCTE_CELLCNT_MASK 0x000001FF /* cell Count */\n-\n-#define SAR_RCTE_AAL0 0x00000000 /* AAL types for ALL field */\n-#define SAR_RCTE_AAL34 0x00010000\n-#define SAR_RCTE_AAL5 0x00020000\n-#define SAR_RCTE_RCQ 0x00030000\n-#define SAR_RCTE_OAM 0x00040000\n-\n-#define TCMDQ_START\t\t0x01000000\n-#define TCMDQ_LACR\t\t0x02000000\n-#define TCMDQ_START_LACR\t0x03000000\n-#define TCMDQ_INIT_ER\t\t0x04000000\n-#define TCMDQ_HALT\t\t0x05000000\n-\n-\n-struct idt77252_skb_prv {\n-\tstruct scqe\ttbd;\t/* Transmit Buffer Descriptor */\n-\tdma_addr_t\tpaddr;\t/* DMA handle */\n-\tu32\t\tpool;\t/* sb_pool handle */\n-} __packed;\n-\n-#define IDT77252_PRV_TBD(skb)\t\\\n-\t(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)\n-#define IDT77252_PRV_PADDR(skb)\t\\\n-\t(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)\n-#define IDT77252_PRV_POOL(skb)\t\\\n-\t(((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)\n-\n-/*****************************************************************************/\n-/* */\n-/* PCI related items */\n-/* */\n-/*****************************************************************************/\n-\n-#ifndef PCI_VENDOR_ID_IDT\n-#define PCI_VENDOR_ID_IDT 0x111D\n-#endif /* PCI_VENDOR_ID_IDT */\n-\n-#ifndef PCI_DEVICE_ID_IDT_IDT77252\n-#define PCI_DEVICE_ID_IDT_IDT77252 0x0003\n-#endif /* PCI_DEVICE_ID_IDT_IDT772052 */\n-\n-\n-#endif /* !(_IDT77252_H) */\ndiff --git a/drivers/atm/idt77252_tables.h b/drivers/atm/idt77252_tables.h\ndeleted file mode 100644\nindex 12b81e046a7b..000000000000\n--- a/drivers/atm/idt77252_tables.h\n+++ /dev/null\n@@ -1,781 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* Do not edit, automatically generated by `./genrtbl'.\n- *\n- * Cell Line Rate: 353207.55 (155520000 bps)\n- */\n-\n-static unsigned int log_to_rate[] =\n-{\n-/* 000 */ 0x8d022e27, /* cps = 10.02, nrm = 3, interval = 35264.00 */\n-/* 001 */ 0x8d362e11, /* cps = 10.42, nrm = 3, interval = 33856.00 */\n-/* 002 */ 0x8d6e2bf8, /* cps = 10.86, nrm = 3, interval = 32512.00 */\n-/* 003 */ 0x8da82bcf, /* cps = 11.31, nrm = 3, interval = 31200.00 */\n-/* 004 */ 0x8de42ba8, /* cps = 11.78, nrm = 3, interval = 29952.00 */\n-/* 005 */ 0x8e242b82, /* cps = 12.28, nrm = 3, interval = 28736.00 */\n-/* 006 */ 0x8e662b5e, /* cps = 12.80, nrm = 3, interval = 27584.00 */\n-/* 007 */ 0x8eaa2b3c, /* cps = 13.33, nrm = 3, interval = 26496.00 */\n-/* 008 */ 0x8ef22b1a, /* cps = 13.89, nrm = 3, interval = 25408.00 */\n-/* 009 */ 0x8f3e2afa, /* cps = 14.48, nrm = 3, interval = 24384.00 */\n-/* 010 */ 0x8f8a2adc, /* cps = 15.08, nrm = 3, interval = 23424.00 */\n-/* 011 */ 0x8fdc2abe, /* cps = 15.72, nrm = 3, interval = 22464.00 */\n-/* 012 */ 0x90182aa2, /* cps = 16.38, nrm = 3, interval = 21568.00 */\n-/* 013 */ 0x90422a87, /* cps = 17.03, nrm = 3, interval = 20704.00 */\n-/* 014 */ 0x90702a6d, /* cps = 17.75, nrm = 3, interval = 19872.00 */\n-/* 015 */ 0x90a02a54, /* cps = 18.50, nrm = 3, interval = 19072.00 */\n-/* 016 */ 0x90d22a3c, /* cps = 19.28, nrm = 3, interval = 18304.00 */\n-/* 017 */ 0x91062a25, /* cps = 20.09, nrm = 3, interval = 17568.00 */\n-/* 018 */ 0x913c2a0f, /* cps = 20.94, nrm = 3, interval = 16864.00 */\n-/* 019 */ 0x917427f3, /* cps = 21.81, nrm = 3, interval = 16176.00 */\n-/* 020 */ 0x91b027ca, /* cps = 22.75, nrm = 3, interval = 15520.00 */\n-/* 021 */ 0x91ec27a3, /* cps = 23.69, nrm = 3, interval = 14896.00 */\n-/* 022 */ 0x922c277e, /* cps = 24.69, nrm = 3, interval = 14304.00 */\n-/* 023 */ 0x926e275a, /* cps = 25.72, nrm = 3, interval = 13728.00 */\n-/* 024 */ 0x92b42737, /* cps = 26.81, nrm = 3, interval = 13168.00 */\n-/* 025 */ 0x92fc2716, /* cps = 27.94, nrm = 3, interval = 12640.00 */\n-/* 026 */ 0x934626f6, /* cps = 29.09, nrm = 3, interval = 12128.00 */\n-/* 027 */ 0x939426d8, /* cps = 30.31, nrm = 3, interval = 11648.00 */\n-/* 028 */ 0x93e426bb, /* cps = 31.56, nrm = 3, interval = 11184.00 */\n-/* 029 */ 0x941e269e, /* cps = 32.94, nrm = 3, interval = 10720.00 */\n-/* 030 */ 0x944a2683, /* cps = 34.31, nrm = 3, interval = 10288.00 */\n-/* 031 */ 0x9476266a, /* cps = 35.69, nrm = 3, interval = 9888.00 */\n-/* 032 */ 0x94a62651, /* cps = 37.19, nrm = 3, interval = 9488.00 */\n-/* 033 */ 0x94d82639, /* cps = 38.75, nrm = 3, interval = 9104.00 */\n-/* 034 */ 0x950c6622, /* cps = 40.38, nrm = 4, interval = 8736.00 */\n-/* 035 */ 0x9544660c, /* cps = 42.12, nrm = 4, interval = 8384.00 */\n-/* 036 */ 0x957c63ee, /* cps = 43.88, nrm = 4, interval = 8048.00 */\n-/* 037 */ 0x95b663c6, /* cps = 45.69, nrm = 4, interval = 7728.00 */\n-/* 038 */ 0x95f4639f, /* cps = 47.62, nrm = 4, interval = 7416.00 */\n-/* 039 */ 0x96346379, /* cps = 49.62, nrm = 4, interval = 7112.00 */\n-/* 040 */ 0x96766356, /* cps = 51.69, nrm = 4, interval = 6832.00 */\n-/* 041 */ 0x96bc6333, /* cps = 53.88, nrm = 4, interval = 6552.00 */\n-/* 042 */ 0x97046312, /* cps = 56.12, nrm = 4, interval = 6288.00 */\n-/* 043 */ 0x974e62f3, /* cps = 58.44, nrm = 4, interval = 6040.00 */\n-/* 044 */ 0x979e62d4, /* cps = 60.94, nrm = 4, interval = 5792.00 */\n-/* 045 */ 0x97f062b7, /* cps = 63.50, nrm = 4, interval = 5560.00 */\n-/* 046 */ 0x9822629b, /* cps = 66.12, nrm = 4, interval = 5336.00 */\n-/* 047 */ 0x984e6280, /* cps = 68.88, nrm = 4, interval = 5120.00 */\n-/* 048 */ 0x987e6266, /* cps = 71.88, nrm = 4, interval = 4912.00 */\n-/* 049 */ 0x98ac624e, /* cps = 74.75, nrm = 4, interval = 4720.00 */\n-/* 050 */ 0x98e06236, /* cps = 78.00, nrm = 4, interval = 4528.00 */\n-/* 051 */ 0x9914a21f, /* cps = 81.25, nrm = 8, interval = 4344.00 */\n-/* 052 */ 0x994aa209, /* cps = 84.62, nrm = 8, interval = 4168.00 */\n-/* 053 */ 0x99829fe9, /* cps = 88.12, nrm = 8, interval = 4004.00 */\n-/* 054 */ 0x99be9fc1, /* cps = 91.88, nrm = 8, interval = 3844.00 */\n-/* 055 */ 0x99fc9f9a, /* cps = 95.75, nrm = 8, interval = 3688.00 */\n-/* 056 */ 0x9a3c9f75, /* cps = 99.75, nrm = 8, interval = 3540.00 */\n-/* 057 */ 0x9a809f51, /* cps = 104.00, nrm = 8, interval = 3396.00 */\n-/* 058 */ 0x9ac49f2f, /* cps = 108.25, nrm = 8, interval = 3260.00 */\n-/* 059 */ 0x9b0e9f0e, /* cps = 112.88, nrm = 8, interval = 3128.00 */\n-/* 060 */ 0x9b589eef, /* cps = 117.50, nrm = 8, interval = 3004.00 */\n-/* 061 */ 0x9ba69ed1, /* cps = 122.38, nrm = 8, interval = 2884.00 */\n-/* 062 */ 0x9bf89eb4, /* cps = 127.50, nrm = 8, interval = 2768.00 */\n-/* 063 */ 0x9c269e98, /* cps = 132.75, nrm = 8, interval = 2656.00 */\n-/* 064 */ 0x9c549e7d, /* cps = 138.50, nrm = 8, interval = 2548.00 */\n-/* 065 */ 0x9c849e63, /* cps = 144.50, nrm = 8, interval = 2444.00 */\n-/* 066 */ 0x9cb29e4b, /* cps = 150.25, nrm = 8, interval = 2348.00 */\n-/* 067 */ 0x9ce69e33, /* cps = 156.75, nrm = 8, interval = 2252.00 */\n-/* 068 */ 0x9d1cde1c, /* cps = 163.50, nrm = 16, interval = 2160.00 */\n-/* 069 */ 0x9d50de07, /* cps = 170.00, nrm = 16, interval = 2076.00 */\n-/* 070 */ 0x9d8adbe4, /* cps = 177.25, nrm = 16, interval = 1992.00 */\n-/* 071 */ 0x9dc4dbbc, /* cps = 184.50, nrm = 16, interval = 1912.00 */\n-/* 072 */ 0x9e02db96, /* cps = 192.25, nrm = 16, interval = 1836.00 */\n-/* 073 */ 0x9e42db71, /* cps = 200.25, nrm = 16, interval = 1762.00 */\n-/* 074 */ 0x9e86db4d, /* cps = 208.75, nrm = 16, interval = 1690.00 */\n-/* 075 */ 0x9ecedb2b, /* cps = 217.75, nrm = 16, interval = 1622.00 */\n-/* 076 */ 0x9f16db0a, /* cps = 226.75, nrm = 16, interval = 1556.00 */\n-/* 077 */ 0x9f62daeb, /* cps = 236.25, nrm = 16, interval = 1494.00 */\n-/* 078 */ 0x9fb2dacd, /* cps = 246.25, nrm = 16, interval = 1434.00 */\n-/* 079 */ 0xa002dab0, /* cps = 256.50, nrm = 16, interval = 1376.00 */\n-/* 080 */ 0xa02eda94, /* cps = 267.50, nrm = 16, interval = 1320.00 */\n-/* 081 */ 0xa05ada7a, /* cps = 278.50, nrm = 16, interval = 1268.00 */\n-/* 082 */ 0xa088da60, /* cps = 290.00, nrm = 16, interval = 1216.00 */\n-/* 083 */ 0xa0b8da48, /* cps = 302.00, nrm = 16, interval = 1168.00 */\n-/* 084 */ 0xa0ecda30, /* cps = 315.00, nrm = 16, interval = 1120.00 */\n-/* 085 */ 0xa1211a1a, /* cps = 328.00, nrm = 32, interval = 1076.00 */\n-/* 086 */ 0xa1591a04, /* cps = 342.00, nrm = 32, interval = 1032.00 */\n-/* 087 */ 0xa19117df, /* cps = 356.00, nrm = 32, interval = 991.00 */\n-/* 088 */ 0xa1cd17b7, /* cps = 371.00, nrm = 32, interval = 951.00 */\n-/* 089 */ 0xa20b1791, /* cps = 386.50, nrm = 32, interval = 913.00 */\n-/* 090 */ 0xa24d176c, /* cps = 403.00, nrm = 32, interval = 876.00 */\n-/* 091 */ 0xa28f1749, /* cps = 419.50, nrm = 32, interval = 841.00 */\n-/* 092 */ 0xa2d71727, /* cps = 437.50, nrm = 32, interval = 807.00 */\n-/* 093 */ 0xa31f1707, /* cps = 455.50, nrm = 32, interval = 775.00 */\n-/* 094 */ 0xa36d16e7, /* cps = 475.00, nrm = 32, interval = 743.00 */\n-/* 095 */ 0xa3bd16c9, /* cps = 495.00, nrm = 32, interval = 713.00 */\n-/* 096 */ 0xa40716ad, /* cps = 515.00, nrm = 32, interval = 685.00 */\n-/* 097 */ 0xa4331691, /* cps = 537.00, nrm = 32, interval = 657.00 */\n-/* 098 */ 0xa45f1677, /* cps = 559.00, nrm = 32, interval = 631.00 */\n-/* 099 */ 0xa48f165d, /* cps = 583.00, nrm = 32, interval = 605.00 */\n-/* 100 */ 0xa4bf1645, /* cps = 607.00, nrm = 32, interval = 581.00 */\n-/* 101 */ 0xa4f1162e, /* cps = 632.00, nrm = 32, interval = 558.00 */\n-/* 102 */ 0xa5291617, /* cps = 660.00, nrm = 32, interval = 535.00 */\n-/* 103 */ 0xa55f1602, /* cps = 687.00, nrm = 32, interval = 514.00 */\n-/* 104 */ 0xa59913da, /* cps = 716.00, nrm = 32, interval = 493.00 */\n-/* 105 */ 0xa5d513b2, /* cps = 746.00, nrm = 32, interval = 473.00 */\n-/* 106 */ 0xa613138c, /* cps = 777.00, nrm = 32, interval = 454.00 */\n-/* 107 */ 0xa6551368, /* cps = 810.00, nrm = 32, interval = 436.00 */\n-/* 108 */ 0xa6971345, /* cps = 843.00, nrm = 32, interval = 418.50 */\n-/* 109 */ 0xa6df1323, /* cps = 879.00, nrm = 32, interval = 401.50 */\n-/* 110 */ 0xa7291303, /* cps = 916.00, nrm = 32, interval = 385.50 */\n-/* 111 */ 0xa77512e4, /* cps = 954.00, nrm = 32, interval = 370.00 */\n-/* 112 */ 0xa7c512c6, /* cps = 994.00, nrm = 32, interval = 355.00 */\n-/* 113 */ 0xa80d12a9, /* cps = 1036.00, nrm = 32, interval = 340.50 */\n-/* 114 */ 0xa839128e, /* cps = 1080.00, nrm = 32, interval = 327.00 */\n-/* 115 */ 0xa8651274, /* cps = 1124.00, nrm = 32, interval = 314.00 */\n-/* 116 */ 0xa895125a, /* cps = 1172.00, nrm = 32, interval = 301.00 */\n-/* 117 */ 0xa8c71242, /* cps = 1222.00, nrm = 32, interval = 289.00 */\n-/* 118 */ 0xa8f9122b, /* cps = 1272.00, nrm = 32, interval = 277.50 */\n-/* 119 */ 0xa92f1214, /* cps = 1326.00, nrm = 32, interval = 266.00 */\n-/* 120 */ 0xa9670ffe, /* cps = 1382.00, nrm = 32, interval = 255.50 */\n-/* 121 */ 0xa9a10fd5, /* cps = 1440.00, nrm = 32, interval = 245.25 */\n-/* 122 */ 0xa9db0fae, /* cps = 1498.00, nrm = 32, interval = 235.50 */\n-/* 123 */ 0xaa1b0f88, /* cps = 1562.00, nrm = 32, interval = 226.00 */\n-/* 124 */ 0xaa5d0f63, /* cps = 1628.00, nrm = 32, interval = 216.75 */\n-/* 125 */ 0xaaa10f41, /* cps = 1696.00, nrm = 32, interval = 208.25 */\n-/* 126 */ 0xaae90f1f, /* cps = 1768.00, nrm = 32, interval = 199.75 */\n-/* 127 */ 0xab330eff, /* cps = 1842.00, nrm = 32, interval = 191.75 */\n-/* 128 */ 0xab7f0ee0, /* cps = 1918.00, nrm = 32, interval = 184.00 */\n-/* 129 */ 0xabd10ec2, /* cps = 2000.00, nrm = 32, interval = 176.50 */\n-/* 130 */ 0xac110ea6, /* cps = 2080.00, nrm = 32, interval = 169.50 */\n-/* 131 */ 0xac3d0e8b, /* cps = 2168.00, nrm = 32, interval = 162.75 */\n-/* 132 */ 0xac6d0e70, /* cps = 2264.00, nrm = 32, interval = 156.00 */\n-/* 133 */ 0xac9b0e57, /* cps = 2356.00, nrm = 32, interval = 149.75 */\n-/* 134 */ 0xaccd0e3f, /* cps = 2456.00, nrm = 32, interval = 143.75 */\n-/* 135 */ 0xacff0e28, /* cps = 2556.00, nrm = 32, interval = 138.00 */\n-/* 136 */ 0xad350e12, /* cps = 2664.00, nrm = 32, interval = 132.50 */\n-/* 137 */ 0xad6d0bf9, /* cps = 2776.00, nrm = 32, interval = 127.12 */\n-/* 138 */ 0xada70bd0, /* cps = 2892.00, nrm = 32, interval = 122.00 */\n-/* 139 */ 0xade30ba9, /* cps = 3012.00, nrm = 32, interval = 117.12 */\n-/* 140 */ 0xae230b83, /* cps = 3140.00, nrm = 32, interval = 112.38 */\n-/* 141 */ 0xae650b5f, /* cps = 3272.00, nrm = 32, interval = 107.88 */\n-/* 142 */ 0xaeab0b3c, /* cps = 3412.00, nrm = 32, interval = 103.50 */\n-/* 143 */ 0xaef10b1b, /* cps = 3552.00, nrm = 32, interval = 99.38 */\n-/* 144 */ 0xaf3b0afb, /* cps = 3700.00, nrm = 32, interval = 95.38 */\n-/* 145 */ 0xaf8b0adc, /* cps = 3860.00, nrm = 32, interval = 91.50 */\n-/* 146 */ 0xafd90abf, /* cps = 4016.00, nrm = 32, interval = 87.88 */\n-/* 147 */ 0xb0170aa3, /* cps = 4184.00, nrm = 32, interval = 84.38 */\n-/* 148 */ 0xb0430a87, /* cps = 4360.00, nrm = 32, interval = 80.88 */\n-/* 149 */ 0xb0710a6d, /* cps = 4544.00, nrm = 32, interval = 77.62 */\n-/* 150 */ 0xb0a10a54, /* cps = 4736.00, nrm = 32, interval = 74.50 */\n-/* 151 */ 0xb0d30a3c, /* cps = 4936.00, nrm = 32, interval = 71.50 */\n-/* 152 */ 0xb1070a25, /* cps = 5144.00, nrm = 32, interval = 68.62 */\n-/* 153 */ 0xb13d0a0f, /* cps = 5360.00, nrm = 32, interval = 65.88 */\n-/* 154 */ 0xb17507f4, /* cps = 5584.00, nrm = 32, interval = 63.25 */\n-/* 155 */ 0xb1af07cb, /* cps = 5816.00, nrm = 32, interval = 60.69 */\n-/* 156 */ 0xb1eb07a4, /* cps = 6056.00, nrm = 32, interval = 58.25 */\n-/* 157 */ 0xb22b077f, /* cps = 6312.00, nrm = 32, interval = 55.94 */\n-/* 158 */ 0xb26d075b, /* cps = 6576.00, nrm = 32, interval = 53.69 */\n-/* 159 */ 0xb2b30738, /* cps = 6856.00, nrm = 32, interval = 51.50 */\n-/* 160 */ 0xb2fb0717, /* cps = 7144.00, nrm = 32, interval = 49.44 */\n-/* 161 */ 0xb34506f7, /* cps = 7440.00, nrm = 32, interval = 47.44 */\n-/* 162 */ 0xb39306d9, /* cps = 7752.00, nrm = 32, interval = 45.56 */\n-/* 163 */ 0xb3e506bb, /* cps = 8080.00, nrm = 32, interval = 43.69 */\n-/* 164 */ 0xb41d069f, /* cps = 8416.00, nrm = 32, interval = 41.94 */\n-/* 165 */ 0xb4490684, /* cps = 8768.00, nrm = 32, interval = 40.25 */\n-/* 166 */ 0xb477066a, /* cps = 9136.00, nrm = 32, interval = 38.62 */\n-/* 167 */ 0xb4a70651, /* cps = 9520.00, nrm = 32, interval = 37.06 */\n-/* 168 */ 0xb4d90639, /* cps = 9920.00, nrm = 32, interval = 35.56 */\n-/* 169 */ 0xb50d0622, /* cps = 10336.00, nrm = 32, interval = 34.12 */\n-/* 170 */ 0xb545060c, /* cps = 10784.00, nrm = 32, interval = 32.75 */\n-/* 171 */ 0xb57b03ef, /* cps = 11216.00, nrm = 32, interval = 31.47 */\n-/* 172 */ 0xb5b503c7, /* cps = 11680.00, nrm = 32, interval = 30.22 */\n-/* 173 */ 0xb5f303a0, /* cps = 12176.00, nrm = 32, interval = 29.00 */\n-/* 174 */ 0xb633037a, /* cps = 12688.00, nrm = 32, interval = 27.81 */\n-/* 175 */ 0xb6750357, /* cps = 13216.00, nrm = 32, interval = 26.72 */\n-/* 176 */ 0xb6bb0334, /* cps = 13776.00, nrm = 32, interval = 25.62 */\n-/* 177 */ 0xb7030313, /* cps = 14352.00, nrm = 32, interval = 24.59 */\n-/* 178 */ 0xb74f02f3, /* cps = 14960.00, nrm = 32, interval = 23.59 */\n-/* 179 */ 0xb79d02d5, /* cps = 15584.00, nrm = 32, interval = 22.66 */\n-/* 180 */ 0xb7ed02b8, /* cps = 16224.00, nrm = 32, interval = 21.75 */\n-/* 181 */ 0xb821029c, /* cps = 16896.00, nrm = 32, interval = 20.88 */\n-/* 182 */ 0xb84f0281, /* cps = 17632.00, nrm = 32, interval = 20.03 */\n-/* 183 */ 0xb87d0267, /* cps = 18368.00, nrm = 32, interval = 19.22 */\n-/* 184 */ 0xb8ad024e, /* cps = 19136.00, nrm = 32, interval = 18.44 */\n-/* 185 */ 0xb8dd0237, /* cps = 19904.00, nrm = 32, interval = 17.72 */\n-/* 186 */ 0xb9130220, /* cps = 20768.00, nrm = 32, interval = 17.00 */\n-/* 187 */ 0xb949020a, /* cps = 21632.00, nrm = 32, interval = 16.31 */\n-/* 188 */ 0xb98301f5, /* cps = 22560.00, nrm = 32, interval = 15.66 */\n-/* 189 */ 0xb9bd01e1, /* cps = 23488.00, nrm = 32, interval = 15.03 */\n-/* 190 */ 0xb9fd01cd, /* cps = 24512.00, nrm = 32, interval = 14.41 */\n-/* 191 */ 0xba3b01bb, /* cps = 25504.00, nrm = 32, interval = 13.84 */\n-/* 192 */ 0xba7f01a9, /* cps = 26592.00, nrm = 32, interval = 13.28 */\n-/* 193 */ 0xbac30198, /* cps = 27680.00, nrm = 32, interval = 12.75 */\n-/* 194 */ 0xbb0f0187, /* cps = 28896.00, nrm = 32, interval = 12.22 */\n-/* 195 */ 0xbb570178, /* cps = 30048.00, nrm = 32, interval = 11.75 */\n-/* 196 */ 0xbbab0168, /* cps = 31392.00, nrm = 32, interval = 11.25 */\n-/* 197 */ 0xbbf9015a, /* cps = 32640.00, nrm = 32, interval = 10.81 */\n-/* 198 */ 0xbc27014c, /* cps = 33984.00, nrm = 32, interval = 10.38 */\n-/* 199 */ 0xbc53013f, /* cps = 35392.00, nrm = 32, interval = 9.97 */\n-/* 200 */ 0xbc830132, /* cps = 36928.00, nrm = 32, interval = 9.56 */\n-/* 201 */ 0xbcb50125, /* cps = 38528.00, nrm = 32, interval = 9.16 */\n-/* 202 */ 0xbce5011a, /* cps = 40064.00, nrm = 32, interval = 8.81 */\n-/* 203 */ 0xbd1d010e, /* cps = 41856.00, nrm = 32, interval = 8.44 */\n-/* 204 */ 0xbd530103, /* cps = 43584.00, nrm = 32, interval = 8.09 */\n-/* 205 */ 0xbd8b00f9, /* cps = 45376.00, nrm = 32, interval = 7.78 */\n-/* 206 */ 0xbdc500ef, /* cps = 47232.00, nrm = 32, interval = 7.47 */\n-/* 207 */ 0xbe0700e5, /* cps = 49344.00, nrm = 32, interval = 7.16 */\n-/* 208 */ 0xbe4500dc, /* cps = 51328.00, nrm = 32, interval = 6.88 */\n-/* 209 */ 0xbe8900d3, /* cps = 53504.00, nrm = 32, interval = 6.59 */\n-/* 210 */ 0xbecb00cb, /* cps = 55616.00, nrm = 32, interval = 6.34 */\n-/* 211 */ 0xbf1d00c2, /* cps = 58240.00, nrm = 32, interval = 6.06 */\n-/* 212 */ 0xbf6100bb, /* cps = 60416.00, nrm = 32, interval = 5.84 */\n-/* 213 */ 0xbfb500b3, /* cps = 63104.00, nrm = 32, interval = 5.59 */\n-/* 214 */ 0xc00300ac, /* cps = 65664.00, nrm = 32, interval = 5.38 */\n-/* 215 */ 0xc02f00a5, /* cps = 68480.00, nrm = 32, interval = 5.16 */\n-/* 216 */ 0xc05d009e, /* cps = 71424.00, nrm = 32, interval = 4.94 */\n-/* 217 */ 0xc0890098, /* cps = 74240.00, nrm = 32, interval = 4.75 */\n-/* 218 */ 0xc0b90092, /* cps = 77312.00, nrm = 32, interval = 4.56 */\n-/* 219 */ 0xc0ed008c, /* cps = 80640.00, nrm = 32, interval = 4.38 */\n-/* 220 */ 0xc1250086, /* cps = 84224.00, nrm = 32, interval = 4.19 */\n-/* 221 */ 0xc1590081, /* cps = 87552.00, nrm = 32, interval = 4.03 */\n-/* 222 */ 0xc191007c, /* cps = 91136.00, nrm = 32, interval = 3.88 */\n-/* 223 */ 0xc1cd0077, /* cps = 94976.00, nrm = 32, interval = 3.72 */\n-/* 224 */ 0xc20d0072, /* cps = 99072.00, nrm = 32, interval = 3.56 */\n-/* 225 */ 0xc255006d, /* cps = 103680.00, nrm = 32, interval = 3.41 */\n-/* 226 */ 0xc2910069, /* cps = 107520.00, nrm = 32, interval = 3.28 */\n-/* 227 */ 0xc2d50065, /* cps = 111872.00, nrm = 32, interval = 3.16 */\n-/* 228 */ 0xc32f0060, /* cps = 117632.00, nrm = 32, interval = 3.00 */\n-/* 229 */ 0xc36b005d, /* cps = 121472.00, nrm = 32, interval = 2.91 */\n-/* 230 */ 0xc3c10059, /* cps = 126976.00, nrm = 32, interval = 2.78 */\n-/* 231 */ 0xc40f0055, /* cps = 132864.00, nrm = 32, interval = 2.66 */\n-/* 232 */ 0xc4350052, /* cps = 137728.00, nrm = 32, interval = 2.56 */\n-/* 233 */ 0xc46d004e, /* cps = 144896.00, nrm = 32, interval = 2.44 */\n-/* 234 */ 0xc499004b, /* cps = 150528.00, nrm = 32, interval = 2.34 */\n-/* 235 */ 0xc4cb0048, /* cps = 156928.00, nrm = 32, interval = 2.25 */\n-/* 236 */ 0xc4ff0045, /* cps = 163584.00, nrm = 32, interval = 2.16 */\n-/* 237 */ 0xc5250043, /* cps = 168448.00, nrm = 32, interval = 2.09 */\n-/* 238 */ 0xc5630040, /* cps = 176384.00, nrm = 32, interval = 2.00 */\n-/* 239 */ 0xc5a7003d, /* cps = 185088.00, nrm = 32, interval = 1.91 */\n-/* 240 */ 0xc5d9003b, /* cps = 191488.00, nrm = 32, interval = 1.84 */\n-/* 241 */ 0xc6290038, /* cps = 201728.00, nrm = 32, interval = 1.75 */\n-/* 242 */ 0xc6630036, /* cps = 209152.00, nrm = 32, interval = 1.69 */\n-/* 243 */ 0xc6a30034, /* cps = 217344.00, nrm = 32, interval = 1.62 */\n-/* 244 */ 0xc6e70032, /* cps = 226048.00, nrm = 32, interval = 1.56 */\n-/* 245 */ 0xc72f0030, /* cps = 235264.00, nrm = 32, interval = 1.50 */\n-/* 246 */ 0xc77f002e, /* cps = 245504.00, nrm = 32, interval = 1.44 */\n-/* 247 */ 0xc7d7002c, /* cps = 256768.00, nrm = 32, interval = 1.38 */\n-/* 248 */ 0xc81b002a, /* cps = 268800.00, nrm = 32, interval = 1.31 */\n-/* 249 */ 0xc84f0028, /* cps = 282112.00, nrm = 32, interval = 1.25 */\n-/* 250 */ 0xc86d0027, /* cps = 289792.00, nrm = 32, interval = 1.22 */\n-/* 251 */ 0xc8a90025, /* cps = 305152.00, nrm = 32, interval = 1.16 */\n-/* 252 */ 0xc8cb0024, /* cps = 313856.00, nrm = 32, interval = 1.12 */\n-/* 253 */ 0xc9130022, /* cps = 332288.00, nrm = 32, interval = 1.06 */\n-/* 254 */ 0xc9390021, /* cps = 342016.00, nrm = 32, interval = 1.03 */\n-/* 255 */ 0xc9630020, /* cps = 352768.00, nrm = 32, interval = 1.00 */\n-};\n-\n-static unsigned char rate_to_log[] =\n-{\n-/* 1.00 => 0 */ 0x00, /* => 10.02 */\n-/* 1.06 => 0 */ 0x00, /* => 10.02 */\n-/* 1.12 => 0 */ 0x00, /* => 10.02 */\n-/* 1.19 => 0 */ 0x00, /* => 10.02 */\n-/* 1.25 => 0 */ 0x00, /* => 10.02 */\n-/* 1.31 => 0 */ 0x00, /* => 10.02 */\n-/* 1.38 => 0 */ 0x00, /* => 10.02 */\n-/* 1.44 => 0 */ 0x00, /* => 10.02 */\n-/* 1.50 => 0 */ 0x00, /* => 10.02 */\n-/* 1.56 => 0 */ 0x00, /* => 10.02 */\n-/* 1.62 => 0 */ 0x00, /* => 10.02 */\n-/* 1.69 => 0 */ 0x00, /* => 10.02 */\n-/* 1.75 => 0 */ 0x00, /* => 10.02 */\n-/* 1.81 => 0 */ 0x00, /* => 10.02 */\n-/* 1.88 => 0 */ 0x00, /* => 10.02 */\n-/* 1.94 => 0 */ 0x00, /* => 10.02 */\n-/* 2.00 => 0 */ 0x00, /* => 10.02 */\n-/* 2.12 => 0 */ 0x00, /* => 10.02 */\n-/* 2.25 => 0 */ 0x00, /* => 10.02 */\n-/* 2.38 => 0 */ 0x00, /* => 10.02 */\n-/* 2.50 => 0 */ 0x00, /* => 10.02 */\n-/* 2.62 => 0 */ 0x00, /* => 10.02 */\n-/* 2.75 => 0 */ 0x00, /* => 10.02 */\n-/* 2.88 => 0 */ 0x00, /* => 10.02 */\n-/* 3.00 => 0 */ 0x00, /* => 10.02 */\n-/* 3.12 => 0 */ 0x00, /* => 10.02 */\n-/* 3.25 => 0 */ 0x00, /* => 10.02 */\n-/* 3.38 => 0 */ 0x00, /* => 10.02 */\n-/* 3.50 => 0 */ 0x00, /* => 10.02 */\n-/* 3.62 => 0 */ 0x00, /* => 10.02 */\n-/* 3.75 => 0 */ 0x00, /* => 10.02 */\n-/* 3.88 => 0 */ 0x00, /* => 10.02 */\n-/* 4.00 => 0 */ 0x00, /* => 10.02 */\n-/* 4.25 => 0 */ 0x00, /* => 10.02 */\n-/* 4.50 => 0 */ 0x00, /* => 10.02 */\n-/* 4.75 => 0 */ 0x00, /* => 10.02 */\n-/* 5.00 => 0 */ 0x00, /* => 10.02 */\n-/* 5.25 => 0 */ 0x00, /* => 10.02 */\n-/* 5.50 => 0 */ 0x00, /* => 10.02 */\n-/* 5.75 => 0 */ 0x00, /* => 10.02 */\n-/* 6.00 => 0 */ 0x00, /* => 10.02 */\n-/* 6.25 => 0 */ 0x00, /* => 10.02 */\n-/* 6.50 => 0 */ 0x00, /* => 10.02 */\n-/* 6.75 => 0 */ 0x00, /* => 10.02 */\n-/* 7.00 => 0 */ 0x00, /* => 10.02 */\n-/* 7.25 => 0 */ 0x00, /* => 10.02 */\n-/* 7.50 => 0 */ 0x00, /* => 10.02 */\n-/* 7.75 => 0 */ 0x00, /* => 10.02 */\n-/* 8.00 => 0 */ 0x00, /* => 10.02 */\n-/* 8.50 => 0 */ 0x00, /* => 10.02 */\n-/* 9.00 => 0 */ 0x00, /* => 10.02 */\n-/* 9.50 => 0 */ 0x00, /* => 10.02 */\n-/* 10.00 => 0 */ 0x00, /* => 10.02 */\n-/* 10.50 => 1 */ 0x01, /* => 10.42 */\n-/* 11.00 => 2 */ 0x02, /* => 10.86 */\n-/* 11.50 => 3 */ 0x03, /* => 11.31 */\n-/* 12.00 => 4 */ 0x04, /* => 11.78 */\n-/* 12.50 => 5 */ 0x05, /* => 12.28 */\n-/* 13.00 => 6 */ 0x06, /* => 12.80 */\n-/* 13.50 => 7 */ 0x07, /* => 13.33 */\n-/* 14.00 => 8 */ 0x08, /* => 13.89 */\n-/* 14.50 => 9 */ 0x09, /* => 14.48 */\n-/* 15.00 => 9 */ 0x09, /* => 14.48 */\n-/* 15.50 => 10 */ 0x0a, /* => 15.08 */\n-/* 16.00 => 11 */ 0x0b, /* => 15.72 */\n-/* 17.00 => 12 */ 0x0c, /* => 16.38 */\n-/* 18.00 => 14 */ 0x0e, /* => 17.75 */\n-/* 19.00 => 15 */ 0x0f, /* => 18.50 */\n-/* 20.00 => 16 */ 0x10, /* => 19.28 */\n-/* 21.00 => 18 */ 0x12, /* => 20.94 */\n-/* 22.00 => 19 */ 0x13, /* => 21.81 */\n-/* 23.00 => 20 */ 0x14, /* => 22.75 */\n-/* 24.00 => 21 */ 0x15, /* => 23.69 */\n-/* 25.00 => 22 */ 0x16, /* => 24.69 */\n-/* 26.00 => 23 */ 0x17, /* => 25.72 */\n-/* 27.00 => 24 */ 0x18, /* => 26.81 */\n-/* 28.00 => 25 */ 0x19, /* => 27.94 */\n-/* 29.00 => 25 */ 0x19, /* => 27.94 */\n-/* 30.00 => 26 */ 0x1a, /* => 29.09 */\n-/* 31.00 => 27 */ 0x1b, /* => 30.31 */\n-/* 32.00 => 28 */ 0x1c, /* => 31.56 */\n-/* 34.00 => 29 */ 0x1d, /* => 32.94 */\n-/* 36.00 => 31 */ 0x1f, /* => 35.69 */\n-/* 38.00 => 32 */ 0x20, /* => 37.19 */\n-/* 40.00 => 33 */ 0x21, /* => 38.75 */\n-/* 42.00 => 34 */ 0x22, /* => 40.38 */\n-/* 44.00 => 36 */ 0x24, /* => 43.88 */\n-/* 46.00 => 37 */ 0x25, /* => 45.69 */\n-/* 48.00 => 38 */ 0x26, /* => 47.62 */\n-/* 50.00 => 39 */ 0x27, /* => 49.62 */\n-/* 52.00 => 40 */ 0x28, /* => 51.69 */\n-/* 54.00 => 41 */ 0x29, /* => 53.88 */\n-/* 56.00 => 41 */ 0x29, /* => 53.88 */\n-/* 58.00 => 42 */ 0x2a, /* => 56.12 */\n-/* 60.00 => 43 */ 0x2b, /* => 58.44 */\n-/* 62.00 => 44 */ 0x2c, /* => 60.94 */\n-/* 64.00 => 45 */ 0x2d, /* => 63.50 */\n-/* 68.00 => 46 */ 0x2e, /* => 66.12 */\n-/* 72.00 => 48 */ 0x30, /* => 71.88 */\n-/* 76.00 => 49 */ 0x31, /* => 74.75 */\n-/* 80.00 => 50 */ 0x32, /* => 78.00 */\n-/* 84.00 => 51 */ 0x33, /* => 81.25 */\n-/* 88.00 => 52 */ 0x34, /* => 84.62 */\n-/* 92.00 => 54 */ 0x36, /* => 91.88 */\n-/* 96.00 => 55 */ 0x37, /* => 95.75 */\n-/* 100.00 => 56 */ 0x38, /* => 99.75 */\n-/* 104.00 => 56 */ 0x38, /* => 99.75 */\n-/* 108.00 => 57 */ 0x39, /* => 104.00 */\n-/* 112.00 => 58 */ 0x3a, /* => 108.25 */\n-/* 116.00 => 59 */ 0x3b, /* => 112.88 */\n-/* 120.00 => 60 */ 0x3c, /* => 117.50 */\n-/* 124.00 => 61 */ 0x3d, /* => 122.38 */\n-/* 128.00 => 62 */ 0x3e, /* => 127.50 */\n-/* 136.00 => 63 */ 0x3f, /* => 132.75 */\n-/* 144.00 => 64 */ 0x40, /* => 138.50 */\n-/* 152.00 => 66 */ 0x42, /* => 150.25 */\n-/* 160.00 => 67 */ 0x43, /* => 156.75 */\n-/* 168.00 => 68 */ 0x44, /* => 163.50 */\n-/* 176.00 => 69 */ 0x45, /* => 170.00 */\n-/* 184.00 => 70 */ 0x46, /* => 177.25 */\n-/* 192.00 => 71 */ 0x47, /* => 184.50 */\n-/* 200.00 => 72 */ 0x48, /* => 192.25 */\n-/* 208.00 => 73 */ 0x49, /* => 200.25 */\n-/* 216.00 => 74 */ 0x4a, /* => 208.75 */\n-/* 224.00 => 75 */ 0x4b, /* => 217.75 */\n-/* 232.00 => 76 */ 0x4c, /* => 226.75 */\n-/* 240.00 => 77 */ 0x4d, /* => 236.25 */\n-/* 248.00 => 78 */ 0x4e, /* => 246.25 */\n-/* 256.00 => 78 */ 0x4e, /* => 246.25 */\n-/* 272.00 => 80 */ 0x50, /* => 267.50 */\n-/* 288.00 => 81 */ 0x51, /* => 278.50 */\n-/* 304.00 => 83 */ 0x53, /* => 302.00 */\n-/* 320.00 => 84 */ 0x54, /* => 315.00 */\n-/* 336.00 => 85 */ 0x55, /* => 328.00 */\n-/* 352.00 => 86 */ 0x56, /* => 342.00 */\n-/* 368.00 => 87 */ 0x57, /* => 356.00 */\n-/* 384.00 => 88 */ 0x58, /* => 371.00 */\n-/* 400.00 => 89 */ 0x59, /* => 386.50 */\n-/* 416.00 => 90 */ 0x5a, /* => 403.00 */\n-/* 432.00 => 91 */ 0x5b, /* => 419.50 */\n-/* 448.00 => 92 */ 0x5c, /* => 437.50 */\n-/* 464.00 => 93 */ 0x5d, /* => 455.50 */\n-/* 480.00 => 94 */ 0x5e, /* => 475.00 */\n-/* 496.00 => 95 */ 0x5f, /* => 495.00 */\n-/* 512.00 => 95 */ 0x5f, /* => 495.00 */\n-/* 544.00 => 97 */ 0x61, /* => 537.00 */\n-/* 576.00 => 98 */ 0x62, /* => 559.00 */\n-/* 608.00 => 100 */ 0x64, /* => 607.00 */\n-/* 640.00 => 101 */ 0x65, /* => 632.00 */\n-/* 672.00 => 102 */ 0x66, /* => 660.00 */\n-/* 704.00 => 103 */ 0x67, /* => 687.00 */\n-/* 736.00 => 104 */ 0x68, /* => 716.00 */\n-/* 768.00 => 105 */ 0x69, /* => 746.00 */\n-/* 800.00 => 106 */ 0x6a, /* => 777.00 */\n-/* 832.00 => 107 */ 0x6b, /* => 810.00 */\n-/* 864.00 => 108 */ 0x6c, /* => 843.00 */\n-/* 896.00 => 109 */ 0x6d, /* => 879.00 */\n-/* 928.00 => 110 */ 0x6e, /* => 916.00 */\n-/* 960.00 => 111 */ 0x6f, /* => 954.00 */\n-/* 992.00 => 111 */ 0x6f, /* => 954.00 */\n-/* 1024.00 => 112 */ 0x70, /* => 994.00 */\n-/* 1088.00 => 114 */ 0x72, /* => 1080.00 */\n-/* 1152.00 => 115 */ 0x73, /* => 1124.00 */\n-/* 1216.00 => 116 */ 0x74, /* => 1172.00 */\n-/* 1280.00 => 118 */ 0x76, /* => 1272.00 */\n-/* 1344.00 => 119 */ 0x77, /* => 1326.00 */\n-/* 1408.00 => 120 */ 0x78, /* => 1382.00 */\n-/* 1472.00 => 121 */ 0x79, /* => 1440.00 */\n-/* 1536.00 => 122 */ 0x7a, /* => 1498.00 */\n-/* 1600.00 => 123 */ 0x7b, /* => 1562.00 */\n-/* 1664.00 => 124 */ 0x7c, /* => 1628.00 */\n-/* 1728.00 => 125 */ 0x7d, /* => 1696.00 */\n-/* 1792.00 => 126 */ 0x7e, /* => 1768.00 */\n-/* 1856.00 => 127 */ 0x7f, /* => 1842.00 */\n-/* 1920.00 => 128 */ 0x80, /* => 1918.00 */\n-/* 1984.00 => 128 */ 0x80, /* => 1918.00 */\n-/* 2048.00 => 129 */ 0x81, /* => 2000.00 */\n-/* 2176.00 => 131 */ 0x83, /* => 2168.00 */\n-/* 2304.00 => 132 */ 0x84, /* => 2264.00 */\n-/* 2432.00 => 133 */ 0x85, /* => 2356.00 */\n-/* 2560.00 => 135 */ 0x87, /* => 2556.00 */\n-/* 2688.00 => 136 */ 0x88, /* => 2664.00 */\n-/* 2816.00 => 137 */ 0x89, /* => 2776.00 */\n-/* 2944.00 => 138 */ 0x8a, /* => 2892.00 */\n-/* 3072.00 => 139 */ 0x8b, /* => 3012.00 */\n-/* 3200.00 => 140 */ 0x8c, /* => 3140.00 */\n-/* 3328.00 => 141 */ 0x8d, /* => 3272.00 */\n-/* 3456.00 => 142 */ 0x8e, /* => 3412.00 */\n-/* 3584.00 => 143 */ 0x8f, /* => 3552.00 */\n-/* 3712.00 => 144 */ 0x90, /* => 3700.00 */\n-/* 3840.00 => 144 */ 0x90, /* => 3700.00 */\n-/* 3968.00 => 145 */ 0x91, /* => 3860.00 */\n-/* 4096.00 => 146 */ 0x92, /* => 4016.00 */\n-/* 4352.00 => 147 */ 0x93, /* => 4184.00 */\n-/* 4608.00 => 149 */ 0x95, /* => 4544.00 */\n-/* 4864.00 => 150 */ 0x96, /* => 4736.00 */\n-/* 5120.00 => 151 */ 0x97, /* => 4936.00 */\n-/* 5376.00 => 153 */ 0x99, /* => 5360.00 */\n-/* 5632.00 => 154 */ 0x9a, /* => 5584.00 */\n-/* 5888.00 => 155 */ 0x9b, /* => 5816.00 */\n-/* 6144.00 => 156 */ 0x9c, /* => 6056.00 */\n-/* 6400.00 => 157 */ 0x9d, /* => 6312.00 */\n-/* 6656.00 => 158 */ 0x9e, /* => 6576.00 */\n-/* 6912.00 => 159 */ 0x9f, /* => 6856.00 */\n-/* 7168.00 => 160 */ 0xa0, /* => 7144.00 */\n-/* 7424.00 => 160 */ 0xa0, /* => 7144.00 */\n-/* 7680.00 => 161 */ 0xa1, /* => 7440.00 */\n-/* 7936.00 => 162 */ 0xa2, /* => 7752.00 */\n-/* 8192.00 => 163 */ 0xa3, /* => 8080.00 */\n-/* 8704.00 => 164 */ 0xa4, /* => 8416.00 */\n-/* 9216.00 => 166 */ 0xa6, /* => 9136.00 */\n-/* 9728.00 => 167 */ 0xa7, /* => 9520.00 */\n-/* 10240.00 => 168 */ 0xa8, /* => 9920.00 */\n-/* 10752.00 => 169 */ 0xa9, /* => 10336.00 */\n-/* 11264.00 => 171 */ 0xab, /* => 11216.00 */\n-/* 11776.00 => 172 */ 0xac, /* => 11680.00 */\n-/* 12288.00 => 173 */ 0xad, /* => 12176.00 */\n-/* 12800.00 => 174 */ 0xae, /* => 12688.00 */\n-/* 13312.00 => 175 */ 0xaf, /* => 13216.00 */\n-/* 13824.00 => 176 */ 0xb0, /* => 13776.00 */\n-/* 14336.00 => 176 */ 0xb0, /* => 13776.00 */\n-/* 14848.00 => 177 */ 0xb1, /* => 14352.00 */\n-/* 15360.00 => 178 */ 0xb2, /* => 14960.00 */\n-/* 15872.00 => 179 */ 0xb3, /* => 15584.00 */\n-/* 16384.00 => 180 */ 0xb4, /* => 16224.00 */\n-/* 17408.00 => 181 */ 0xb5, /* => 16896.00 */\n-/* 18432.00 => 183 */ 0xb7, /* => 18368.00 */\n-/* 19456.00 => 184 */ 0xb8, /* => 19136.00 */\n-/* 20480.00 => 185 */ 0xb9, /* => 19904.00 */\n-/* 21504.00 => 186 */ 0xba, /* => 20768.00 */\n-/* 22528.00 => 187 */ 0xbb, /* => 21632.00 */\n-/* 23552.00 => 189 */ 0xbd, /* => 23488.00 */\n-/* 24576.00 => 190 */ 0xbe, /* => 24512.00 */\n-/* 25600.00 => 191 */ 0xbf, /* => 25504.00 */\n-/* 26624.00 => 192 */ 0xc0, /* => 26592.00 */\n-/* 27648.00 => 192 */ 0xc0, /* => 26592.00 */\n-/* 28672.00 => 193 */ 0xc1, /* => 27680.00 */\n-/* 29696.00 => 194 */ 0xc2, /* => 28896.00 */\n-/* 30720.00 => 195 */ 0xc3, /* => 30048.00 */\n-/* 31744.00 => 196 */ 0xc4, /* => 31392.00 */\n-/* 32768.00 => 197 */ 0xc5, /* => 32640.00 */\n-/* 34816.00 => 198 */ 0xc6, /* => 33984.00 */\n-/* 36864.00 => 199 */ 0xc7, /* => 35392.00 */\n-/* 38912.00 => 201 */ 0xc9, /* => 38528.00 */\n-/* 40960.00 => 202 */ 0xca, /* => 40064.00 */\n-/* 43008.00 => 203 */ 0xcb, /* => 41856.00 */\n-/* 45056.00 => 204 */ 0xcc, /* => 43584.00 */\n-/* 47104.00 => 205 */ 0xcd, /* => 45376.00 */\n-/* 49152.00 => 206 */ 0xce, /* => 47232.00 */\n-/* 51200.00 => 207 */ 0xcf, /* => 49344.00 */\n-/* 53248.00 => 208 */ 0xd0, /* => 51328.00 */\n-/* 55296.00 => 209 */ 0xd1, /* => 53504.00 */\n-/* 57344.00 => 210 */ 0xd2, /* => 55616.00 */\n-/* 59392.00 => 211 */ 0xd3, /* => 58240.00 */\n-/* 61440.00 => 212 */ 0xd4, /* => 60416.00 */\n-/* 63488.00 => 213 */ 0xd5, /* => 63104.00 */\n-/* 65536.00 => 213 */ 0xd5, /* => 63104.00 */\n-/* 69632.00 => 215 */ 0xd7, /* => 68480.00 */\n-/* 73728.00 => 216 */ 0xd8, /* => 71424.00 */\n-/* 77824.00 => 218 */ 0xda, /* => 77312.00 */\n-/* 81920.00 => 219 */ 0xdb, /* => 80640.00 */\n-/* 86016.00 => 220 */ 0xdc, /* => 84224.00 */\n-/* 90112.00 => 221 */ 0xdd, /* => 87552.00 */\n-/* 94208.00 => 222 */ 0xde, /* => 91136.00 */\n-/* 98304.00 => 223 */ 0xdf, /* => 94976.00 */\n-/* 102400.00 => 224 */ 0xe0, /* => 99072.00 */\n-/* 106496.00 => 225 */ 0xe1, /* => 103680.00 */\n-/* 110592.00 => 226 */ 0xe2, /* => 107520.00 */\n-/* 114688.00 => 227 */ 0xe3, /* => 111872.00 */\n-/* 118784.00 => 228 */ 0xe4, /* => 117632.00 */\n-/* 122880.00 => 229 */ 0xe5, /* => 121472.00 */\n-/* 126976.00 => 229 */ 0xe5, /* => 121472.00 */\n-/* 131072.00 => 230 */ 0xe6, /* => 126976.00 */\n-/* 139264.00 => 232 */ 0xe8, /* => 137728.00 */\n-/* 147456.00 => 233 */ 0xe9, /* => 144896.00 */\n-/* 155648.00 => 234 */ 0xea, /* => 150528.00 */\n-/* 163840.00 => 236 */ 0xec, /* => 163584.00 */\n-/* 172032.00 => 237 */ 0xed, /* => 168448.00 */\n-/* 180224.00 => 238 */ 0xee, /* => 176384.00 */\n-/* 188416.00 => 239 */ 0xef, /* => 185088.00 */\n-/* 196608.00 => 240 */ 0xf0, /* => 191488.00 */\n-/* 204800.00 => 241 */ 0xf1, /* => 201728.00 */\n-/* 212992.00 => 242 */ 0xf2, /* => 209152.00 */\n-/* 221184.00 => 243 */ 0xf3, /* => 217344.00 */\n-/* 229376.00 => 244 */ 0xf4, /* => 226048.00 */\n-/* 237568.00 => 245 */ 0xf5, /* => 235264.00 */\n-/* 245760.00 => 246 */ 0xf6, /* => 245504.00 */\n-/* 253952.00 => 246 */ 0xf6, /* => 245504.00 */\n-/* 262144.00 => 247 */ 0xf7, /* => 256768.00 */\n-/* 278528.00 => 248 */ 0xf8, /* => 268800.00 */\n-/* 294912.00 => 250 */ 0xfa, /* => 289792.00 */\n-/* 311296.00 => 251 */ 0xfb, /* => 305152.00 */\n-/* 327680.00 => 252 */ 0xfc, /* => 313856.00 */\n-/* 344064.00 => 254 */ 0xfe, /* => 342016.00 */\n-/* 360448.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 376832.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 393216.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 409600.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 425984.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 442368.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 458752.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 475136.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 491520.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 507904.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 524288.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 557056.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 589824.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 622592.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 655360.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 688128.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 720896.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 753664.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 786432.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 819200.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 851968.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 884736.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 917504.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 950272.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 983040.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1015808.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1048576.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1114112.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1179648.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1245184.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1310720.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1376256.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1441792.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1507328.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1572864.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1638400.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1703936.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1769472.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1835008.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1900544.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1966080.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2031616.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2097152.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2228224.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2359296.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2490368.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2621440.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2752512.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2883584.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3014656.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3145728.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3276800.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3407872.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3538944.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3670016.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3801088.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3932160.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4063232.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4194304.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4456448.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4718592.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4980736.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 5242880.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 5505024.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 5767168.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 6029312.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 6291456.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 6553600.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 6815744.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 7077888.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 7340032.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 7602176.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 7864320.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 8126464.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 8388608.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 8912896.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 9437184.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 9961472.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 10485760.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 11010048.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 11534336.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 12058624.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 12582912.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 13107200.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 13631488.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 14155776.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 14680064.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 15204352.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 15728640.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 16252928.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 16777216.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 17825792.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 18874368.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 19922944.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 20971520.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 22020096.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 23068672.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 24117248.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 25165824.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 26214400.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 27262976.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 28311552.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 29360128.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 30408704.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 31457280.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 32505856.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 33554432.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 35651584.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 37748736.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 39845888.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 41943040.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 44040192.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 46137344.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 48234496.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 50331648.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 52428800.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 54525952.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 56623104.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 58720256.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 60817408.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 62914560.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 65011712.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 67108864.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 71303168.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 75497472.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 79691776.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 83886080.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 88080384.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 92274688.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 96468992.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 100663296.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 104857600.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 109051904.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 113246208.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 117440512.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 121634816.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 125829120.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 130023424.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 134217728.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 142606336.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 150994944.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 159383552.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 167772160.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 176160768.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 184549376.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 192937984.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 201326592.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 209715200.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 218103808.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 226492416.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 234881024.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 243269632.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 251658240.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 260046848.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 268435456.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 285212672.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 301989888.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 318767104.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 335544320.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 352321536.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 369098752.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 385875968.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 402653184.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 419430400.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 436207616.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 452984832.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 469762048.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 486539264.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 503316480.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 520093696.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 536870912.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 570425344.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 603979776.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 637534208.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 671088640.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 704643072.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 738197504.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 771751936.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 805306368.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 838860800.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 872415232.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 905969664.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 939524096.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 973078528.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1006632960.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1040187392.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1073741824.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1140850688.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1207959552.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1275068416.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1342177280.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1409286144.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1476395008.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1543503872.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1610612736.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1677721600.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1744830464.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1811939328.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1879048192.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 1946157056.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2013265920.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2080374784.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2147483648.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2281701376.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2415919104.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2550136832.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2684354560.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2818572288.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 2952790016.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3087007744.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3221225472.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3355443200.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3489660928.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3623878656.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3758096384.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 3892314112.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4026531840.00 => 255 */ 0xff, /* => 352768.00 */\n-/* 4160749568.00 => 255 */ 0xff, /* => 352768.00 */\n-};\ndiff --git a/drivers/atm/iphase.h b/drivers/atm/iphase.h\ndeleted file mode 100644\nindex 2f5f8875cbd1..000000000000\n--- a/drivers/atm/iphase.h\n+++ /dev/null\n@@ -1,1452 +0,0 @@\n-/******************************************************************************\n- Device driver for Interphase ATM PCI adapter cards \n- Author: Peter Wang \n- Interphase Corporation \n- Version: 1.0 \n- iphase.h: This is the header file for iphase.c. \n-*******************************************************************************\n- \n- This software may be used and distributed according to the terms\n- of the GNU General Public License (GPL), incorporated herein by reference.\n- Drivers based on this skeleton fall under the GPL and must retain\n- the authorship (implicit copyright) notice.\n-\n- This program is distributed in the hope that it will be useful, but\n- WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n- General Public License for more details.\n- \n- Modified from an incomplete driver for Interphase 5575 1KVC 1M card which \n- was originally written by Monalisa Agrawal at UNH. Now this driver \n- supports a variety of varients of Interphase ATM PCI (i)Chip adapter \n- card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM) \n- in terms of PHY type, the size of control memory and the size of \n- packet memory. The following are the change log and history:\n- \n- Bugfix the Mona's UBR driver.\n- Modify the basic memory allocation and dma logic.\n- Port the driver to the latest kernel from 2.0.46.\n- Complete the ABR logic of the driver, and added the ABR work-\n- around for the hardware anormalies.\n- Add the CBR support.\n-\t Add the flow control logic to the driver to allow rate-limit VC.\n- Add 4K VC support to the board with 512K control memory.\n- Add the support of all the variants of the Interphase ATM PCI \n- (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525\n- (25M UTP25) and x531 (DS3 and E3).\n- Add SMP support.\n-\n- Support and updates available at: ftp://ftp.iphase.com/pub/atm\n-\n-*******************************************************************************/\n- \n-#ifndef IPHASE_H \n-#define IPHASE_H \n-\n-\n-/************************ IADBG DEFINE *********************************/\n-/* IADebugFlag Bit Map */ \n-#define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info\n-#define IF_IADBG_TX 0x00000002 // debug TX\n-#define IF_IADBG_RX 0x00000004 // debug RX\n-#define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call\n-#define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event\n-#define IF_IADBG_INTR 0x00000020 // debug interrupt DPC\n-#define IF_IADBG_TXPKT 0x00000040 \t // debug TX PKT\n-#define IF_IADBG_RXPKT 0x00000080 \t // debug RX PKT\n-#define IF_IADBG_ERR 0x00000100 // debug system error\n-#define IF_IADBG_EVENT 0x00000200 // debug event\n-#define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt\n-#define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt\n-#define IF_IADBG_LOUD 0x00004000 // debugging info\n-#define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info\n-#define IF_IADBG_CBR 0x00100000 \t //\n-#define IF_IADBG_UBR 0x00200000 \t //\n-#define IF_IADBG_ABR 0x00400000 //\n-#define IF_IADBG_DESC 0x01000000 //\n-#define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics\n-#define IF_IADBG_RESET 0x04000000 \n-\n-#define IF_IADBG(f) if (IADebugFlag & (f))\n-\n-#ifdef CONFIG_ATM_IA_DEBUG /* Debug build */\n-\n-#define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }\n-#define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }\n-#define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }\n-\n-#define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }\n-#define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }\n-#define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }\n-#define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }\n-#define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }\n-\n-#define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }\n-#define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }\n-#define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }\n-\n-#define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }\n-#define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }\n-#define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }\n-#define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }\n-\n-#define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }\n-#define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }\n-#define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }\n-#define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }\n-#define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }\n-\n-#else /* free build */\n-#define IF_LOUD(A)\n-#define IF_VERY_LOUD(A)\n-#define IF_INIT_ADAPTER(A)\n-#define IF_INIT(A)\n-#define IF_SUNI_STAT(A)\n-#define IF_PVC_CHKPKT(A)\n-#define IF_QUERY_INFO(A)\n-#define IF_COPY_OVER(A)\n-#define IF_HANG(A)\n-#define IF_INTR(A)\n-#define IF_DIS_INTR(A)\n-#define IF_EN_INTR(A)\n-#define IF_TX(A)\n-#define IF_RX(A)\n-#define IF_TXDEBUG(A)\n-#define IF_VC(A)\n-#define IF_ERR(A) \n-#define IF_CBR(A)\n-#define IF_UBR(A)\n-#define IF_ABR(A)\n-#define IF_SHUTDOWN(A)\n-#define DbgPrint(A)\n-#define IF_EVENT(A)\n-#define IF_TXPKT(A) \n-#define IF_RXPKT(A)\n-#endif /* CONFIG_ATM_IA_DEBUG */ \n-\n-#define ATM_DESC(skb) (skb->protocol)\n-#define IA_SKB_STATE(skb) (skb->protocol)\n-#define IA_DLED 1\n-#define IA_TX_DONE 2\n-\n-/* iadbg defines */\n-#define IA_CMD 0x7749\n-typedef struct {\n-\tint cmd;\n- int sub_cmd;\n- int len;\n- u32 maddr;\n- int status;\n- void __user *buf;\n-} IA_CMDBUF, *PIA_CMDBUF;\n-\n-/* cmds */\n-#define MEMDUMP \t\t0x01\n-\n-/* sub_cmds */\n-#define MEMDUMP_SEGREG 0x2\n-#define MEMDUMP_DEV \t\t0x1\n-#define MEMDUMP_REASSREG 0x3\n-#define MEMDUMP_FFL 0x4\n-#define READ_REG 0x5\n-#define WAKE_DBG_WAIT 0x6\n-\n-/************************ IADBG DEFINE END ***************************/\n-\n-#define Boolean(x) \t((x) ? 1 : 0)\n-#define NR_VCI 1024\t\t/* number of VCIs */ \n-#define NR_VCI_LD 10\t\t/* log2(NR_VCI) */ \n-#define NR_VCI_4K 4096 \t\t/* number of VCIs */ \n-#define NR_VCI_4K_LD 12\t\t/* log2(NR_VCI) */ \n-#define MEM_VALID 0xfffffff0\t/* mask base address with this */ \n- \n-#ifndef PCI_VENDOR_ID_IPHASE \n-#define PCI_VENDOR_ID_IPHASE 0x107e \n-#endif \n-#ifndef PCI_DEVICE_ID_IPHASE_5575 \n-#define PCI_DEVICE_ID_IPHASE_5575 0x0008 \n-#endif \n-#define DEV_LABEL \t\"ia\" \n-#define PCR\t207692 \n-#define ICR\t100000 \n-#define MCR\t0 \n-#define TBE\t1000 \n-#define FRTT\t1 \n-#define RIF\t2\t\t \n-#define RDF\t4 \n-#define NRMCODE 5\t/* 0 - 7 */ \n-#define TRMCODE\t3\t/* 0 - 7 */ \n-#define CDFCODE\t6 \n-#define ATDFCODE 2\t/* 0 - 15 */ \n- \n-/*---------------------- Packet/Cell Memory ------------------------*/ \n-#define TX_PACKET_RAM \t0x00000 /* start of Trasnmit Packet memory - 0 */ \n-#define DFL_TX_BUF_SZ\t10240\t/* 10 K buffers */ \n-#define DFL_TX_BUFFERS 50 \t/* number of packet buffers for Tx \n-\t\t\t\t\t- descriptor 0 unused */ \n-#define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */ \n-#define RX_PACKET_RAM \t0x80000 /* start of Receive Packet memory - 512K */ \n-#define DFL_RX_BUF_SZ\t10240\t/* 10k buffers */ \n-#define DFL_RX_BUFFERS 50\t/* number of packet buffers for Rx \n-\t\t\t\t\t- descriptor 0 unused */ \n- \n-struct cpcs_trailer \n-{ \n-\tu_short control; \n-\tu_short length; \n-\tu_int\tcrc32; \n-}; \n-\n-struct cpcs_trailer_desc\n-{\n-\tstruct cpcs_trailer *cpcs;\n-\tdma_addr_t dma_addr;\n-};\n-\n-struct ia_vcc \n-{ \n-\tint rxing;\t \n-\tint txing;\t\t \n- int NumCbrEntry;\n- u32 pcr;\n- u32 saved_tx_quota;\n- int flow_inc;\n- struct sk_buff_head txing_skb; \n- int ltimeout; \n- u8 vc_desc_cnt; \n- \n-}; \n- \n-struct abr_vc_table \n-{ \n-\tu_char status; \n-\tu_char rdf; \n-\tu_short air; \n-\tu_int res[3]; \n-\tu_int req_rm_cell_data1; \n-\tu_int req_rm_cell_data2; \n-\tu_int add_rm_cell_data1; \n-\tu_int add_rm_cell_data2; \n-}; \n- \n-/* 32 byte entries */ \n-struct main_vc \n-{ \n-\tu_short \ttype; \n-#define ABR\t0x8000 \n-#define UBR \t0xc000 \n-#define CBR\t0x0000 \n-\t/* ABR fields */ \n-\tu_short \tnrm;\t \n- \tu_short \ttrm;\t \n-\tu_short \trm_timestamp_hi; \n-\tu_short \trm_timestamp_lo:8, \n-\t\t\tcrm:8;\t\t \n-\tu_short \tremainder; \t/* ABR and UBR fields - last 10 bits*/ \n-\tu_short \tnext_vc_sched; \n-\tu_short \tpresent_desc;\t/* all classes */ \n-\tu_short \tlast_cell_slot;\t/* ABR and UBR */ \n-\tu_short \tpcr; \n-\tu_short \tfraction; \n-\tu_short \ticr; \n-\tu_short \tatdf; \n-\tu_short \tmcr; \n-\tu_short \tacr;\t\t \n-\tu_short \tunack:8, \n-\t\t\tstatus:8;\t/* all classes */ \n-#define UIOLI 0x80 \n-#define CRC_APPEND 0x40\t\t\t/* for status field - CRC-32 append */ \n-#define ABR_STATE 0x02 \n- \n-}; \n- \n- \n-/* 8 byte entries */ \n-struct ext_vc \n-{ \n-\tu_short \tatm_hdr1; \n-\tu_short \tatm_hdr2; \n-\tu_short \tlast_desc; \n- \tu_short \tout_of_rate_link; /* reserved for UBR and CBR */ \n-}; \n- \n- \n-#define DLE_ENTRIES 256 \n-#define DMA_INT_ENABLE 0x0002\t/* use for both Tx and Rx */ \n-#define TX_DLE_PSI 0x0001 \n-#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)\n- \n-/* Descriptor List Entries (DLE) */ \n-struct dle \n-{ \n-\tu32 \tsys_pkt_addr; \n-\tu32 \tlocal_pkt_addr; \n-\tu32 \tbytes; \n-\tu16 \tprq_wr_ptr_data; \n-\tu16 \tmode; \n-}; \n- \n-struct dle_q \n-{ \n-\tstruct dle \t*start; \n-\tstruct dle \t*end; \n-\tstruct dle \t*read; \n-\tstruct dle \t*write; \n-}; \n- \n-struct free_desc_q \n-{ \n-\tint \tdesc;\t/* Descriptor number */ \n-\tstruct free_desc_q *next; \n-}; \n- \n-struct tx_buf_desc { \n-\tunsigned short desc_mode; \n-\tunsigned short vc_index; \n-\tunsigned short res1;\t\t/* reserved field */ \n-\tunsigned short bytes; \n-\tunsigned short buf_start_hi; \n-\tunsigned short buf_start_lo; \n-\tunsigned short res2[10];\t/* reserved field */ \n-}; \n-\t \n- \n-struct rx_buf_desc { \n-\tunsigned short desc_mode;\n-\tunsigned short vc_index;\n-\tunsigned short vpi; \n-\tunsigned short bytes; \n-\tunsigned short buf_start_hi; \n-\tunsigned short buf_start_lo; \n-\tunsigned short dma_start_hi; \n-\tunsigned short dma_start_lo; \n-\tunsigned short crc_upper; \n-\tunsigned short crc_lower; \n-\tunsigned short res:8, timeout:8; \n-\tunsigned short res2[5];\t/* reserved field */ \n-}; \n- \n-/*--------SAR stuff ---------------------*/ \n- \n-#define EPROM_SIZE 0x40000\t/* says 64K in the docs ??? */ \n-#define MAC1_LEN\t4\t \t\t\t\t\t \n-#define MAC2_LEN\t2 \n- \n-/*------------ PCI Memory Space Map, 128K SAR memory ----------------*/ \n-#define IPHASE5575_PCI_CONFIG_REG_BASE\t0x0000 \n-#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000\t/* offsets 0x00 - 0x3c */ \n-#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000 \n-#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000 \n-#define IPHASE5575_DMA_CONTROL_REG_BASE\t0x4000 \n-#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE \n-#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000 \n-#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000 \n- \n-/*------------ Bus interface control registers -----------------*/ \n-#define IPHASE5575_BUS_CONTROL_REG\t0x00 \n-#define IPHASE5575_BUS_STATUS_REG\t0x01\t/* actual offset 0x04 */ \n-#define IPHASE5575_MAC1\t\t\t0x02 \n-#define IPHASE5575_REV\t\t\t0x03 \n-#define IPHASE5575_MAC2\t\t\t0x03\t/*actual offset 0x0e-reg 0x0c*/ \n-#define IPHASE5575_EXT_RESET\t\t0x04 \n-#define IPHASE5575_INT_RESET\t\t0x05\t/* addr 1c ?? reg 0x06 */ \n-#define IPHASE5575_PCI_ADDR_PAGE\t0x07\t/* reg 0x08, 0x09 ?? */ \n-#define IPHASE5575_EEPROM_ACCESS\t0x0a\t/* actual offset 0x28 */ \n-#define IPHASE5575_CELL_FIFO_QUEUE_SZ\t0x0b \n-#define IPHASE5575_CELL_FIFO_MARK_STATE\t0x0c \n-#define IPHASE5575_CELL_FIFO_READ_PTR\t0x0d \n-#define IPHASE5575_CELL_FIFO_WRITE_PTR\t0x0e \n-#define IPHASE5575_CELL_FIFO_CELLS_AVL\t0x0f\t/* actual offset 0x3c */ \n- \n-/* Bus Interface Control Register bits */ \n-#define CTRL_FE_RST\t0x80000000 \n-#define CTRL_LED\t0x40000000 \n-#define CTRL_25MBPHY\t0x10000000 \n-#define CTRL_ENCMBMEM\t0x08000000 \n-#define CTRL_ENOFFSEG\t0x01000000 \n-#define CTRL_ERRMASK\t0x00400000 \n-#define CTRL_DLETMASK\t0x00100000 \n-#define CTRL_DLERMASK\t0x00080000 \n-#define CTRL_FEMASK\t0x00040000 \n-#define CTRL_SEGMASK\t0x00020000 \n-#define CTRL_REASSMASK\t0x00010000 \n-#define CTRL_CSPREEMPT\t0x00002000 \n-#define CTRL_B128\t0x00000200 \n-#define CTRL_B64\t0x00000100 \n-#define CTRL_B48\t0x00000080 \n-#define CTRL_B32\t0x00000040 \n-#define CTRL_B16\t0x00000020 \n-#define CTRL_B8\t\t0x00000010 \n- \n-/* Bus Interface Status Register bits */ \n-#define STAT_CMEMSIZ\t0xc0000000 \n-#define STAT_ADPARCK\t0x20000000 \n-#define STAT_RESVD\t0x1fffff80 \n-#define STAT_ERRINT\t0x00000040 \n-#define STAT_MARKINT\t0x00000020 \n-#define STAT_DLETINT\t0x00000010 \n-#define STAT_DLERINT\t0x00000008 \n-#define STAT_FEINT\t0x00000004 \n-#define STAT_SEGINT\t0x00000002 \n-#define STAT_REASSINT\t0x00000001 \n- \n- \n-/*--------------- Segmentation control registers -----------------*/ \n-/* The segmentation registers are 16 bits access and the addresses \n-\tare defined as such so the addresses are the actual \"offsets\" */ \n-#define IDLEHEADHI\t0x00 \n-#define IDLEHEADLO\t0x01 \n-#define MAXRATE\t\t0x02 \n-/* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */ \n-#define RATE155\t\t0x64b1 // 16 bits float format \n-#define MAX_ATM_155 352768 // Cells/second p.118\n-#define RATE25\t\t0x5f9d \n- \n-#define STPARMS\t\t0x03 \n-#define STPARMS_1K\t0x008c \n-#define STPARMS_2K\t0x0049 \n-#define STPARMS_4K\t0x0026 \n-#define COMP_EN\t\t0x4000 \n-#define CBR_EN\t\t0x2000 \n-#define ABR_EN\t\t0x0800 \n-#define UBR_EN\t\t0x0400 \n- \n-#define ABRUBR_ARB\t0x04 \n-#define RM_TYPE\t\t0x05 \n-/*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/ \n-#define RM_TYPE_4_0\t0x0100 \n- \n-#define SEG_COMMAND_REG\t\t0x17 \n-/* Values for the command register */ \n-#define RESET_SEG 0x0055 \n-#define RESET_SEG_STATE\t0x00aa \n-#define RESET_TX_CELL_CTR 0x00cc \n- \n-#define CBR_PTR_BASE\t0x20 \n-#define ABR_SBPTR_BASE\t0x22 \n-#define UBR_SBPTR_BASE 0x23 \n-#define ABRWQ_BASE\t0x26 \n-#define UBRWQ_BASE\t0x27 \n-#define VCT_BASE\t0x28 \n-#define VCTE_BASE\t0x29 \n-#define CBR_TAB_BEG\t0x2c \n-#define CBR_TAB_END\t0x2d \n-#define PRQ_ST_ADR\t0x30 \n-#define PRQ_ED_ADR\t0x31 \n-#define PRQ_RD_PTR\t0x32 \n-#define PRQ_WR_PTR\t0x33 \n-#define TCQ_ST_ADR\t0x34 \n-#define TCQ_ED_ADR \t0x35 \n-#define TCQ_RD_PTR\t0x36 \n-#define TCQ_WR_PTR\t0x37 \n-#define SEG_QUEUE_BASE\t0x40 \n-#define SEG_DESC_BASE\t0x41 \n-#define MODE_REG_0\t0x45 \n-#define T_ONLINE\t0x0002\t\t/* (i)chipSAR is online */ \n- \n-#define MODE_REG_1\t0x46 \n-#define MODE_REG_1_VAL\t0x0400\t\t/*for propoer device operation*/ \n- \n-#define SEG_INTR_STATUS_REG 0x47 \n-#define SEG_MASK_REG\t0x48 \n-#define TRANSMIT_DONE 0x0200\n-#define TCQ_NOT_EMPTY 0x1000\t/* this can be used for both the interrupt \n-\t\t\t\tstatus registers as well as the mask register */ \n- \n-#define CELL_CTR_HIGH_AUTO 0x49 \n-#define CELL_CTR_HIGH_NOAUTO 0xc9 \n-#define CELL_CTR_LO_AUTO 0x4a \n-#define CELL_CTR_LO_NOAUTO 0xca \n- \n-/* Diagnostic registers */ \n-#define NEXTDESC \t0x59 \n-#define NEXTVC\t\t0x5a \n-#define PSLOTCNT\t0x5d \n-#define NEWDN\t\t0x6a \n-#define NEWVC\t\t0x6b \n-#define SBPTR\t\t0x6c \n-#define ABRWQ_WRPTR\t0x6f \n-#define ABRWQ_RDPTR\t0x70 \n-#define UBRWQ_WRPTR\t0x71 \n-#define UBRWQ_RDPTR\t0x72 \n-#define CBR_VC\t\t0x73 \n-#define ABR_SBVC\t0x75 \n-#define UBR_SBVC\t0x76 \n-#define ABRNEXTLINK\t0x78 \n-#define UBRNEXTLINK\t0x79 \n- \n- \n-/*----------------- Reassembly control registers ---------------------*/ \n-/* The reassembly registers are 16 bits access and the addresses \n-\tare defined as such so the addresses are the actual \"offsets\" */ \n-#define MODE_REG\t0x00 \n-#define R_ONLINE\t0x0002\t\t/* (i)chip is online */ \n-#define IGN_RAW_FL \t0x0004\n- \n-#define PROTOCOL_ID\t0x01 \n-#define REASS_MASK_REG\t0x02 \n-#define REASS_INTR_STATUS_REG\t0x03 \n-/* Interrupt Status register bits */ \n-#define RX_PKT_CTR_OF\t0x8000 \n-#define RX_ERR_CTR_OF\t0x4000 \n-#define RX_CELL_CTR_OF\t0x1000 \n-#define RX_FREEQ_EMPT\t0x0200 \n-#define RX_EXCPQ_FL\t0x0080 \n-#define\tRX_RAWQ_FL\t0x0010 \n-#define RX_EXCP_RCVD\t0x0008 \n-#define RX_PKT_RCVD\t0x0004 \n-#define RX_RAW_RCVD\t0x0001 \n- \n-#define DRP_PKT_CNTR\t0x04 \n-#define ERR_CNTR\t0x05 \n-#define RAW_BASE_ADR\t0x08 \n-#define CELL_CTR0\t0x0c \n-#define CELL_CTR1\t0x0d \n-#define REASS_COMMAND_REG\t0x0f \n-/* Values for command register */ \n-#define RESET_REASS\t0x0055 \n-#define RESET_REASS_STATE 0x00aa \n-#define RESET_DRP_PKT_CNTR 0x00f1 \n-#define RESET_ERR_CNTR\t0x00f2 \n-#define RESET_CELL_CNTR 0x00f8 \n-#define RESET_REASS_ALL_REGS 0x00ff \n- \n-#define REASS_DESC_BASE\t0x10 \n-#define VC_LKUP_BASE\t0x11 \n-#define REASS_TABLE_BASE 0x12 \n-#define REASS_QUEUE_BASE 0x13 \n-#define PKT_TM_CNT\t0x16 \n-#define TMOUT_RANGE\t0x17 \n-#define INTRVL_CNTR\t0x18 \n-#define TMOUT_INDX\t0x19 \n-#define VP_LKUP_BASE\t0x1c \n-#define VP_FILTER\t0x1d \n-#define ABR_LKUP_BASE\t0x1e \n-#define FREEQ_ST_ADR\t0x24 \n-#define FREEQ_ED_ADR\t0x25 \n-#define FREEQ_RD_PTR\t0x26 \n-#define FREEQ_WR_PTR\t0x27 \n-#define PCQ_ST_ADR\t0x28 \n-#define PCQ_ED_ADR\t0x29 \n-#define PCQ_RD_PTR\t0x2a \n-#define PCQ_WR_PTR\t0x2b \n-#define EXCP_Q_ST_ADR\t0x2c \n-#define EXCP_Q_ED_ADR\t0x2d \n-#define EXCP_Q_RD_PTR\t0x2e \n-#define EXCP_Q_WR_PTR\t0x2f \n-#define CC_FIFO_ST_ADR\t0x34 \n-#define CC_FIFO_ED_ADR\t0x35 \n-#define CC_FIFO_RD_PTR\t0x36 \n-#define CC_FIFO_WR_PTR\t0x37 \n-#define STATE_REG\t0x38 \n-#define BUF_SIZE\t0x42 \n-#define XTRA_RM_OFFSET\t0x44 \n-#define DRP_PKT_CNTR_NC\t0x84 \n-#define ERR_CNTR_NC\t0x85 \n-#define CELL_CNTR0_NC\t0x8c \n-#define CELL_CNTR1_NC\t0x8d \n- \n-/* State Register bits */ \n-#define EXCPQ_EMPTY\t0x0040 \n-#define PCQ_EMPTY\t0x0010 \n-#define FREEQ_EMPTY\t0x0004 \n- \n- \n-/*----------------- Front End registers/ DMA control --------------*/ \n-/* There is a lot of documentation error regarding these offsets ??? \n-\teg:- 2 offsets given 800, a00 for rx counter \n-\tsimilarly many others \n- Remember again that the offsets are to be 4*register number, so \n-\tcorrect the #defines here \n-*/ \n-#define IPHASE5575_TX_COUNTER\t\t0x200\t/* offset - 0x800 */ \n-#define IPHASE5575_RX_COUNTER\t\t0x280\t/* offset - 0xa00 */ \n-#define IPHASE5575_TX_LIST_ADDR\t\t0x300\t/* offset - 0xc00 */ \n-#define IPHASE5575_RX_LIST_ADDR\t\t0x380\t/* offset - 0xe00 */ \n- \n-/*--------------------------- RAM ---------------------------*/ \n-/* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */ \n- \n-/* Segmentation Control Memory map */ \n-#define TX_DESC_BASE\t0x0000\t/* Buffer Decriptor Table */ \n-#define TX_COMP_Q\t0x1000\t/* Transmit Complete Queue */ \n-#define PKT_RDY_Q\t0x1400\t/* Packet Ready Queue */ \n-#define CBR_SCHED_TABLE\t0x1800\t/* CBR Table */ \n-#define UBR_SCHED_TABLE\t0x3000\t/* UBR Table */ \n-#define UBR_WAIT_Q\t0x4000\t/* UBR Wait Queue */ \n-#define ABR_SCHED_TABLE\t0x5000\t/* ABR Table */ \n-#define ABR_WAIT_Q\t0x5800\t/* ABR Wait Queue */ \n-#define EXT_VC_TABLE\t0x6000\t/* Extended VC Table */ \n-#define MAIN_VC_TABLE\t0x8000\t/* Main VC Table */ \n-#define SCHEDSZ\t\t1024\t/* ABR and UBR Scheduling Table size */ \n-#define TX_DESC_TABLE_SZ 128\t/* Number of entries in the Transmit \n-\t\t\t\t\tBuffer Descriptor Table */ \n- \n-/* These are used as table offsets in Descriptor Table address generation */ \n-#define DESC_MODE\t0x0 \n-#define VC_INDEX\t0x1 \n-#define BYTE_CNT\t0x3 \n-#define PKT_START_HI\t0x4 \n-#define PKT_START_LO\t0x5 \n- \n-/* Descriptor Mode Word Bits */ \n-#define EOM_EN\t0x0800 \n-#define AAL5\t0x0100 \n-#define APP_CRC32 0x0400 \n-#define CMPL_INT 0x1000\n- \n-#define TABLE_ADDRESS(db, dn, to) \\\n-\t(((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1) \n- \n-/* Reassembly Control Memory Map */ \n-#define RX_DESC_BASE\t0x0000\t/* Buffer Descriptor Table */ \n-#define VP_TABLE\t0x5c00\t/* VP Table */ \n-#define EXCEPTION_Q\t0x5e00\t/* Exception Queue */ \n-#define FREE_BUF_DESC_Q\t0x6000\t/* Free Buffer Descriptor Queue */ \n-#define PKT_COMP_Q\t0x6800\t/* Packet Complete Queue */ \n-#define REASS_TABLE\t0x7000\t/* Reassembly Table */ \n-#define RX_VC_TABLE\t0x7800\t/* VC Table */ \n-#define ABR_VC_TABLE\t0x8000\t/* ABR VC Table */ \n-#define RX_DESC_TABLE_SZ 736\t/* Number of entries in the Receive \n-\t\t\t\t\tBuffer Descriptor Table */ \n-#define VP_TABLE_SZ\t256\t /* Number of entries in VPTable */ \n-#define RX_VC_TABLE_SZ \t1024\t/* Number of entries in VC Table */ \n-#define REASS_TABLE_SZ \t1024\t/* Number of entries in Reassembly Table */ \n- /* Buffer Descriptor Table */ \n-#define RX_ACT\t0x8000 \n-#define RX_VPVC\t0x4000 \n-#define RX_CNG\t0x0040 \n-#define RX_CER\t0x0008 \n-#define RX_PTE\t0x0004 \n-#define RX_OFL\t0x0002 \n-#define NUM_RX_EXCP 32\n-\n-/* Reassembly Table */ \n-#define NO_AAL5_PKT\t0x0000 \n-#define AAL5_PKT_REASSEMBLED 0x4000 \n-#define AAL5_PKT_TERMINATED 0x8000 \n-#define RAW_PKT\t\t0xc000 \n-#define REASS_ABR\t0x2000 \n- \n-/*-------------------- Base Registers --------------------*/ \n-#define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE \n-#define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE \n-#define PHY_BASE IPHASE5575_FRONT_END_REG_BASE \n-#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE \n-#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE \n-\n-typedef volatile u_int\tffreg_t;\n-typedef u_int rreg_t;\n-\n-typedef struct _ffredn_t {\n-\tffreg_t\tidlehead_high;\t/* Idle cell header (high)\t\t*/\n-\tffreg_t\tidlehead_low;\t/* Idle cell header (low)\t\t*/\n-\tffreg_t\tmaxrate;\t/* Maximum rate\t\t\t\t*/\n-\tffreg_t\tstparms;\t/* Traffic Management Parameters\t*/\n-\tffreg_t\tabrubr_abr;\t/* ABRUBR Priority Byte 1, TCR Byte 0\t*/\n-\tffreg_t\trm_type;\t/*\t\t\t\t\t*/\n-\tu_int\tfiller5[0x17 - 0x06];\n-\tffreg_t\tcmd_reg;\t/* Command register\t\t\t*/\n-\tu_int\tfiller18[0x20 - 0x18];\n-\tffreg_t\tcbr_base;\t/* CBR Pointer Base\t\t\t*/\n-\tffreg_t\tvbr_base;\t/* VBR Pointer Base\t\t\t*/\n-\tffreg_t\tabr_base;\t/* ABR Pointer Base\t\t\t*/\n-\tffreg_t\tubr_base;\t/* UBR Pointer Base\t\t\t*/\n-\tu_int\tfiller24;\n-\tffreg_t\tvbrwq_base;\t/* VBR Wait Queue Base\t\t\t*/\n-\tffreg_t\tabrwq_base;\t/* ABR Wait Queue Base\t\t\t*/\n-\tffreg_t\tubrwq_base;\t/* UBR Wait Queue Base\t\t\t*/\n-\tffreg_t\tvct_base;\t/* Main VC Table Base\t\t\t*/\n-\tffreg_t\tvcte_base;\t/* Extended Main VC Table Base\t\t*/\n-\tu_int\tfiller2a[0x2C - 0x2A];\n-\tffreg_t\tcbr_tab_beg;\t/* CBR Table Begin\t\t\t*/\n-\tffreg_t\tcbr_tab_end;\t/* CBR Table End\t\t\t*/\n-\tffreg_t\tcbr_pointer;\t/* CBR Pointer\t\t\t\t*/\n-\tu_int\tfiller2f[0x30 - 0x2F];\n-\tffreg_t\tprq_st_adr;\t/* Packet Ready Queue Start Address\t*/\n-\tffreg_t\tprq_ed_adr;\t/* Packet Ready Queue End Address\t*/\n-\tffreg_t\tprq_rd_ptr;\t/* Packet Ready Queue read pointer\t*/\n-\tffreg_t\tprq_wr_ptr;\t/* Packet Ready Queue write pointer\t*/\n-\tffreg_t\ttcq_st_adr;\t/* Transmit Complete Queue Start Address*/\n-\tffreg_t\ttcq_ed_adr;\t/* Transmit Complete Queue End Address\t*/\n-\tffreg_t\ttcq_rd_ptr;\t/* Transmit Complete Queue read pointer */\n-\tffreg_t\ttcq_wr_ptr;\t/* Transmit Complete Queue write pointer*/\n-\tu_int\tfiller38[0x40 - 0x38];\n-\tffreg_t\tqueue_base;\t/* Base address for PRQ and TCQ\t\t*/\n-\tffreg_t\tdesc_base;\t/* Base address of descriptor table\t*/\n-\tu_int\tfiller42[0x45 - 0x42];\n-\tffreg_t\tmode_reg_0;\t/* Mode register 0\t\t\t*/\n-\tffreg_t\tmode_reg_1;\t/* Mode register 1\t\t\t*/\n-\tffreg_t\tintr_status_reg;/* Interrupt Status register\t\t*/\n-\tffreg_t\tmask_reg;\t/* Mask Register\t\t\t*/\n-\tffreg_t\tcell_ctr_high1; /* Total cell transfer count (high)\t*/\n-\tffreg_t\tcell_ctr_lo1;\t/* Total cell transfer count (low)\t*/\n-\tffreg_t\tstate_reg;\t/* Status register\t\t\t*/\n-\tu_int\tfiller4c[0x58 - 0x4c];\n-\tffreg_t\tcurr_desc_num;\t/* Contains the current descriptor num\t*/\n-\tffreg_t\tnext_desc;\t/* Next descriptor\t\t\t*/\n-\tffreg_t\tnext_vc;\t/* Next VC\t\t\t\t*/\n-\tu_int\tfiller5b[0x5d - 0x5b];\n-\tffreg_t\tpresent_slot_cnt;/* Present slot count\t\t\t*/\n-\tu_int\tfiller5e[0x6a - 0x5e];\n-\tffreg_t\tnew_desc_num;\t/* New descriptor number\t\t*/\n-\tffreg_t\tnew_vc;\t\t/* New VC\t\t\t\t*/\n-\tffreg_t\tsched_tbl_ptr;\t/* Schedule table pointer\t\t*/\n-\tffreg_t\tvbrwq_wptr;\t/* VBR wait queue write pointer\t\t*/\n-\tffreg_t\tvbrwq_rptr;\t/* VBR wait queue read pointer\t\t*/\n-\tffreg_t\tabrwq_wptr;\t/* ABR wait queue write pointer\t\t*/\n-\tffreg_t\tabrwq_rptr;\t/* ABR wait queue read pointer\t\t*/\n-\tffreg_t\tubrwq_wptr;\t/* UBR wait queue write pointer\t\t*/\n-\tffreg_t\tubrwq_rptr;\t/* UBR wait queue read pointer\t\t*/\n-\tffreg_t\tcbr_vc;\t\t/* CBR VC\t\t\t\t*/\n-\tffreg_t\tvbr_sb_vc;\t/* VBR SB VC\t\t\t\t*/\n-\tffreg_t\tabr_sb_vc;\t/* ABR SB VC\t\t\t\t*/\n-\tffreg_t\tubr_sb_vc;\t/* UBR SB VC\t\t\t\t*/\n-\tffreg_t\tvbr_next_link;\t/* VBR next link\t\t\t*/\n-\tffreg_t\tabr_next_link;\t/* ABR next link\t\t\t*/\n-\tffreg_t\tubr_next_link;\t/* UBR next link\t\t\t*/\n-\tu_int\tfiller7a[0x7c-0x7a];\n-\tffreg_t\tout_rate_head;\t/* Out of rate head\t\t\t*/\n-\tu_int\tfiller7d[0xca-0x7d]; /* pad out to full address space\t*/\n-\tffreg_t\tcell_ctr_high1_nc;/* Total cell transfer count (high)\t*/\n-\tffreg_t\tcell_ctr_lo1_nc;/* Total cell transfer count (low)\t*/\n-\tu_int\tfillercc[0x100-0xcc]; /* pad out to full address space\t */\n-} ffredn_t;\n-\n-typedef struct _rfredn_t {\n- rreg_t mode_reg_0; /* Mode register 0 */\n- rreg_t protocol_id; /* Protocol ID */\n- rreg_t mask_reg; /* Mask Register */\n- rreg_t intr_status_reg;/* Interrupt status register */\n- rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */\n- rreg_t err_cntr; /* Error Counter (cleared on read) */\n- u_int filler6[0x08 - 0x06];\n- rreg_t raw_base_adr; /* Base addr for raw cell Q */\n- u_int filler2[0x0c - 0x09];\n- rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */\n- rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */\n- u_int filler3[0x0f - 0x0e];\n- rreg_t cmd_reg; /* Command register */\n- rreg_t desc_base; /* Base address for description table */\n- rreg_t vc_lkup_base; /* Base address for VC lookup table */\n- rreg_t reass_base; /* Base address for reassembler table */\n- rreg_t queue_base; /* Base address for Communication queue */\n- u_int filler14[0x16 - 0x14];\n- rreg_t pkt_tm_cnt; /* Packet Timeout and count register */\n- rreg_t tmout_range; /* Range of reassembley IDs for timeout */\n- rreg_t intrvl_cntr; /* Packet aging interval counter */\n- rreg_t tmout_indx; /* index of pkt being tested for aging */\n- u_int filler1a[0x1c - 0x1a];\n- rreg_t vp_lkup_base; /* Base address for VP lookup table */\n- rreg_t vp_filter; /* VP filter register */\n- rreg_t abr_lkup_base; /* Base address of ABR VC Table */\n- u_int filler1f[0x24 - 0x1f];\n- rreg_t fdq_st_adr; /* Free desc queue start address */\n- rreg_t fdq_ed_adr; /* Free desc queue end address */\n- rreg_t fdq_rd_ptr; /* Free desc queue read pointer */\n- rreg_t fdq_wr_ptr; /* Free desc queue write pointer */\n- rreg_t pcq_st_adr; /* Packet Complete queue start address */\n- rreg_t pcq_ed_adr; /* Packet Complete queue end address */\n- rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */\n- rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */\n- rreg_t excp_st_adr; /* Exception queue start address */\n- rreg_t excp_ed_adr; /* Exception queue end address */\n- rreg_t excp_rd_ptr; /* Exception queue read pointer */\n- rreg_t excp_wr_ptr; /* Exception queue write pointer */\n- u_int filler30[0x34 - 0x30];\n- rreg_t raw_st_adr; /* Raw Cell start address */\n- rreg_t raw_ed_adr; /* Raw Cell end address */\n- rreg_t raw_rd_ptr; /* Raw Cell read pointer */\n- rreg_t raw_wr_ptr; /* Raw Cell write pointer */\n- rreg_t state_reg; /* State Register */\n- u_int filler39[0x42 - 0x39];\n- rreg_t buf_size; /* Buffer size */\n- u_int filler43;\n- rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */\n- u_int filler45[0x84 - 0x45];\n- rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */\n- rreg_t err_cntr_nc; /* Error Counter, Not clear on read */\n- u_int filler86[0x8c - 0x86];\n- rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */\n- rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */\n- u_int filler8e[0x100-0x8e]; /* pad out to full address space */\n-} rfredn_t;\n-\n-typedef struct {\n- /* Atlantic */\n- ffredn_t ffredn; /* F FRED */\n- rfredn_t rfredn; /* R FRED */\n-} ia_regs_t;\n-\n-typedef struct {\n-\tu_short\t\tf_vc_type;\t/* VC type */\n-\tu_short\t\tf_nrm;\t\t/* Nrm\t\t\t*/\n-\tu_short\t\tf_nrmexp;\t/* Nrm Exp */\n-\tu_short\t\treserved6;\t/* \t\t\t*/\n-\tu_short\t\tf_crm;\t\t/* Crm\t\t\t*/\n-\tu_short\t\treserved10;\t/* Reserved\t\t*/\n-\tu_short\t\treserved12;\t/* Reserved\t\t*/\n-\tu_short\t\treserved14;\t/* Reserved\t\t*/\n-\tu_short\t\tlast_cell_slot;\t/* last_cell_slot_count\t*/\n-\tu_short\t\tf_pcr;\t\t/* Peak Cell Rate\t*/\n-\tu_short\t\tfraction;\t/* fraction\t\t*/\n-\tu_short\t\tf_icr;\t\t/* Initial Cell Rate\t*/\n-\tu_short\t\tf_cdf;\t\t/* */\n-\tu_short\t\tf_mcr;\t\t/* Minimum Cell Rate\t*/\n-\tu_short\t\tf_acr;\t\t/* Allowed Cell Rate\t*/\n-\tu_short\t\tf_status;\t/* */\n-} f_vc_abr_entry;\n-\n-typedef struct {\n- u_short r_status_rdf; /* status + RDF */\n- u_short r_air; /* AIR */\n- u_short reserved4[14]; /* Reserved */\n-} r_vc_abr_entry; \n-\n-#define MRM 3\n-\n-typedef struct srv_cls_param {\n- u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */\n- u32 pcr; /* Peak Cell Rate (24-bit) */ \n- /* VBR parameters */\n- u32 scr; /* sustainable cell rate */\n- u32 max_burst_size; /* ?? cell rate or data rate */\n- \n- /* ABR only UNI 4.0 Parameters */\n- u32 mcr; /* Min Cell Rate (24-bit) */\n- u32 icr; /* Initial Cell Rate (24-bit) */\n- u32 tbe; /* Transient Buffer Exposure (24-bit) */\n- u32 frtt; /* Fixed Round Trip Time (24-bit) */\n- \n-#if 0 /* Additional Parameters of TM 4.0 */\n-bits 31 30 29 28 27-25 24-22 21-19 18-9\n------------------------------------------------------------------------------\n-| NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |\n------------------------------------------------------------------------------\n-#endif /* 0 */\n- \n- u8 nrm; /* Max # of Cells for each forward RM\n- cell (3-bit) */\n- u8 trm; /* Time between forward RM cells (3-bit) */\n- u16 adtf; /* ACR Decrease Time Factor (10-bit) */\n- u8 cdf; /* Cutoff Decrease Factor (3-bit) */\n- u8 rif; /* Rate Increment Factor (4-bit) */\n- u8 rdf; /* Rate Decrease Factor (4-bit) */\n- u8 reserved; /* 8 bits to keep structure word aligned */\n-} srv_cls_param_t;\n-\n-struct testTable_t {\n-\tu16 lastTime; \n-\tu16 fract; \n-\tu8 vc_status;\n-}; \n-\n-typedef struct {\n-\tu16 vci;\n-\tu16 error;\n-} RX_ERROR_Q;\n-\n-typedef struct {\n-\tu8 active: 1; \n-\tu8 abr: 1; \n-\tu8 ubr: 1; \n-\tu8 cnt: 5;\n-#define VC_ACTIVE \t0x01\n-#define VC_ABR\t\t0x02\n-#define VC_UBR\t\t0x04\n-} vcstatus_t;\n- \n-struct ia_rfL_t {\n- \tu32 fdq_st; /* Free desc queue start address */\n- u32 fdq_ed; /* Free desc queue end address */\n- u32 fdq_rd; /* Free desc queue read pointer */\n- u32 fdq_wr; /* Free desc queue write pointer */\n- u32 pcq_st; /* Packet Complete queue start address */\n- u32 pcq_ed; /* Packet Complete queue end address */\n- u32 pcq_rd; /* Packet Complete queue read pointer */\n- u32 pcq_wr; /* Packet Complete queue write pointer */ \n-};\n-\n-struct ia_ffL_t {\n-\tu32 prq_st; /* Packet Ready Queue Start Address */\n- u32 prq_ed; /* Packet Ready Queue End Address */\n- u32 prq_wr; /* Packet Ready Queue write pointer */\n- u32 tcq_st; /* Transmit Complete Queue Start Address*/\n- u32 tcq_ed; /* Transmit Complete Queue End Address */\n- u32 tcq_rd; /* Transmit Complete Queue read pointer */\n-};\n-\n-struct desc_tbl_t {\n- u32 timestamp;\n- struct ia_vcc *iavcc;\n- struct sk_buff *txskb;\n-}; \n-\n-typedef struct ia_rtn_q {\n- struct desc_tbl_t data;\n- struct ia_rtn_q *next, *tail;\n-} IARTN_Q;\n-\n-#define SUNI_LOSV \t0x04\n-enum ia_suni {\n-\tSUNI_MASTER_RESET\t= 0x000, /* SUNI Master Reset and Identity */\n-\tSUNI_MASTER_CONFIG\t= 0x004, /* SUNI Master Configuration */\n-\tSUNI_MASTER_INTR_STAT\t= 0x008, /* SUNI Master Interrupt Status */\n-\tSUNI_RESERVED1\t\t= 0x00c, /* Reserved */\n-\tSUNI_MASTER_CLK_MONITOR\t= 0x010, /* SUNI Master Clock Monitor */\n-\tSUNI_MASTER_CONTROL\t= 0x014, /* SUNI Master Clock Monitor */\n-\t\t\t\t\t /* Reserved (10) */\n-\tSUNI_RSOP_CONTROL\t= 0x040, /* RSOP Control/Interrupt Enable */\n-\tSUNI_RSOP_STATUS\t= 0x044, /* RSOP Status/Interrupt States */\n-\tSUNI_RSOP_SECTION_BIP8L\t= 0x048, /* RSOP Section BIP-8 LSB */\n-\tSUNI_RSOP_SECTION_BIP8M\t= 0x04c, /* RSOP Section BIP-8 MSB */\n-\n-\tSUNI_TSOP_CONTROL\t= 0x050, /* TSOP Control */\n-\tSUNI_TSOP_DIAG\t\t= 0x054, /* TSOP Disgnostics */\n-\t\t\t\t\t /* Reserved (2) */\n-\tSUNI_RLOP_CS\t\t= 0x060, /* RLOP Control/Status */\n-\tSUNI_RLOP_INTR\t\t= 0x064, /* RLOP Interrupt Enable/Status */\n-\tSUNI_RLOP_LINE_BIP24L\t= 0x068, /* RLOP Line BIP-24 LSB */\n-\tSUNI_RLOP_LINE_BIP24\t= 0x06c, /* RLOP Line BIP-24 */\n-\tSUNI_RLOP_LINE_BIP24M\t= 0x070, /* RLOP Line BIP-24 MSB */\n-\tSUNI_RLOP_LINE_FEBEL\t= 0x074, /* RLOP Line FEBE LSB */\n-\tSUNI_RLOP_LINE_FEBE\t= 0x078, /* RLOP Line FEBE */\n-\tSUNI_RLOP_LINE_FEBEM\t= 0x07c, /* RLOP Line FEBE MSB */\n-\n-\tSUNI_TLOP_CONTROL\t= 0x080, /* TLOP Control */\n-\tSUNI_TLOP_DISG\t\t= 0x084, /* TLOP Disgnostics */\n-\t\t\t\t\t /* Reserved (14) */\n-\tSUNI_RPOP_CS\t\t= 0x0c0, /* RPOP Status/Control */\n-\tSUNI_RPOP_INTR\t\t= 0x0c4, /* RPOP Interrupt/Status */\n-\tSUNI_RPOP_RESERVED\t= 0x0c8, /* RPOP Reserved */\n-\tSUNI_RPOP_INTR_ENA\t= 0x0cc, /* RPOP Interrupt Enable */\n-\t\t\t\t\t /* Reserved (3) */\n-\tSUNI_RPOP_PATH_SIG\t= 0x0dc, /* RPOP Path Signal Label */\n-\tSUNI_RPOP_BIP8L\t\t= 0x0e0, /* RPOP Path BIP-8 LSB */\n-\tSUNI_RPOP_BIP8M\t\t= 0x0e4, /* RPOP Path BIP-8 MSB */\n-\tSUNI_RPOP_FEBEL\t\t= 0x0e8, /* RPOP Path FEBE LSB */\n-\tSUNI_RPOP_FEBEM\t\t= 0x0ec, /* RPOP Path FEBE MSB */\n-\t\t\t\t\t /* Reserved (4) */\n-\tSUNI_TPOP_CNTRL_DAIG\t= 0x100, /* TPOP Control/Disgnostics */\n-\tSUNI_TPOP_POINTER_CTRL\t= 0x104, /* TPOP Pointer Control */\n-\tSUNI_TPOP_SOURCER_CTRL\t= 0x108, /* TPOP Source Control */\n-\t\t\t\t\t /* Reserved (2) */\n-\tSUNI_TPOP_ARB_PRTL\t= 0x114, /* TPOP Arbitrary Pointer LSB */\n-\tSUNI_TPOP_ARB_PRTM\t= 0x118, /* TPOP Arbitrary Pointer MSB */\n-\tSUNI_TPOP_RESERVED2\t= 0x11c, /* TPOP Reserved */\n-\tSUNI_TPOP_PATH_SIG\t= 0x120, /* TPOP Path Signal Lable */\n-\tSUNI_TPOP_PATH_STATUS\t= 0x124, /* TPOP Path Status */\n-\t\t\t\t\t /* Reserved (6) */\n-\tSUNI_RACP_CS\t\t= 0x140, /* RACP Control/Status */\n-\tSUNI_RACP_INTR\t\t= 0x144, /* RACP Interrupt Enable/Status */\n-\tSUNI_RACP_HDR_PATTERN\t= 0x148, /* RACP Match Header Pattern */\n-\tSUNI_RACP_HDR_MASK\t= 0x14c, /* RACP Match Header Mask */\n-\tSUNI_RACP_CORR_HCS\t= 0x150, /* RACP Correctable HCS Error Count */\n-\tSUNI_RACP_UNCORR_HCS\t= 0x154, /* RACP Uncorrectable HCS Err Count */\n-\t\t\t\t\t /* Reserved (10) */\n-\tSUNI_TACP_CONTROL\t= 0x180, /* TACP Control */\n-\tSUNI_TACP_IDLE_HDR_PAT\t= 0x184, /* TACP Idle Cell Header Pattern */\n-\tSUNI_TACP_IDLE_PAY_PAY\t= 0x188, /* TACP Idle Cell Payld Octet Patrn */\n-\t\t\t\t\t /* Reserved (5) */\n-\t\t\t\t\t /* Reserved (24) */\n-\t/* FIXME: unused but name conflicts.\n-\t * SUNI_MASTER_TEST\t= 0x200, SUNI Master Test */\n-\tSUNI_RESERVED_TEST\t= 0x204 /* SUNI Reserved for Test */\n-};\n-\n-typedef struct _SUNI_STATS_\n-{\n- u32 valid; // 1 = oc3 PHY card\n- u32 carrier_detect; // GPIN input\n- // RSOP: receive section overhead processor\n- u16 rsop_oof_state; // 1 = out of frame\n- u16 rsop_lof_state; // 1 = loss of frame\n- u16 rsop_los_state; // 1 = loss of signal\n- u32 rsop_los_count; // loss of signal count\n- u32 rsop_bse_count; // section BIP-8 error count\n- // RLOP: receive line overhead processor\n- u16 rlop_ferf_state; // 1 = far end receive failure\n- u16 rlop_lais_state; // 1 = line AIS\n- u32 rlop_lbe_count; // BIP-24 count\n- u32 rlop_febe_count; // FEBE count;\n- // RPOP: receive path overhead processor\n- u16 rpop_lop_state; // 1 = LOP\n- u16 rpop_pais_state; // 1 = path AIS\n- u16 rpop_pyel_state; // 1 = path yellow alert\n- u32 rpop_bip_count; // path BIP-8 error count\n- u32 rpop_febe_count; // path FEBE error count\n- u16 rpop_psig; // path signal label value\n- // RACP: receive ATM cell processor\n- u16 racp_hp_state; // hunt/presync state\n- u32 racp_fu_count; // FIFO underrun count\n- u32 racp_fo_count; // FIFO overrun count\n- u32 racp_chcs_count; // correctable HCS error count\n- u32 racp_uchcs_count; // uncorrectable HCS error count\n-} IA_SUNI_STATS; \n-\n-typedef struct iadev_priv {\n-\t/*-----base pointers into (i)chipSAR+ address space */ \n-\tu32 __iomem *phy;\t/* Base pointer into phy (SUNI). */\n-\tu32 __iomem *dma;\t/* Base pointer into DMA control registers. */\n-\tu32 __iomem *reg;\t/* Base pointer to SAR registers. */\n-\tu32 __iomem *seg_reg;\t\t/* base pointer to segmentation engine \n-\t\t\t\t\t\tinternal registers */ \n-\tu32 __iomem *reass_reg;\t\t/* base pointer to reassemble engine \n-\t\t\t\t\t\tinternal registers */ \n-\tu32 __iomem *ram;\t\t/* base pointer to SAR RAM */ \n-\tvoid __iomem *seg_ram; \n-\tvoid __iomem *reass_ram; \n-\tstruct dle_q tx_dle_q; \n-\tstruct free_desc_q *tx_free_desc_qhead; \n-\tstruct sk_buff_head tx_dma_q, tx_backlog; \n- spinlock_t tx_lock;\n- IARTN_Q tx_return_q;\n- u32 close_pending;\n- wait_queue_head_t close_wait;\n- wait_queue_head_t timeout_wait;\n-\tstruct cpcs_trailer_desc *tx_buf;\n- u16 num_tx_desc, tx_buf_sz, rate_limit;\n- u32 tx_cell_cnt, tx_pkt_cnt;\n- void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;\n-\tstruct dle_q rx_dle_q; \n-\tstruct free_desc_q *rx_free_desc_qhead; \n-\tstruct sk_buff_head rx_dma_q; \n-\tspinlock_t rx_lock;\n-\tstruct atm_vcc **rx_open;\t/* list of all open VCs */ \n- u16 num_rx_desc, rx_buf_sz, rxing;\n- u32 rx_pkt_ram, rx_tmp_cnt;\n- unsigned long rx_tmp_jif;\n- void __iomem *RX_DESC_BASE_ADDR;\n- u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;\n-\tstruct atm_dev *next_board;\t/* other iphase devices */ \n-\tstruct pci_dev *pci; \n-\tint mem; \n-\tunsigned int real_base;\t/* real and virtual base address */ \n-\tvoid __iomem *base;\n-\tunsigned int pci_map_size;\t/*pci map size of board */ \n-\tunsigned char irq; \n-\tunsigned char bus; \n-\tunsigned char dev_fn; \n- u_short phy_type;\n- u_short num_vc, memSize, memType;\n- struct ia_ffL_t ffL;\n- struct ia_rfL_t rfL;\n- /* Suni stat */\n- // IA_SUNI_STATS suni_stats;\n- unsigned char carrier_detect;\n- /* CBR related */\n- // transmit DMA & Receive\n- unsigned int tx_dma_cnt; // number of elements on dma queue\n- unsigned int rx_dma_cnt; // number of elements on rx dma queue\n- unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR\n- // receive MARK for Cell FIFO\n- unsigned int rx_mark_cnt; // number of elements on mark queue\n- unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table.\n- unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table.\n- unsigned int CbrEntryPt; // CBR Sched Table Entry Point.\n- unsigned int Granularity; // CBR Granularity given Table Size.\n- /* ABR related */\n-\tunsigned int sum_mcr, sum_cbr, LineRate;\n-\tunsigned int n_abr;\n- struct desc_tbl_t *desc_tbl;\n- u_short host_tcq_wr;\n- struct testTable_t **testTable;\n-\tdma_addr_t tx_dle_dma;\n-\tdma_addr_t rx_dle_dma;\n-} IADEV;\n- \n- \n-#define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data) \n-#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data) \n-\n-/******************* IDT77105 25MB/s PHY DEFINE *****************************/\n-enum ia_mb25 {\n-\tMB25_MASTER_CTRL\t= 0x00, /* Master control\t\t */\n-\tMB25_INTR_STATUS\t= 0x04,\t/* Interrupt status\t\t */\n-\tMB25_DIAG_CONTROL\t= 0x08,\t/* Diagnostic control\t\t */\n-\tMB25_LED_HEC\t\t= 0x0c,\t/* LED driver and HEC status/control */\n-\tMB25_LOW_BYTE_COUNTER\t= 0x10,\n-\tMB25_HIGH_BYTE_COUNTER\t= 0x14\n-};\n-\n-/*\n- * Master Control\n- */\n-#define\tMB25_MC_UPLO\t0x80\t\t/* UPLO\t\t\t\t */\n-#define\tMB25_MC_DREC\t0x40\t\t/* Discard receive cell errors\t */\n-#define\tMB25_MC_ECEIO\t0x20\t\t/* Enable Cell Error Interrupts Only */\n-#define\tMB25_MC_TDPC\t0x10\t\t/* Transmit data parity check\t */\n-#define\tMB25_MC_DRIC\t0x08\t\t/* Discard receive idle cells\t */\n-#define\tMB25_MC_HALTTX\t0x04\t\t/* Halt Tx\t\t\t */\n-#define\tMB25_MC_UMS\t0x02\t\t/* UTOPIA mode select\t\t */\n-#define\tMB25_MC_ENABLED\t0x01\t\t/* Enable interrupt\t\t */\n-\n-/*\n- * Interrupt Status\n- */\n-#define\tMB25_IS_GSB\t0x40\t\t/* GOOD Symbol Bit\t\t */\t\n-#define\tMB25_IS_HECECR\t0x20\t\t/* HEC error cell received\t */\n-#define\tMB25_IS_SCR\t0x10\t\t/* \"Short Cell\" Received\t */\n-#define\tMB25_IS_TPE\t0x08\t\t/* Trnamsit Parity Error\t */\n-#define\tMB25_IS_RSCC\t0x04\t\t/* Receive Signal Condition change */\n-#define\tMB25_IS_RCSE\t0x02\t\t/* Received Cell Symbol Error\t */\n-#define\tMB25_IS_RFIFOO\t0x01\t\t/* Received FIFO Overrun\t */\n-\n-/*\n- * Diagnostic Control\n- */\n-#define\tMB25_DC_FTXCD\t0x80\t\t/* Force TxClav deassert\t */\t\n-#define\tMB25_DC_RXCOS\t0x40\t\t/* RxClav operation select\t */\n-#define\tMB25_DC_ECEIO\t0x20\t\t/* Single/Multi-PHY config select */\n-#define\tMB25_DC_RLFLUSH\t0x10\t\t/* Clear receive FIFO\t\t */\n-#define\tMB25_DC_IXPE\t0x08\t\t/* Insert xmit payload error\t */\n-#define\tMB25_DC_IXHECE\t0x04\t\t/* Insert Xmit HEC Error\t */\n-#define\tMB25_DC_LB_MASK\t0x03\t\t/* Loopback control mask\t */\n-\n-#define\tMB25_DC_LL\t0x03\t\t/* Line Loopback\t\t */\n-#define\tMB25_DC_PL\t0x02\t\t/* PHY Loopback\t\t\t */\n-#define\tMB25_DC_NM\t0x00\t\t\n-\n-#define FE_MASK \t0x00F0\n-#define FE_MULTI_MODE\t0x0000\n-#define FE_SINGLE_MODE 0x0010 \n-#define FE_UTP_OPTION \t0x0020\n-#define FE_25MBIT_PHY\t0x0040\n-#define FE_DS3_PHY 0x0080 /* DS3 */\n-#define FE_E3_PHY 0x0090 /* E3 */\n-\t\t \n-/*********************** SUNI_PM7345 PHY DEFINE HERE *********************/\n-enum suni_pm7345 {\n-\tSUNI_CONFIG\t\t\t= 0x000, /* SUNI Configuration */\n-\tSUNI_INTR_ENBL\t\t\t= 0x004, /* SUNI Interrupt Enable */\n-\tSUNI_INTR_STAT\t\t\t= 0x008, /* SUNI Interrupt Status */\n-\tSUNI_CONTROL\t\t\t= 0x00c, /* SUNI Control */\n-\tSUNI_ID_RESET\t\t\t= 0x010, /* SUNI Reset and Identity */\n-\tSUNI_DATA_LINK_CTRL\t\t= 0x014,\n-\tSUNI_RBOC_CONF_INTR_ENBL\t= 0x018,\n-\tSUNI_RBOC_STAT\t\t\t= 0x01c,\n-\tSUNI_DS3_FRM_CFG\t\t= 0x020,\n-\tSUNI_DS3_FRM_INTR_ENBL\t\t= 0x024,\n-\tSUNI_DS3_FRM_INTR_STAT\t\t= 0x028,\n-\tSUNI_DS3_FRM_STAT\t\t= 0x02c,\n-\tSUNI_RFDL_CFG\t\t\t= 0x030,\n-\tSUNI_RFDL_ENBL_STAT\t\t= 0x034,\n-\tSUNI_RFDL_STAT\t\t\t= 0x038,\n-\tSUNI_RFDL_DATA\t\t\t= 0x03c,\n-\tSUNI_PMON_CHNG\t\t\t= 0x040,\n-\tSUNI_PMON_INTR_ENBL_STAT\t= 0x044,\n-\t/* SUNI_RESERVED1 (0x13 - 0x11) */\n-\tSUNI_PMON_LCV_EVT_CNT_LSB\t= 0x050,\n-\tSUNI_PMON_LCV_EVT_CNT_MSB\t= 0x054,\n-\tSUNI_PMON_FBE_EVT_CNT_LSB\t= 0x058,\n-\tSUNI_PMON_FBE_EVT_CNT_MSB\t= 0x05c,\n-\tSUNI_PMON_SEZ_DET_CNT_LSB\t= 0x060,\n-\tSUNI_PMON_SEZ_DET_CNT_MSB\t= 0x064,\n-\tSUNI_PMON_PE_EVT_CNT_LSB\t= 0x068,\n-\tSUNI_PMON_PE_EVT_CNT_MSB\t= 0x06c,\n-\tSUNI_PMON_PPE_EVT_CNT_LSB\t= 0x070,\n-\tSUNI_PMON_PPE_EVT_CNT_MSB\t= 0x074,\n-\tSUNI_PMON_FEBE_EVT_CNT_LSB\t= 0x078,\n-\tSUNI_PMON_FEBE_EVT_CNT_MSB\t= 0x07c,\n-\tSUNI_DS3_TRAN_CFG\t\t= 0x080,\n-\tSUNI_DS3_TRAN_DIAG\t\t= 0x084,\n-\t/* SUNI_RESERVED2 (0x23 - 0x21) */\n-\tSUNI_XFDL_CFG\t\t\t= 0x090,\n-\tSUNI_XFDL_INTR_ST\t\t= 0x094,\n-\tSUNI_XFDL_XMIT_DATA\t\t= 0x098,\n-\tSUNI_XBOC_CODE\t\t\t= 0x09c,\n-\tSUNI_SPLR_CFG\t\t\t= 0x0a0,\n-\tSUNI_SPLR_INTR_EN\t\t= 0x0a4,\n-\tSUNI_SPLR_INTR_ST\t\t= 0x0a8,\n-\tSUNI_SPLR_STATUS\t\t= 0x0ac,\n-\tSUNI_SPLT_CFG\t\t\t= 0x0b0,\n-\tSUNI_SPLT_CNTL\t\t\t= 0x0b4,\n-\tSUNI_SPLT_DIAG_G1\t\t= 0x0b8,\n-\tSUNI_SPLT_F1\t\t\t= 0x0bc,\n-\tSUNI_CPPM_LOC_METERS\t\t= 0x0c0,\n-\tSUNI_CPPM_CHG_OF_CPPM_PERF_METR\t= 0x0c4,\n-\tSUNI_CPPM_B1_ERR_CNT_LSB\t= 0x0c8,\n-\tSUNI_CPPM_B1_ERR_CNT_MSB\t= 0x0cc,\n-\tSUNI_CPPM_FRAMING_ERR_CNT_LSB\t= 0x0d0,\n-\tSUNI_CPPM_FRAMING_ERR_CNT_MSB\t= 0x0d4,\n-\tSUNI_CPPM_FEBE_CNT_LSB\t\t= 0x0d8,\n-\tSUNI_CPPM_FEBE_CNT_MSB\t\t= 0x0dc,\n-\tSUNI_CPPM_HCS_ERR_CNT_LSB\t= 0x0e0,\n-\tSUNI_CPPM_HCS_ERR_CNT_MSB\t= 0x0e4,\n-\tSUNI_CPPM_IDLE_UN_CELL_CNT_LSB\t= 0x0e8,\n-\tSUNI_CPPM_IDLE_UN_CELL_CNT_MSB\t= 0x0ec,\n-\tSUNI_CPPM_RCV_CELL_CNT_LSB\t= 0x0f0,\n-\tSUNI_CPPM_RCV_CELL_CNT_MSB\t= 0x0f4,\n-\tSUNI_CPPM_XMIT_CELL_CNT_LSB\t= 0x0f8,\n-\tSUNI_CPPM_XMIT_CELL_CNT_MSB\t= 0x0fc,\n-\tSUNI_RXCP_CTRL\t\t\t= 0x100,\n-\tSUNI_RXCP_FCTRL\t\t\t= 0x104,\n-\tSUNI_RXCP_INTR_EN_STS\t\t= 0x108,\n-\tSUNI_RXCP_IDLE_PAT_H1\t\t= 0x10c,\n-\tSUNI_RXCP_IDLE_PAT_H2\t\t= 0x110,\n-\tSUNI_RXCP_IDLE_PAT_H3\t\t= 0x114,\n-\tSUNI_RXCP_IDLE_PAT_H4\t\t= 0x118,\n-\tSUNI_RXCP_IDLE_MASK_H1\t\t= 0x11c,\n-\tSUNI_RXCP_IDLE_MASK_H2\t\t= 0x120,\n-\tSUNI_RXCP_IDLE_MASK_H3\t\t= 0x124,\n-\tSUNI_RXCP_IDLE_MASK_H4\t\t= 0x128,\n-\tSUNI_RXCP_CELL_PAT_H1\t\t= 0x12c,\n-\tSUNI_RXCP_CELL_PAT_H2\t\t= 0x130,\n-\tSUNI_RXCP_CELL_PAT_H3\t\t= 0x134,\n-\tSUNI_RXCP_CELL_PAT_H4\t\t= 0x138,\n-\tSUNI_RXCP_CELL_MASK_H1\t\t= 0x13c,\n-\tSUNI_RXCP_CELL_MASK_H2\t\t= 0x140,\n-\tSUNI_RXCP_CELL_MASK_H3\t\t= 0x144,\n-\tSUNI_RXCP_CELL_MASK_H4\t\t= 0x148,\n-\tSUNI_RXCP_HCS_CS\t\t= 0x14c,\n-\tSUNI_RXCP_LCD_CNT_THRESHOLD\t= 0x150,\n-\t/* SUNI_RESERVED3 (0x57 - 0x54) */\n-\tSUNI_TXCP_CTRL\t\t\t= 0x160,\n-\tSUNI_TXCP_INTR_EN_STS\t\t= 0x164,\n-\tSUNI_TXCP_IDLE_PAT_H1\t\t= 0x168,\n-\tSUNI_TXCP_IDLE_PAT_H2\t\t= 0x16c,\n-\tSUNI_TXCP_IDLE_PAT_H3\t\t= 0x170,\n-\tSUNI_TXCP_IDLE_PAT_H4\t\t= 0x174,\n-\tSUNI_TXCP_IDLE_PAT_H5\t\t= 0x178,\n-\tSUNI_TXCP_IDLE_PAYLOAD\t\t= 0x17c,\n-\tSUNI_E3_FRM_FRAM_OPTIONS\t= 0x180,\n-\tSUNI_E3_FRM_MAINT_OPTIONS\t= 0x184,\n-\tSUNI_E3_FRM_FRAM_INTR_ENBL\t= 0x188,\n-\tSUNI_E3_FRM_FRAM_INTR_IND_STAT\t= 0x18c,\n-\tSUNI_E3_FRM_MAINT_INTR_ENBL\t= 0x190,\n-\tSUNI_E3_FRM_MAINT_INTR_IND\t= 0x194,\n-\tSUNI_E3_FRM_MAINT_STAT\t\t= 0x198,\n-\tSUNI_RESERVED4\t\t\t= 0x19c,\n-\tSUNI_E3_TRAN_FRAM_OPTIONS\t= 0x1a0,\n-\tSUNI_E3_TRAN_STAT_DIAG_OPTIONS\t= 0x1a4,\n-\tSUNI_E3_TRAN_BIP_8_ERR_MASK\t= 0x1a8,\n-\tSUNI_E3_TRAN_MAINT_ADAPT_OPTS\t= 0x1ac,\n-\tSUNI_TTB_CTRL\t\t\t= 0x1b0,\n-\tSUNI_TTB_TRAIL_TRACE_ID_STAT\t= 0x1b4,\n-\tSUNI_TTB_IND_ADDR\t\t= 0x1b8,\n-\tSUNI_TTB_IND_DATA\t\t= 0x1bc,\n-\tSUNI_TTB_EXP_PAYLOAD_TYPE\t= 0x1c0,\n-\tSUNI_TTB_PAYLOAD_TYPE_CTRL_STAT\t= 0x1c4,\n-\t/* SUNI_PAD5 (0x7f - 0x71) */\n-\tSUNI_MASTER_TEST\t\t= 0x200,\n-\t/* SUNI_PAD6 (0xff - 0x80) */\n-};\n-\n-#define SUNI_PM7345_T suni_pm7345_t\n-#define SUNI_PM7345 0x20 /* Suni chip type */\n-#define SUNI_PM5346 0x30 /* Suni chip type */\n-/*\n- * SUNI_PM7345 Configuration\n- */\n-#define SUNI_PM7345_CLB 0x01 /* Cell loopback */\n-#define SUNI_PM7345_PLB 0x02 /* Payload loopback */\n-#define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */\n-#define SUNI_PM7345_LLB 0x80 /* Line loopback */\n-#define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */\n-#define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */\n-#define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */\n-#define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */\n-/*\n- * DS3 FRMR Interrupt Enable\n- */\n-#define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */\n-#define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */\n-#define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */\n-#define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/\n-#define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */\n-#define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/\n-#define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */\n-#define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */\n- \n-/*\n- * DS3 FRMR Status\n- */\n-#define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */\n-#define SUNI_DS3_REDV 0x40 /* DS3 RED state */\n-#define SUNI_DS3_CBITV 0x20 /* Application ID channel state */\n-#define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/\n-#define SUNI_DS3_IDLV 0x08 /* Idle signal state */\n-#define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/\n-#define SUNI_DS3_OOFV 0x02 /* Out of frame state */\n-#define SUNI_DS3_LOSV 0x01 /* Loss of signal state */\n-\n-/*\n- * E3 FRMR Interrupt/Status\n- */\n-#define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */\n-#define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */\n-#define SUNI_E3_LCVI 0x10 /* Line code violation intr */\n-#define SUNI_E3_COFAI 0x08 /* Change of frame align intr */\n-#define SUNI_E3_OOFI 0x04 /* Out of frame intr status */\n-#define SUNI_E3_LOS 0x02 /* Loss of signal state */\n-#define SUNI_E3_OOF 0x01 /* Out of frame state */\n-\n-/*\n- * E3 FRMR Maintenance Status\n- */\n-#define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/\n-#define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */\n-#define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/\n-\n-/*\n- * RXCP Control/Status\n- */\n-#define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */\n-#define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */\n-#define SUNI_DS3_HCSADD 0x20 /* Add coset poly */\n-#define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/\n-#define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */\n-#define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */\n-#define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */\n-#define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */\n-\n-/*\n- * RXCP Interrupt Enable/Status\n- */\n-#define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */\n-#define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */\n-#define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */\n-#define SUNI_DS3_OOCDI 0x10 /* SYNC state */\n-#define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */\n-#define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */\n-#define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */\n-#define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */\n-\n-///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////\n-\n-/* ia_eeprom define*/\n-#define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/\n-#define MEM_SIZE_128K 0x0000 /* board has 128k buffer */\n-#define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */\n-#define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */\n- /* 0x3 to 0xF are reserved for future */\n-\n-#define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */\n-#define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */\n-#define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */\n-#define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */\n-\n-#define\tNOVRAM_SIZE\t64\n-#define\tCMD_LEN\t\t10\n-\n-/***********\n- *\n- *\tSwitches and defines for header files.\n- *\n- *\tThe following defines are used to turn on and off\n- *\tvarious options in the header files. Primarily useful\n- *\tfor debugging.\n- *\n- ***********/\n-\n-/*\n- * a list of the commands that can be sent to the NOVRAM\n- */\n-\n-#define\tEXTEND\t0x100\n-#define\tIAWRITE\t0x140\n-#define\tIAREAD\t0x180\n-#define\tERASE\t0x1c0\n-\n-#define\tEWDS\t0x00\n-#define\tWRAL\t0x10\n-#define\tERAL\t0x20\n-#define\tEWEN\t0x30\n-\n-/*\n- * these bits duplicate the hw_flip.h register settings\n- * note: how the data in / out bits are defined in the flipper specification \n- */\n-\n-#define\tNVCE\t0x02\n-#define\tNVSK\t0x01\n-#define\tNVDO\t0x08\t\n-#define NVDI\t0x04\n-/***********************\n- *\n- * This define ands the value and the current config register and puts\n- * the result in the config register\n- *\n- ***********************/\n-\n-#define\tCFG_AND(val) { \\\n-\t\tu32 t; \\\n-\t\tt = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \\\n-\t\tt &= (val); \\\n-\t\twritel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \\\n-\t}\n-\n-/***********************\n- *\n- * This define ors the value and the current config register and puts\n- * the result in the config register\n- *\n- ***********************/\n-\n-#define\tCFG_OR(val) { \\\n-\t\tu32 t; \\\n-\t\tt = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \\\n-\t\tt |= (val); \\\n-\t\twritel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \\\n-\t}\n-\n-/***********************\n- *\n- * Send a command to the NOVRAM, the command is in cmd.\n- *\n- * clear CE and SK. Then assert CE.\n- * Clock each of the command bits out in the correct order with SK\n- * exit with CE still asserted\n- *\n- ***********************/\n-\n-#define\tNVRAM_CMD(cmd) { \\\n-\t\tint\ti; \\\n-\t\tu_short c = cmd; \\\n-\t\tCFG_AND(~(NVCE|NVSK)); \\\n-\t\tCFG_OR(NVCE); \\\n-\t\tfor (i=0; ireg+IPHASE5575_EEPROM_ACCESS); \\\n-\t\tvalue = (_t & NVDO) ? 1 : 0; \\\n-\t}\n-\n-\n-#endif /* IPHASE_H */\ndiff --git a/drivers/atm/midway.h b/drivers/atm/midway.h\ndeleted file mode 100644\nindex d47307adc0c9..000000000000\n--- a/drivers/atm/midway.h\n+++ /dev/null\n@@ -1,266 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */\n- \n-/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */\n- \n-\n-#ifndef DRIVERS_ATM_MIDWAY_H\n-#define DRIVERS_ATM_MIDWAY_H\n-\n-\n-#define NR_VCI\t\t1024\t\t/* number of VCIs */\n-#define NR_VCI_LD\t10\t\t/* log2(NR_VCI) */\n-#define NR_DMA_RX\t512\t\t/* RX DMA queue entries */\n-#define NR_DMA_TX\t512\t\t/* TX DMA queue entries */\n-#define NR_SERVICE\tNR_VCI\t\t/* service list size */\n-#define NR_CHAN\t\t8\t\t/* number of TX channels */\n-#define TS_CLOCK\t25000000\t/* traffic shaper clock (cell/sec) */\n-\n-#define MAP_MAX_SIZE\t0x00400000\t/* memory window for max config */\n-#define EPROM_SIZE\t0x00010000\n-#define\tMEM_VALID\t0xffc00000\t/* mask base address with this */\n-#define PHY_BASE\t0x00020000\t/* offset of PHY register are */\n-#define REG_BASE\t0x00040000\t/* offset of Midway register area */\n-#define RAM_BASE\t0x00200000\t/* offset of RAM area */\n-#define RAM_INCREMENT\t0x00020000\t/* probe for RAM every 128kB */\n-\n-#define MID_VCI_BASE\tRAM_BASE\n-#define MID_DMA_RX_BASE\t(MID_VCI_BASE+NR_VCI*16)\n-#define MID_DMA_TX_BASE\t(MID_DMA_RX_BASE+NR_DMA_RX*8)\n-#define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8)\n-#define MID_FREE_BASE\t(MID_SERVICE_BASE+NR_SERVICE*4)\n-\n-#define MAC_LEN 6 /* atm.h */\n-\n-#define MID_MIN_BUF_SIZE (1024)\t\t/* 1 kB is minimum */\n-#define MID_MAX_BUF_SIZE (128*1024)\t/* 128 kB is maximum */\n-\n-#define RX_DESCR_SIZE\t1\t\t/* RX PDU descr is 1 longword */\n-#define TX_DESCR_SIZE\t2\t\t/* TX PDU descr is 2 longwords */\n-#define AAL5_TRAILER\t(ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */\n-\n-#define TX_GAP\t\t8\t\t/* TX buffer gap (words) */\n-\n-/*\n- * Midway Reset/ID\n- *\n- * All values read-only. Writing to this register resets Midway chip.\n- */\n-\n-#define MID_RES_ID_MCON\t0x00\t\t/* Midway Reset/ID */\n-\n-#define MID_ID\t\t0xf0000000\t/* Midway version */\n-#define MID_SHIFT\t24\n-#define MID_MOTHER_ID\t0x00000700\t/* mother board id */\n-#define MID_MOTHER_SHIFT 8\n-#define MID_CON_TI\t0x00000080\t/* 0: normal ctrl; 1: SABRE */\n-#define MID_CON_SUNI\t0x00000040\t/* 0: UTOPIA; 1: SUNI */\n-#define MID_CON_V6\t0x00000020\t/* 0: non-pipel UTOPIA (required iff\n-\t\t\t\t\t !CON_SUNI; 1: UTOPIA */\n-#define DAUGHTER_ID\t0x0000001f\t/* daughter board id */\n-\n-/*\n- * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable\n- */\n-\n-#define MID_ISA\t\t0x01\t\t/* Interrupt Status Acknowledge */\n-#define MID_IS\t\t0x02\t\t/* Interrupt Status */\n-#define MID_IE\t\t0x03\t\t/* Interrupt Enable */\n-\n-#define MID_TX_COMPLETE_7 0x00010000\t/* channel N completed a PDU */\n-#define MID_TX_COMPLETE_6 0x00008000\t/* transmission */\n-#define MID_TX_COMPLETE_5 0x00004000\n-#define MID_TX_COMPLETE_4 0x00002000\n-#define MID_TX_COMPLETE_3 0x00001000\n-#define MID_TX_COMPLETE_2 0x00000800\n-#define MID_TX_COMPLETE_1 0x00000400\n-#define MID_TX_COMPLETE_0 0x00000200\n-#define MID_TX_COMPLETE\t0x0001fe00\t/* any TX */\n-#define MID_TX_DMA_OVFL\t0x00000100\t/* DMA to adapter overflow */\n-#define MID_TX_IDENT_MISM 0x00000080\t/* TX: ident mismatch => halted */\n-#define MID_DMA_LERR_ACK 0x00000040\t/* LERR - SBus ? */\n-#define MID_DMA_ERR_ACK\t0x00000020\t/* DMA error */\n-#define\tMID_RX_DMA_COMPLETE 0x00000010\t/* DMA to host done */\n-#define MID_TX_DMA_COMPLETE 0x00000008\t/* DMA from host done */\n-#define MID_SERVICE\t0x00000004\t/* something in service list */\n-#define MID_SUNI_INT\t0x00000002\t/* interrupt from SUNI */\n-#define MID_STAT_OVFL\t0x00000001\t/* statistics overflow */\n-\n-/*\n- * Master Control/Status\n- */\n-\n-#define MID_MC_S\t0x04\n-\n-#define MID_INT_SELECT\t0x000001C0\t/* Interrupt level (000: off) */\n-#define MID_INT_SEL_SHIFT 6\n-#define\tMID_TX_LOCK_MODE 0x00000020\t/* 0: streaming; 1: TX ovfl->lock */\n-#define MID_DMA_ENABLE\t0x00000010\t/* R: 0: disable; 1: enable\n-\t\t\t\t\t W: 0: no change; 1: enable */\n-#define MID_TX_ENABLE\t0x00000008\t/* R: 0: TX disabled; 1: enabled\n-\t\t\t\t\t W: 0: no change; 1: enable */\n-#define MID_RX_ENABLE\t0x00000004\t/* like TX */\n-#define MID_WAIT_1MS\t0x00000002\t/* R: 0: timer not running; 1: running\n-\t\t\t\t\t W: 0: no change; 1: no interrupts\n-\t\t\t\t\t\t\t for 1 ms */\n-#define MID_WAIT_500US\t0x00000001\t/* like WAIT_1MS, but 0.5 ms */\n-\n-/*\n- * Statistics\n- *\n- * Cleared when reading.\n- */\n-\n-#define MID_STAT\t\t0x05\n-\n-#define MID_VCI_TRASH\t0xFFFF0000\t/* trashed cells because of VCI mode */\n-#define MID_VCI_TRASH_SHIFT 16\n-#define MID_OVFL_TRASH\t0x0000FFFF\t/* trashed cells because of overflow */\n-\n-/*\n- * Address registers\n- */\n-\n-#define MID_SERV_WRITE\t0x06\t/* free pos in service area (R, 10 bits) */\n-#define MID_DMA_ADDR\t0x07\t/* virtual DMA address (R, 32 bits) */\n-#define MID_DMA_WR_RX\t0x08\t/* (RW, 9 bits) */\n-#define MID_DMA_RD_RX\t0x09\n-#define MID_DMA_WR_TX\t0x0A\n-#define MID_DMA_RD_TX\t0x0B\n-\n-/*\n- * Transmit Place Registers (0x10+4*channel)\n- */\n-\n-#define MID_TX_PLACE(c)\t(0x10+4*(c))\n-\n-#define MID_SIZE\t0x00003800\t/* size, N*256 x 32 bit */\n-#define MID_SIZE_SHIFT\t11\n-#define MID_LOCATION\t0x000007FF\t/* location in adapter memory (word) */\n-\n-#define MID_LOC_SKIP\t8\t\t/* 8 bits of location are always zero\n-\t\t\t\t\t (applies to all uses of location) */\n-\n-/*\n- * Transmit ReadPtr Registers (0x11+4*channel)\n- */\n-\n-#define MID_TX_RDPTR(c)\t(0x11+4*(c))\n-\n-#define MID_READ_PTR\t0x00007FFF\t/* next word for PHY */\n-\n-/*\n- * Transmit DescrStart Registers (0x12+4*channel)\n- */\n-\n-#define MID_TX_DESCRSTART(c) (0x12+4*(c))\n-\n-#define MID_DESCR_START\t0x00007FFF\t/* seg buffer being DMAed */\n-\n-#define ENI155_MAGIC\t0xa54b872d\n-\n-struct midway_eprom {\n-\tunsigned char mac[MAC_LEN],inv_mac[MAC_LEN];\n-\tunsigned char pad[36];\n-\tu32 serial,inv_serial;\n-\tu32 magic,inv_magic;\n-};\n-\n-\n-/*\n- * VCI table entry\n- */\n-\n-#define MID_VCI_IN_SERVICE\t0x00000001\t/* set if VCI is currently in\n-\t\t\t\t\t\t service list */\n-#define MID_VCI_SIZE\t\t0x00038000\t/* reassembly buffer size,\n-\t\t\t\t\t\t 2* kB */\n-#define MID_VCI_SIZE_SHIFT\t15\n-#define MID_VCI_LOCATION\t0x1ffc0000\t/* buffer location */\n-#define MID_VCI_LOCATION_SHIFT\t18\n-#define MID_VCI_PTI_MODE\t0x20000000\t/* 0: trash, 1: preserve */\n-#define MID_VCI_MODE\t\t0xc0000000\n-#define MID_VCI_MODE_SHIFT\t30\n-#define MID_VCI_READ\t\t0x00007fff\n-#define MID_VCI_READ_SHIFT\t0\n-#define MID_VCI_DESCR\t\t0x7fff0000\n-#define MID_VCI_DESCR_SHIFT\t16\n-#define MID_VCI_COUNT\t\t0x000007ff\n-#define MID_VCI_COUNT_SHIFT\t0\n-#define MID_VCI_STATE\t\t0x0000c000\n-#define MID_VCI_STATE_SHIFT\t14\n-#define MID_VCI_WRITE\t\t0x7fff0000\n-#define MID_VCI_WRITE_SHIFT\t16\n-\n-#define MID_MODE_TRASH\t0\n-#define MID_MODE_RAW\t1\n-#define MID_MODE_AAL5\t2\n-\n-/*\n- * Reassembly buffer descriptor\n- */\n-\n-#define MID_RED_COUNT\t\t0x000007ff\n-#define MID_RED_CRC_ERR\t\t0x00000800\n-#define MID_RED_T\t\t0x00001000\n-#define MID_RED_CE\t\t0x00010000\n-#define MID_RED_CLP\t\t0x01000000\n-#define MID_RED_IDEN\t\t0xfe000000\n-#define MID_RED_SHIFT\t\t25\n-\n-#define MID_RED_RX_ID\t\t0x1b\t\t/* constant identifier */\n-\n-/*\n- * Segmentation buffer descriptor\n- */\n-\n-#define MID_SEG_COUNT\t\tMID_RED_COUNT\n-#define MID_SEG_RATE\t\t0x01f80000\n-#define MID_SEG_RATE_SHIFT\t19\n-#define MID_SEG_PR\t\t0x06000000\n-#define MID_SEG_PR_SHIFT\t25\n-#define MID_SEG_AAL5\t\t0x08000000\n-#define MID_SEG_ID\t\t0xf0000000\n-#define MID_SEG_ID_SHIFT\t28\n-#define MID_SEG_MAX_RATE\t63\n-\n-#define MID_SEG_CLP\t\t0x00000001\n-#define MID_SEG_PTI\t\t0x0000000e\n-#define MID_SEG_PTI_SHIFT\t1\n-#define MID_SEG_VCI\t\t0x00003ff0\n-#define MID_SEG_VCI_SHIFT\t4\n-\n-#define MID_SEG_TX_ID\t\t0xb\t\t/* constant identifier */\n-\n-/*\n- * DMA entry\n- */\n-\n-#define MID_DMA_COUNT\t\t0xffff0000\n-#define MID_DMA_COUNT_SHIFT\t16\n-#define MID_DMA_END\t\t0x00000020\n-#define MID_DMA_TYPE\t\t0x0000000f\n-\n-#define MID_DT_JK\t0x3\n-#define MID_DT_WORD\t0x0\n-#define MID_DT_2W\t0x7\n-#define MID_DT_4W\t0x4\n-#define MID_DT_8W\t0x5\n-#define MID_DT_16W\t0x6\n-#define MID_DT_2WM\t0xf\n-#define MID_DT_4WM\t0xc\n-#define MID_DT_8WM\t0xd\n-#define MID_DT_16WM\t0xe\n-\n-/* only for RX*/\n-#define MID_DMA_VCI\t\t0x0000ffc0\n-#define\tMID_DMA_VCI_SHIFT\t6\n-\n-/* only for TX */\n-#define MID_DMA_CHAN\t\t0x000001c0\n-#define MID_DMA_CHAN_SHIFT\t6\n-\n-#define MID_DT_BYTE\t0x1\n-#define MID_DT_HWORD\t0x2\n-\n-#endif\ndiff --git a/drivers/atm/nicstar.h b/drivers/atm/nicstar.h\ndeleted file mode 100644\nindex 1b7f1dfc1735..000000000000\n--- a/drivers/atm/nicstar.h\n+++ /dev/null\n@@ -1,759 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/*\n- * nicstar.h\n- *\n- * Header file for the nicstar device driver.\n- *\n- * Author: Rui Prior (rprior@inescn.pt)\n- * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999\n- *\n- * (C) INESC 1998\n- */\n-\n-#ifndef _LINUX_NICSTAR_H_\n-#define _LINUX_NICSTAR_H_\n-\n-/* Includes */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-/* Options */\n-\n-#define NS_MAX_CARDS 4\t\t/* Maximum number of NICStAR based cards\n-\t\t\t\t controlled by the device driver. Must\n-\t\t\t\t be <= 5 */\n-\n-#undef RCQ_SUPPORT\t\t/* Do not define this for now */\n-\n-#define NS_TST_NUM_ENTRIES 2340\t/* + 1 for return */\n-#define NS_TST_RESERVED 340\t/* N. entries reserved for UBR/ABR/VBR */\n-\n-#define NS_SMBUFSIZE 48\t\t/* 48, 96, 240 or 2048 */\n-#define NS_LGBUFSIZE 16384\t/* 2048, 4096, 8192 or 16384 */\n-#define NS_RSQSIZE 8192\t\t/* 2048, 4096 or 8192 */\n-#define NS_VPIBITS 2\t\t/* 0, 1, 2, or 8 */\n-\n-#define NS_MAX_RCTSIZE 4096\t/* Number of entries. 4096 or 16384.\n-\t\t\t\t Define 4096 only if (all) your card(s)\n-\t\t\t\t have 32K x 32bit SRAM, in which case\n-\t\t\t\t setting this to 16384 will just waste a\n-\t\t\t\t lot of memory.\n-\t\t\t\t Setting this to 4096 for a card with\n-\t\t\t\t 128K x 32bit SRAM will limit the maximum\n-\t\t\t\t VCI. */\n-\n-\t\t\t\t/*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */\n-\n-\t/* Number of buffers initially allocated */\n-#define NUM_SB 32\t\t/* Must be even */\n-#define NUM_LB 24\t\t/* Must be even */\n-#define NUM_HB 8\t\t/* Pre-allocated huge buffers */\n-#define NUM_IOVB 48\t\t/* Iovec buffers */\n-\n-\t/* Lower level for count of buffers */\n-#define MIN_SB 8\t\t/* Must be even */\n-#define MIN_LB 8\t\t/* Must be even */\n-#define MIN_HB 6\n-#define MIN_IOVB 8\n-\n-\t/* Upper level for count of buffers */\n-#define MAX_SB 64\t\t/* Must be even, <= 508 */\n-#define MAX_LB 48\t\t/* Must be even, <= 508 */\n-#define MAX_HB 10\n-#define MAX_IOVB 80\n-\n-\t/* These are the absolute maximum allowed for the ioctl() */\n-#define TOP_SB 256\t\t/* Must be even, <= 508 */\n-#define TOP_LB 128\t\t/* Must be even, <= 508 */\n-#define TOP_HB 64\n-#define TOP_IOVB 256\n-\n-#define MAX_TBD_PER_VC 1\t/* Number of TBDs before a TSR */\n-#define MAX_TBD_PER_SCQ 10\t/* Only meaningful for variable rate SCQs */\n-\n-#undef ENABLE_TSQFIE\n-\n-#define SCQFULL_TIMEOUT (5 * HZ)\n-\n-#define NS_POLL_PERIOD (HZ)\n-\n-#define PCR_TOLERANCE (1.0001)\n-\n-/* ESI stuff */\n-\n-#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C\n-#define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6\n-\n-/* #defines */\n-\n-#define NS_IOREMAP_SIZE 4096\n-\n-/*\n- * BUF_XX distinguish the Rx buffers depending on their (small/large) size.\n- * BUG_SM and BUG_LG are both used by the driver and the device.\n- * BUF_NONE is only used by the driver.\n- */\n-#define BUF_SM\t\t0x00000000\t/* These two are used for push_rxbufs() */\n-#define BUF_LG\t\t0x00000001\t/* CMD, Write_FreeBufQ, LBUF bit */\n-#define BUF_NONE \t0xffffffff\t/* Software only: */\n-\n-#define NS_HBUFSIZE 65568\t/* Size of max. AAL5 PDU */\n-#define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \\\n- (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))\n-#define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))\n-\n-#define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)\n-#define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)\n-\n-#define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD)\t/* 4 bytes */\n-\n-#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)\n-#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)\n-\n-/* NICStAR structures located in host memory */\n-\n-/*\n- * RSQ - Receive Status Queue\n- *\n- * Written by the NICStAR, read by the device driver.\n- */\n-\n-typedef struct ns_rsqe {\n-\tu32 word_1;\n-\tu32 buffer_handle;\n-\tu32 final_aal5_crc32;\n-\tu32 word_4;\n-} ns_rsqe;\n-\n-#define ns_rsqe_vpi(ns_rsqep) \\\n- ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)\n-#define ns_rsqe_vci(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)\n-\n-#define NS_RSQE_VALID 0x80000000\n-#define NS_RSQE_NZGFC 0x00004000\n-#define NS_RSQE_EOPDU 0x00002000\n-#define NS_RSQE_BUFSIZE 0x00001000\n-#define NS_RSQE_CONGESTION 0x00000800\n-#define NS_RSQE_CLP 0x00000400\n-#define NS_RSQE_CRCERR 0x00000200\n-\n-#define NS_RSQE_BUFSIZE_SM 0x00000000\n-#define NS_RSQE_BUFSIZE_LG 0x00001000\n-\n-#define ns_rsqe_valid(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)\n-#define ns_rsqe_nzgfc(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)\n-#define ns_rsqe_eopdu(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)\n-#define ns_rsqe_bufsize(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)\n-#define ns_rsqe_congestion(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)\n-#define ns_rsqe_clp(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)\n-#define ns_rsqe_crcerr(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)\n-\n-#define ns_rsqe_cellcount(ns_rsqep) \\\n- (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)\n-#define ns_rsqe_init(ns_rsqep) \\\n- ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))\n-\n-#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)\n-#define NS_RSQ_ALIGNMENT NS_RSQSIZE\n-\n-/*\n- * RCQ - Raw Cell Queue\n- *\n- * Written by the NICStAR, read by the device driver.\n- */\n-\n-typedef struct cell_payload {\n-\tu32 word[12];\n-} cell_payload;\n-\n-typedef struct ns_rcqe {\n-\tu32 word_1;\n-\tu32 word_2;\n-\tu32 word_3;\n-\tu32 word_4;\n-\tcell_payload payload;\n-} ns_rcqe;\n-\n-#define NS_RCQE_SIZE 64\t\t/* bytes */\n-\n-#define ns_rcqe_islast(ns_rcqep) \\\n- (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)\n-#define ns_rcqe_cellheader(ns_rcqep) \\\n- (le32_to_cpu((ns_rcqep)->word_1))\n-#define ns_rcqe_nextbufhandle(ns_rcqep) \\\n- (le32_to_cpu((ns_rcqep)->word_2))\n-\n-/*\n- * SCQ - Segmentation Channel Queue\n- *\n- * Written by the device driver, read by the NICStAR.\n- */\n-\n-typedef struct ns_scqe {\n-\tu32 word_1;\n-\tu32 word_2;\n-\tu32 word_3;\n-\tu32 word_4;\n-} ns_scqe;\n-\n- /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)\n- or TSR (Transmit Status Requests) */\n-\n-#define NS_SCQE_TYPE_TBD 0x00000000\n-#define NS_SCQE_TYPE_TSR 0x80000000\n-\n-#define NS_TBD_EOPDU 0x40000000\n-#define NS_TBD_AAL0 0x00000000\n-#define NS_TBD_AAL34 0x04000000\n-#define NS_TBD_AAL5 0x08000000\n-\n-#define NS_TBD_VPI_MASK 0x0FF00000\n-#define NS_TBD_VCI_MASK 0x000FFFF0\n-#define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)\n-\n-#define NS_TBD_VPI_SHIFT 20\n-#define NS_TBD_VCI_SHIFT 4\n-\n-#define ns_tbd_mkword_1(flags, m, n, buflen) \\\n- (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))\n-#define ns_tbd_mkword_1_novbr(flags, buflen) \\\n- (cpu_to_le32((flags) | (buflen) | 0x00810000))\n-#define ns_tbd_mkword_3(control, pdulen) \\\n- (cpu_to_le32((control) << 16 | (pdulen)))\n-#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \\\n- (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))\n-\n-#define NS_TSR_INTENABLE 0x20000000\n-\n-#define NS_TSR_SCDISVBR 0xFFFF\t/* Use as scdi for VBR SCD */\n-\n-#define ns_tsr_mkword_1(flags) \\\n- (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))\n-#define ns_tsr_mkword_2(scdi, scqi) \\\n- (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))\n-\n-#define ns_scqe_is_tsr(ns_scqep) \\\n- (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)\n-\n-#define VBR_SCQ_NUM_ENTRIES 512\n-#define VBR_SCQSIZE 8192\n-#define CBR_SCQ_NUM_ENTRIES 64\n-#define CBR_SCQSIZE 1024\n-\n-#define NS_SCQE_SIZE 16\n-\n-/*\n- * TSQ - Transmit Status Queue\n- *\n- * Written by the NICStAR, read by the device driver.\n- */\n-\n-typedef struct ns_tsi {\n-\tu32 word_1;\n-\tu32 word_2;\n-} ns_tsi;\n-\n- /* NOTE: The first word can be a status word copied from the TSR which\n- originated the TSI, or a timer overflow indicator. In this last\n- case, the value of the first word is all zeroes. */\n-\n-#define NS_TSI_EMPTY 0x80000000\n-#define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF\n-\n-#define ns_tsi_isempty(ns_tsip) \\\n- (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)\n-#define ns_tsi_gettimestamp(ns_tsip) \\\n- (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)\n-\n-#define ns_tsi_init(ns_tsip) \\\n- ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))\n-\n-#define NS_TSQSIZE 8192\n-#define NS_TSQ_NUM_ENTRIES 1024\n-#define NS_TSQ_ALIGNMENT 8192\n-\n-#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR\n-\n-#define ns_tsi_tmrof(ns_tsip) \\\n- (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)\n-#define ns_tsi_getscdindex(ns_tsip) \\\n- ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)\n-#define ns_tsi_getscqpos(ns_tsip) \\\n- (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)\n-\n-/* NICStAR structures located in local SRAM */\n-\n-/*\n- * RCT - Receive Connection Table\n- *\n- * Written by both the NICStAR and the device driver.\n- */\n-\n-typedef struct ns_rcte {\n-\tu32 word_1;\n-\tu32 buffer_handle;\n-\tu32 dma_address;\n-\tu32 aal5_crc32;\n-} ns_rcte;\n-\n-#define NS_RCTE_BSFB 0x00200000\t/* Rev. D only */\n-#define NS_RCTE_NZGFC 0x00100000\n-#define NS_RCTE_CONNECTOPEN 0x00080000\n-#define NS_RCTE_AALMASK 0x00070000\n-#define NS_RCTE_AAL0 0x00000000\n-#define NS_RCTE_AAL34 0x00010000\n-#define NS_RCTE_AAL5 0x00020000\n-#define NS_RCTE_RCQ 0x00030000\n-#define NS_RCTE_RAWCELLINTEN 0x00008000\n-#define NS_RCTE_RXCONSTCELLADDR 0x00004000\n-#define NS_RCTE_BUFFVALID 0x00002000\n-#define NS_RCTE_FBDSIZE 0x00001000\n-#define NS_RCTE_EFCI 0x00000800\n-#define NS_RCTE_CLP 0x00000400\n-#define NS_RCTE_CRCERROR 0x00000200\n-#define NS_RCTE_CELLCOUNT_MASK 0x000001FF\n-\n-#define NS_RCTE_FBDSIZE_SM 0x00000000\n-#define NS_RCTE_FBDSIZE_LG 0x00001000\n-\n-#define NS_RCT_ENTRY_SIZE 4\t/* Number of dwords */\n-\n- /* NOTE: We could make macros to contruct the first word of the RCTE,\n- but that doesn't seem to make much sense... */\n-\n-/*\n- * FBD - Free Buffer Descriptor\n- *\n- * Written by the device driver using via the command register.\n- */\n-\n-typedef struct ns_fbd {\n-\tu32 buffer_handle;\n-\tu32 dma_address;\n-} ns_fbd;\n-\n-/*\n- * TST - Transmit Schedule Table\n- *\n- * Written by the device driver.\n- */\n-\n-typedef u32 ns_tste;\n-\n-#define NS_TST_OPCODE_MASK 0x60000000\n-\n-#define NS_TST_OPCODE_NULL 0x00000000\t/* Insert null cell */\n-#define NS_TST_OPCODE_FIXED 0x20000000\t/* Cell from a fixed rate channel */\n-#define NS_TST_OPCODE_VARIABLE 0x40000000\n-#define NS_TST_OPCODE_END 0x60000000\t/* Jump */\n-\n-#define ns_tste_make(opcode, sramad) (opcode | sramad)\n-\n- /* NOTE:\n-\n- - When the opcode is FIXED, sramad specifies the SRAM address of the\n- SCD for that fixed rate channel.\n- - When the opcode is END, sramad specifies the SRAM address of the\n- location of the next TST entry to read.\n- */\n-\n-/*\n- * SCD - Segmentation Channel Descriptor\n- *\n- * Written by both the device driver and the NICStAR\n- */\n-\n-typedef struct ns_scd {\n-\tu32 word_1;\n-\tu32 word_2;\n-\tu32 partial_aal5_crc;\n-\tu32 reserved;\n-\tns_scqe cache_a;\n-\tns_scqe cache_b;\n-} ns_scd;\n-\n-#define NS_SCD_BASE_MASK_VAR 0xFFFFE000\t/* Variable rate */\n-#define NS_SCD_BASE_MASK_FIX 0xFFFFFC00\t/* Fixed rate */\n-#define NS_SCD_TAIL_MASK_VAR 0x00001FF0\n-#define NS_SCD_TAIL_MASK_FIX 0x000003F0\n-#define NS_SCD_HEAD_MASK_VAR 0x00001FF0\n-#define NS_SCD_HEAD_MASK_FIX 0x000003F0\n-#define NS_SCD_XMITFOREVER 0x02000000\n-\n- /* NOTE: There are other fields in word 2 of the SCD, but as they should\n- not be needed in the device driver they are not defined here. */\n-\n-/* NICStAR local SRAM memory map */\n-\n-#define NS_RCT 0x00000\n-#define NS_RCT_32_END 0x03FFF\n-#define NS_RCT_128_END 0x0FFFF\n-#define NS_UNUSED_32 0x04000\n-#define NS_UNUSED_128 0x10000\n-#define NS_UNUSED_END 0x1BFFF\n-#define NS_TST_FRSCD 0x1C000\n-#define NS_TST_FRSCD_END 0x1E7DB\n-#define NS_VRSCD2 0x1E7DC\n-#define NS_VRSCD2_END 0x1E7E7\n-#define NS_VRSCD1 0x1E7E8\n-#define NS_VRSCD1_END 0x1E7F3\n-#define NS_VRSCD0 0x1E7F4\n-#define NS_VRSCD0_END 0x1E7FF\n-#define NS_RXFIFO 0x1E800\n-#define NS_RXFIFO_END 0x1F7FF\n-#define NS_SMFBQ 0x1F800\n-#define NS_SMFBQ_END 0x1FBFF\n-#define NS_LGFBQ 0x1FC00\n-#define NS_LGFBQ_END 0x1FFFF\n-\n-/* NISCtAR operation registers */\n-\n-/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */\n-\n-enum ns_regs {\n-\tDR0 = 0x00,\t\t/* Data Register 0 R/W */\n-\tDR1 = 0x04,\t\t/* Data Register 1 W */\n-\tDR2 = 0x08,\t\t/* Data Register 2 W */\n-\tDR3 = 0x0C,\t\t/* Data Register 3 W */\n-\tCMD = 0x10,\t\t/* Command W */\n-\tCFG = 0x14,\t\t/* Configuration R/W */\n-\tSTAT = 0x18,\t\t/* Status R/W */\n-\tRSQB = 0x1C,\t\t/* Receive Status Queue Base W */\n-\tRSQT = 0x20,\t\t/* Receive Status Queue Tail R */\n-\tRSQH = 0x24,\t\t/* Receive Status Queue Head W */\n-\tCDC = 0x28,\t\t/* Cell Drop Counter R/clear */\n-\tVPEC = 0x2C,\t\t/* VPI/VCI Lookup Error Count R/clear */\n-\tICC = 0x30,\t\t/* Invalid Cell Count R/clear */\n-\tRAWCT = 0x34,\t\t/* Raw Cell Tail R */\n-\tTMR = 0x38,\t\t/* Timer R */\n-\tTSTB = 0x3C,\t\t/* Transmit Schedule Table Base R/W */\n-\tTSQB = 0x40,\t\t/* Transmit Status Queue Base W */\n-\tTSQT = 0x44,\t\t/* Transmit Status Queue Tail R */\n-\tTSQH = 0x48,\t\t/* Transmit Status Queue Head W */\n-\tGP = 0x4C,\t\t/* General Purpose R/W */\n-\tVPM = 0x50\t\t/* VPI/VCI Mask W */\n-};\n-\n-/* NICStAR commands issued to the CMD register */\n-\n-/* Top 4 bits are command opcode, lower 28 are parameters. */\n-\n-#define NS_CMD_NO_OPERATION 0x00000000\n-\t/* params always 0 */\n-\n-#define NS_CMD_OPENCLOSE_CONNECTION 0x20000000\n-\t/* b19{1=open,0=close} b18-2{SRAM addr} */\n-\n-#define NS_CMD_WRITE_SRAM 0x40000000\n-\t/* b18-2{SRAM addr} b1-0{burst size} */\n-\n-#define NS_CMD_READ_SRAM 0x50000000\n-\t/* b18-2{SRAM addr} */\n-\n-#define NS_CMD_WRITE_FREEBUFQ 0x60000000\n-\t/* b0{large buf indicator} */\n-\n-#define NS_CMD_READ_UTILITY 0x80000000\n-\t/* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */\n-\n-#define NS_CMD_WRITE_UTILITY 0x90000000\n-\t/* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */\n-\n-#define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)\n-#define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION\n-\n-/* NICStAR configuration bits */\n-\n-#define NS_CFG_SWRST 0x80000000\t/* Software Reset */\n-#define NS_CFG_RXPATH 0x20000000\t/* Receive Path Enable */\n-#define NS_CFG_SMBUFSIZE_MASK 0x18000000\t/* Small Receive Buffer Size */\n-#define NS_CFG_LGBUFSIZE_MASK 0x06000000\t/* Large Receive Buffer Size */\n-#define NS_CFG_EFBIE 0x01000000\t/* Empty Free Buffer Queue\n-\t\t\t\t\t\t Interrupt Enable */\n-#define NS_CFG_RSQSIZE_MASK 0x00C00000\t/* Receive Status Queue Size */\n-#define NS_CFG_ICACCEPT 0x00200000\t/* Invalid Cell Accept */\n-#define NS_CFG_IGNOREGFC 0x00100000\t/* Ignore General Flow Control */\n-#define NS_CFG_VPIBITS_MASK 0x000C0000\t/* VPI/VCI Bits Size Select */\n-#define NS_CFG_RCTSIZE_MASK 0x00030000\t/* Receive Connection Table Size */\n-#define NS_CFG_VCERRACCEPT 0x00008000\t/* VPI/VCI Error Cell Accept */\n-#define NS_CFG_RXINT_MASK 0x00007000\t/* End of Receive PDU Interrupt\n-\t\t\t\t\t\t Handling */\n-#define NS_CFG_RAWIE 0x00000800\t/* Raw Cell Qu' Interrupt Enable */\n-#define NS_CFG_RSQAFIE 0x00000400\t/* Receive Queue Almost Full\n-\t\t\t\t\t\t Interrupt Enable */\n-#define NS_CFG_RXRM 0x00000200\t/* Receive RM Cells */\n-#define NS_CFG_TMRROIE 0x00000080\t/* Timer Roll Over Interrupt\n-\t\t\t\t\t\t Enable */\n-#define NS_CFG_TXEN 0x00000020\t/* Transmit Operation Enable */\n-#define NS_CFG_TXIE 0x00000010\t/* Transmit Status Interrupt\n-\t\t\t\t\t\t Enable */\n-#define NS_CFG_TXURIE 0x00000008\t/* Transmit Under-run Interrupt\n-\t\t\t\t\t\t Enable */\n-#define NS_CFG_UMODE 0x00000004\t/* Utopia Mode (cell/byte) Select */\n-#define NS_CFG_TSQFIE 0x00000002\t/* Transmit Status Queue Full\n-\t\t\t\t\t\t Interrupt Enable */\n-#define NS_CFG_PHYIE 0x00000001\t/* PHY Interrupt Enable */\n-\n-#define NS_CFG_SMBUFSIZE_48 0x00000000\n-#define NS_CFG_SMBUFSIZE_96 0x08000000\n-#define NS_CFG_SMBUFSIZE_240 0x10000000\n-#define NS_CFG_SMBUFSIZE_2048 0x18000000\n-\n-#define NS_CFG_LGBUFSIZE_2048 0x00000000\n-#define NS_CFG_LGBUFSIZE_4096 0x02000000\n-#define NS_CFG_LGBUFSIZE_8192 0x04000000\n-#define NS_CFG_LGBUFSIZE_16384 0x06000000\n-\n-#define NS_CFG_RSQSIZE_2048 0x00000000\n-#define NS_CFG_RSQSIZE_4096 0x00400000\n-#define NS_CFG_RSQSIZE_8192 0x00800000\n-\n-#define NS_CFG_VPIBITS_0 0x00000000\n-#define NS_CFG_VPIBITS_1 0x00040000\n-#define NS_CFG_VPIBITS_2 0x00080000\n-#define NS_CFG_VPIBITS_8 0x000C0000\n-\n-#define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000\n-#define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000\n-#define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000\n-\n-#define NS_CFG_RXINT_NOINT 0x00000000\n-#define NS_CFG_RXINT_NODELAY 0x00001000\n-#define NS_CFG_RXINT_314US 0x00002000\n-#define NS_CFG_RXINT_624US 0x00003000\n-#define NS_CFG_RXINT_899US 0x00004000\n-\n-/* NICStAR STATus bits */\n-\n-#define NS_STAT_SFBQC_MASK 0xFF000000\t/* hi 8 bits Small Buffer Queue Count */\n-#define NS_STAT_LFBQC_MASK 0x00FF0000\t/* hi 8 bits Large Buffer Queue Count */\n-#define NS_STAT_TSIF 0x00008000\t/* Transmit Status Queue Indicator */\n-#define NS_STAT_TXICP 0x00004000\t/* Transmit Incomplete PDU */\n-#define NS_STAT_TSQF 0x00001000\t/* Transmit Status Queue Full */\n-#define NS_STAT_TMROF 0x00000800\t/* Timer Overflow */\n-#define NS_STAT_PHYI 0x00000400\t/* PHY Device Interrupt */\n-#define NS_STAT_CMDBZ 0x00000200\t/* Command Busy */\n-#define NS_STAT_SFBQF 0x00000100\t/* Small Buffer Queue Full */\n-#define NS_STAT_LFBQF 0x00000080\t/* Large Buffer Queue Full */\n-#define NS_STAT_RSQF 0x00000040\t/* Receive Status Queue Full */\n-#define NS_STAT_EOPDU 0x00000020\t/* End of PDU */\n-#define NS_STAT_RAWCF 0x00000010\t/* Raw Cell Flag */\n-#define NS_STAT_SFBQE 0x00000008\t/* Small Buffer Queue Empty */\n-#define NS_STAT_LFBQE 0x00000004\t/* Large Buffer Queue Empty */\n-#define NS_STAT_RSQAF 0x00000002\t/* Receive Status Queue Almost Full */\n-\n-#define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)\n-#define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)\n-\n-/* #defines which depend on other #defines */\n-\n-#define NS_TST0 NS_TST_FRSCD\n-#define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)\n-\n-#define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)\n-#define NS_FRSCD_SIZE 12\t/* 12 dwords */\n-#define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)\n-\n-#if (NS_SMBUFSIZE == 48)\n-#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48\n-#elif (NS_SMBUFSIZE == 96)\n-#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96\n-#elif (NS_SMBUFSIZE == 240)\n-#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240\n-#elif (NS_SMBUFSIZE == 2048)\n-#define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048\n-#else\n-#error NS_SMBUFSIZE is incorrect in nicstar.h\n-#endif /* NS_SMBUFSIZE */\n-\n-#if (NS_LGBUFSIZE == 2048)\n-#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048\n-#elif (NS_LGBUFSIZE == 4096)\n-#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096\n-#elif (NS_LGBUFSIZE == 8192)\n-#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192\n-#elif (NS_LGBUFSIZE == 16384)\n-#define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384\n-#else\n-#error NS_LGBUFSIZE is incorrect in nicstar.h\n-#endif /* NS_LGBUFSIZE */\n-\n-#if (NS_RSQSIZE == 2048)\n-#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048\n-#elif (NS_RSQSIZE == 4096)\n-#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096\n-#elif (NS_RSQSIZE == 8192)\n-#define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192\n-#else\n-#error NS_RSQSIZE is incorrect in nicstar.h\n-#endif /* NS_RSQSIZE */\n-\n-#if (NS_VPIBITS == 0)\n-#define NS_CFG_VPIBITS NS_CFG_VPIBITS_0\n-#elif (NS_VPIBITS == 1)\n-#define NS_CFG_VPIBITS NS_CFG_VPIBITS_1\n-#elif (NS_VPIBITS == 2)\n-#define NS_CFG_VPIBITS NS_CFG_VPIBITS_2\n-#elif (NS_VPIBITS == 8)\n-#define NS_CFG_VPIBITS NS_CFG_VPIBITS_8\n-#else\n-#error NS_VPIBITS is incorrect in nicstar.h\n-#endif /* NS_VPIBITS */\n-\n-#ifdef RCQ_SUPPORT\n-#define NS_CFG_RAWIE_OPT NS_CFG_RAWIE\n-#else\n-#define NS_CFG_RAWIE_OPT 0x00000000\n-#endif /* RCQ_SUPPORT */\n-\n-#ifdef ENABLE_TSQFIE\n-#define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE\n-#else\n-#define NS_CFG_TSQFIE_OPT 0x00000000\n-#endif /* ENABLE_TSQFIE */\n-\n-/* PCI stuff */\n-\n-#ifndef PCI_VENDOR_ID_IDT\n-#define PCI_VENDOR_ID_IDT 0x111D\n-#endif /* PCI_VENDOR_ID_IDT */\n-\n-#ifndef PCI_DEVICE_ID_IDT_IDT77201\n-#define PCI_DEVICE_ID_IDT_IDT77201 0x0001\n-#endif /* PCI_DEVICE_ID_IDT_IDT77201 */\n-\n-/* Device driver structures */\n-\n-struct ns_skb_prv {\n-\tu32 buf_type;\t\t/* BUF_SM/BUF_LG/BUF_NONE */\n-\tu32 dma;\n-\tint iovcnt;\n-};\n-\n-#define NS_PRV_BUFTYPE(skb) \\\n- (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->buf_type)\n-#define NS_PRV_DMA(skb) \\\n- (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->dma)\n-#define NS_PRV_IOVCNT(skb) \\\n- (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->iovcnt)\n-\n-typedef struct tsq_info {\n-\tvoid *org;\n- dma_addr_t dma;\n-\tns_tsi *base;\n-\tns_tsi *next;\n-\tns_tsi *last;\n-} tsq_info;\n-\n-typedef struct scq_info {\n-\tvoid *org;\n-\tdma_addr_t dma;\n-\tns_scqe *base;\n-\tns_scqe *last;\n-\tns_scqe *next;\n-\tvolatile ns_scqe *tail;\t/* Not related to the nicstar register */\n-\tunsigned num_entries;\n-\tstruct sk_buff **skb;\t/* Pointer to an array of pointers\n-\t\t\t\t to the sk_buffs used for tx */\n-\tu32 scd;\t\t/* SRAM address of the corresponding\n-\t\t\t\t SCD */\n-\tint tbd_count;\t\t/* Only meaningful on variable rate */\n-\twait_queue_head_t scqfull_waitq;\n-\tvolatile char full;\t/* SCQ full indicator */\n-\tspinlock_t lock;\t/* SCQ spinlock */\n-} scq_info;\n-\n-typedef struct rsq_info {\n-\tvoid *org;\n- dma_addr_t dma;\n-\tns_rsqe *base;\n-\tns_rsqe *next;\n-\tns_rsqe *last;\n-} rsq_info;\n-\n-typedef struct skb_pool {\n-\tvolatile int count;\t/* number of buffers in the queue */\n-\tstruct sk_buff_head queue;\n-} skb_pool;\n-\n-/* NOTE: for small and large buffer pools, the count is not used, as the\n- actual value used for buffer management is the one read from the\n-\t card. */\n-\n-typedef struct vc_map {\n-\tvolatile unsigned int tx:1;\t/* TX vc? */\n-\tvolatile unsigned int rx:1;\t/* RX vc? */\n-\tstruct atm_vcc *tx_vcc, *rx_vcc;\n-\tstruct sk_buff *rx_iov;\t/* RX iovector skb */\n-\tscq_info *scq;\t\t/* To keep track of the SCQ */\n-\tu32 cbr_scd;\t\t/* SRAM address of the corresponding\n-\t\t\t\t SCD. 0x00000000 for UBR/VBR/ABR */\n-\tint tbd_count;\n-} vc_map;\n-\n-typedef struct ns_dev {\n-\tint index;\t\t/* Card ID to the device driver */\n-\tint sram_size;\t\t/* In k x 32bit words. 32 or 128 */\n-\tvoid __iomem *membase;\t/* Card's memory base address */\n-\tunsigned long max_pcr;\n-\tint rct_size;\t\t/* Number of entries */\n-\tint vpibits;\n-\tint vcibits;\n-\tstruct pci_dev *pcidev;\n-\tstruct idr idr;\n-\tstruct atm_dev *atmdev;\n-\ttsq_info tsq;\n-\trsq_info rsq;\n-\tscq_info *scq0, *scq1, *scq2;\t/* VBR SCQs */\n-\tskb_pool sbpool;\t/* Small buffers */\n-\tskb_pool lbpool;\t/* Large buffers */\n-\tskb_pool hbpool;\t/* Pre-allocated huge buffers */\n-\tskb_pool iovpool;\t/* iovector buffers */\n-\tvolatile int efbie;\t/* Empty free buf. queue int. enabled */\n-\tvolatile u32 tst_addr;\t/* SRAM address of the TST in use */\n-\tvolatile int tst_free_entries;\n-\tvc_map vcmap[NS_MAX_RCTSIZE];\n-\tvc_map *tste2vc[NS_TST_NUM_ENTRIES];\n-\tvc_map *scd2vc[NS_FRSCD_NUM];\n-\tbuf_nr sbnr;\n-\tbuf_nr lbnr;\n-\tbuf_nr hbnr;\n-\tbuf_nr iovnr;\n-\tint sbfqc;\n-\tint lbfqc;\n-\tstruct sk_buff *sm_handle;\n-\tu32 sm_addr;\n-\tstruct sk_buff *lg_handle;\n-\tu32 lg_addr;\n-\tstruct sk_buff *rcbuf;\t/* Current raw cell buffer */\n- struct ns_rcqe *rawcell;\n-\tu32 rawch;\t\t/* Raw cell queue head */\n-\tunsigned intcnt;\t/* Interrupt counter */\n-\tspinlock_t int_lock;\t/* Interrupt lock */\n-\tspinlock_t res_lock;\t/* Card resource lock */\n-} ns_dev;\n-\n- /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding\n- CBR vc. If the entry is not allocated, it must be NULL.\n-\n- There are two TSTs so the driver can modify them on the fly\n- without stopping the transmission.\n-\n- scd2vc allows us to find out unused fixed rate SCDs, because\n- they must have a NULL pointer here. */\n-\n-#endif /* _LINUX_NICSTAR_H_ */\ndiff --git a/drivers/atm/suni.h b/drivers/atm/suni.h\ndeleted file mode 100644\nindex d28a50d47d8b..000000000000\n--- a/drivers/atm/suni.h\n+++ /dev/null\n@@ -1,242 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/*\n- * drivers/atm/suni.h - S/UNI PHY driver\n- */\n- \n-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */\n-\n-#ifndef DRIVER_ATM_SUNI_H\n-#define DRIVER_ATM_SUNI_H\n-\n-#include \n-#include \n-#include \n-\n-/* SUNI registers */\n-\n-#define SUNI_MRI\t\t0x00\t/* Master Reset and Identity / Load\n-\t\t\t\t\t Meter */\n-#define SUNI_MC\t\t\t0x01\t/* Master Configuration */\n-#define SUNI_MIS\t\t0x02\t/* Master Interrupt Status */\n-\t\t\t /* no 0x03 */\n-#define SUNI_MCM\t\t0x04\t/* Master Clock Monitor */\n-#define SUNI_MCT\t\t0x05\t/* Master Control */\n-#define SUNI_CSCS\t\t0x06\t/* Clock Synthesis Control and Status */\n-#define SUNI_CRCS\t\t0x07\t/* Clock Recovery Control and Status */\n-\t\t\t /* 0x08-0x0F reserved */\n-#define SUNI_RSOP_CIE\t\t0x10\t/* RSOP Control/Interrupt Enable */\n-#define SUNI_RSOP_SIS\t\t0x11\t/* RSOP Status/Interrupt Status */\n-#define SUNI_RSOP_SBL\t\t0x12\t/* RSOP Section BIP-8 LSB */\n-#define SUNI_RSOP_SBM\t\t0x13\t/* RSOP Section BIP-8 MSB */\n-#define SUNI_TSOP_CTRL\t\t0x14\t/* TSOP Control */\n-#define SUNI_TSOP_DIAG\t\t0x15\t/* TSOP Diagnostic */\n-\t\t\t /* 0x16-0x17 reserved */\n-#define SUNI_RLOP_CS\t\t0x18\t/* RLOP Control/Status */\n-#define SUNI_RLOP_IES\t\t0x19\t/* RLOP Interrupt Enable/Status */\n-#define SUNI_RLOP_LBL\t\t0x1A\t/* RLOP Line BIP-8/24 LSB */\n-#define SUNI_RLOP_LB\t\t0x1B\t/* RLOP Line BIP-8/24 */\n-#define SUNI_RLOP_LBM\t\t0x1C\t/* RLOP Line BIP-8/24 MSB */\n-#define SUNI_RLOP_LFL\t\t0x1D\t/* RLOP Line FEBE LSB */\n-#define SUNI_RLOP_LF \t\t0x1E\t/* RLOP Line FEBE */\n-#define SUNI_RLOP_LFM\t\t0x1F\t/* RLOP Line FEBE MSB */\n-#define SUNI_TLOP_CTRL\t\t0x20\t/* TLOP Control */\n-#define SUNI_TLOP_DIAG\t\t0x21\t/* TLOP Diagnostic */\n-\t\t\t /* 0x22-0x27 reserved */\n-#define SUNI_SSTB_CTRL\t\t0x28\n-#define SUNI_RPOP_SC\t\t0x30\t/* RPOP Status/Control */\n-#define SUNI_RPOP_IS\t\t0x31\t/* RPOP Interrupt Status */\n-\t\t\t /* 0x32 reserved */\n-#define SUNI_RPOP_IE\t\t0x33\t/* RPOP Interrupt Enable */\n-\t\t\t /* 0x34-0x36 reserved */\n-#define SUNI_RPOP_PSL\t\t0x37\t/* RPOP Path Signal Label */\n-#define SUNI_RPOP_PBL\t\t0x38\t/* RPOP Path BIP-8 LSB */\n-#define SUNI_RPOP_PBM\t\t0x39\t/* RPOP Path BIP-8 MSB */\n-#define SUNI_RPOP_PFL\t\t0x3A\t/* RPOP Path FEBE LSB */\n-#define SUNI_RPOP_PFM\t\t0x3B\t/* RPOP Path FEBE MSB */\n-\t\t\t /* 0x3C reserved */\n-#define SUNI_RPOP_PBC\t\t0x3D\t/* RPOP Path BIP-8 Configuration */\n-#define SUNI_RPOP_RC\t\t0x3D\t/* RPOP Ring Control (PM5355) */\n-\t\t\t /* 0x3E-0x3F reserved */\n-#define SUNI_TPOP_CD\t\t0x40\t/* TPOP Control/Diagnostic */\n-#define SUNI_TPOP_PC\t\t0x41\t/* TPOP Pointer Control */\n-\t\t\t /* 0x42-0x44 reserved */\n-#define SUNI_TPOP_APL\t\t0x45\t/* TPOP Arbitrary Pointer LSB */\n-#define SUNI_TPOP_APM\t\t0x46\t/* TPOP Arbitrary Pointer MSB */\n-\t\t\t /* 0x47 reserved */\n-#define SUNI_TPOP_PSL\t\t0x48\t/* TPOP Path Signal Label */\n-#define SUNI_TPOP_PS\t\t0x49\t/* TPOP Path Status */\n-\t\t\t /* 0x4A-0x4F reserved */\n-#define SUNI_RACP_CS\t\t0x50\t/* RACP Control/Status */\n-#define SUNI_RACP_IES\t\t0x51\t/* RACP Interrupt Enable/Status */\n-#define SUNI_RACP_MHP\t\t0x52\t/* RACP Match Header Pattern */\n-#define SUNI_RACP_MHM\t\t0x53\t/* RACP Match Header Mask */\n-#define SUNI_RACP_CHEC\t\t0x54\t/* RACP Correctable HCS Error Count */\n-#define SUNI_RACP_UHEC\t\t0x55\t/* RACP Uncorrectable HCS Err Count */\n-#define SUNI_RACP_RCCL\t\t0x56\t/* RACP Receive Cell Counter LSB */\n-#define SUNI_RACP_RCC\t\t0x57\t/* RACP Receive Cell Counter */\n-#define SUNI_RACP_RCCM\t\t0x58\t/* RACP Receive Cell Counter MSB */\n-#define SUNI_RACP_CFG\t\t0x59\t/* RACP Configuration */\n-\t\t\t /* 0x5A-0x5F reserved */\n-#define SUNI_TACP_CS\t\t0x60\t/* TACP Control/Status */\n-#define SUNI_TACP_IUCHP\t\t0x61\t/* TACP Idle/Unassigned Cell Hdr Pat */\n-#define SUNI_TACP_IUCPOP\t0x62\t/* TACP Idle/Unassigned Cell Payload\n-\t\t\t\t\t Octet Pattern */\n-#define SUNI_TACP_FIFO\t\t0x63\t/* TACP FIFO Configuration */\n-#define SUNI_TACP_TCCL\t\t0x64\t/* TACP Transmit Cell Counter LSB */\n-#define SUNI_TACP_TCC\t\t0x65\t/* TACP Transmit Cell Counter */\n-#define SUNI_TACP_TCCM\t\t0x66\t/* TACP Transmit Cell Counter MSB */\n-#define SUNI_TACP_CFG\t\t0x67\t/* TACP Configuration */\n-#define SUNI_SPTB_CTRL\t\t0x68\t/* SPTB Control */\n-\t\t\t /* 0x69-0x7F reserved */\n-#define\tSUNI_MT\t\t\t0x80\t/* Master Test */\n-\t\t\t /* 0x81-0xFF reserved */\n-\n-/* SUNI register values */\n-\n-\n-/* MRI is reg 0 */\n-#define SUNI_MRI_ID\t\t0x0f\t/* R, SUNI revision number */\n-#define SUNI_MRI_ID_SHIFT \t0\n-#define SUNI_MRI_TYPE\t\t0x70\t/* R, SUNI type (lite is 011) */\n-#define SUNI_MRI_TYPE_SHIFT \t4\n-#define SUNI_MRI_TYPE_PM5346\t0x3\t/* S/UNI 155 LITE */\n-#define SUNI_MRI_TYPE_PM5347\t0x4\t/* S/UNI 155 PLUS */\n-#define SUNI_MRI_TYPE_PM5350\t0x7\t/* S/UNI 155 ULTRA */\n-#define SUNI_MRI_TYPE_PM5355\t0x1\t/* S/UNI 622 */\n-#define SUNI_MRI_RESET\t\t0x80\t/* RW, reset & power down chip\n-\t\t\t\t\t 0: normal operation\n-\t\t\t\t\t 1: reset & low power */\n-\n-/* MCM is reg 0x4 */\n-#define SUNI_MCM_LLE\t\t0x20\t/* line loopback (PM5355) */\n-#define SUNI_MCM_DLE\t\t0x10\t/* diagnostic loopback (PM5355) */\n-\n-/* MCT is reg 5 */\n-#define SUNI_MCT_LOOPT\t\t0x01\t/* RW, timing source, 0: from\n-\t\t\t\t\t TRCLK+/- */\n-#define SUNI_MCT_DLE\t\t0x02\t/* RW, diagnostic loopback */\n-#define SUNI_MCT_LLE\t\t0x04\t/* RW, line loopback */\n-#define SUNI_MCT_FIXPTR\t\t0x20\t/* RW, disable transmit payload pointer\n-\t\t\t\t\t adjustments\n-\t\t\t\t\t 0: payload ptr controlled by TPOP\n-\t\t\t\t\t ptr control reg\n-\t\t\t\t\t 1: payload pointer fixed at 522 */\n-#define SUNI_MCT_LCDV\t\t0x40\t/* R, loss of cell delineation */\n-#define SUNI_MCT_LCDE\t\t0x80\t/* RW, loss of cell delineation\n-\t\t\t\t\t interrupt (1: on) */\n-/* RSOP_CIE is reg 0x10 */\n-#define SUNI_RSOP_CIE_OOFE\t0x01\t/* RW, enable interrupt on frame alarm\n-\t\t\t\t\t state change */\n-#define SUNI_RSOP_CIE_LOFE\t0x02\t/* RW, enable interrupt on loss of\n-\t\t\t\t\t frame state change */\n-#define SUNI_RSOP_CIE_LOSE\t0x04\t/* RW, enable interrupt on loss of\n-\t\t\t\t\t signal state change */\n-#define SUNI_RSOP_CIE_BIPEE\t0x08\t/* RW, enable interrupt on section\n-\t\t\t\t\t BIP-8 error (B1) */\n-#define SUNI_RSOP_CIE_FOOF\t0x20\t/* W, force RSOP out of frame at next\n-\t\t\t\t\t boundary */\n-#define SUNI_RSOP_CIE_DDS\t0x40\t/* RW, disable scrambling */\n-\n-/* RSOP_SIS is reg 0x11 */\n-#define SUNI_RSOP_SIS_OOFV\t0x01\t/* R, out of frame */\n-#define SUNI_RSOP_SIS_LOFV\t0x02\t/* R, loss of frame */\n-#define SUNI_RSOP_SIS_LOSV\t0x04\t/* R, loss of signal */\n-#define SUNI_RSOP_SIS_OOFI\t0x08\t/* R, out of frame interrupt */\n-#define SUNI_RSOP_SIS_LOFI\t0x10\t/* R, loss of frame interrupt */\n-#define SUNI_RSOP_SIS_LOSI\t0x20\t/* R, loss of signal interrupt */\n-#define SUNI_RSOP_SIS_BIPEI\t0x40\t/* R, section BIP-8 interrupt */\n-\n-/* TSOP_CTRL is reg 0x14 */\n-#define SUNI_TSOP_CTRL_LAIS\t0x01\t/* insert alarm indication signal */\n-#define SUNI_TSOP_CTRL_DS\t0x40\t/* disable scrambling */\n-\n-/* TSOP_DIAG is reg 0x15 */\n-#define SUNI_TSOP_DIAG_DFP\t0x01\t/* insert single bit error cont. */\n-#define SUNI_TSOP_DIAG_DBIP8\t0x02\t/* insert section BIP err (cont) */\n-#define SUNI_TSOP_DIAG_DLOS\t0x04\t/* set line to zero (loss of signal) */\n-\n-/* TLOP_DIAG is reg 0x21 */\n-#define SUNI_TLOP_DIAG_DBIP\t0x01\t/* insert line BIP err (continuously) */\n-\n-/* SSTB_CTRL is reg 0x28 */\n-#define SUNI_SSTB_CTRL_LEN16\t0x01\t/* path trace message length bit */\n-\n-/* RPOP_RC is reg 0x3D (PM5355) */\n-#define SUNI_RPOP_RC_ENSS\t0x40\t/* enable size bit */\n-\n-/* TPOP_DIAG is reg 0x40 */\n-#define SUNI_TPOP_DIAG_PAIS\t0x01\t/* insert STS path alarm ind (cont) */\n-#define SUNI_TPOP_DIAG_DB3\t0x02\t/* insert path BIP err (continuously) */\n-\n-/* TPOP_APM is reg 0x46 */\n-#define SUNI_TPOP_APM_APTR\t0x03\t/* RW, arbitrary pointer, upper 2\n-\t\t\t\t\t bits */\n-#define SUNI_TPOP_APM_APTR_SHIFT 0\n-#define SUNI_TPOP_APM_S\t\t0x0c\t/* RW, \"unused\" bits of payload\n-\t\t\t\t\t pointer */\n-#define SUNI_TPOP_APM_S_SHIFT\t2\n-#define SUNI_TPOP_APM_NDF\t0xf0\t /* RW, NDF bits */\n-#define SUNI_TPOP_APM_NDF_SHIFT\t4\n-\n-#define SUNI_TPOP_S_SONET\t0\t/* set S bits to 00 */\n-#define SUNI_TPOP_S_SDH\t\t2\t/* set S bits to 10 */\n-\n-/* RACP_IES is reg 0x51 */\n-#define SUNI_RACP_IES_FOVRI\t0x02\t/* R, FIFO overrun */\n-#define SUNI_RACP_IES_UHCSI\t0x04\t/* R, uncorrectable HCS error */\n-#define SUNI_RACP_IES_CHCSI\t0x08\t/* R, correctable HCS error */\n-#define SUNI_RACP_IES_OOCDI\t0x10\t/* R, change of cell delineation\n-\t\t\t\t\t state */\n-#define SUNI_RACP_IES_FIFOE\t0x20\t/* RW, enable FIFO overrun interrupt */\n-#define SUNI_RACP_IES_HCSE\t0x40\t/* RW, enable HCS error interrupt */\n-#define SUNI_RACP_IES_OOCDE\t0x80\t/* RW, enable cell delineation state\n-\t\t\t\t\t change interrupt */\n-\n-/* TACP_CS is reg 0x60 */\n-#define SUNI_TACP_CS_FIFORST\t0x01\t/* RW, reset transmit FIFO (sticky) */\n-#define SUNI_TACP_CS_DSCR\t0x02\t/* RW, disable payload scrambling */\n-#define SUNI_TACP_CS_HCAADD\t0x04\t/* RW, add coset polynomial to HCS */\n-#define SUNI_TACP_CS_DHCS\t0x10\t/* RW, insert HCS errors */\n-#define SUNI_TACP_CS_FOVRI\t0x20\t/* R, FIFO overrun */\n-#define SUNI_TACP_CS_TSOCI\t0x40\t/* R, TSOC input high */\n-#define SUNI_TACP_CS_FIFOE\t0x80\t/* RW, enable FIFO overrun interrupt */\n-\n-/* TACP_IUCHP is reg 0x61 */\n-#define SUNI_TACP_IUCHP_CLP\t0x01\t/* RW, 8th bit of 4th octet of i/u\n-\t\t\t\t\t pattern */\n-#define SUNI_TACP_IUCHP_PTI\t0x0e\t/* RW, 5th-7th bits of 4th octet of i/u\n-\t\t\t\t\t pattern */\n-#define SUNI_TACP_IUCHP_PTI_SHIFT 1\n-#define SUNI_TACP_IUCHP_GFC\t0xf0\t/* RW, 1st-4th bits of 1st octet of i/u\n-\t\t\t\t\t pattern */\n-#define SUNI_TACP_IUCHP_GFC_SHIFT 4\n-\n-/* SPTB_CTRL is reg 0x68 */\n-#define SUNI_SPTB_CTRL_LEN16\t0x01\t/* path trace message length */\n-\n-/* MT is reg 0x80 */\n-#define SUNI_MT_HIZIO\t\t0x01\t/* RW, all but data bus & MP interface\n-\t\t\t\t\t tri-state */\n-#define SUNI_MT_HIZDATA\t\t0x02\t/* W, also tri-state data bus */\n-#define SUNI_MT_IOTST\t\t0x04\t/* RW, enable test mode */\n-#define SUNI_MT_DBCTRL\t\t0x08\t/* W, control data bus by CSB pin */\n-#define SUNI_MT_PMCTST\t\t0x10\t/* W, PMC test mode */\n-#define SUNI_MT_DS27_53\t\t0x80\t/* RW, select between 8- or 16- bit */\n-\n-\n-#define SUNI_IDLE_PATTERN 0x6a /* idle pattern */\n-\n-\n-#ifdef __KERNEL__\n-struct suni_priv {\n-\tstruct k_sonet_stats sonet_stats;\t/* link diagnostics */\n-\tint loop_mode;\t\t\t\t/* loopback mode */\n-\tint type;\t\t\t\t/* phy type */\n-\tstruct atm_dev *dev;\t\t\t/* device back-pointer */\n-\tstruct suni_priv *next;\t\t\t/* next SUNI */\n-};\n-\n-int suni_init(struct atm_dev *dev);\n-#endif\n-\n-#endif\ndiff --git a/drivers/atm/tonga.h b/drivers/atm/tonga.h\ndeleted file mode 100644\nindex 771b3f95246c..000000000000\n--- a/drivers/atm/tonga.h\n+++ /dev/null\n@@ -1,21 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* drivers/atm/tonga.h - Efficient Networks Tonga (PCI bridge) declarations */\n- \n-/* Written 1995 by Werner Almesberger, EPFL LRC */\n- \n-\n-#ifndef DRIVER_ATM_TONGA_H\n-#define DRIVER_ATM_TONGA_H\n-\n-#define PCI_TONGA_CTRL\t0x60\t/* control register */\n-\n-#define END_SWAP_DMA\t0x80\t/* endian swap on DMA */\n-#define END_SWAP_BYTE\t0x40\t/* endian swap on slave byte accesses */\n-#define END_SWAP_WORD\t0x20\t/* endian swap on slave word accesses */\n-#define SEPROM_MAGIC\t0x0c\t/* obscure required pattern (ASIC only) */\n-#define SEPROM_DATA\t0x02\t/* serial EEPROM data (ASIC only) */\n-#define SEPROM_CLK\t0x01\t/* serial EEPROM clock (ASIC only) */\n-\n-#define SEPROM_ESI_BASE\t64\t/* start of ESI in serial EEPROM */\n-\n-#endif\ndiff --git a/drivers/atm/zeprom.h b/drivers/atm/zeprom.h\ndeleted file mode 100644\nindex 8e8819a3840d..000000000000\n--- a/drivers/atm/zeprom.h\n+++ /dev/null\n@@ -1,35 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/* drivers/atm/zeprom.h - ZeitNet ZN122x EEPROM (NM93C46) declarations */\n-\n-/* Written 1995,1996 by Werner Almesberger, EPFL LRC */\n-\n-\n-#ifndef DRIVER_ATM_ZEPROM_H\n-#define DRIVER_ATM_ZEPROM_H\n-\n-/* Different versions use different control registers */\n-\n-#define ZEPROM_V1_REG\tPCI_VENDOR_ID\t/* PCI register */\n-#define ZEPROM_V2_REG\t0x40\n-\n-/* Bits in control register */\n-\n-#define ZEPROM_SK\t0x80000000\t/* strobe (probably on raising edge) */\n-#define ZEPROM_CS\t0x40000000\t/* Chip Select */\n-#define ZEPROM_DI\t0x20000000\t/* Data Input */\n-#define ZEPROM_DO\t0x10000000\t/* Data Output */\n-\n-#define ZEPROM_SIZE\t32\t\t/* 32 bytes */\n-#define ZEPROM_V1_ESI_OFF 24\t\t/* ESI offset in EEPROM (V1) */\n-#define ZEPROM_V2_ESI_OFF 4\t\t/* ESI offset in EEPROM (V2) */\n-\n-#define ZEPROM_CMD_LEN\t3\t\t/* commands are three bits */\n-#define ZEPROM_ADDR_LEN\t6\t\t/* addresses are six bits */\n-\n-/* Commands (3 bits) */\n-\n-#define ZEPROM_CMD_READ\t6\n-\n-/* No other commands are needed. */\n-\n-#endif\ndiff --git a/net/atm/lec.h b/net/atm/lec.h\ndeleted file mode 100644\nindex ec85709bf818..000000000000\n--- a/net/atm/lec.h\n+++ /dev/null\n@@ -1,155 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/*\n- * Lan Emulation client header file\n- *\n- * Marko Kiiskila \n- */\n-\n-#ifndef _LEC_H_\n-#define _LEC_H_\n-\n-#include \n-#include \n-#include \n-\n-#define LEC_HEADER_LEN 16\n-\n-struct lecdatahdr_8023 {\n-\t__be16 le_header;\n-\tunsigned char h_dest[ETH_ALEN];\n-\tunsigned char h_source[ETH_ALEN];\n-\t__be16 h_type;\n-};\n-\n-struct lecdatahdr_8025 {\n-\t__be16 le_header;\n-\tunsigned char ac_pad;\n-\tunsigned char fc;\n-\tunsigned char h_dest[ETH_ALEN];\n-\tunsigned char h_source[ETH_ALEN];\n-};\n-\n-#define LEC_MINIMUM_8023_SIZE 62\n-#define LEC_MINIMUM_8025_SIZE 16\n-\n-/*\n- * Operations that LANE2 capable device can do. Two first functions\n- * are used to make the device do things. See spec 3.1.3 and 3.1.4.\n- *\n- * The third function is intended for the MPOA component sitting on\n- * top of the LANE device. The MPOA component assigns it's own function\n- * to (*associate_indicator)() and the LANE device will use that\n- * function to tell about TLVs it sees floating through.\n- *\n- */\n-struct lane2_ops {\n-\tint (*resolve) (struct net_device *dev, const u8 *dst_mac, int force,\n-\t\t\tu8 **tlvs, u32 *sizeoftlvs);\n-\tint (*associate_req) (struct net_device *dev, const u8 *lan_dst,\n-\t\t\t const u8 *tlvs, u32 sizeoftlvs);\n-\tvoid (*associate_indicator) (struct net_device *dev, const u8 *mac_addr,\n-\t\t\t\t const u8 *tlvs, u32 sizeoftlvs);\n-};\n-\n-/*\n- * ATM LAN Emulation supports both LLC & Dix Ethernet EtherType\n- * frames.\n- *\n- * 1. Dix Ethernet EtherType frames encoded by placing EtherType\n- * field in h_type field. Data follows immediately after header.\n- * 2. LLC Data frames whose total length, including LLC field and data,\n- * but not padding required to meet the minimum data frame length,\n- * is less than ETH_P_802_3_MIN MUST be encoded by placing that length\n- * in the h_type field. The LLC field follows header immediately.\n- * 3. LLC data frames longer than this maximum MUST be encoded by placing\n- * the value 0 in the h_type field.\n- *\n- */\n-\n-/* Hash table size */\n-#define LEC_ARP_TABLE_SIZE 16\n-\n-struct lec_priv {\n-\tunsigned short lecid;\t\t\t/* Lecid of this client */\n-\tstruct hlist_head lec_arp_empty_ones;\n-\t\t\t\t\t\t/* Used for storing VCC's that don't have a MAC address attached yet */\n-\tstruct hlist_head lec_arp_tables[LEC_ARP_TABLE_SIZE];\n-\t\t\t\t\t\t/* Actual LE ARP table */\n-\tstruct hlist_head lec_no_forward;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * Used for storing VCC's (and forward packets from) which are to\n-\t\t\t\t\t\t * age out by not using them to forward packets.\n-\t\t\t\t\t\t * This is because to some LE clients there will be 2 VCCs. Only\n-\t\t\t\t\t\t * one of them gets used.\n-\t\t\t\t\t\t */\n-\tstruct hlist_head mcast_fwds;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * With LANEv2 it is possible that BUS (or a special multicast server)\n-\t\t\t\t\t\t * establishes multiple Multicast Forward VCCs to us. This list\n-\t\t\t\t\t\t * collects all those VCCs. LANEv1 client has only one item in this\n-\t\t\t\t\t\t * list. These entries are not aged out.\n-\t\t\t\t\t\t */\n-\tspinlock_t lec_arp_lock;\n-\tstruct atm_vcc *mcast_vcc;\t\t/* Default Multicast Send VCC */\n-\tstruct atm_vcc __rcu *lecd;\n-\tstruct delayed_work lec_arp_work;\t/* C10 */\n-\tunsigned int maximum_unknown_frame_count;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * Within the period of time defined by this variable, the client will send\n-\t\t\t\t\t\t * no more than C10 frames to BUS for a given unicast destination. (C11)\n-\t\t\t\t\t\t */\n-\tunsigned long max_unknown_frame_time;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * If no traffic has been sent in this vcc for this period of time,\n-\t\t\t\t\t\t * vcc will be torn down (C12)\n-\t\t\t\t\t\t */\n-\tunsigned long vcc_timeout_period;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * An LE Client MUST not retry an LE_ARP_REQUEST for a\n-\t\t\t\t\t\t * given frame's LAN Destination more than maximum retry count times,\n-\t\t\t\t\t\t * after the first LEC_ARP_REQUEST (C13)\n-\t\t\t\t\t\t */\n-\tunsigned short max_retry_count;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * Max time the client will maintain an entry in its arp cache in\n-\t\t\t\t\t\t * absence of a verification of that relationship (C17)\n-\t\t\t\t\t\t */\n-\tunsigned long aging_time;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * Max time the client will maintain an entry in cache when\n-\t\t\t\t\t\t * topology change flag is true (C18)\n-\t\t\t\t\t\t */\n-\tunsigned long forward_delay_time;\t/* Topology change flag (C19) */\n-\tint topology_change;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * Max time the client expects an LE_ARP_REQUEST/LE_ARP_RESPONSE\n-\t\t\t\t\t\t * cycle to take (C20)\n-\t\t\t\t\t\t */\n-\tunsigned long arp_response_time;\n-\t\t\t\t\t\t/*\n-\t\t\t\t\t\t * Time limit ot wait to receive an LE_FLUSH_RESPONSE after the\n-\t\t\t\t\t\t * LE_FLUSH_REQUEST has been sent before taking recover action. (C21)\n-\t\t\t\t\t\t */\n-\tunsigned long flush_timeout;\n-\t\t\t\t\t\t/* The time since sending a frame to the bus after which the\n-\t\t\t\t\t\t * LE Client may assume that the frame has been either discarded or\n-\t\t\t\t\t\t * delivered to the recipient (C22)\n-\t\t\t\t\t\t */\n-\tunsigned long path_switching_delay;\n-\n-\tu8 *tlvs;\t\t\t\t/* LANE2: TLVs are new */\n-\tu32 sizeoftlvs;\t\t\t\t/* The size of the tlv array in bytes */\n-\tint lane_version;\t\t\t/* LANE2 */\n-\tint itfnum;\t\t\t\t/* e.g. 2 for lec2, 5 for lec5 */\n-\tstruct lane2_ops *lane2_ops;\t\t/* can be NULL for LANE v1 */\n-\tint is_proxy;\t\t\t\t/* bridge between ATM and Ethernet */\n-};\n-\n-struct lec_vcc_priv {\n-\tvoid (*old_pop) (struct atm_vcc *vcc, struct sk_buff *skb);\n-\tint xoff;\n-};\n-\n-#define LEC_VCC_PRIV(vcc)\t((struct lec_vcc_priv *)((vcc)->user_back))\n-\n-#endif\t\t\t\t/* _LEC_H_ */\ndiff --git a/net/atm/lec_arpc.h b/net/atm/lec_arpc.h\ndeleted file mode 100644\nindex 39115fe074c4..000000000000\n--- a/net/atm/lec_arpc.h\n+++ /dev/null\n@@ -1,97 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/*\n- * Lec arp cache\n- *\n- * Marko Kiiskila \n- */\n-#ifndef _LEC_ARP_H_\n-#define _LEC_ARP_H_\n-#include \n-#include \n-#include \n-#include \n-\n-struct lec_arp_table {\n-\tstruct hlist_node next;\t\t/* Linked entry list */\n-\tunsigned char atm_addr[ATM_ESA_LEN];\t/* Atm address */\n-\tunsigned char mac_addr[ETH_ALEN];\t/* Mac address */\n-\tint is_rdesc;\t\t\t/* Mac address is a route descriptor */\n-\tstruct atm_vcc *vcc;\t\t/* Vcc this entry is attached */\n-\tstruct atm_vcc *recv_vcc;\t/* Vcc we receive data from */\n-\n-\tvoid (*old_push) (struct atm_vcc *vcc, struct sk_buff *skb);\n-\t\t\t\t\t/* Push that leads to daemon */\n-\n-\tvoid (*old_recv_push) (struct atm_vcc *vcc, struct sk_buff *skb);\n-\t\t\t\t\t/* Push that leads to daemon */\n-\n-\tunsigned long last_used;\t/* For expiry */\n-\tunsigned long timestamp;\t/* Used for various timestamping things:\n-\t\t\t\t\t * 1. FLUSH started\n-\t\t\t\t\t * (status=ESI_FLUSH_PENDING)\n-\t\t\t\t\t * 2. Counting to\n-\t\t\t\t\t * max_unknown_frame_time\n-\t\t\t\t\t * (status=ESI_ARP_PENDING||\n-\t\t\t\t\t * status=ESI_VC_PENDING)\n-\t\t\t\t\t */\n-\tunsigned char no_tries;\t\t/* No of times arp retry has been tried */\n-\tunsigned char status;\t\t/* Status of this entry */\n-\tunsigned short flags;\t\t/* Flags for this entry */\n-\tunsigned short packets_flooded;\t/* Data packets flooded */\n-\tunsigned long flush_tran_id;\t/* Transaction id in flush protocol */\n-\tstruct timer_list timer;\t/* Arping timer */\n-\tstruct lec_priv *priv;\t\t/* Pointer back */\n-\tu8 *tlvs;\n-\tu32 sizeoftlvs;\t\t\t/*\n-\t\t\t\t\t * LANE2: Each MAC address can have TLVs\n-\t\t\t\t\t * associated with it. sizeoftlvs tells\n-\t\t\t\t\t * the length of the tlvs array\n-\t\t\t\t\t */\n-\tstruct sk_buff_head tx_wait;\t/* wait queue for outgoing packets */\n-\trefcount_t usage;\t\t/* usage count */\n-};\n-\n-/*\n- * LANE2: Template tlv struct for accessing\n- * the tlvs in the lec_arp_table->tlvs array\n- */\n-struct tlv {\n-\tu32 type;\n-\tu8 length;\n-\tu8 value[255];\n-};\n-\n-/* Status fields */\n-#define ESI_UNKNOWN 0\t\t/*\n-\t\t\t\t * Next packet sent to this mac address\n-\t\t\t\t * causes ARP-request to be sent\n-\t\t\t\t */\n-#define ESI_ARP_PENDING 1\t/*\n-\t\t\t\t * There is no ATM address associated with this\n-\t\t\t\t * 48-bit address. The LE-ARP protocol is in\n-\t\t\t\t * progress.\n-\t\t\t\t */\n-#define ESI_VC_PENDING 2\t/*\n-\t\t\t\t * There is a valid ATM address associated with\n-\t\t\t\t * this 48-bit address but there is no VC set\n-\t\t\t\t * up to that ATM address. The signaling\n-\t\t\t\t * protocol is in process.\n-\t\t\t\t */\n-#define ESI_FLUSH_PENDING 4\t/*\n-\t\t\t\t * The LEC has been notified of the FLUSH_START\n-\t\t\t\t * status and it is assumed that the flush\n-\t\t\t\t * protocol is in process.\n-\t\t\t\t */\n-#define ESI_FORWARD_DIRECT 5\t/*\n-\t\t\t\t * Either the Path Switching Delay (C22) has\n-\t\t\t\t * elapsed or the LEC has notified the Mapping\n-\t\t\t\t * that the flush protocol has completed. In\n-\t\t\t\t * either case, it is safe to forward packets\n-\t\t\t\t * to this address via the data direct VC.\n-\t\t\t\t */\n-\n-/* Flag values */\n-#define LEC_REMOTE_FLAG 0x0001\n-#define LEC_PERMANENT_FLAG 0x0002\n-\n-#endif /* _LEC_ARP_H_ */\ndiff --git a/net/atm/mpc.h b/net/atm/mpc.h\ndeleted file mode 100644\nindex 454abd07651a..000000000000\n--- a/net/atm/mpc.h\n+++ /dev/null\n@@ -1,65 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-#ifndef _MPC_H_\n-#define _MPC_H_\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \"mpoa_caches.h\"\n-\n-/* kernel -> mpc-daemon */\n-int msg_to_mpoad(struct k_message *msg, struct mpoa_client *mpc);\n-\n-struct mpoa_client {\n-\tstruct mpoa_client *next;\n-\tstruct net_device *dev; /* lec in question */\n-\tint dev_num; /* e.g. 2 for lec2 */\n-\n-\tstruct atm_vcc *mpoad_vcc; /* control channel to mpoad */\n-\tuint8_t mps_ctrl_addr[ATM_ESA_LEN]; /* MPS control ATM address */\n-\tuint8_t our_ctrl_addr[ATM_ESA_LEN]; /* MPC's control ATM address */\n-\n-\trwlock_t ingress_lock;\n-\tconst struct in_cache_ops *in_ops; /* ingress cache operations */\n-\tin_cache_entry *in_cache; /* the ingress cache of this MPC */\n-\n-\trwlock_t egress_lock;\n-\tconst struct eg_cache_ops *eg_ops; /* egress cache operations */\n-\teg_cache_entry *eg_cache; /* the egress cache of this MPC */\n-\n-\tuint8_t *mps_macs; /* array of MPS MAC addresses, >=1 */\n-\tint number_of_mps_macs; /* number of the above MAC addresses */\n-\tstruct mpc_parameters parameters; /* parameters for this client */\n-\n-\tconst struct net_device_ops *old_ops;\n-\tstruct net_device_ops new_ops;\n-};\n-\n-\n-struct atm_mpoa_qos {\n-\tstruct atm_mpoa_qos *next;\n-\t__be32 ipaddr;\n-\tstruct atm_qos qos;\n-};\n-\n-\n-/* MPOA QoS operations */\n-struct atm_mpoa_qos *atm_mpoa_add_qos(__be32 dst_ip, struct atm_qos *qos);\n-struct atm_mpoa_qos *atm_mpoa_search_qos(__be32 dst_ip);\n-int atm_mpoa_delete_qos(struct atm_mpoa_qos *qos);\n-\n-/* Display QoS entries. This is for the procfs */\n-struct seq_file;\n-void atm_mpoa_disp_qos(struct seq_file *m);\n-\n-#ifdef CONFIG_PROC_FS\n-int mpc_proc_init(void);\n-void mpc_proc_clean(void);\n-#else\n-#define mpc_proc_init() (0)\n-#define mpc_proc_clean() do { } while(0)\n-#endif\n-\n-#endif /* _MPC_H_ */\ndiff --git a/net/atm/mpoa_caches.h b/net/atm/mpoa_caches.h\ndeleted file mode 100644\nindex 464c4c7f8d1f..000000000000\n--- a/net/atm/mpoa_caches.h\n+++ /dev/null\n@@ -1,99 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-#ifndef MPOA_CACHES_H\n-#define MPOA_CACHES_H\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-struct mpoa_client;\n-\n-void atm_mpoa_init_cache(struct mpoa_client *mpc);\n-\n-typedef struct in_cache_entry {\n-\tstruct in_cache_entry *next;\n-\tstruct in_cache_entry *prev;\n-\ttime64_t time;\n-\ttime64_t reply_wait;\n-\ttime64_t hold_down;\n-\tuint32_t packets_fwded;\n-\tuint16_t entry_state;\n-\tuint32_t retry_time;\n-\tuint32_t refresh_time;\n-\tuint32_t count;\n-\tstruct atm_vcc *shortcut;\n-\tuint8_t MPS_ctrl_ATM_addr[ATM_ESA_LEN];\n-\tstruct in_ctrl_info ctrl_info;\n-\trefcount_t use;\n-} in_cache_entry;\n-\n-struct in_cache_ops{\n-\tin_cache_entry *(*add_entry)(__be32 dst_ip,\n-\t\t\t\t struct mpoa_client *client);\n-\tin_cache_entry *(*get)(__be32 dst_ip, struct mpoa_client *client);\n-\tin_cache_entry *(*get_with_mask)(__be32 dst_ip,\n-\t\t\t\t\t struct mpoa_client *client,\n-\t\t\t\t\t __be32 mask);\n-\tin_cache_entry *(*get_by_vcc)(struct atm_vcc *vcc,\n-\t\t\t\t struct mpoa_client *client);\n-\tvoid (*put)(in_cache_entry *entry);\n-\tvoid (*remove_entry)(in_cache_entry *delEntry,\n-\t\t\t\t\tstruct mpoa_client *client );\n-\tint (*cache_hit)(in_cache_entry *entry,\n-\t\t\t\t struct mpoa_client *client);\n-\tvoid (*clear_count)(struct mpoa_client *client);\n-\tvoid (*check_resolving)(struct mpoa_client *client);\n-\tvoid (*refresh)(struct mpoa_client *client);\n-\tvoid (*destroy_cache)(struct mpoa_client *mpc);\n-};\n-\n-typedef struct eg_cache_entry{\n-\tstruct eg_cache_entry *next;\n-\tstruct eg_cache_entry *prev;\n-\ttime64_t\t time;\n-\tuint8_t MPS_ctrl_ATM_addr[ATM_ESA_LEN];\n-\tstruct atm_vcc *shortcut;\n-\tuint32_t packets_rcvd;\n-\tuint16_t entry_state;\n-\t__be32 latest_ip_addr; /* The src IP address of the last packet */\n-\tstruct eg_ctrl_info ctrl_info;\n-\trefcount_t use;\n-} eg_cache_entry;\n-\n-struct eg_cache_ops{\n-\teg_cache_entry *(*add_entry)(struct k_message *msg, struct mpoa_client *client);\n-\teg_cache_entry *(*get_by_cache_id)(__be32 cache_id, struct mpoa_client *client);\n-\teg_cache_entry *(*get_by_tag)(__be32 cache_id, struct mpoa_client *client);\n-\teg_cache_entry *(*get_by_vcc)(struct atm_vcc *vcc, struct mpoa_client *client);\n-\teg_cache_entry *(*get_by_src_ip)(__be32 ipaddr, struct mpoa_client *client);\n-\tvoid (*put)(eg_cache_entry *entry);\n-\tvoid (*remove_entry)(eg_cache_entry *entry, struct mpoa_client *client);\n-\tvoid (*update)(eg_cache_entry *entry, uint16_t holding_time);\n-\tvoid (*clear_expired)(struct mpoa_client *client);\n-\tvoid (*destroy_cache)(struct mpoa_client *mpc);\n-};\n-\n-\n-/* Ingress cache entry states */\n-\n-#define INGRESS_REFRESHING 3\n-#define INGRESS_RESOLVED 2\n-#define INGRESS_RESOLVING 1\n-#define INGRESS_INVALID 0\n-\n-/* VCC states */\n-\n-#define OPEN 1\n-#define CLOSED 0\n-\n-/* Egress cache entry states */\n-\n-#define EGRESS_RESOLVED 2\n-#define EGRESS_PURGE 1\n-#define EGRESS_INVALID 0\n-\n-#endif\ndiff --git a/net/bridge/br_private.h b/net/bridge/br_private.h\nindex 361a9b84451e..bed1b1d9b282 100644\n--- a/net/bridge/br_private.h\n+++ b/net/bridge/br_private.h\n@@ -855,7 +855,6 @@ void br_fdb_delete_by_port(struct net_bridge *br,\n struct net_bridge_fdb_entry *br_fdb_find_rcu(struct net_bridge *br,\n \t\t\t\t\t const unsigned char *addr,\n \t\t\t\t\t __u16 vid);\n-int br_fdb_test_addr(struct net_device *dev, unsigned char *addr);\n int br_fdb_fillbuf(struct net_bridge *br, void *buf, unsigned long count,\n \t\t unsigned long off);\n int br_fdb_add_local(struct net_bridge *br, struct net_bridge_port *source,\n@@ -2065,9 +2064,6 @@ void br_stp_port_timer_init(struct net_bridge_port *p);\n unsigned long br_timer_value(const struct timer_list *timer);\n \n /* br.c */\n-#if IS_ENABLED(CONFIG_ATM_LANE)\n-extern int (*br_fdb_test_addr_hook)(struct net_device *dev, unsigned char *addr);\n-#endif\n \n /* br_mrp.c */\n #if IS_ENABLED(CONFIG_BRIDGE_MRP)\ndiff --git a/drivers/atm/adummy.c b/drivers/atm/adummy.c\ndeleted file mode 100644\nindex c8d00537d236..000000000000\n--- a/drivers/atm/adummy.c\n+++ /dev/null\n@@ -1,202 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * adummy.c: a dummy ATM driver\n- */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \n-#include \n-#include \n-\n-/* version definition */\n-\n-#define DRV_VERSION \"1.0\"\n-\n-#define DEV_LABEL \"adummy\"\n-\n-#define ADUMMY_DEV(dev) ((struct adummy_dev *) (dev)->dev_data)\n-\n-struct adummy_dev {\n-\tstruct atm_dev *atm_dev;\n-\n-\tstruct list_head entry;\n-};\n-\n-/* globals */\n-\n-static LIST_HEAD(adummy_devs);\n-\n-static ssize_t __set_signal(struct device *dev,\n-\t\tstruct device_attribute *attr,\n-\t\tconst char *buf, size_t len)\n-{\n-\tstruct atm_dev *atm_dev = container_of(dev, struct atm_dev, class_dev);\n-\tint signal;\n-\n-\tif (sscanf(buf, \"%d\", &signal) == 1) {\n-\n-\t\tif (signal < ATM_PHY_SIG_LOST || signal > ATM_PHY_SIG_FOUND)\n-\t\t\tsignal = ATM_PHY_SIG_UNKNOWN;\n-\n-\t\tatm_dev_signal_change(atm_dev, signal);\n-\t\treturn 1;\n-\t}\n-\treturn -EINVAL;\n-}\n-\n-static ssize_t __show_signal(struct device *dev,\n-\tstruct device_attribute *attr, char *buf)\n-{\n-\tstruct atm_dev *atm_dev = container_of(dev, struct atm_dev, class_dev);\n-\treturn sprintf(buf, \"%d\\n\", atm_dev->signal);\n-}\n-static DEVICE_ATTR(signal, 0644, __show_signal, __set_signal);\n-\n-static struct attribute *adummy_attrs[] = {\n-\t&dev_attr_signal.attr,\n-\tNULL\n-};\n-\n-static const struct attribute_group adummy_group_attrs = {\n-\t.name = NULL, /* We want them in dev's root folder */\n-\t.attrs = adummy_attrs\n-};\n-\n-static int __init\n-adummy_start(struct atm_dev *dev)\n-{\n-\tdev->ci_range.vpi_bits = 4;\n-\tdev->ci_range.vci_bits = 12;\n-\n-\treturn 0;\n-}\n-\n-static int\n-adummy_open(struct atm_vcc *vcc)\n-{\n-\tshort vpi = vcc->vpi;\n-\tint vci = vcc->vci;\n-\n-\tif (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)\n-\t\treturn 0;\n-\n-\tset_bit(ATM_VF_ADDR, &vcc->flags);\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\n-\treturn 0;\n-}\n-\n-static void\n-adummy_close(struct atm_vcc *vcc)\n-{\n-\tclear_bit(ATM_VF_READY, &vcc->flags);\n-\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-}\n-\n-static int\n-adummy_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tif (vcc->pop)\n-\t\tvcc->pop(vcc, skb);\n-\telse\n-\t\tdev_kfree_skb_any(skb);\n-\tatomic_inc(&vcc->stats->tx);\n-\n-\treturn 0;\n-}\n-\n-static int\n-adummy_proc_read(struct atm_dev *dev, loff_t *pos, char *page)\n-{\n-\tint left = *pos;\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"version %s\\n\", DRV_VERSION);\n-\n-\treturn 0;\n-}\n-\n-static const struct atmdev_ops adummy_ops =\n-{\n-\t.open =\t\tadummy_open,\n-\t.close =\tadummy_close,\t\n-\t.send =\t\tadummy_send,\n-\t.proc_read =\tadummy_proc_read,\n-\t.owner =\tTHIS_MODULE\n-};\n-\n-static int __init adummy_init(void)\n-{\n-\tstruct atm_dev *atm_dev;\n-\tstruct adummy_dev *adummy_dev;\n-\tint err = 0;\n-\n-\tprintk(KERN_ERR \"adummy: version %s\\n\", DRV_VERSION);\n-\n-\tadummy_dev = kzalloc_obj(struct adummy_dev);\n-\tif (!adummy_dev) {\n-\t\tprintk(KERN_ERR DEV_LABEL \": kzalloc() failed\\n\");\n-\t\terr = -ENOMEM;\n-\t\tgoto out;\n-\t}\n-\tatm_dev = atm_dev_register(DEV_LABEL, NULL, &adummy_ops, -1, NULL);\n-\tif (!atm_dev) {\n-\t\tprintk(KERN_ERR DEV_LABEL \": atm_dev_register() failed\\n\");\n-\t\terr = -ENODEV;\n-\t\tgoto out_kfree;\n-\t}\n-\n-\tadummy_dev->atm_dev = atm_dev;\n-\tatm_dev->dev_data = adummy_dev;\n-\n-\tif (sysfs_create_group(&atm_dev->class_dev.kobj, &adummy_group_attrs))\n-\t\tdev_err(&atm_dev->class_dev, \"Could not register attrs for adummy\\n\");\n-\n-\tif (adummy_start(atm_dev)) {\n-\t\tprintk(KERN_ERR DEV_LABEL \": adummy_start() failed\\n\");\n-\t\terr = -ENODEV;\n-\t\tgoto out_unregister;\n-\t}\n-\n-\tlist_add(&adummy_dev->entry, &adummy_devs);\n-out:\n-\treturn err;\n-\n-out_unregister:\n-\tatm_dev_deregister(atm_dev);\n-out_kfree:\n-\tkfree(adummy_dev);\n-\tgoto out;\n-}\n-\n-static void __exit adummy_cleanup(void)\n-{\n-\tstruct adummy_dev *adummy_dev, *next;\n-\n-\tlist_for_each_entry_safe(adummy_dev, next, &adummy_devs, entry) {\n-\t\tatm_dev_deregister(adummy_dev->atm_dev);\n-\t\tkfree(adummy_dev);\n-\t}\n-}\n-\n-module_init(adummy_init);\n-module_exit(adummy_cleanup);\n-\n-MODULE_AUTHOR(\"chas williams \");\n-MODULE_DESCRIPTION(\"dummy ATM driver\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/atm/atmtcp.c b/drivers/atm/atmtcp.c\ndeleted file mode 100644\nindex 96719851ae2a..000000000000\n--- a/drivers/atm/atmtcp.c\n+++ /dev/null\n@@ -1,513 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/* drivers/atm/atmtcp.c - ATM over TCP \"device\" driver */\n-\n-/* Written 1997-2000 by Werner Almesberger, EPFL LRC/ICA */\n-\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-\n-extern int atm_init_aal5(struct atm_vcc *vcc); /* \"raw\" AAL5 transport */\n-\n-\n-#define PRIV(dev) ((struct atmtcp_dev_data *) ((dev)->dev_data))\n-\n-\n-struct atmtcp_dev_data {\n-\tstruct atm_vcc *vcc;\t/* control VCC; NULL if detached */\n-\tint persist;\t\t/* non-zero if persistent */\n-};\n-\n-\n-#define DEV_LABEL \"atmtcp\"\n-\n-#define MAX_VPI_BITS 8\t/* simplifies life */\n-#define MAX_VCI_BITS 16\n-\n-\n-/*\n- * Hairy code ahead: the control VCC may be closed while we're still\n- * waiting for an answer, so we need to re-validate out_vcc every once\n- * in a while.\n- */\n-\n-\n-static int atmtcp_send_control(struct atm_vcc *vcc,int type,\n- const struct atmtcp_control *msg,int flag)\n-{\n-\tDECLARE_WAITQUEUE(wait,current);\n-\tstruct atm_vcc *out_vcc;\n-\tstruct sk_buff *skb;\n-\tstruct atmtcp_control *new_msg;\n-\tint old_test;\n-\tint error = 0;\n-\n-\tout_vcc = PRIV(vcc->dev) ? PRIV(vcc->dev)->vcc : NULL;\n-\tif (!out_vcc) return -EUNATCH;\n-\tskb = alloc_skb(sizeof(*msg),GFP_KERNEL);\n-\tif (!skb) return -ENOMEM;\n-\tmb();\n-\tout_vcc = PRIV(vcc->dev) ? PRIV(vcc->dev)->vcc : NULL;\n-\tif (!out_vcc) {\n-\t\tdev_kfree_skb(skb);\n-\t\treturn -EUNATCH;\n-\t}\n-\tatm_force_charge(out_vcc,skb->truesize);\n-\tnew_msg = skb_put(skb, sizeof(*new_msg));\n-\t*new_msg = *msg;\n-\tnew_msg->hdr.length = ATMTCP_HDR_MAGIC;\n-\tnew_msg->type = type;\n-\tmemset(&new_msg->vcc,0,sizeof(atm_kptr_t));\n-\t*(struct atm_vcc **) &new_msg->vcc = vcc;\n-\told_test = test_bit(flag,&vcc->flags);\n-\tout_vcc->push(out_vcc,skb);\n-\tadd_wait_queue(sk_sleep(sk_atm(vcc)), &wait);\n-\twhile (test_bit(flag,&vcc->flags) == old_test) {\n-\t\tmb();\n-\t\tout_vcc = PRIV(vcc->dev) ? PRIV(vcc->dev)->vcc : NULL;\n-\t\tif (!out_vcc) {\n-\t\t\terror = -EUNATCH;\n-\t\t\tbreak;\n-\t\t}\n-\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t\tschedule();\n-\t}\n-\tset_current_state(TASK_RUNNING);\n-\tremove_wait_queue(sk_sleep(sk_atm(vcc)), &wait);\n-\treturn error;\n-}\n-\n-\n-static int atmtcp_recv_control(const struct atmtcp_control *msg)\n-{\n-\tstruct atm_vcc *vcc = *(struct atm_vcc **) &msg->vcc;\n-\n-\tvcc->vpi = msg->addr.sap_addr.vpi;\n-\tvcc->vci = msg->addr.sap_addr.vci;\n-\tvcc->qos = msg->qos;\n-\tsk_atm(vcc)->sk_err = -msg->result;\n-\tswitch (msg->type) {\n-\t case ATMTCP_CTRL_OPEN:\n-\t\tchange_bit(ATM_VF_READY,&vcc->flags);\n-\t\tbreak;\n-\t case ATMTCP_CTRL_CLOSE:\n-\t\tchange_bit(ATM_VF_ADDR,&vcc->flags);\n-\t\tbreak;\n-\t default:\n-\t\tprintk(KERN_ERR \"atmtcp_recv_control: unknown type %d\\n\",\n-\t\t msg->type);\n-\t\treturn -EINVAL;\n-\t}\n-\twake_up(sk_sleep(sk_atm(vcc)));\n-\treturn 0;\n-}\n-\n-\n-static void atmtcp_v_dev_close(struct atm_dev *dev)\n-{\n-\t/* Nothing.... Isn't this simple :-) -- REW */\n-}\n-\n-\n-static int atmtcp_v_open(struct atm_vcc *vcc)\n-{\n-\tstruct atmtcp_control msg;\n-\tint error;\n-\tshort vpi = vcc->vpi;\n-\tint vci = vcc->vci;\n-\n-\tmemset(&msg,0,sizeof(msg));\n-\tmsg.addr.sap_family = AF_ATMPVC;\n-\tmsg.hdr.vpi = htons(vpi);\n-\tmsg.addr.sap_addr.vpi = vpi;\n-\tmsg.hdr.vci = htons(vci);\n-\tmsg.addr.sap_addr.vci = vci;\n-\tif (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) return 0;\n-\tmsg.type = ATMTCP_CTRL_OPEN;\n-\tmsg.qos = vcc->qos;\n-\tset_bit(ATM_VF_ADDR,&vcc->flags);\n-\tclear_bit(ATM_VF_READY,&vcc->flags); /* just in case ... */\n-\terror = atmtcp_send_control(vcc,ATMTCP_CTRL_OPEN,&msg,ATM_VF_READY);\n-\tif (error) return error;\n-\treturn -sk_atm(vcc)->sk_err;\n-}\n-\n-\n-static void atmtcp_v_close(struct atm_vcc *vcc)\n-{\n-\tstruct atmtcp_control msg;\n-\n-\tmemset(&msg,0,sizeof(msg));\n-\tmsg.addr.sap_family = AF_ATMPVC;\n-\tmsg.addr.sap_addr.vpi = vcc->vpi;\n-\tmsg.addr.sap_addr.vci = vcc->vci;\n-\tclear_bit(ATM_VF_READY,&vcc->flags);\n-\t(void) atmtcp_send_control(vcc,ATMTCP_CTRL_CLOSE,&msg,ATM_VF_ADDR);\n-}\n-\n-\n-static int atmtcp_v_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)\n-{\n-\tstruct atm_cirange ci;\n-\tstruct atm_vcc *vcc;\n-\tstruct sock *s;\n-\tint i;\n-\n-\tif (cmd != ATM_SETCIRANGE) return -ENOIOCTLCMD;\n-\tif (copy_from_user(&ci, arg,sizeof(ci))) return -EFAULT;\n-\tif (ci.vpi_bits == ATM_CI_MAX) ci.vpi_bits = MAX_VPI_BITS;\n-\tif (ci.vci_bits == ATM_CI_MAX) ci.vci_bits = MAX_VCI_BITS;\n-\tif (ci.vpi_bits > MAX_VPI_BITS || ci.vpi_bits < 0 ||\n-\t ci.vci_bits > MAX_VCI_BITS || ci.vci_bits < 0) return -EINVAL;\n-\tread_lock(&vcc_sklist_lock);\n-\tfor(i = 0; i < VCC_HTABLE_SIZE; ++i) {\n-\t\tstruct hlist_head *head = &vcc_hash[i];\n-\n-\t\tsk_for_each(s, head) {\n-\t\t\tvcc = atm_sk(s);\n-\t\t\tif (vcc->dev != dev)\n-\t\t\t\tcontinue;\n-\t\t\tif ((vcc->vpi >> ci.vpi_bits) ||\n-\t\t\t (vcc->vci >> ci.vci_bits)) {\n-\t\t\t\tread_unlock(&vcc_sklist_lock);\n-\t\t\t\treturn -EBUSY;\n-\t\t\t}\n-\t\t}\n-\t}\n-\tread_unlock(&vcc_sklist_lock);\n-\tdev->ci_range = ci;\n-\treturn 0;\n-}\n-\n-\n-static int atmtcp_v_send(struct atm_vcc *vcc,struct sk_buff *skb)\n-{\n-\tstruct atmtcp_dev_data *dev_data;\n-\tstruct atm_vcc *out_vcc=NULL; /* Initializer quietens GCC warning */\n-\tstruct sk_buff *new_skb;\n-\tstruct atmtcp_hdr *hdr;\n-\tint size;\n-\n-\tif (vcc->qos.txtp.traffic_class == ATM_NONE) {\n-\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\telse dev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\tdev_data = PRIV(vcc->dev);\n-\tif (dev_data) out_vcc = dev_data->vcc;\n-\tif (!dev_data || !out_vcc) {\n-\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\telse dev_kfree_skb(skb);\n-\t\tif (dev_data) return 0;\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\treturn -ENOLINK;\n-\t}\n-\tsize = skb->len+sizeof(struct atmtcp_hdr);\n-\tnew_skb = atm_alloc_charge(out_vcc,size,GFP_ATOMIC);\n-\tif (!new_skb) {\n-\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\telse dev_kfree_skb(skb);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\treturn -ENOBUFS;\n-\t}\n-\thdr = skb_put(new_skb, sizeof(struct atmtcp_hdr));\n-\thdr->vpi = htons(vcc->vpi);\n-\thdr->vci = htons(vcc->vci);\n-\thdr->length = htonl(skb->len);\n-\tskb_copy_from_linear_data(skb, skb_put(new_skb, skb->len), skb->len);\n-\tif (vcc->pop) vcc->pop(vcc,skb);\n-\telse dev_kfree_skb(skb);\n-\tout_vcc->push(out_vcc,new_skb);\n-\tatomic_inc(&vcc->stats->tx);\n-\tatomic_inc(&out_vcc->stats->rx);\n-\treturn 0;\n-}\n-\n-\n-static int atmtcp_v_proc(struct atm_dev *dev,loff_t *pos,char *page)\n-{\n-\tstruct atmtcp_dev_data *dev_data = PRIV(dev);\n-\n-\tif (*pos) return 0;\n-\tif (!dev_data->persist) return sprintf(page,\"ephemeral\\n\");\n-\treturn sprintf(page,\"persistent, %sconnected\\n\",\n-\t dev_data->vcc ? \"\" : \"dis\");\n-}\n-\n-\n-static void atmtcp_c_close(struct atm_vcc *vcc)\n-{\n-\tstruct atm_dev *atmtcp_dev;\n-\tstruct atmtcp_dev_data *dev_data;\n-\n-\tatmtcp_dev = (struct atm_dev *) vcc->dev_data;\n-\tdev_data = PRIV(atmtcp_dev);\n-\tdev_data->vcc = NULL;\n-\tif (dev_data->persist) return;\n-\tatmtcp_dev->dev_data = NULL;\n-\tkfree(dev_data);\n-\tatm_dev_deregister(atmtcp_dev);\n-\tvcc->dev_data = NULL;\n-\tmodule_put(THIS_MODULE);\n-}\n-\n-\n-static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)\n-{\n- struct hlist_head *head;\n- struct atm_vcc *vcc;\n- struct sock *s;\n-\n- head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];\n-\n-\tsk_for_each(s, head) {\n- vcc = atm_sk(s);\n- if (vcc->dev == dev &&\n- vcc->vci == vci && vcc->vpi == vpi &&\n- vcc->qos.rxtp.traffic_class != ATM_NONE) {\n- return vcc;\n- }\n- }\n- return NULL;\n-}\n-\n-static int atmtcp_c_pre_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct atmtcp_hdr *hdr;\n-\n-\tif (skb->len < sizeof(struct atmtcp_hdr))\n-\t\treturn -EINVAL;\n-\n-\thdr = (struct atmtcp_hdr *)skb->data;\n-\tif (hdr->length == ATMTCP_HDR_MAGIC)\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n-static int atmtcp_c_send(struct atm_vcc *vcc,struct sk_buff *skb)\n-{\n-\tstruct atm_dev *dev;\n-\tstruct atmtcp_hdr *hdr;\n-\tstruct atm_vcc *out_vcc;\n-\tstruct sk_buff *new_skb;\n-\tint result = 0;\n-\n-\tdev = vcc->dev_data;\n-\thdr = (struct atmtcp_hdr *) skb->data;\n-\tif (hdr->length == ATMTCP_HDR_MAGIC) {\n-\t\tresult = atmtcp_recv_control(\n-\t\t (struct atmtcp_control *) skb->data);\n-\t\tgoto done;\n-\t}\n-\tread_lock(&vcc_sklist_lock);\n-\tout_vcc = find_vcc(dev, ntohs(hdr->vpi), ntohs(hdr->vci));\n-\tread_unlock(&vcc_sklist_lock);\n-\tif (!out_vcc) {\n-\t\tresult = -EUNATCH;\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tgoto done;\n-\t}\n-\tskb_pull(skb,sizeof(struct atmtcp_hdr));\n-\tnew_skb = atm_alloc_charge(out_vcc,skb->len,GFP_KERNEL);\n-\tif (!new_skb) {\n-\t\tresult = -ENOBUFS;\n-\t\tgoto done;\n-\t}\n-\t__net_timestamp(new_skb);\n-\tskb_copy_from_linear_data(skb, skb_put(new_skb, skb->len), skb->len);\n-\tout_vcc->push(out_vcc,new_skb);\n-\tatomic_inc(&vcc->stats->tx);\n-\tatomic_inc(&out_vcc->stats->rx);\n-done:\n-\tif (vcc->pop) vcc->pop(vcc,skb);\n-\telse dev_kfree_skb(skb);\n-\treturn result;\n-}\n-\n-\n-/*\n- * Device operations for the virtual ATM devices created by ATMTCP.\n- */\n-\n-\n-static const struct atmdev_ops atmtcp_v_dev_ops = {\n-\t.dev_close\t= atmtcp_v_dev_close,\n-\t.open\t\t= atmtcp_v_open,\n-\t.close\t\t= atmtcp_v_close,\n-\t.ioctl\t\t= atmtcp_v_ioctl,\n-\t.send\t\t= atmtcp_v_send,\n-\t.proc_read\t= atmtcp_v_proc,\n-\t.owner\t\t= THIS_MODULE\n-};\n-\n-\n-/*\n- * Device operations for the ATMTCP control device.\n- */\n-\n-\n-static const struct atmdev_ops atmtcp_c_dev_ops = {\n-\t.close\t\t= atmtcp_c_close,\n-\t.pre_send\t= atmtcp_c_pre_send,\n-\t.send\t\t= atmtcp_c_send\n-};\n-\n-\n-static struct atm_dev atmtcp_control_dev = {\n-\t.ops\t\t= &atmtcp_c_dev_ops,\n-\t.type\t\t= \"atmtcp\",\n-\t.number\t\t= 999,\n-\t.lock\t\t= __SPIN_LOCK_UNLOCKED(atmtcp_control_dev.lock)\n-};\n-\n-\n-static int atmtcp_create(int itf,int persist,struct atm_dev **result)\n-{\n-\tstruct atmtcp_dev_data *dev_data;\n-\tstruct atm_dev *dev;\n-\n-\tdev_data = kmalloc_obj(*dev_data);\n-\tif (!dev_data)\n-\t\treturn -ENOMEM;\n-\n-\tdev = atm_dev_register(DEV_LABEL,NULL,&atmtcp_v_dev_ops,itf,NULL);\n-\tif (!dev) {\n-\t\tkfree(dev_data);\n-\t\treturn itf == -1 ? -ENOMEM : -EBUSY;\n-\t}\n-\tdev->ci_range.vpi_bits = MAX_VPI_BITS;\n-\tdev->ci_range.vci_bits = MAX_VCI_BITS;\n-\tdev->dev_data = dev_data;\n-\tPRIV(dev)->vcc = NULL;\n-\tPRIV(dev)->persist = persist;\n-\tif (result) *result = dev;\n-\treturn 0;\n-}\n-\n-\n-static int atmtcp_attach(struct atm_vcc *vcc,int itf)\n-{\n-\tstruct atm_dev *dev;\n-\n-\tdev = NULL;\n-\tif (itf != -1) dev = atm_dev_lookup(itf);\n-\tif (dev) {\n-\t\tif (dev->ops != &atmtcp_v_dev_ops) {\n-\t\t\tatm_dev_put(dev);\n-\t\t\treturn -EMEDIUMTYPE;\n-\t\t}\n-\t\tif (PRIV(dev)->vcc) {\n-\t\t\tatm_dev_put(dev);\n-\t\t\treturn -EBUSY;\n-\t\t}\n-\t}\n-\telse {\n-\t\tint error;\n-\n-\t\terror = atmtcp_create(itf,0,&dev);\n-\t\tif (error) return error;\n-\t}\n-\tPRIV(dev)->vcc = vcc;\n-\tvcc->dev = &atmtcp_control_dev;\n-\tvcc_insert_socket(sk_atm(vcc));\n-\tset_bit(ATM_VF_META,&vcc->flags);\n-\tset_bit(ATM_VF_READY,&vcc->flags);\n-\tvcc->dev_data = dev;\n-\t(void) atm_init_aal5(vcc); /* @@@ losing AAL in transit ... */\n-\tvcc->stats = &atmtcp_control_dev.stats.aal5;\n-\treturn dev->number;\n-}\n-\n-\n-static int atmtcp_create_persistent(int itf)\n-{\n-\treturn atmtcp_create(itf,1,NULL);\n-}\n-\n-\n-static int atmtcp_remove_persistent(int itf)\n-{\n-\tstruct atm_dev *dev;\n-\tstruct atmtcp_dev_data *dev_data;\n-\n-\tdev = atm_dev_lookup(itf);\n-\tif (!dev) return -ENODEV;\n-\tif (dev->ops != &atmtcp_v_dev_ops) {\n-\t\tatm_dev_put(dev);\n-\t\treturn -EMEDIUMTYPE;\n-\t}\n-\tdev_data = PRIV(dev);\n-\tif (!dev_data->persist) {\n-\t\tatm_dev_put(dev);\n-\t\treturn 0;\n-\t}\n-\tdev_data->persist = 0;\n-\tif (PRIV(dev)->vcc) {\n-\t\tatm_dev_put(dev);\n-\t\treturn 0;\n-\t}\n-\tkfree(dev_data);\n-\tatm_dev_put(dev);\n-\tatm_dev_deregister(dev);\n-\treturn 0;\n-}\n-\n-static int atmtcp_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)\n-{\n-\tint err = 0;\n-\tstruct atm_vcc *vcc = ATM_SD(sock);\n-\n-\tif (cmd != SIOCSIFATMTCP && cmd != ATMTCP_CREATE && cmd != ATMTCP_REMOVE)\n-\t\treturn -ENOIOCTLCMD;\n-\n-\tif (!capable(CAP_NET_ADMIN))\n-\t\treturn -EPERM;\n-\n-\tswitch (cmd) {\n-\t\tcase SIOCSIFATMTCP:\n-\t\t\terr = atmtcp_attach(vcc, (int) arg);\n-\t\t\tif (err >= 0) {\n-\t\t\t\tsock->state = SS_CONNECTED;\n-\t\t\t\t__module_get(THIS_MODULE);\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase ATMTCP_CREATE:\n-\t\t\terr = atmtcp_create_persistent((int) arg);\n-\t\t\tbreak;\n-\t\tcase ATMTCP_REMOVE:\n-\t\t\terr = atmtcp_remove_persistent((int) arg);\n-\t\t\tbreak;\n-\t}\n-\treturn err;\n-}\n-\n-static struct atm_ioctl atmtcp_ioctl_ops = {\n-\t.owner \t= THIS_MODULE,\n-\t.ioctl\t= atmtcp_ioctl,\n-};\n-\n-static __init int atmtcp_init(void)\n-{\n-\tregister_atm_ioctl(&atmtcp_ioctl_ops);\n-\treturn 0;\n-}\n-\n-\n-static void __exit atmtcp_exit(void)\n-{\n-\tderegister_atm_ioctl(&atmtcp_ioctl_ops);\n-}\n-\n-MODULE_DESCRIPTION(\"ATM over TCP\");\n-MODULE_LICENSE(\"GPL\");\n-module_init(atmtcp_init);\n-module_exit(atmtcp_exit);\ndiff --git a/drivers/atm/eni.c b/drivers/atm/eni.c\ndeleted file mode 100644\nindex 12cb3aa588bc..000000000000\n--- a/drivers/atm/eni.c\n+++ /dev/null\n@@ -1,2321 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/* drivers/atm/eni.c - Efficient Networks ENI155P device driver */\n- \n-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */\n- \n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \"tonga.h\"\n-#include \"midway.h\"\n-#include \"suni.h\"\n-#include \"eni.h\"\n-\n-/*\n- * TODO:\n- *\n- * Show stoppers\n- * none\n- *\n- * Minor\n- * - OAM support\n- * - fix bugs listed below\n- */\n-\n-/*\n- * KNOWN BUGS:\n- *\n- * - may run into JK-JK bug and deadlock\n- * - should allocate UBR channel first\n- * - buffer space allocation algorithm is stupid\n- * (RX: should be maxSDU+maxdelay*rate\n- * TX: should be maxSDU+min(maxSDU,maxdelay*rate) )\n- * - doesn't support OAM cells\n- * - eni_put_free may hang if not putting memory fragments that _complete_\n- * 2^n block (never happens in real life, though)\n- */\n-\n-\n-#if 0\n-#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)\n-#else\n-#define DPRINTK(format,args...)\n-#endif\n-\n-\n-#ifndef CONFIG_ATM_ENI_TUNE_BURST\n-#define CONFIG_ATM_ENI_BURST_TX_8W\n-#define CONFIG_ATM_ENI_BURST_RX_4W\n-#endif\n-\n-\n-#ifndef CONFIG_ATM_ENI_DEBUG\n-\n-\n-#define NULLCHECK(x)\n-\n-#define EVENT(s,a,b)\n-\n-\n-static void event_dump(void)\n-{\n-}\n-\n-\n-#else\n-\n-\n-/* \n- * NULL pointer checking\n- */\n-\n-#define NULLCHECK(x) \\\n-\tif ((unsigned long) (x) < 0x30) \\\n-\t\tprintk(KERN_CRIT #x \"==0x%lx\\n\",(unsigned long) (x))\n-\n-/*\n- * Very extensive activity logging. Greatly improves bug detection speed but\n- * costs a few Mbps if enabled.\n- */\n-\n-#define EV 64\n-\n-static const char *ev[EV];\n-static unsigned long ev_a[EV],ev_b[EV];\n-static int ec = 0;\n-\n-\n-static void EVENT(const char *s,unsigned long a,unsigned long b)\n-{\n-\tev[ec] = s; \n-\tev_a[ec] = a;\n-\tev_b[ec] = b;\n-\tec = (ec+1) % EV;\n-}\n-\n-\n-static void event_dump(void)\n-{\n-\tint n,i;\n-\n-\tfor (n = 0; n < EV; n++) {\n-\t\ti = (ec+n) % EV;\n-\t\tprintk(KERN_NOTICE);\n-\t\tprintk(ev[i] ? ev[i] : \"(null)\",ev_a[i],ev_b[i]);\n-\t}\n-}\n-\n-\n-#endif /* CONFIG_ATM_ENI_DEBUG */\n-\n-\n-/*\n- * NExx must not be equal at end\n- * EExx may be equal at end\n- * xxPJOK verify validity of pointer jumps\n- * xxPMOK operating on a circular buffer of \"c\" words\n- */\n-\n-#define NEPJOK(a0,a1,b) \\\n- ((a0) < (a1) ? (b) <= (a0) || (b) > (a1) : (b) <= (a0) && (b) > (a1))\n-#define EEPJOK(a0,a1,b) \\\n- ((a0) < (a1) ? (b) < (a0) || (b) >= (a1) : (b) < (a0) && (b) >= (a1))\n-#define NEPMOK(a0,d,b,c) NEPJOK(a0,(a0+d) & (c-1),b)\n-#define EEPMOK(a0,d,b,c) EEPJOK(a0,(a0+d) & (c-1),b)\n-\n-\n-static int tx_complete = 0,dma_complete = 0,queued = 0,requeued = 0,\n- backlogged = 0,rx_enqueued = 0,rx_dequeued = 0,pushed = 0,submitted = 0,\n- putting = 0;\n-\n-static struct atm_dev *eni_boards = NULL;\n-\n-/* Read/write registers on card */\n-#define eni_in(r)\treadl(eni_dev->reg+(r)*4)\n-#define eni_out(v,r)\twritel((v),eni_dev->reg+(r)*4)\n-\n-\n-/*-------------------------------- utilities --------------------------------*/\n-\n-\n-static void dump_mem(struct eni_dev *eni_dev)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < eni_dev->free_len; i++)\n-\t\tprintk(KERN_DEBUG \" %d: %p %d\\n\",i,\n-\t\t eni_dev->free_list[i].start,\n-\t\t 1 << eni_dev->free_list[i].order);\n-}\n-\n-\n-static void dump(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\n-\tint i;\n-\n-\teni_dev = ENI_DEV(dev);\n-\tprintk(KERN_NOTICE \"Free memory\\n\");\n-\tdump_mem(eni_dev);\n-\tprintk(KERN_NOTICE \"TX buffers\\n\");\n-\tfor (i = 0; i < NR_CHAN; i++)\n-\t\tif (eni_dev->tx[i].send)\n-\t\t\tprintk(KERN_NOTICE \" TX %d @ %p: %ld\\n\",i,\n-\t\t\t eni_dev->tx[i].send,eni_dev->tx[i].words*4);\n-\tprintk(KERN_NOTICE \"RX buffers\\n\");\n-\tfor (i = 0; i < 1024; i++)\n-\t\tif (eni_dev->rx_map[i] && ENI_VCC(eni_dev->rx_map[i])->rx)\n-\t\t\tprintk(KERN_NOTICE \" RX %d @ %p: %ld\\n\",i,\n-\t\t\t ENI_VCC(eni_dev->rx_map[i])->recv,\n-\t\t\t ENI_VCC(eni_dev->rx_map[i])->words*4);\n-\tprintk(KERN_NOTICE \"----\\n\");\n-}\n-\n-\n-static void eni_put_free(struct eni_dev *eni_dev, void __iomem *start,\n- unsigned long size)\n-{\n-\tstruct eni_free *list;\n-\tint len,order;\n-\n-\tDPRINTK(\"init 0x%lx+%ld(0x%lx)\\n\",start,size,size);\n-\tstart += eni_dev->base_diff;\n-\tlist = eni_dev->free_list;\n-\tlen = eni_dev->free_len;\n-\twhile (size) {\n-\t\tif (len >= eni_dev->free_list_size) {\n-\t\t\tprintk(KERN_CRIT \"eni_put_free overflow (%p,%ld)\\n\",\n-\t\t\t start,size);\n-\t\t\tbreak;\n-\t\t}\n-\t\tfor (order = 0; !(((unsigned long)start | size) & (1 << order)); order++);\n-\t\tif (MID_MIN_BUF_SIZE > (1 << order)) {\n-\t\t\tprintk(KERN_CRIT \"eni_put_free: order %d too small\\n\",\n-\t\t\t order);\n-\t\t\tbreak;\n-\t\t}\n-\t\tlist[len].start = (void __iomem *) start;\n-\t\tlist[len].order = order;\n-\t\tlen++;\n-\t\tstart += 1 << order;\n-\t\tsize -= 1 << order;\n-\t}\n-\teni_dev->free_len = len;\n-\t/*dump_mem(eni_dev);*/\n-}\n-\n-\n-static void __iomem *eni_alloc_mem(struct eni_dev *eni_dev, unsigned long *size)\n-{\n-\tstruct eni_free *list;\n-\tvoid __iomem *start;\n-\tint len,i,order,best_order,index;\n-\n-\tlist = eni_dev->free_list;\n-\tlen = eni_dev->free_len;\n-\tif (*size < MID_MIN_BUF_SIZE) *size = MID_MIN_BUF_SIZE;\n-\tif (*size > MID_MAX_BUF_SIZE) return NULL;\n-\tfor (order = 0; (1 << order) < *size; order++)\n-\t\t;\n-\tDPRINTK(\"trying: %ld->%d\\n\",*size,order);\n-\tbest_order = 65; /* we don't have more than 2^64 of anything ... */\n-\tindex = 0; /* silence GCC */\n-\tfor (i = 0; i < len; i++)\n-\t\tif (list[i].order == order) {\n-\t\t\tbest_order = order;\n-\t\t\tindex = i;\n-\t\t\tbreak;\n-\t\t}\n-\t\telse if (best_order > list[i].order && list[i].order > order) {\n-\t\t\t\tbest_order = list[i].order;\n-\t\t\t\tindex = i;\n-\t\t\t}\n-\tif (best_order == 65) return NULL;\n-\tstart = list[index].start-eni_dev->base_diff;\n-\tlist[index] = list[--len];\n-\teni_dev->free_len = len;\n-\t*size = 1 << order;\n-\teni_put_free(eni_dev,start+*size,(1 << best_order)-*size);\n-\tDPRINTK(\"%ld bytes (order %d) at 0x%lx\\n\",*size,order,start);\n-\tmemset_io(start,0,*size); /* never leak data */\n-\t/*dump_mem(eni_dev);*/\n-\treturn start;\n-}\n-\n-\n-static void eni_free_mem(struct eni_dev *eni_dev, void __iomem *start,\n- unsigned long size)\n-{\n-\tstruct eni_free *list;\n-\tint len,i,order;\n-\n-\tstart += eni_dev->base_diff;\n-\tlist = eni_dev->free_list;\n-\tlen = eni_dev->free_len;\n-\tfor (order = -1; size; order++) size >>= 1;\n-\tDPRINTK(\"eni_free_mem: %p+0x%lx (order %d)\\n\",start,size,order);\n-\tfor (i = 0; i < len; i++)\n-\t\tif (((unsigned long) list[i].start) == ((unsigned long)start^(1 << order)) &&\n-\t\t list[i].order == order) {\n-\t\t\tDPRINTK(\"match[%d]: 0x%lx/0x%lx(0x%x), %d/%d\\n\",i,\n-\t\t\t list[i].start,start,1 << order,list[i].order,order);\n-\t\t\tlist[i] = list[--len];\n-\t\t\tstart = (void __iomem *) ((unsigned long) start & ~(unsigned long) (1 << order));\n-\t\t\torder++;\n-\t\t\ti = -1;\n-\t\t\tcontinue;\n-\t\t}\n-\tif (len >= eni_dev->free_list_size) {\n-\t\tprintk(KERN_ALERT \"eni_free_mem overflow (%p,%d)\\n\",start,\n-\t\t order);\n-\t\treturn;\n-\t}\n-\tlist[len].start = start;\n-\tlist[len].order = order;\n-\teni_dev->free_len = len+1;\n-\t/*dump_mem(eni_dev);*/\n-}\n-\n-\n-/*----------------------------------- RX ------------------------------------*/\n-\n-\n-#define ENI_VCC_NOS ((struct atm_vcc *) 1)\n-\n-\n-static void rx_ident_err(struct atm_vcc *vcc)\n-{\n-\tstruct atm_dev *dev;\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\n-\tdev = vcc->dev;\n-\teni_dev = ENI_DEV(dev);\n-\t/* immediately halt adapter */\n-\teni_out(eni_in(MID_MC_S) &\n-\t ~(MID_DMA_ENABLE | MID_TX_ENABLE | MID_RX_ENABLE),MID_MC_S);\n-\t/* dump useful information */\n-\teni_vcc = ENI_VCC(vcc);\n-\tprintk(KERN_ALERT DEV_LABEL \"(itf %d): driver error - RX ident \"\n-\t \"mismatch\\n\",dev->number);\n-\tprintk(KERN_ALERT \" VCI %d, rxing %d, words %ld\\n\",vcc->vci,\n-\t eni_vcc->rxing,eni_vcc->words);\n-\tprintk(KERN_ALERT \" host descr 0x%lx, rx pos 0x%lx, descr value \"\n-\t \"0x%x\\n\",eni_vcc->descr,eni_vcc->rx_pos,\n-\t (unsigned) readl(eni_vcc->recv+eni_vcc->descr*4));\n-\tprintk(KERN_ALERT \" last %p, servicing %d\\n\",eni_vcc->last,\n-\t eni_vcc->servicing);\n-\tEVENT(\"---dump ends here---\\n\",0,0);\n-\tprintk(KERN_NOTICE \"---recent events---\\n\");\n-\tevent_dump();\n-\tENI_DEV(dev)->fast = NULL; /* really stop it */\n-\tENI_DEV(dev)->slow = NULL;\n-\tskb_queue_head_init(&ENI_DEV(dev)->rx_queue);\n-}\n-\n-\n-static int do_rx_dma(struct atm_vcc *vcc,struct sk_buff *skb,\n- unsigned long skip,unsigned long size,unsigned long eff)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\tu32 dma_rd,dma_wr;\n-\tu32 dma[RX_DMA_BUF*2];\n-\tdma_addr_t paddr;\n-\tunsigned long here;\n-\tint i,j;\n-\n-\teni_dev = ENI_DEV(vcc->dev);\n-\teni_vcc = ENI_VCC(vcc);\n-\tpaddr = 0; /* GCC, shut up */\n-\tif (skb) {\n-\t\tpaddr = dma_map_single(&eni_dev->pci_dev->dev,skb->data,skb->len,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tif (dma_mapping_error(&eni_dev->pci_dev->dev, paddr))\n-\t\t\tgoto dma_map_error;\n-\t\tENI_PRV_PADDR(skb) = paddr;\n-\t\tif (paddr & 3)\n-\t\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): VCI %d has \"\n-\t\t\t \"mis-aligned RX data (0x%lx)\\n\",vcc->dev->number,\n-\t\t\t vcc->vci,(unsigned long) paddr);\n-\t\tENI_PRV_SIZE(skb) = size+skip;\n-\t\t /* PDU plus descriptor */\n-\t\tATM_SKB(skb)->vcc = vcc;\n-\t}\n-\tj = 0;\n-\tif ((eff && skip) || 1) { /* @@@ actually, skip is always == 1 ... */\n-\t\there = (eni_vcc->descr+skip) & (eni_vcc->words-1);\n-\t\tdma[j++] = (here << MID_DMA_COUNT_SHIFT) | (vcc->vci\n-\t\t << MID_DMA_VCI_SHIFT) | MID_DT_JK;\n-\t\tdma[j++] = 0;\n-\t}\n-\there = (eni_vcc->descr+size+skip) & (eni_vcc->words-1);\n-\tif (!eff) size += skip;\n-\telse {\n-\t\tunsigned long words;\n-\n-\t\tif (!size) {\n-\t\t\tDPRINTK(\"strange things happen ...\\n\");\n-\t\t\tEVENT(\"strange things happen ... (skip=%ld,eff=%ld)\\n\",\n-\t\t\t size,eff);\n-\t\t}\n-\t\twords = eff;\n-\t\tif (paddr & 15) {\n-\t\t\tunsigned long init;\n-\n-\t\t\tinit = 4-((paddr & 15) >> 2);\n-\t\t\tif (init > words) init = words;\n-\t\t\tdma[j++] = MID_DT_WORD | (init << MID_DMA_COUNT_SHIFT) |\n-\t\t\t (vcc->vci << MID_DMA_VCI_SHIFT);\n-\t\t\tdma[j++] = paddr;\n-\t\t\tpaddr += init << 2;\n-\t\t\twords -= init;\n-\t\t}\n-#ifdef CONFIG_ATM_ENI_BURST_RX_16W /* may work with some PCI chipsets ... */\n-\t\tif (words & ~15) {\n-\t\t\tdma[j++] = MID_DT_16W | ((words >> 4) <<\n-\t\t\t MID_DMA_COUNT_SHIFT) | (vcc->vci <<\n-\t\t\t MID_DMA_VCI_SHIFT);\n-\t\t\tdma[j++] = paddr;\n-\t\t\tpaddr += (words & ~15) << 2;\n-\t\t\twords &= 15;\n-\t\t}\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_8W /* works only with *some* PCI chipsets ... */\n-\t\tif (words & ~7) {\n-\t\t\tdma[j++] = MID_DT_8W | ((words >> 3) <<\n-\t\t\t MID_DMA_COUNT_SHIFT) | (vcc->vci <<\n-\t\t\t MID_DMA_VCI_SHIFT);\n-\t\t\tdma[j++] = paddr;\n-\t\t\tpaddr += (words & ~7) << 2;\n-\t\t\twords &= 7;\n-\t\t}\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_4W /* recommended */\n-\t\tif (words & ~3) {\n-\t\t\tdma[j++] = MID_DT_4W | ((words >> 2) <<\n-\t\t\t MID_DMA_COUNT_SHIFT) | (vcc->vci <<\n-\t\t\t MID_DMA_VCI_SHIFT);\n-\t\t\tdma[j++] = paddr;\n-\t\t\tpaddr += (words & ~3) << 2;\n-\t\t\twords &= 3;\n-\t\t}\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_2W /* probably useless if RX_4W, RX_8W, ... */\n-\t\tif (words & ~1) {\n-\t\t\tdma[j++] = MID_DT_2W | ((words >> 1) <<\n-\t\t\t MID_DMA_COUNT_SHIFT) | (vcc->vci <<\n-\t\t\t MID_DMA_VCI_SHIFT);\n-\t\t\tdma[j++] = paddr;\n-\t\t\tpaddr += (words & ~1) << 2;\n-\t\t\twords &= 1;\n-\t\t}\n-#endif\n-\t\tif (words) {\n-\t\t\tdma[j++] = MID_DT_WORD | (words << MID_DMA_COUNT_SHIFT)\n-\t\t\t | (vcc->vci << MID_DMA_VCI_SHIFT);\n-\t\t\tdma[j++] = paddr;\n-\t\t}\n-\t}\n-\tif (size != eff) {\n-\t\tdma[j++] = (here << MID_DMA_COUNT_SHIFT) |\n-\t\t (vcc->vci << MID_DMA_VCI_SHIFT) | MID_DT_JK;\n-\t\tdma[j++] = 0;\n-\t}\n-\tif (!j || j > 2*RX_DMA_BUF) {\n-\t\tprintk(KERN_CRIT DEV_LABEL \"!j or j too big!!!\\n\");\n-\t\tgoto trouble;\n-\t}\n-\tdma[j-2] |= MID_DMA_END;\n-\tj = j >> 1;\n-\tdma_wr = eni_in(MID_DMA_WR_RX);\n-\tdma_rd = eni_in(MID_DMA_RD_RX);\n-\t/*\n-\t * Can I move the dma_wr pointer by 2j+1 positions without overwriting\n-\t * data that hasn't been read (position of dma_rd) yet ?\n-\t */\n-\tif (!NEPMOK(dma_wr,j+j+1,dma_rd,NR_DMA_RX)) { /* @@@ +1 is ugly */\n-\t\tprintk(KERN_WARNING DEV_LABEL \"(itf %d): RX DMA full\\n\",\n-\t\t vcc->dev->number);\n-\t\tgoto trouble;\n-\t}\n- for (i = 0; i < j; i++) {\n-\t\twritel(dma[i*2],eni_dev->rx_dma+dma_wr*8);\n-\t\twritel(dma[i*2+1],eni_dev->rx_dma+dma_wr*8+4);\n-\t\tdma_wr = (dma_wr+1) & (NR_DMA_RX-1);\n- }\n-\tif (skb) {\n-\t\tENI_PRV_POS(skb) = eni_vcc->descr+size+1;\n-\t\tskb_queue_tail(&eni_dev->rx_queue,skb);\n-\t\teni_vcc->last = skb;\n-\t\trx_enqueued++;\n-\t}\n-\teni_vcc->descr = here;\n-\teni_out(dma_wr,MID_DMA_WR_RX);\n-\treturn 0;\n-\n-trouble:\n-\tif (paddr)\n-\t\tdma_unmap_single(&eni_dev->pci_dev->dev,paddr,skb->len,\n-\t\t\t\t DMA_FROM_DEVICE);\n-dma_map_error:\n-\tif (skb) dev_kfree_skb_irq(skb);\n-\treturn -1;\n-}\n-\n-\n-static void discard(struct atm_vcc *vcc,unsigned long size)\n-{\n-\tstruct eni_vcc *eni_vcc;\n-\n-\teni_vcc = ENI_VCC(vcc);\n-\tEVENT(\"discard (size=%ld)\\n\",size,0);\n-\twhile (do_rx_dma(vcc,NULL,1,size,0)) EVENT(\"BUSY LOOP\",0,0);\n-\t /* could do a full fallback, but that might be more expensive */\n-\tif (eni_vcc->rxing) ENI_PRV_POS(eni_vcc->last) += size+1;\n-\telse eni_vcc->rx_pos = (eni_vcc->rx_pos+size+1) & (eni_vcc->words-1);\n-}\n-\n-\n-/*\n- * TODO: should check whether direct copies (without DMA setup, dequeuing on\n- * interrupt, etc.) aren't much faster for AAL0\n- */\n-\n-static int rx_aal0(struct atm_vcc *vcc)\n-{\n-\tstruct eni_vcc *eni_vcc;\n-\tunsigned long descr;\n-\tunsigned long length;\n-\tstruct sk_buff *skb;\n-\n-\tDPRINTK(\">rx_aal0\\n\");\n-\teni_vcc = ENI_VCC(vcc);\n-\tdescr = readl(eni_vcc->recv+eni_vcc->descr*4);\n-\tif ((descr & MID_RED_IDEN) != (MID_RED_RX_ID << MID_RED_SHIFT)) {\n-\t\trx_ident_err(vcc);\n-\t\treturn 1;\n-\t}\n-\tif (descr & MID_RED_T) {\n-\t\tDPRINTK(DEV_LABEL \"(itf %d): trashing empty cell\\n\",\n-\t\t vcc->dev->number);\n-\t\tlength = 0;\n-\t\tatomic_inc(&vcc->stats->rx_err);\n-\t}\n-\telse {\n-\t\tlength = ATM_CELL_SIZE-1; /* no HEC */\n-\t}\n-\tskb = length ? atm_alloc_charge(vcc,length,GFP_ATOMIC) : NULL;\n-\tif (!skb) {\n-\t\tdiscard(vcc,length >> 2);\n-\t\treturn 0;\n-\t}\n-\tskb_put(skb,length);\n-\tskb->tstamp = eni_vcc->timestamp;\n-\tDPRINTK(\"got len %ld\\n\",length);\n-\tif (do_rx_dma(vcc,skb,1,length >> 2,length >> 2)) return 1;\n-\teni_vcc->rxing++;\n-\treturn 0;\n-}\n-\n-\n-static int rx_aal5(struct atm_vcc *vcc)\n-{\n-\tstruct eni_vcc *eni_vcc;\n-\tunsigned long descr;\n-\tunsigned long size,eff,length;\n-\tstruct sk_buff *skb;\n-\n-\tEVENT(\"rx_aal5\\n\",0,0);\n-\tDPRINTK(\">rx_aal5\\n\");\n-\teni_vcc = ENI_VCC(vcc);\n-\tdescr = readl(eni_vcc->recv+eni_vcc->descr*4);\n-\tif ((descr & MID_RED_IDEN) != (MID_RED_RX_ID << MID_RED_SHIFT)) {\n-\t\trx_ident_err(vcc);\n-\t\treturn 1;\n-\t}\n-\tif (descr & (MID_RED_T | MID_RED_CRC_ERR)) {\n-\t\tif (descr & MID_RED_T) {\n-\t\t\tEVENT(\"empty cell (descr=0x%lx)\\n\",descr,0);\n-\t\t\tDPRINTK(DEV_LABEL \"(itf %d): trashing empty cell\\n\",\n-\t\t\t vcc->dev->number);\n-\t\t\tsize = 0;\n-\t\t}\n-\t\telse {\n-\t\t\tstatic unsigned long silence = 0;\n-\n-\t\t\tif (time_after(jiffies, silence) || silence == 0) {\n-\t\t\t\tprintk(KERN_WARNING DEV_LABEL \"(itf %d): \"\n-\t\t\t\t \"discarding PDU(s) with CRC error\\n\",\n-\t\t\t\t vcc->dev->number);\n-\t\t\t\tsilence = (jiffies+2*HZ)|1;\n-\t\t\t}\n-\t\t\tsize = (descr & MID_RED_COUNT)*(ATM_CELL_PAYLOAD >> 2);\n-\t\t\tEVENT(\"CRC error (descr=0x%lx,size=%ld)\\n\",descr,\n-\t\t\t size);\n-\t\t}\n-\t\teff = length = 0;\n-\t\tatomic_inc(&vcc->stats->rx_err);\n-\t}\n-\telse {\n-\t\tsize = (descr & MID_RED_COUNT)*(ATM_CELL_PAYLOAD >> 2);\n-\t\tDPRINTK(\"size=%ld\\n\",size);\n-\t\tlength = readl(eni_vcc->recv+(((eni_vcc->descr+size-1) &\n-\t\t (eni_vcc->words-1)))*4) & 0xffff;\n-\t\t\t\t/* -trailer(2)+header(1) */\n-\t\tif (length && length <= (size << 2)-8 && length <=\n-\t\t ATM_MAX_AAL5_PDU) eff = (length+3) >> 2;\n-\t\telse {\t\t\t\t /* ^ trailer length (8) */\n-\t\t\tEVENT(\"bad PDU (descr=0x08%lx,length=%ld)\\n\",descr,\n-\t\t\t length);\n-\t\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): bad AAL5 PDU \"\n-\t\t\t \"(VCI=%d,length=%ld,size=%ld (descr 0x%lx))\\n\",\n-\t\t\t vcc->dev->number,vcc->vci,length,size << 2,descr);\n-\t\t\tlength = eff = 0;\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t}\n-\t}\n-\tskb = eff ? atm_alloc_charge(vcc,eff << 2,GFP_ATOMIC) : NULL;\n-\tif (!skb) {\n-\t\tdiscard(vcc,size);\n-\t\treturn 0;\n-\t}\n-\tskb_put(skb,length);\n-\tDPRINTK(\"got len %ld\\n\",length);\n-\tif (do_rx_dma(vcc,skb,1,size,eff)) return 1;\n-\teni_vcc->rxing++;\n-\treturn 0;\n-}\n-\n-\n-static inline int rx_vcc(struct atm_vcc *vcc)\n-{\n-\tvoid __iomem *vci_dsc;\n-\tunsigned long tmp;\n-\tstruct eni_vcc *eni_vcc;\n-\n-\teni_vcc = ENI_VCC(vcc);\n-\tvci_dsc = ENI_DEV(vcc->dev)->vci+vcc->vci*16;\n-\tEVENT(\"rx_vcc(1)\\n\",0,0);\n-\twhile (eni_vcc->descr != (tmp = (readl(vci_dsc+4) & MID_VCI_DESCR) >>\n-\t MID_VCI_DESCR_SHIFT)) {\n-\t\tEVENT(\"rx_vcc(2: host dsc=0x%lx, nic dsc=0x%lx)\\n\",\n-\t\t eni_vcc->descr,tmp);\n-\t\tDPRINTK(\"CB_DESCR %ld REG_DESCR %d\\n\",ENI_VCC(vcc)->descr,\n-\t\t (((unsigned) readl(vci_dsc+4) & MID_VCI_DESCR) >>\n-\t\t MID_VCI_DESCR_SHIFT));\n-\t\tif (ENI_VCC(vcc)->rx(vcc)) return 1;\n-\t}\n-\t/* clear IN_SERVICE flag */\n-\twritel(readl(vci_dsc) & ~MID_VCI_IN_SERVICE,vci_dsc);\n-\t/*\n-\t * If new data has arrived between evaluating the while condition and\n-\t * clearing IN_SERVICE, we wouldn't be notified until additional data\n-\t * follows. So we have to loop again to be sure.\n-\t */\n-\tEVENT(\"rx_vcc(3)\\n\",0,0);\n-\twhile (ENI_VCC(vcc)->descr != (tmp = (readl(vci_dsc+4) & MID_VCI_DESCR)\n-\t >> MID_VCI_DESCR_SHIFT)) {\n-\t\tEVENT(\"rx_vcc(4: host dsc=0x%lx, nic dsc=0x%lx)\\n\",\n-\t\t eni_vcc->descr,tmp);\n-\t\tDPRINTK(\"CB_DESCR %ld REG_DESCR %d\\n\",ENI_VCC(vcc)->descr,\n-\t\t (((unsigned) readl(vci_dsc+4) & MID_VCI_DESCR) >>\n-\t\t MID_VCI_DESCR_SHIFT));\n-\t\tif (ENI_VCC(vcc)->rx(vcc)) return 1;\n-\t}\n-\treturn 0;\n-}\n-\n-\n-static void poll_rx(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tstruct atm_vcc *curr;\n-\n-\teni_dev = ENI_DEV(dev);\n-\twhile ((curr = eni_dev->fast)) {\n-\t\tEVENT(\"poll_rx.fast\\n\",0,0);\n-\t\tif (rx_vcc(curr)) return;\n-\t\teni_dev->fast = ENI_VCC(curr)->next;\n-\t\tENI_VCC(curr)->next = ENI_VCC_NOS;\n-\t\tbarrier();\n-\t\tENI_VCC(curr)->servicing--;\n-\t}\n-\twhile ((curr = eni_dev->slow)) {\n-\t\tEVENT(\"poll_rx.slow\\n\",0,0);\n-\t\tif (rx_vcc(curr)) return;\n-\t\teni_dev->slow = ENI_VCC(curr)->next;\n-\t\tENI_VCC(curr)->next = ENI_VCC_NOS;\n-\t\tbarrier();\n-\t\tENI_VCC(curr)->servicing--;\n-\t}\n-}\n-\n-\n-static void get_service(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tstruct atm_vcc *vcc;\n-\tunsigned long vci;\n-\n-\tDPRINTK(\">get_service\\n\");\n-\teni_dev = ENI_DEV(dev);\n-\twhile (eni_in(MID_SERV_WRITE) != eni_dev->serv_read) {\n-\t\tvci = readl(eni_dev->service+eni_dev->serv_read*4);\n-\t\teni_dev->serv_read = (eni_dev->serv_read+1) & (NR_SERVICE-1);\n-\t\tvcc = eni_dev->rx_map[vci & 1023];\n-\t\tif (!vcc) {\n-\t\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): VCI %ld not \"\n-\t\t\t \"found\\n\",dev->number,vci);\n-\t\t\tcontinue; /* nasty but we try to go on anyway */\n-\t\t\t/* @@@ nope, doesn't work */\n-\t\t}\n-\t\tEVENT(\"getting from service\\n\",0,0);\n-\t\tif (ENI_VCC(vcc)->next != ENI_VCC_NOS) {\n-\t\t\tEVENT(\"double service\\n\",0,0);\n-\t\t\tDPRINTK(\"Grr, servicing VCC %ld twice\\n\",vci);\n-\t\t\tcontinue;\n-\t\t}\n-\t\tENI_VCC(vcc)->timestamp = ktime_get_real();\n-\t\tENI_VCC(vcc)->next = NULL;\n-\t\tif (vcc->qos.rxtp.traffic_class == ATM_CBR) {\n-\t\t\tif (eni_dev->fast)\n-\t\t\t\tENI_VCC(eni_dev->last_fast)->next = vcc;\n-\t\t\telse eni_dev->fast = vcc;\n-\t\t\teni_dev->last_fast = vcc;\n-\t\t}\n-\t\telse {\n-\t\t\tif (eni_dev->slow)\n-\t\t\t\tENI_VCC(eni_dev->last_slow)->next = vcc;\n-\t\t\telse eni_dev->slow = vcc;\n-\t\t\teni_dev->last_slow = vcc;\n-\t\t}\n-\t\tputting++;\n-\t\tENI_VCC(vcc)->servicing++;\n-\t}\n-}\n-\n-\n-static void dequeue_rx(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\tstruct atm_vcc *vcc;\n-\tstruct sk_buff *skb;\n-\tvoid __iomem *vci_dsc;\n-\tint first;\n-\n-\teni_dev = ENI_DEV(dev);\n-\tfirst = 1;\n-\twhile (1) {\n-\t\tskb = skb_dequeue(&eni_dev->rx_queue);\n-\t\tif (!skb) {\n-\t\t\tif (first) {\n-\t\t\t\tDPRINTK(DEV_LABEL \"(itf %d): RX but not \"\n-\t\t\t\t \"rxing\\n\",dev->number);\n-\t\t\t\tEVENT(\"nothing to dequeue\\n\",0,0);\n-\t\t\t}\n-\t\t\tbreak;\n-\t\t}\n-\t\tEVENT(\"dequeued (size=%ld,pos=0x%lx)\\n\",ENI_PRV_SIZE(skb),\n-\t\t ENI_PRV_POS(skb));\n-\t\trx_dequeued++;\n-\t\tvcc = ATM_SKB(skb)->vcc;\n-\t\teni_vcc = ENI_VCC(vcc);\n-\t\tfirst = 0;\n-\t\tvci_dsc = eni_dev->vci+vcc->vci*16;\n-\t\tif (!EEPMOK(eni_vcc->rx_pos,ENI_PRV_SIZE(skb),\n-\t\t (readl(vci_dsc+4) & MID_VCI_READ) >> MID_VCI_READ_SHIFT,\n-\t\t eni_vcc->words)) {\n-\t\t\tEVENT(\"requeuing\\n\",0,0);\n-\t\t\tskb_queue_head(&eni_dev->rx_queue,skb);\n-\t\t\tbreak;\n-\t\t}\n-\t\teni_vcc->rxing--;\n-\t\teni_vcc->rx_pos = ENI_PRV_POS(skb) & (eni_vcc->words-1);\n-\t\tdma_unmap_single(&eni_dev->pci_dev->dev,ENI_PRV_PADDR(skb),skb->len,\n-\t\t\t DMA_TO_DEVICE);\n-\t\tif (!skb->len) dev_kfree_skb_irq(skb);\n-\t\telse {\n-\t\t\tEVENT(\"pushing (len=%ld)\\n\",skb->len,0);\n-\t\t\tif (vcc->qos.aal == ATM_AAL0)\n-\t\t\t\t*(unsigned long *) skb->data =\n-\t\t\t\t ntohl(*(unsigned long *) skb->data);\n-\t\t\tmemset(skb->cb,0,sizeof(struct eni_skb_prv));\n-\t\t\tvcc->push(vcc,skb);\n-\t\t\tpushed++;\n-\t\t}\n-\t\tatomic_inc(&vcc->stats->rx);\n-\t}\n-\twake_up(&eni_dev->rx_wait);\n-}\n-\n-\n-static int open_rx_first(struct atm_vcc *vcc)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\tunsigned long size;\n-\n-\tDPRINTK(\"open_rx_first\\n\");\n-\teni_dev = ENI_DEV(vcc->dev);\n-\teni_vcc = ENI_VCC(vcc);\n-\teni_vcc->rx = NULL;\n-\tif (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;\n-\tsize = vcc->qos.rxtp.max_sdu*eni_dev->rx_mult/100;\n-\tif (size > MID_MAX_BUF_SIZE && vcc->qos.rxtp.max_sdu <=\n-\t MID_MAX_BUF_SIZE)\n-\t\tsize = MID_MAX_BUF_SIZE;\n-\teni_vcc->recv = eni_alloc_mem(eni_dev,&size);\n-\tDPRINTK(\"rx at 0x%lx\\n\",eni_vcc->recv);\n-\teni_vcc->words = size >> 2;\n-\tif (!eni_vcc->recv) return -ENOBUFS;\n-\teni_vcc->rx = vcc->qos.aal == ATM_AAL5 ? rx_aal5 : rx_aal0;\n-\teni_vcc->descr = 0;\n-\teni_vcc->rx_pos = 0;\n-\teni_vcc->rxing = 0;\n-\teni_vcc->servicing = 0;\n-\teni_vcc->next = ENI_VCC_NOS;\n-\treturn 0;\n-}\n-\n-\n-static int open_rx_second(struct atm_vcc *vcc)\n-{\n-\tvoid __iomem *here;\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\tunsigned long size;\n-\tint order;\n-\n-\tDPRINTK(\"open_rx_second\\n\");\n-\teni_dev = ENI_DEV(vcc->dev);\n-\teni_vcc = ENI_VCC(vcc);\n-\tif (!eni_vcc->rx) return 0;\n-\t/* set up VCI descriptor */\n-\there = eni_dev->vci+vcc->vci*16;\n-\tDPRINTK(\"loc 0x%x\\n\",(unsigned) (eni_vcc->recv-eni_dev->ram)/4);\n-\tsize = eni_vcc->words >> 8;\n-\tfor (order = -1; size; order++) size >>= 1;\n-\twritel(0,here+4); /* descr, read = 0 */\n-\twritel(0,here+8); /* write, state, count = 0 */\n-\tif (eni_dev->rx_map[vcc->vci])\n-\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): BUG - VCI %d already \"\n-\t\t \"in use\\n\",vcc->dev->number,vcc->vci);\n-\teni_dev->rx_map[vcc->vci] = vcc; /* now it counts */\n-\twritel(((vcc->qos.aal != ATM_AAL5 ? MID_MODE_RAW : MID_MODE_AAL5) <<\n-\t MID_VCI_MODE_SHIFT) | MID_VCI_PTI_MODE |\n-\t (((eni_vcc->recv-eni_dev->ram) >> (MID_LOC_SKIP+2)) <<\n-\t MID_VCI_LOCATION_SHIFT) | (order << MID_VCI_SIZE_SHIFT),here);\n-\treturn 0;\n-}\n-\n-\n-static void close_rx(struct atm_vcc *vcc)\n-{\n-\tDECLARE_WAITQUEUE(wait,current);\n-\tvoid __iomem *here;\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\n-\teni_vcc = ENI_VCC(vcc);\n-\tif (!eni_vcc->rx) return;\n-\teni_dev = ENI_DEV(vcc->dev);\n-\tif (vcc->vpi != ATM_VPI_UNSPEC && vcc->vci != ATM_VCI_UNSPEC) {\n-\t\there = eni_dev->vci+vcc->vci*16;\n-\t\t/* block receiver */\n-\t\twritel((readl(here) & ~MID_VCI_MODE) | (MID_MODE_TRASH <<\n-\t\t MID_VCI_MODE_SHIFT),here);\n-\t\t/* wait for receiver to become idle */\n-\t\tudelay(27);\n-\t\t/* discard pending cell */\n-\t\twritel(readl(here) & ~MID_VCI_IN_SERVICE,here);\n-\t\t/* don't accept any new ones */\n-\t\teni_dev->rx_map[vcc->vci] = NULL;\n-\t\t/* wait for RX queue to drain */\n-\t\tDPRINTK(\"eni_close: waiting for RX ...\\n\");\n-\t\tEVENT(\"RX closing\\n\",0,0);\n-\t\tadd_wait_queue(&eni_dev->rx_wait,&wait);\n-\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t\tbarrier();\n-\t\tfor (;;) {\n-\t\t\t/* transition service->rx: rxing++, servicing-- */\n-\t\t\tif (!eni_vcc->servicing) {\n-\t\t\t\tbarrier();\n-\t\t\t\tif (!eni_vcc->rxing) break;\n-\t\t\t}\n-\t\t\tEVENT(\"drain PDUs (rx %ld, serv %ld)\\n\",eni_vcc->rxing,\n-\t\t\t eni_vcc->servicing);\n-\t\t\tprintk(KERN_INFO \"%d+%d RX left\\n\",eni_vcc->servicing,\n-\t\t\t eni_vcc->rxing);\n-\t\t\tschedule();\n-\t\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t\t}\n-\t\tfor (;;) {\n-\t\t\tint at_end;\n-\t\t\tu32 tmp;\n-\n-\t\t\ttasklet_disable(&eni_dev->task);\n-\t\t\ttmp = readl(eni_dev->vci+vcc->vci*16+4) & MID_VCI_READ;\n-\t\t\tat_end = eni_vcc->rx_pos == tmp >> MID_VCI_READ_SHIFT;\n-\t\t\ttasklet_enable(&eni_dev->task);\n-\t\t\tif (at_end) break;\n-\t\t\tEVENT(\"drain discard (host 0x%lx, nic 0x%lx)\\n\",\n-\t\t\t eni_vcc->rx_pos,tmp);\n-\t\t\tprintk(KERN_INFO \"draining RX: host 0x%lx, nic 0x%x\\n\",\n-\t\t\t eni_vcc->rx_pos,tmp);\n-\t\t\tschedule();\n-\t\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t\t}\n-\t\tset_current_state(TASK_RUNNING);\n-\t\tremove_wait_queue(&eni_dev->rx_wait,&wait);\n-\t}\n-\teni_free_mem(eni_dev,eni_vcc->recv,eni_vcc->words << 2);\n-\teni_vcc->rx = NULL;\n-}\n-\n-\n-static int start_rx(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\n-\teni_dev = ENI_DEV(dev);\n-\teni_dev->rx_map = (struct atm_vcc **) get_zeroed_page(GFP_KERNEL);\n-\tif (!eni_dev->rx_map) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): couldn't get free page\\n\",\n-\t\t dev->number);\n-\t\tfree_page((unsigned long) eni_dev->free_list);\n-\t\treturn -ENOMEM;\n-\t}\n-\teni_dev->rx_mult = DEFAULT_RX_MULT;\n-\teni_dev->fast = eni_dev->last_fast = NULL;\n-\teni_dev->slow = eni_dev->last_slow = NULL;\n-\tinit_waitqueue_head(&eni_dev->rx_wait);\n-\tskb_queue_head_init(&eni_dev->rx_queue);\n-\teni_dev->serv_read = eni_in(MID_SERV_WRITE);\n-\teni_out(0,MID_DMA_WR_RX);\n-\treturn 0;\n-}\n-\n-\n-/*----------------------------------- TX ------------------------------------*/\n-\n-\n-enum enq_res { enq_ok,enq_next,enq_jam };\n-\n-\n-static inline void put_dma(int chan,u32 *dma,int *j,dma_addr_t paddr,\n- u32 size)\n-{\n-\tu32 init,words;\n-\n-\tDPRINTK(\"put_dma: 0x%lx+0x%x\\n\",(unsigned long) paddr,size);\n-\tEVENT(\"put_dma: 0x%lx+0x%lx\\n\",(unsigned long) paddr,size);\n-#if 0 /* don't complain anymore */\n-\tif (paddr & 3)\n-\t\tprintk(KERN_ERR \"put_dma: unaligned addr (0x%lx)\\n\",paddr);\n-\tif (size & 3)\n-\t\tprintk(KERN_ERR \"put_dma: unaligned size (0x%lx)\\n\",size);\n-#endif\n-\tif (paddr & 3) {\n-\t\tinit = 4-(paddr & 3);\n-\t\tif (init > size || size < 7) init = size;\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d/%d bytes\\n\",\n-\t\t (unsigned long) paddr,init,size);\n-\t\tdma[(*j)++] = MID_DT_BYTE | (init << MID_DMA_COUNT_SHIFT) |\n-\t\t (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += init;\n-\t\tsize -= init;\n-\t}\n-\twords = size >> 2;\n-\tsize &= 3;\n-\tif (words && (paddr & 31)) {\n-\t\tinit = 8-((paddr & 31) >> 2);\n-\t\tif (init > words) init = words;\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d/%d words\\n\",\n-\t\t (unsigned long) paddr,init,words);\n-\t\tdma[(*j)++] = MID_DT_WORD | (init << MID_DMA_COUNT_SHIFT) |\n-\t\t (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += init << 2;\n-\t\twords -= init;\n-\t}\n-#ifdef CONFIG_ATM_ENI_BURST_TX_16W /* may work with some PCI chipsets ... */\n-\tif (words & ~15) {\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d*16/%d words\\n\",\n-\t\t (unsigned long) paddr,words >> 4,words);\n-\t\tdma[(*j)++] = MID_DT_16W | ((words >> 4) << MID_DMA_COUNT_SHIFT)\n-\t\t | (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += (words & ~15) << 2;\n-\t\twords &= 15;\n-\t}\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_8W /* recommended */\n-\tif (words & ~7) {\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d*8/%d words\\n\",\n-\t\t (unsigned long) paddr,words >> 3,words);\n-\t\tdma[(*j)++] = MID_DT_8W | ((words >> 3) << MID_DMA_COUNT_SHIFT)\n-\t\t | (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += (words & ~7) << 2;\n-\t\twords &= 7;\n-\t}\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_4W /* probably useless if TX_8W or TX_16W */\n-\tif (words & ~3) {\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d*4/%d words\\n\",\n-\t\t (unsigned long) paddr,words >> 2,words);\n-\t\tdma[(*j)++] = MID_DT_4W | ((words >> 2) << MID_DMA_COUNT_SHIFT)\n-\t\t | (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += (words & ~3) << 2;\n-\t\twords &= 3;\n-\t}\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_2W /* probably useless if TX_4W, TX_8W, ... */\n-\tif (words & ~1) {\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d*2/%d words\\n\",\n-\t\t (unsigned long) paddr,words >> 1,words);\n-\t\tdma[(*j)++] = MID_DT_2W | ((words >> 1) << MID_DMA_COUNT_SHIFT)\n-\t\t | (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += (words & ~1) << 2;\n-\t\twords &= 1;\n-\t}\n-#endif\n-\tif (words) {\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d words\\n\",(unsigned long) paddr,\n-\t\t words);\n-\t\tdma[(*j)++] = MID_DT_WORD | (words << MID_DMA_COUNT_SHIFT) |\n-\t\t (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t\tpaddr += words << 2;\n-\t}\n-\tif (size) {\n-\t\tDPRINTK(\"put_dma: %lx DMA: %d bytes\\n\",(unsigned long) paddr,\n-\t\t size);\n-\t\tdma[(*j)++] = MID_DT_BYTE | (size << MID_DMA_COUNT_SHIFT) |\n-\t\t (chan << MID_DMA_CHAN_SHIFT);\n-\t\tdma[(*j)++] = paddr;\n-\t}\n-}\n-\n-\n-static enum enq_res do_tx(struct sk_buff *skb)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\tstruct eni_tx *tx;\n-\tdma_addr_t paddr;\n-\tu32 dma_rd,dma_wr;\n-\tu32 size; /* in words */\n-\tint aal5,dma_size,i,j;\n-\tunsigned char skb_data3;\n-\n-\tDPRINTK(\">do_tx\\n\");\n-\tNULLCHECK(skb);\n-\tEVENT(\"do_tx: skb=0x%lx, %ld bytes\\n\",(unsigned long) skb,skb->len);\n-\tvcc = ATM_SKB(skb)->vcc;\n-\tNULLCHECK(vcc);\n-\teni_dev = ENI_DEV(vcc->dev);\n-\tNULLCHECK(eni_dev);\n-\teni_vcc = ENI_VCC(vcc);\n-\ttx = eni_vcc->tx;\n-\tNULLCHECK(tx);\n-#if 0 /* Enable this for testing with the \"align\" program */\n-\t{\n-\t\tunsigned int hack = *((char *) skb->data)-'0';\n-\n-\t\tif (hack < 8) {\n-\t\t\tskb->data += hack;\n-\t\t\tskb->len -= hack;\n-\t\t}\n-\t}\n-#endif\n-#if 0 /* should work now */\n-\tif ((unsigned long) skb->data & 3)\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): VCI %d has mis-aligned \"\n-\t\t \"TX data\\n\",vcc->dev->number,vcc->vci);\n-#endif\n-\t/*\n-\t * Potential future IP speedup: make hard_header big enough to put\n-\t * segmentation descriptor directly into PDU. Saves: 4 slave writes,\n-\t * 1 DMA xfer & 2 DMA'ed bytes (protocol layering is for wimps :-)\n-\t */\n-\n-\taal5 = vcc->qos.aal == ATM_AAL5;\n-\t/* check space in buffer */\n-\tif (!aal5)\n-\t\tsize = (ATM_CELL_PAYLOAD >> 2)+TX_DESCR_SIZE;\n-\t\t\t/* cell without HEC plus segmentation header (includes\n-\t\t\t four-byte cell header) */\n-\telse {\n-\t\tsize = skb->len+4*AAL5_TRAILER+ATM_CELL_PAYLOAD-1;\n-\t\t\t/* add AAL5 trailer */\n-\t\tsize = ((size-(size % ATM_CELL_PAYLOAD)) >> 2)+TX_DESCR_SIZE;\n-\t\t\t\t\t\t/* add segmentation header */\n-\t}\n-\t/*\n-\t * Can I move tx_pos by size bytes without getting closer than TX_GAP\n-\t * to the read pointer ? TX_GAP means to leave some space for what\n-\t * the manual calls \"too close\".\n-\t */\n-\tif (!NEPMOK(tx->tx_pos,size+TX_GAP,\n-\t eni_in(MID_TX_RDPTR(tx->index)),tx->words)) {\n-\t\tDPRINTK(DEV_LABEL \"(itf %d): TX full (size %d)\\n\",\n-\t\t vcc->dev->number,size);\n-\t\treturn enq_next;\n-\t}\n-\t/* check DMA */\n-\tdma_wr = eni_in(MID_DMA_WR_TX);\n-\tdma_rd = eni_in(MID_DMA_RD_TX);\n-\tdma_size = 3; /* JK for descriptor and final fill, plus final size\n-\t\t\t mis-alignment fix */\n-DPRINTK(\"iovcnt = %d\\n\",skb_shinfo(skb)->nr_frags);\n-\tif (!skb_shinfo(skb)->nr_frags) dma_size += 5;\n-\telse dma_size += 5*(skb_shinfo(skb)->nr_frags+1);\n-\tif (dma_size > TX_DMA_BUF) {\n-\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): needs %d DMA entries \"\n-\t\t \"(got only %d)\\n\",vcc->dev->number,dma_size,TX_DMA_BUF);\n-\t}\n-\tDPRINTK(\"dma_wr is %d, tx_pos is %ld\\n\",dma_wr,tx->tx_pos);\n-\tif (dma_wr != dma_rd && ((dma_rd+NR_DMA_TX-dma_wr) & (NR_DMA_TX-1)) <\n-\t dma_size) {\n-\t\tprintk(KERN_WARNING DEV_LABEL \"(itf %d): TX DMA full\\n\",\n-\t\t vcc->dev->number);\n-\t\treturn enq_jam;\n-\t}\n-\tskb_data3 = skb->data[3];\n-\tpaddr = dma_map_single(&eni_dev->pci_dev->dev,skb->data,skb->len,\n-\t\t\t DMA_TO_DEVICE);\n-\tif (dma_mapping_error(&eni_dev->pci_dev->dev, paddr))\n-\t\treturn enq_next;\n-\tENI_PRV_PADDR(skb) = paddr;\n-\t/* prepare DMA queue entries */\n-\tj = 0;\n-\teni_dev->dma[j++] = (((tx->tx_pos+TX_DESCR_SIZE) & (tx->words-1)) <<\n-\t MID_DMA_COUNT_SHIFT) | (tx->index << MID_DMA_CHAN_SHIFT) |\n-\t MID_DT_JK;\n-\tj++;\n-\tif (!skb_shinfo(skb)->nr_frags)\n-\t\tif (aal5) put_dma(tx->index,eni_dev->dma,&j,paddr,skb->len);\n-\t\telse put_dma(tx->index,eni_dev->dma,&j,paddr+4,skb->len-4);\n-\telse {\n-DPRINTK(\"doing direct send\\n\"); /* @@@ well, this doesn't work anyway */\n-\t\tfor (i = -1; i < skb_shinfo(skb)->nr_frags; i++)\n-\t\t\tif (i == -1)\n-\t\t\t\tput_dma(tx->index,eni_dev->dma,&j,(unsigned long)\n-\t\t\t\t skb->data,\n-\t\t\t\t skb_headlen(skb));\n-\t\t\telse\n-\t\t\t\tput_dma(tx->index,eni_dev->dma,&j,(unsigned long)\n-\t\t\t\t skb_frag_page(&skb_shinfo(skb)->frags[i]) +\n-\t\t\t\t\tskb_frag_off(&skb_shinfo(skb)->frags[i]),\n-\t\t\t\t skb_frag_size(&skb_shinfo(skb)->frags[i]));\n-\t}\n-\tif (skb->len & 3) {\n-\t\tput_dma(tx->index, eni_dev->dma, &j, eni_dev->zero.dma,\n-\t\t\t4 - (skb->len & 3));\n-\t}\n-\t/* JK for AAL5 trailer - AAL0 doesn't need it, but who cares ... */\n-\teni_dev->dma[j++] = (((tx->tx_pos+size) & (tx->words-1)) <<\n-\t MID_DMA_COUNT_SHIFT) | (tx->index << MID_DMA_CHAN_SHIFT) |\n-\t MID_DMA_END | MID_DT_JK;\n-\tj++;\n-\tDPRINTK(\"DMA at end: %d\\n\",j);\n-\t/* store frame */\n-\twritel((MID_SEG_TX_ID << MID_SEG_ID_SHIFT) |\n-\t (aal5 ? MID_SEG_AAL5 : 0) | (tx->prescaler << MID_SEG_PR_SHIFT) |\n-\t (tx->resolution << MID_SEG_RATE_SHIFT) |\n-\t (size/(ATM_CELL_PAYLOAD/4)),tx->send+tx->tx_pos*4);\n-/*printk(\"dsc = 0x%08lx\\n\",(unsigned long) readl(tx->send+tx->tx_pos*4));*/\n-\twritel((vcc->vci << MID_SEG_VCI_SHIFT) |\n- (aal5 ? 0 : (skb_data3 & 0xf)) |\n-\t (ATM_SKB(skb)->atm_options & ATM_ATMOPT_CLP ? MID_SEG_CLP : 0),\n-\t tx->send+((tx->tx_pos+1) & (tx->words-1))*4);\n-\tDPRINTK(\"size: %d, len:%d\\n\",size,skb->len);\n-\tif (aal5)\n-\t\twritel(skb->len,tx->send+\n- ((tx->tx_pos+size-AAL5_TRAILER) & (tx->words-1))*4);\n-\tj = j >> 1;\n-\tfor (i = 0; i < j; i++) {\n-\t\twritel(eni_dev->dma[i*2],eni_dev->tx_dma+dma_wr*8);\n-\t\twritel(eni_dev->dma[i*2+1],eni_dev->tx_dma+dma_wr*8+4);\n-\t\tdma_wr = (dma_wr+1) & (NR_DMA_TX-1);\n-\t}\n-\tENI_PRV_POS(skb) = tx->tx_pos;\n-\tENI_PRV_SIZE(skb) = size;\n-\tENI_VCC(vcc)->txing += size;\n-\ttx->tx_pos = (tx->tx_pos+size) & (tx->words-1);\n-\tDPRINTK(\"dma_wr set to %d, tx_pos is now %ld\\n\",dma_wr,tx->tx_pos);\n-\teni_out(dma_wr,MID_DMA_WR_TX);\n-\tskb_queue_tail(&eni_dev->tx_queue,skb);\n-\tqueued++;\n-\treturn enq_ok;\n-}\n-\n-\n-static void poll_tx(struct atm_dev *dev)\n-{\n-\tstruct eni_tx *tx;\n-\tstruct sk_buff *skb;\n-\tenum enq_res res;\n-\tint i;\n-\n-\tDPRINTK(\">poll_tx\\n\");\n-\tfor (i = NR_CHAN-1; i >= 0; i--) {\n-\t\ttx = &ENI_DEV(dev)->tx[i];\n-\t\tif (tx->send)\n-\t\t\twhile ((skb = skb_dequeue(&tx->backlog))) {\n-\t\t\t\tres = do_tx(skb);\n-\t\t\t\tif (res == enq_ok) continue;\n-\t\t\t\tDPRINTK(\"re-queuing TX PDU\\n\");\n-\t\t\t\tskb_queue_head(&tx->backlog,skb);\n-\t\t\t\trequeued++;\n-\t\t\t\tif (res == enq_jam) return;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t}\n-}\n-\n-\n-static void dequeue_tx(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tstruct atm_vcc *vcc;\n-\tstruct sk_buff *skb;\n-\tstruct eni_tx *tx;\n-\n-\tNULLCHECK(dev);\n-\teni_dev = ENI_DEV(dev);\n-\tNULLCHECK(eni_dev);\n-\twhile ((skb = skb_dequeue(&eni_dev->tx_queue))) {\n-\t\tvcc = ATM_SKB(skb)->vcc;\n-\t\tNULLCHECK(vcc);\n-\t\ttx = ENI_VCC(vcc)->tx;\n-\t\tNULLCHECK(ENI_VCC(vcc)->tx);\n-\t\tDPRINTK(\"dequeue_tx: next 0x%lx curr 0x%x\\n\",ENI_PRV_POS(skb),\n-\t\t (unsigned) eni_in(MID_TX_DESCRSTART(tx->index)));\n-\t\tif (ENI_VCC(vcc)->txing < tx->words && ENI_PRV_POS(skb) ==\n-\t\t eni_in(MID_TX_DESCRSTART(tx->index))) {\n-\t\t\tskb_queue_head(&eni_dev->tx_queue,skb);\n-\t\t\tbreak;\n-\t\t}\n-\t\tENI_VCC(vcc)->txing -= ENI_PRV_SIZE(skb);\n-\t\tdma_unmap_single(&eni_dev->pci_dev->dev,ENI_PRV_PADDR(skb),skb->len,\n-\t\t\t\t DMA_TO_DEVICE);\n-\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\telse dev_kfree_skb_irq(skb);\n-\t\tatomic_inc(&vcc->stats->tx);\n-\t\twake_up(&eni_dev->tx_wait);\n-\t\tdma_complete++;\n-\t}\n-}\n-\n-\n-static struct eni_tx *alloc_tx(struct eni_dev *eni_dev,int ubr)\n-{\n-\tint i;\n-\n-\tfor (i = !ubr; i < NR_CHAN; i++)\n-\t\tif (!eni_dev->tx[i].send) return eni_dev->tx+i;\n-\treturn NULL;\n-}\n-\n-\n-static int comp_tx(struct eni_dev *eni_dev,int *pcr,int reserved,int *pre,\n- int *res,int unlimited)\n-{\n-\tstatic const int pre_div[] = { 4,16,128,2048 };\n-\t /* 2^(((x+2)^2-(x+2))/2+1) */\n-\n-\tif (unlimited) *pre = *res = 0;\n-\telse {\n-\t\tif (*pcr > 0) {\n-\t\t\tint div;\n-\n-\t\t\tfor (*pre = 0; *pre < 3; (*pre)++)\n-\t\t\t\tif (TS_CLOCK/pre_div[*pre]/64 <= *pcr) break;\n-\t\t\tdiv = pre_div[*pre]**pcr;\n-\t\t\tDPRINTK(\"min div %d\\n\",div);\n-\t\t\t*res = TS_CLOCK/div-1;\n-\t\t}\n-\t\telse {\n-\t\t\tint div;\n-\n-\t\t\tif (!*pcr) *pcr = eni_dev->tx_bw+reserved;\n-\t\t\tfor (*pre = 3; *pre >= 0; (*pre)--)\n-\t\t\t\tif (TS_CLOCK/pre_div[*pre]/64 > -*pcr) break;\n-\t\t\tif (*pre < 3) (*pre)++; /* else fail later */\n-\t\t\tdiv = pre_div[*pre]*-*pcr;\n-\t\t\tDPRINTK(\"max div %d\\n\",div);\n-\t\t\t*res = DIV_ROUND_UP(TS_CLOCK, div)-1;\n-\t\t}\n-\t\tif (*res < 0) *res = 0;\n-\t\tif (*res > MID_SEG_MAX_RATE) *res = MID_SEG_MAX_RATE;\n-\t}\n-\t*pcr = TS_CLOCK/pre_div[*pre]/(*res+1);\n-\tDPRINTK(\"out pcr: %d (%d:%d)\\n\",*pcr,*pre,*res);\n-\treturn 0;\n-}\n-\n-\n-static int reserve_or_set_tx(struct atm_vcc *vcc,struct atm_trafprm *txtp,\n- int set_rsv,int set_shp)\n-{\n-\tstruct eni_dev *eni_dev = ENI_DEV(vcc->dev);\n-\tstruct eni_vcc *eni_vcc = ENI_VCC(vcc);\n-\tstruct eni_tx *tx;\n-\tunsigned long size;\n-\tvoid __iomem *mem;\n-\tint rate,ubr,unlimited,new_tx;\n-\tint pre,res,order;\n-\tint error;\n-\n-\trate = atm_pcr_goal(txtp);\n-\tubr = txtp->traffic_class == ATM_UBR;\n-\tunlimited = ubr && (!rate || rate <= -ATM_OC3_PCR ||\n-\t rate >= ATM_OC3_PCR);\n-\tif (!unlimited) {\n-\t\tsize = txtp->max_sdu*eni_dev->tx_mult/100;\n-\t\tif (size > MID_MAX_BUF_SIZE && txtp->max_sdu <=\n-\t\t MID_MAX_BUF_SIZE)\n-\t\t\tsize = MID_MAX_BUF_SIZE;\n-\t}\n-\telse {\n-\t\tif (eni_dev->ubr) {\n-\t\t\teni_vcc->tx = eni_dev->ubr;\n-\t\t\ttxtp->pcr = ATM_OC3_PCR;\n-\t\t\treturn 0;\n-\t\t}\n-\t\tsize = UBR_BUFFER;\n-\t}\n-\tnew_tx = !eni_vcc->tx;\n-\tmem = NULL; /* for gcc */\n-\tif (!new_tx) tx = eni_vcc->tx;\n-\telse {\n-\t\tmem = eni_alloc_mem(eni_dev,&size);\n-\t\tif (!mem) return -ENOBUFS;\n-\t\ttx = alloc_tx(eni_dev,unlimited);\n-\t\tif (!tx) {\n-\t\t\teni_free_mem(eni_dev,mem,size);\n-\t\t\treturn -EBUSY;\n-\t\t}\n-\t\tDPRINTK(\"got chan %d\\n\",tx->index);\n-\t\ttx->reserved = tx->shaping = 0;\n-\t\ttx->send = mem;\n-\t\ttx->words = size >> 2;\n-\t\tskb_queue_head_init(&tx->backlog);\n-\t\tfor (order = 0; size > (1 << (order+10)); order++);\n-\t\teni_out((order << MID_SIZE_SHIFT) |\n-\t\t ((tx->send-eni_dev->ram) >> (MID_LOC_SKIP+2)),\n-\t\t MID_TX_PLACE(tx->index));\n-\t\ttx->tx_pos = eni_in(MID_TX_DESCRSTART(tx->index)) &\n-\t\t MID_DESCR_START;\n-\t}\n-\terror = comp_tx(eni_dev,&rate,tx->reserved,&pre,&res,unlimited);\n-\tif (!error && txtp->min_pcr > rate) error = -EINVAL;\n-\tif (!error && txtp->max_pcr && txtp->max_pcr != ATM_MAX_PCR &&\n-\t txtp->max_pcr < rate) error = -EINVAL;\n-\tif (!error && !ubr && rate > eni_dev->tx_bw+tx->reserved)\n-\t\terror = -EINVAL;\n-\tif (!error && set_rsv && !set_shp && rate < tx->shaping)\n-\t\terror = -EINVAL;\n-\tif (!error && !set_rsv && rate > tx->reserved && !ubr)\n-\t\terror = -EINVAL;\n-\tif (error) {\n-\t\tif (new_tx) {\n-\t\t\ttx->send = NULL;\n-\t\t\teni_free_mem(eni_dev,mem,size);\n-\t\t}\n-\t\treturn error;\n-\t}\n-\ttxtp->pcr = rate;\n-\tif (set_rsv && !ubr) {\n-\t\teni_dev->tx_bw += tx->reserved;\n-\t\ttx->reserved = rate;\n-\t\teni_dev->tx_bw -= rate;\n-\t}\n-\tif (set_shp || (unlimited && new_tx)) {\n-\t\tif (unlimited && new_tx) eni_dev->ubr = tx;\n-\t\ttx->prescaler = pre;\n-\t\ttx->resolution = res;\n-\t\ttx->shaping = rate;\n-\t}\n-\tif (set_shp) eni_vcc->tx = tx;\n-\tDPRINTK(\"rsv %d shp %d\\n\",tx->reserved,tx->shaping);\n-\treturn 0;\n-}\n-\n-\n-static int open_tx_first(struct atm_vcc *vcc)\n-{\n-\tENI_VCC(vcc)->tx = NULL;\n-\tif (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;\n-\tENI_VCC(vcc)->txing = 0;\n-\treturn reserve_or_set_tx(vcc,&vcc->qos.txtp,1,1);\n-}\n-\n-\n-static int open_tx_second(struct atm_vcc *vcc)\n-{\n-\treturn 0; /* nothing to do */\n-}\n-\n-\n-static void close_tx(struct atm_vcc *vcc)\n-{\n-\tDECLARE_WAITQUEUE(wait,current);\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_vcc *eni_vcc;\n-\n-\teni_vcc = ENI_VCC(vcc);\n-\tif (!eni_vcc->tx) return;\n-\teni_dev = ENI_DEV(vcc->dev);\n-\t/* wait for TX queue to drain */\n-\tDPRINTK(\"eni_close: waiting for TX ...\\n\");\n-\tadd_wait_queue(&eni_dev->tx_wait,&wait);\n-\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\tfor (;;) {\n-\t\tint txing;\n-\n-\t\ttasklet_disable(&eni_dev->task);\n-\t\ttxing = skb_peek(&eni_vcc->tx->backlog) || eni_vcc->txing;\n-\t\ttasklet_enable(&eni_dev->task);\n-\t\tif (!txing) break;\n-\t\tDPRINTK(\"%d TX left\\n\",eni_vcc->txing);\n-\t\tschedule();\n-\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t}\n-\tset_current_state(TASK_RUNNING);\n-\tremove_wait_queue(&eni_dev->tx_wait,&wait);\n-\tif (eni_vcc->tx != eni_dev->ubr) {\n-\t\t/*\n-\t\t * Looping a few times in here is probably far cheaper than\n-\t\t * keeping track of TX completions all the time, so let's poll\n-\t\t * a bit ...\n-\t\t */\n-\t\twhile (eni_in(MID_TX_RDPTR(eni_vcc->tx->index)) !=\n-\t\t eni_in(MID_TX_DESCRSTART(eni_vcc->tx->index)))\n-\t\t\tschedule();\n-\t\teni_free_mem(eni_dev,eni_vcc->tx->send,eni_vcc->tx->words << 2);\n-\t\teni_vcc->tx->send = NULL;\n-\t\teni_dev->tx_bw += eni_vcc->tx->reserved;\n-\t}\n-\teni_vcc->tx = NULL;\n-}\n-\n-\n-static int start_tx(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tint i;\n-\n-\teni_dev = ENI_DEV(dev);\n-\teni_dev->lost = 0;\n-\teni_dev->tx_bw = ATM_OC3_PCR;\n-\teni_dev->tx_mult = DEFAULT_TX_MULT;\n-\tinit_waitqueue_head(&eni_dev->tx_wait);\n-\teni_dev->ubr = NULL;\n-\tskb_queue_head_init(&eni_dev->tx_queue);\n-\teni_out(0,MID_DMA_WR_TX);\n-\tfor (i = 0; i < NR_CHAN; i++) {\n-\t\teni_dev->tx[i].send = NULL;\n-\t\teni_dev->tx[i].index = i;\n-\t}\n-\treturn 0;\n-}\n-\n-\n-/*--------------------------------- common ----------------------------------*/\n-\n-\n-#if 0 /* may become useful again when tuning things */\n-\n-static void foo(void)\n-{\n-printk(KERN_INFO\n- \"tx_complete=%d,dma_complete=%d,queued=%d,requeued=%d,sub=%d,\\n\"\n- \"backlogged=%d,rx_enqueued=%d,rx_dequeued=%d,putting=%d,pushed=%d\\n\",\n- tx_complete,dma_complete,queued,requeued,submitted,backlogged,\n- rx_enqueued,rx_dequeued,putting,pushed);\n-if (eni_boards) printk(KERN_INFO \"loss: %ld\\n\",ENI_DEV(eni_boards)->lost);\n-}\n-\n-#endif\n-\n-\n-static void bug_int(struct atm_dev *dev,unsigned long reason)\n-{\n-\tDPRINTK(\">bug_int\\n\");\n-\tif (reason & MID_DMA_ERR_ACK)\n-\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): driver error - DMA \"\n-\t\t \"error\\n\",dev->number);\n-\tif (reason & MID_TX_IDENT_MISM)\n-\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): driver error - ident \"\n-\t\t \"mismatch\\n\",dev->number);\n-\tif (reason & MID_TX_DMA_OVFL)\n-\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): driver error - DMA \"\n-\t\t \"overflow\\n\",dev->number);\n-\tEVENT(\"---dump ends here---\\n\",0,0);\n-\tprintk(KERN_NOTICE \"---recent events---\\n\");\n-\tevent_dump();\n-}\n-\n-\n-static irqreturn_t eni_int(int irq,void *dev_id)\n-{\n-\tstruct atm_dev *dev;\n-\tstruct eni_dev *eni_dev;\n-\tu32 reason;\n-\n-\tDPRINTK(\">eni_int\\n\");\n-\tdev = dev_id;\n-\teni_dev = ENI_DEV(dev);\n-\treason = eni_in(MID_ISA);\n-\tDPRINTK(DEV_LABEL \": int 0x%lx\\n\",(unsigned long) reason);\n-\t/*\n-\t * Must handle these two right now, because reading ISA doesn't clear\n-\t * them, so they re-occur and we never make it to the tasklet. Since\n-\t * they're rare, we don't mind the occasional invocation of eni_tasklet\n-\t * with eni_dev->events == 0.\n-\t */\n-\tif (reason & MID_STAT_OVFL) {\n-\t\tEVENT(\"stat overflow\\n\",0,0);\n-\t\teni_dev->lost += eni_in(MID_STAT) & MID_OVFL_TRASH;\n-\t}\n-\tif (reason & MID_SUNI_INT) {\n-\t\tEVENT(\"SUNI int\\n\",0,0);\n-\t\tdev->phy->interrupt(dev);\n-#if 0\n-\t\tfoo();\n-#endif\n-\t}\n-\tspin_lock(&eni_dev->lock);\n-\teni_dev->events |= reason;\n-\tspin_unlock(&eni_dev->lock);\n-\ttasklet_schedule(&eni_dev->task);\n-\treturn IRQ_HANDLED;\n-}\n-\n-\n-static void eni_tasklet(unsigned long data)\n-{\n-\tstruct atm_dev *dev = (struct atm_dev *) data;\n-\tstruct eni_dev *eni_dev = ENI_DEV(dev);\n-\tunsigned long flags;\n-\tu32 events;\n-\n-\tDPRINTK(\"eni_tasklet (dev %p)\\n\",dev);\n-\tspin_lock_irqsave(&eni_dev->lock,flags);\n-\tevents = xchg(&eni_dev->events,0);\n-\tspin_unlock_irqrestore(&eni_dev->lock,flags);\n-\tif (events & MID_RX_DMA_COMPLETE) {\n-\t\tEVENT(\"INT: RX DMA complete, starting dequeue_rx\\n\",0,0);\n-\t\tdequeue_rx(dev);\n-\t\tEVENT(\"dequeue_rx done, starting poll_rx\\n\",0,0);\n-\t\tpoll_rx(dev);\n-\t\tEVENT(\"poll_rx done\\n\",0,0);\n-\t\t/* poll_tx ? */\n-\t}\n-\tif (events & MID_SERVICE) {\n-\t\tEVENT(\"INT: service, starting get_service\\n\",0,0);\n-\t\tget_service(dev);\n-\t\tEVENT(\"get_service done, starting poll_rx\\n\",0,0);\n-\t\tpoll_rx(dev);\n-\t\tEVENT(\"poll_rx done\\n\",0,0);\n-\t}\n- \tif (events & MID_TX_DMA_COMPLETE) {\n-\t\tEVENT(\"INT: TX DMA COMPLETE\\n\",0,0);\n-\t\tdequeue_tx(dev);\n-\t}\n-\tif (events & MID_TX_COMPLETE) {\n-\t\tEVENT(\"INT: TX COMPLETE\\n\",0,0);\n-\t\ttx_complete++;\n-\t\twake_up(&eni_dev->tx_wait);\n-\t\t/* poll_rx ? */\n-\t}\n-\tif (events & (MID_DMA_ERR_ACK | MID_TX_IDENT_MISM | MID_TX_DMA_OVFL)) {\n-\t\tEVENT(\"bug interrupt\\n\",0,0);\n-\t\tbug_int(dev,events);\n-\t}\n-\tpoll_tx(dev);\n-}\n-\n-\n-/*--------------------------------- entries ---------------------------------*/\n-\n-\n-static char * const media_name[] = {\n- \"MMF\", \"SMF\", \"MMF\", \"03?\", /* 0- 3 */\n- \"UTP\", \"05?\", \"06?\", \"07?\", /* 4- 7 */\n- \"TAXI\",\"09?\", \"10?\", \"11?\", /* 8-11 */\n- \"12?\", \"13?\", \"14?\", \"15?\", /* 12-15 */\n- \"MMF\", \"SMF\", \"18?\", \"19?\", /* 16-19 */\n- \"UTP\", \"21?\", \"22?\", \"23?\", /* 20-23 */\n- \"24?\", \"25?\", \"26?\", \"27?\", /* 24-27 */\n- \"28?\", \"29?\", \"30?\", \"31?\" /* 28-31 */\n-};\n-\n-\n-#define SET_SEPROM \\\n- ({ if (!error && !pci_error) { \\\n- pci_error = pci_write_config_byte(eni_dev->pci_dev,PCI_TONGA_CTRL,tonga); \\\n- udelay(10); /* 10 usecs */ \\\n- } })\n-#define GET_SEPROM \\\n- ({ if (!error && !pci_error) { \\\n- pci_error = pci_read_config_byte(eni_dev->pci_dev,PCI_TONGA_CTRL,&tonga); \\\n- udelay(10); /* 10 usecs */ \\\n- } })\n-\n-\n-static int get_esi_asic(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\tunsigned char tonga;\n-\tint error,failed,pci_error;\n-\tint address,i,j;\n-\n-\teni_dev = ENI_DEV(dev);\n-\terror = pci_error = 0;\n-\ttonga = SEPROM_MAGIC | SEPROM_DATA | SEPROM_CLK;\n-\tSET_SEPROM;\n-\tfor (i = 0; i < ESI_LEN && !error && !pci_error; i++) {\n-\t\t/* start operation */\n-\t\ttonga |= SEPROM_DATA;\n-\t\tSET_SEPROM;\n-\t\ttonga |= SEPROM_CLK;\n-\t\tSET_SEPROM;\n-\t\ttonga &= ~SEPROM_DATA;\n-\t\tSET_SEPROM;\n-\t\ttonga &= ~SEPROM_CLK;\n-\t\tSET_SEPROM;\n-\t\t/* send address */\n-\t\taddress = ((i+SEPROM_ESI_BASE) << 1)+1;\n-\t\tfor (j = 7; j >= 0; j--) {\n-\t\t\ttonga = (address >> j) & 1 ? tonga | SEPROM_DATA :\n-\t\t\t tonga & ~SEPROM_DATA;\n-\t\t\tSET_SEPROM;\n-\t\t\ttonga |= SEPROM_CLK;\n-\t\t\tSET_SEPROM;\n-\t\t\ttonga &= ~SEPROM_CLK;\n-\t\t\tSET_SEPROM;\n-\t\t}\n-\t\t/* get ack */\n-\t\ttonga |= SEPROM_DATA;\n-\t\tSET_SEPROM;\n-\t\ttonga |= SEPROM_CLK;\n-\t\tSET_SEPROM;\n-\t\tGET_SEPROM;\n-\t\tfailed = tonga & SEPROM_DATA;\n-\t\ttonga &= ~SEPROM_CLK;\n-\t\tSET_SEPROM;\n-\t\ttonga |= SEPROM_DATA;\n-\t\tSET_SEPROM;\n-\t\tif (failed) error = -EIO;\n-\t\telse {\n-\t\t\tdev->esi[i] = 0;\n-\t\t\tfor (j = 7; j >= 0; j--) {\n-\t\t\t\tdev->esi[i] <<= 1;\n-\t\t\t\ttonga |= SEPROM_DATA;\n-\t\t\t\tSET_SEPROM;\n-\t\t\t\ttonga |= SEPROM_CLK;\n-\t\t\t\tSET_SEPROM;\n-\t\t\t\tGET_SEPROM;\n-\t\t\t\tif (tonga & SEPROM_DATA) dev->esi[i] |= 1;\n-\t\t\t\ttonga &= ~SEPROM_CLK;\n-\t\t\t\tSET_SEPROM;\n-\t\t\t\ttonga |= SEPROM_DATA;\n-\t\t\t\tSET_SEPROM;\n-\t\t\t}\n-\t\t\t/* get ack */\n-\t\t\ttonga |= SEPROM_DATA;\n-\t\t\tSET_SEPROM;\n-\t\t\ttonga |= SEPROM_CLK;\n-\t\t\tSET_SEPROM;\n-\t\t\tGET_SEPROM;\n-\t\t\tif (!(tonga & SEPROM_DATA)) error = -EIO;\n-\t\t\ttonga &= ~SEPROM_CLK;\n-\t\t\tSET_SEPROM;\n-\t\t\ttonga |= SEPROM_DATA;\n-\t\t\tSET_SEPROM;\n-\t\t}\n-\t\t/* stop operation */\n-\t\ttonga &= ~SEPROM_DATA;\n-\t\tSET_SEPROM;\n-\t\ttonga |= SEPROM_CLK;\n-\t\tSET_SEPROM;\n-\t\ttonga |= SEPROM_DATA;\n-\t\tSET_SEPROM;\n-\t}\n-\tif (pci_error) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): error reading ESI \"\n-\t\t \"(0x%02x)\\n\",dev->number,pci_error);\n-\t\terror = -EIO;\n-\t}\n-\treturn error;\n-}\n-\n-\n-#undef SET_SEPROM\n-#undef GET_SEPROM\n-\n-\n-static int get_esi_fpga(struct atm_dev *dev, void __iomem *base)\n-{\n-\tvoid __iomem *mac_base;\n-\tint i;\n-\n-\tmac_base = base+EPROM_SIZE-sizeof(struct midway_eprom);\n-\tfor (i = 0; i < ESI_LEN; i++) dev->esi[i] = readb(mac_base+(i^3));\n-\treturn 0;\n-}\n-\n-\n-static int eni_do_init(struct atm_dev *dev)\n-{\n-\tstruct midway_eprom __iomem *eprom;\n-\tstruct eni_dev *eni_dev;\n-\tstruct pci_dev *pci_dev;\n-\tunsigned long real_base;\n-\tvoid __iomem *base;\n-\tint error,i,last;\n-\n-\tDPRINTK(\">eni_init\\n\");\n-\tdev->ci_range.vpi_bits = 0;\n-\tdev->ci_range.vci_bits = NR_VCI_LD;\n-\tdev->link_rate = ATM_OC3_PCR;\n-\teni_dev = ENI_DEV(dev);\n-\tpci_dev = eni_dev->pci_dev;\n-\treal_base = pci_resource_start(pci_dev, 0);\n-\teni_dev->irq = pci_dev->irq;\n-\tif ((error = pci_write_config_word(pci_dev,PCI_COMMAND,\n-\t PCI_COMMAND_MEMORY |\n-\t (eni_dev->asic ? PCI_COMMAND_PARITY | PCI_COMMAND_SERR : 0)))) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't enable memory \"\n-\t\t \"(0x%02x)\\n\",dev->number,error);\n-\t\treturn -EIO;\n-\t}\n-\tprintk(KERN_NOTICE DEV_LABEL \"(itf %d): rev.%d,base=0x%lx,irq=%d,\",\n-\t dev->number,pci_dev->revision,real_base,eni_dev->irq);\n-\tif (!(base = ioremap(real_base,MAP_MAX_SIZE))) {\n-\t\tprintk(\"\\n\");\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't set up page \"\n-\t\t \"mapping\\n\",dev->number);\n-\t\treturn -ENOMEM;\n-\t}\n-\teni_dev->ioaddr = base;\n-\teni_dev->base_diff = real_base - (unsigned long) base;\n-\t/* id may not be present in ASIC Tonga boards - check this @@@ */\n-\tif (!eni_dev->asic) {\n-\t\teprom = (base+EPROM_SIZE-sizeof(struct midway_eprom));\n-\t\tif (readl(&eprom->magic) != ENI155_MAGIC) {\n-\t\t\tprintk(\"\\n\");\n-\t\t\tprintk(KERN_ERR DEV_LABEL\n-\t\t\t \"(itf %d): bad magic - expected 0x%x, got 0x%x\\n\",\n-\t\t\t dev->number, ENI155_MAGIC,\n-\t\t\t (unsigned)readl(&eprom->magic));\n-\t\t\terror = -EINVAL;\n-\t\t\tgoto unmap;\n-\t\t}\n-\t}\n-\teni_dev->phy = base+PHY_BASE;\n-\teni_dev->reg = base+REG_BASE;\n-\teni_dev->ram = base+RAM_BASE;\n-\tlast = MAP_MAX_SIZE-RAM_BASE;\n-\tfor (i = last-RAM_INCREMENT; i >= 0; i -= RAM_INCREMENT) {\n-\t\twritel(0x55555555,eni_dev->ram+i);\n-\t\tif (readl(eni_dev->ram+i) != 0x55555555) last = i;\n-\t\telse {\n-\t\t\twritel(0xAAAAAAAA,eni_dev->ram+i);\n-\t\t\tif (readl(eni_dev->ram+i) != 0xAAAAAAAA) last = i;\n-\t\t\telse writel(i,eni_dev->ram+i);\n-\t\t}\n-\t}\n-\tfor (i = 0; i < last; i += RAM_INCREMENT)\n-\t\tif (readl(eni_dev->ram+i) != i) break;\n-\teni_dev->mem = i;\n-\tmemset_io(eni_dev->ram,0,eni_dev->mem);\n-\t/* TODO: should shrink allocation now */\n-\tprintk(\"mem=%dkB (\",eni_dev->mem >> 10);\n-\t/* TODO: check for non-SUNI, check for TAXI ? */\n-\tif (!(eni_in(MID_RES_ID_MCON) & 0x200) != !eni_dev->asic) {\n-\t\tprintk(\")\\n\");\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): ERROR - wrong id 0x%x\\n\",\n-\t\t dev->number,(unsigned) eni_in(MID_RES_ID_MCON));\n-\t\terror = -EINVAL;\n-\t\tgoto unmap;\n-\t}\n-\terror = eni_dev->asic ? get_esi_asic(dev) : get_esi_fpga(dev,base);\n-\tif (error)\n-\t\tgoto unmap;\n-\tfor (i = 0; i < ESI_LEN; i++)\n-\t\tprintk(\"%s%02X\",i ? \"-\" : \"\",dev->esi[i]);\n-\tprintk(\")\\n\");\n-\tprintk(KERN_NOTICE DEV_LABEL \"(itf %d): %s,%s\\n\",dev->number,\n-\t eni_in(MID_RES_ID_MCON) & 0x200 ? \"ASIC\" : \"FPGA\",\n-\t media_name[eni_in(MID_RES_ID_MCON) & DAUGHTER_ID]);\n-\n-\terror = suni_init(dev);\n-\tif (error)\n-\t\tgoto unmap;\n-out:\n-\treturn error;\n-unmap:\n-\tiounmap(base);\n-\tgoto out;\n-}\n-\n-static void eni_do_release(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *ed = ENI_DEV(dev);\n-\n-\tdev->phy->stop(dev);\n-\tdev->phy = NULL;\n-\tiounmap(ed->ioaddr);\n-}\n-\n-static int eni_start(struct atm_dev *dev)\n-{\n-\tstruct eni_dev *eni_dev;\n-\t\n-\tvoid __iomem *buf;\n-\tunsigned long buffer_mem;\n-\tint error;\n-\n-\tDPRINTK(\">eni_start\\n\");\n-\teni_dev = ENI_DEV(dev);\n-\tif (request_irq(eni_dev->irq,&eni_int,IRQF_SHARED,DEV_LABEL,dev)) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): IRQ%d is already in use\\n\",\n-\t\t dev->number,eni_dev->irq);\n-\t\terror = -EAGAIN;\n-\t\tgoto out;\n-\t}\n-\tpci_set_master(eni_dev->pci_dev);\n-\tif ((error = pci_write_config_word(eni_dev->pci_dev,PCI_COMMAND,\n-\t PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |\n-\t (eni_dev->asic ? PCI_COMMAND_PARITY | PCI_COMMAND_SERR : 0)))) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't enable memory+\"\n-\t\t \"master (0x%02x)\\n\",dev->number,error);\n-\t\tgoto free_irq;\n-\t}\n-\tif ((error = pci_write_config_byte(eni_dev->pci_dev,PCI_TONGA_CTRL,\n-\t END_SWAP_DMA))) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't set endian swap \"\n-\t\t \"(0x%02x)\\n\",dev->number,error);\n-\t\tgoto free_irq;\n-\t}\n-\t/* determine addresses of internal tables */\n-\teni_dev->vci = eni_dev->ram;\n-\teni_dev->rx_dma = eni_dev->ram+NR_VCI*16;\n-\teni_dev->tx_dma = eni_dev->rx_dma+NR_DMA_RX*8;\n-\teni_dev->service = eni_dev->tx_dma+NR_DMA_TX*8;\n-\tbuf = eni_dev->service+NR_SERVICE*4;\n-\tDPRINTK(\"vci 0x%lx,rx 0x%lx, tx 0x%lx,srv 0x%lx,buf 0x%lx\\n\",\n-\t eni_dev->vci,eni_dev->rx_dma,eni_dev->tx_dma,\n-\t eni_dev->service,buf);\n-\tspin_lock_init(&eni_dev->lock);\n-\ttasklet_init(&eni_dev->task,eni_tasklet,(unsigned long) dev);\n-\teni_dev->events = 0;\n-\t/* initialize memory management */\n-\tbuffer_mem = eni_dev->mem - (buf - eni_dev->ram);\n-\teni_dev->free_list_size = buffer_mem/MID_MIN_BUF_SIZE/2;\n-\teni_dev->free_list = kmalloc_objs(*eni_dev->free_list,\n-\t\t\t\t\t eni_dev->free_list_size + 1);\n-\tif (!eni_dev->free_list) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): couldn't get free page\\n\",\n-\t\t dev->number);\n-\t\terror = -ENOMEM;\n-\t\tgoto free_irq;\n-\t}\n-\teni_dev->free_len = 0;\n-\teni_put_free(eni_dev,buf,buffer_mem);\n-\tmemset_io(eni_dev->vci,0,16*NR_VCI); /* clear VCI table */\n-\t/*\n-\t * byte_addr free (k)\n-\t * 0x00000000 512 VCI table\n-\t * 0x00004000\t 496 RX DMA\n-\t * 0x00005000\t 492 TX DMA\n-\t * 0x00006000\t 488 service list\n-\t * 0x00007000\t 484 buffers\n-\t * 0x00080000\t 0 end (512kB)\n-\t */\n-\teni_out(0xffffffff,MID_IE);\n-\terror = start_tx(dev);\n-\tif (error) goto free_list;\n-\terror = start_rx(dev);\n-\tif (error) goto free_list;\n-\terror = dev->phy->start(dev);\n-\tif (error) goto free_list;\n-\teni_out(eni_in(MID_MC_S) | (1 << MID_INT_SEL_SHIFT) |\n-\t MID_TX_LOCK_MODE | MID_DMA_ENABLE | MID_TX_ENABLE | MID_RX_ENABLE,\n-\t MID_MC_S);\n-\t /* Tonga uses SBus INTReq1 */\n-\t(void) eni_in(MID_ISA); /* clear Midway interrupts */\n-\treturn 0;\n-\n-free_list:\n-\tkfree(eni_dev->free_list);\n-\n-free_irq:\n-\tfree_irq(eni_dev->irq, dev);\n-\n-out:\n-\treturn error;\n-}\n-\n-\n-static void eni_close(struct atm_vcc *vcc)\n-{\n-\tDPRINTK(\">eni_close\\n\");\n-\tif (!ENI_VCC(vcc)) return;\n-\tclear_bit(ATM_VF_READY,&vcc->flags);\n-\tclose_rx(vcc);\n-\tclose_tx(vcc);\n-\tDPRINTK(\"eni_close: done waiting\\n\");\n-\t/* deallocate memory */\n-\tkfree(ENI_VCC(vcc));\n-\tvcc->dev_data = NULL;\n-\tclear_bit(ATM_VF_ADDR,&vcc->flags);\n-\t/*foo();*/\n-}\n-\n-\n-static int eni_open(struct atm_vcc *vcc)\n-{\n-\tstruct eni_vcc *eni_vcc;\n-\tint error;\n-\tshort vpi = vcc->vpi;\n-\tint vci = vcc->vci;\n-\n-\tDPRINTK(\">eni_open\\n\");\n-\tEVENT(\"eni_open\\n\",0,0);\n-\tif (!test_bit(ATM_VF_PARTIAL,&vcc->flags))\n-\t\tvcc->dev_data = NULL;\n-\tif (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)\n-\t\tset_bit(ATM_VF_ADDR,&vcc->flags);\n-\tif (vcc->qos.aal != ATM_AAL0 && vcc->qos.aal != ATM_AAL5)\n-\t\treturn -EINVAL;\n-\tDPRINTK(DEV_LABEL \"(itf %d): open %d.%d\\n\",vcc->dev->number,vcc->vpi,\n-\t vcc->vci);\n-\tif (!test_bit(ATM_VF_PARTIAL,&vcc->flags)) {\n-\t\teni_vcc = kmalloc_obj(struct eni_vcc);\n-\t\tif (!eni_vcc) return -ENOMEM;\n-\t\tvcc->dev_data = eni_vcc;\n-\t\teni_vcc->tx = NULL; /* for eni_close after open_rx */\n-\t\tif ((error = open_rx_first(vcc))) {\n-\t\t\teni_close(vcc);\n-\t\t\treturn error;\n-\t\t}\n-\t\tif ((error = open_tx_first(vcc))) {\n-\t\t\teni_close(vcc);\n-\t\t\treturn error;\n-\t\t}\n-\t}\n-\tif (vci == ATM_VPI_UNSPEC || vpi == ATM_VCI_UNSPEC) return 0;\n-\tif ((error = open_rx_second(vcc))) {\n-\t\teni_close(vcc);\n-\t\treturn error;\n-\t}\n-\tif ((error = open_tx_second(vcc))) {\n-\t\teni_close(vcc);\n-\t\treturn error;\n-\t}\n-\tset_bit(ATM_VF_READY,&vcc->flags);\n-\t/* should power down SUNI while !ref_count @@@ */\n-\treturn 0;\n-}\n-\n-\n-static int eni_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flgs)\n-{\n-\tstruct eni_dev *eni_dev = ENI_DEV(vcc->dev);\n-\tstruct eni_tx *tx = ENI_VCC(vcc)->tx;\n-\tstruct sk_buff *skb;\n-\tint error,rate,rsv,shp;\n-\n-\tif (qos->txtp.traffic_class == ATM_NONE) return 0;\n-\tif (tx == eni_dev->ubr) return -EBADFD;\n-\trate = atm_pcr_goal(&qos->txtp);\n-\tif (rate < 0) rate = -rate;\n-\trsv = shp = 0;\n-\tif ((flgs & ATM_MF_DEC_RSV) && rate && rate < tx->reserved) rsv = 1;\n-\tif ((flgs & ATM_MF_INC_RSV) && (!rate || rate > tx->reserved)) rsv = 1;\n-\tif ((flgs & ATM_MF_DEC_SHP) && rate && rate < tx->shaping) shp = 1;\n-\tif ((flgs & ATM_MF_INC_SHP) && (!rate || rate > tx->shaping)) shp = 1;\n-\tif (!rsv && !shp) return 0;\n-\terror = reserve_or_set_tx(vcc,&qos->txtp,rsv,shp);\n-\tif (error) return error;\n-\tif (shp && !(flgs & ATM_MF_IMMED)) return 0;\n-\t/*\n-\t * Walk through the send buffer and patch the rate information in all\n-\t * segmentation buffer descriptors of this VCC.\n-\t */\n-\ttasklet_disable(&eni_dev->task);\n-\tskb_queue_walk(&eni_dev->tx_queue, skb) {\n-\t\tvoid __iomem *dsc;\n-\n-\t\tif (ATM_SKB(skb)->vcc != vcc) continue;\n-\t\tdsc = tx->send+ENI_PRV_POS(skb)*4;\n-\t\twritel((readl(dsc) & ~(MID_SEG_RATE | MID_SEG_PR)) |\n-\t\t (tx->prescaler << MID_SEG_PR_SHIFT) |\n-\t\t (tx->resolution << MID_SEG_RATE_SHIFT), dsc);\n-\t}\n-\ttasklet_enable(&eni_dev->task);\n-\treturn 0;\n-}\n-\n-\n-static int eni_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)\n-{\n-\tstruct eni_dev *eni_dev = ENI_DEV(dev);\n-\n-\tif (cmd == ENI_MEMDUMP) {\n-\t\tif (!capable(CAP_NET_ADMIN)) return -EPERM;\n-\t\tprintk(KERN_WARNING \"Please use /proc/atm/\" DEV_LABEL \":%d \"\n-\t\t \"instead of obsolete ioctl ENI_MEMDUMP\\n\",dev->number);\n-\t\tdump(dev);\n-\t\treturn 0;\n-\t}\n-\tif (cmd == ENI_SETMULT) {\n-\t\tstruct eni_multipliers mult;\n-\n-\t\tif (!capable(CAP_NET_ADMIN)) return -EPERM;\n-\t\tif (copy_from_user(&mult, arg,\n-\t\t sizeof(struct eni_multipliers)))\n-\t\t\treturn -EFAULT;\n-\t\tif ((mult.tx && mult.tx <= 100) || (mult.rx &&mult.rx <= 100) ||\n-\t\t mult.tx > 65536 || mult.rx > 65536)\n-\t\t\treturn -EINVAL;\n-\t\tif (mult.tx) eni_dev->tx_mult = mult.tx;\n-\t\tif (mult.rx) eni_dev->rx_mult = mult.rx;\n-\t\treturn 0;\n-\t}\n-\tif (cmd == ATM_SETCIRANGE) {\n-\t\tstruct atm_cirange ci;\n-\n-\t\tif (copy_from_user(&ci, arg,sizeof(struct atm_cirange)))\n-\t\t\treturn -EFAULT;\n-\t\tif ((ci.vpi_bits == 0 || ci.vpi_bits == ATM_CI_MAX) &&\n-\t\t (ci.vci_bits == NR_VCI_LD || ci.vpi_bits == ATM_CI_MAX))\n-\t\t return 0;\n-\t\treturn -EINVAL;\n-\t}\n-\tif (!dev->phy->ioctl) return -ENOIOCTLCMD;\n-\treturn dev->phy->ioctl(dev,cmd,arg);\n-}\n-\n-static int eni_send(struct atm_vcc *vcc,struct sk_buff *skb)\n-{\n-\tenum enq_res res;\n-\n-\tDPRINTK(\">eni_send\\n\");\n-\tif (!ENI_VCC(vcc)->tx) {\n-\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\telse dev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\tif (!skb) {\n-\t\tprintk(KERN_CRIT \"!skb in eni_send ?\\n\");\n-\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\treturn -EINVAL;\n-\t}\n-\tif (vcc->qos.aal == ATM_AAL0) {\n-\t\tif (skb->len != ATM_CELL_SIZE-1) {\n-\t\t\tif (vcc->pop) vcc->pop(vcc,skb);\n-\t\t\telse dev_kfree_skb(skb);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\t*(u32 *) skb->data = htonl(*(u32 *) skb->data);\n-\t}\n-\tsubmitted++;\n-\tATM_SKB(skb)->vcc = vcc;\n-\ttasklet_disable_in_atomic(&ENI_DEV(vcc->dev)->task);\n-\tres = do_tx(skb);\n-\ttasklet_enable(&ENI_DEV(vcc->dev)->task);\n-\tif (res == enq_ok) return 0;\n-\tskb_queue_tail(&ENI_VCC(vcc)->tx->backlog,skb);\n-\tbacklogged++;\n-\ttasklet_schedule(&ENI_DEV(vcc->dev)->task);\n-\treturn 0;\n-}\n-\n-static void eni_phy_put(struct atm_dev *dev,unsigned char value,\n- unsigned long addr)\n-{\n-\twritel(value,ENI_DEV(dev)->phy+addr*4);\n-}\n-\n-\n-\n-static unsigned char eni_phy_get(struct atm_dev *dev,unsigned long addr)\n-{\n-\treturn readl(ENI_DEV(dev)->phy+addr*4);\n-}\n-\n-\n-static int eni_proc_read(struct atm_dev *dev,loff_t *pos,char *page)\n-{\n-\tstruct sock *s;\n-\tstatic const char *signal[] = { \"LOST\",\"unknown\",\"okay\" };\n-\tstruct eni_dev *eni_dev = ENI_DEV(dev);\n-\tstruct atm_vcc *vcc;\n-\tint left,i;\n-\n-\tleft = *pos;\n-\tif (!left)\n-\t\treturn sprintf(page,DEV_LABEL \"(itf %d) signal %s, %dkB, \"\n-\t\t \"%d cps remaining\\n\",dev->number,signal[(int) dev->signal],\n-\t\t eni_dev->mem >> 10,eni_dev->tx_bw);\n-\tif (!--left)\n-\t\treturn sprintf(page,\"%4sBursts: TX\"\n-#if !defined(CONFIG_ATM_ENI_BURST_TX_16W) && \\\n- !defined(CONFIG_ATM_ENI_BURST_TX_8W) && \\\n- !defined(CONFIG_ATM_ENI_BURST_TX_4W) && \\\n- !defined(CONFIG_ATM_ENI_BURST_TX_2W)\n-\t\t \" none\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_16W\n-\t\t \" 16W\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_8W\n-\t\t \" 8W\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_4W\n-\t\t \" 4W\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_TX_2W\n-\t\t \" 2W\"\n-#endif\n-\t\t \", RX\"\n-#if !defined(CONFIG_ATM_ENI_BURST_RX_16W) && \\\n- !defined(CONFIG_ATM_ENI_BURST_RX_8W) && \\\n- !defined(CONFIG_ATM_ENI_BURST_RX_4W) && \\\n- !defined(CONFIG_ATM_ENI_BURST_RX_2W)\n-\t\t \" none\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_16W\n-\t\t \" 16W\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_8W\n-\t\t \" 8W\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_4W\n-\t\t \" 4W\"\n-#endif\n-#ifdef CONFIG_ATM_ENI_BURST_RX_2W\n-\t\t \" 2W\"\n-#endif\n-#ifndef CONFIG_ATM_ENI_TUNE_BURST\n-\t\t \" (default)\"\n-#endif\n-\t\t \"\\n\",\"\");\n-\tif (!--left) \n-\t\treturn sprintf(page,\"%4sBuffer multipliers: tx %d%%, rx %d%%\\n\",\n-\t\t \"\",eni_dev->tx_mult,eni_dev->rx_mult);\n-\tfor (i = 0; i < NR_CHAN; i++) {\n-\t\tstruct eni_tx *tx = eni_dev->tx+i;\n-\n-\t\tif (!tx->send) continue;\n-\t\tif (!--left) {\n-\t\t\treturn sprintf(page, \"tx[%d]: 0x%lx-0x%lx \"\n-\t\t\t \"(%6ld bytes), rsv %d cps, shp %d cps%s\\n\",i,\n-\t\t\t (unsigned long) (tx->send - eni_dev->ram),\n-\t\t\t tx->send-eni_dev->ram+tx->words*4-1,tx->words*4,\n-\t\t\t tx->reserved,tx->shaping,\n-\t\t\t tx == eni_dev->ubr ? \" (UBR)\" : \"\");\n-\t\t}\n-\t\tif (--left) continue;\n-\t\treturn sprintf(page,\"%10sbacklog %u packets\\n\",\"\",\n-\t\t skb_queue_len(&tx->backlog));\n-\t}\n-\tread_lock(&vcc_sklist_lock);\n-\tfor(i = 0; i < VCC_HTABLE_SIZE; ++i) {\n-\t\tstruct hlist_head *head = &vcc_hash[i];\n-\n-\t\tsk_for_each(s, head) {\n-\t\t\tstruct eni_vcc *eni_vcc;\n-\t\t\tint length;\n-\n-\t\t\tvcc = atm_sk(s);\n-\t\t\tif (vcc->dev != dev)\n-\t\t\t\tcontinue;\n-\t\t\teni_vcc = ENI_VCC(vcc);\n-\t\t\tif (--left) continue;\n-\t\t\tlength = sprintf(page,\"vcc %4d: \",vcc->vci);\n-\t\t\tif (eni_vcc->rx) {\n-\t\t\t\tlength += sprintf(page+length, \"0x%lx-0x%lx \"\n-\t\t\t\t \"(%6ld bytes)\",\n-\t\t\t\t (unsigned long) (eni_vcc->recv - eni_dev->ram),\n-\t\t\t\t eni_vcc->recv-eni_dev->ram+eni_vcc->words*4-1,\n-\t\t\t\t eni_vcc->words*4);\n-\t\t\t\tif (eni_vcc->tx) length += sprintf(page+length,\", \");\n-\t\t\t}\n-\t\t\tif (eni_vcc->tx)\n-\t\t\t\tlength += sprintf(page+length,\"tx[%d], txing %d bytes\",\n-\t\t\t\t eni_vcc->tx->index,eni_vcc->txing);\n-\t\t\tpage[length] = '\\n';\n-\t\t\tread_unlock(&vcc_sklist_lock);\n-\t\t\treturn length+1;\n-\t\t}\n-\t}\n-\tread_unlock(&vcc_sklist_lock);\n-\tfor (i = 0; i < eni_dev->free_len; i++) {\n-\t\tstruct eni_free *fe = eni_dev->free_list+i;\n-\t\tunsigned long offset;\n-\n-\t\tif (--left) continue;\n-\t\toffset = (unsigned long) eni_dev->ram+eni_dev->base_diff;\n-\t\treturn sprintf(page,\"free %p-%p (%6d bytes)\\n\",\n-\t\t fe->start-offset,fe->start-offset+(1 << fe->order)-1,\n-\t\t 1 << fe->order);\n-\t}\n-\treturn 0;\n-}\n-\n-\n-static const struct atmdev_ops ops = {\n-\t.open\t\t= eni_open,\n-\t.close\t\t= eni_close,\n-\t.ioctl\t\t= eni_ioctl,\n-\t.send\t\t= eni_send,\n-\t.phy_put\t= eni_phy_put,\n-\t.phy_get\t= eni_phy_get,\n-\t.change_qos\t= eni_change_qos,\n-\t.proc_read\t= eni_proc_read\n-};\n-\n-\n-static int eni_init_one(struct pci_dev *pci_dev,\n-\t\t\tconst struct pci_device_id *ent)\n-{\n-\tstruct atm_dev *dev;\n-\tstruct eni_dev *eni_dev;\n-\tstruct eni_zero *zero;\n-\tint rc;\n-\n-\trc = pci_enable_device(pci_dev);\n-\tif (rc < 0)\n-\t\tgoto out;\n-\n-\trc = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));\n-\tif (rc < 0)\n-\t\tgoto err_disable;\n-\n-\trc = -ENOMEM;\n-\teni_dev = kmalloc_obj(struct eni_dev);\n-\tif (!eni_dev)\n-\t\tgoto err_disable;\n-\n-\tzero = &eni_dev->zero;\n-\tzero->addr = dma_alloc_coherent(&pci_dev->dev,\n-\t\t\t\t\tENI_ZEROES_SIZE, &zero->dma, GFP_KERNEL);\n-\tif (!zero->addr)\n-\t\tgoto err_kfree;\n-\n-\tdev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &ops, -1, NULL);\n-\tif (!dev)\n-\t\tgoto err_free_consistent;\n-\n-\tdev->dev_data = eni_dev;\n-\tpci_set_drvdata(pci_dev, dev);\n-\teni_dev->pci_dev = pci_dev;\n-\teni_dev->asic = ent->driver_data;\n-\n-\trc = eni_do_init(dev);\n-\tif (rc < 0)\n-\t\tgoto err_unregister;\n-\n-\trc = eni_start(dev);\n-\tif (rc < 0)\n-\t\tgoto err_eni_release;\n-\n-\teni_dev->more = eni_boards;\n-\teni_boards = dev;\n-out:\n-\treturn rc;\n-\n-err_eni_release:\n-\tdev->phy = NULL;\n-\tiounmap(ENI_DEV(dev)->ioaddr);\n-err_unregister:\n-\tatm_dev_deregister(dev);\n-err_free_consistent:\n-\tdma_free_coherent(&pci_dev->dev, ENI_ZEROES_SIZE, zero->addr, zero->dma);\n-err_kfree:\n-\tkfree(eni_dev);\n-err_disable:\n-\tpci_disable_device(pci_dev);\n-\tgoto out;\n-}\n-\n-\n-static const struct pci_device_id eni_pci_tbl[] = {\n-\t{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_FPGA), 0 /* FPGA */ },\n-\t{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_ASIC), 1 /* ASIC */ },\n-\t{ 0, }\n-};\n-MODULE_DEVICE_TABLE(pci,eni_pci_tbl);\n-\n-\n-static void eni_remove_one(struct pci_dev *pdev)\n-{\n-\tstruct atm_dev *dev = pci_get_drvdata(pdev);\n-\tstruct eni_dev *ed = ENI_DEV(dev);\n-\tstruct eni_zero *zero = &ed->zero;\n-\n-\teni_do_release(dev);\n-\tatm_dev_deregister(dev);\n-\tdma_free_coherent(&pdev->dev, ENI_ZEROES_SIZE, zero->addr, zero->dma);\n-\tkfree(ed);\n-\tpci_disable_device(pdev);\n-}\n-\n-\n-static struct pci_driver eni_driver = {\n-\t.name\t\t= DEV_LABEL,\n-\t.id_table\t= eni_pci_tbl,\n-\t.probe\t\t= eni_init_one,\n-\t.remove\t\t= eni_remove_one,\n-};\n-\n-\n-static int __init eni_init(void)\n-{\n-\tstruct sk_buff *skb; /* dummy for sizeof */\n-\n-\tBUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct eni_skb_prv));\n-\treturn pci_register_driver(&eni_driver);\n-}\n-\n-\n-module_init(eni_init);\n-/* @@@ since exit routine not defined, this module can not be unloaded */\n-\n-MODULE_DESCRIPTION(\"Efficient Networks ENI155P ATM NIC driver\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/atm/fore200e.c b/drivers/atm/fore200e.c\ndeleted file mode 100644\nindex 2423eed506c1..000000000000\n--- a/drivers/atm/fore200e.c\n+++ /dev/null\n@@ -1,3012 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later\n-/*\n- A FORE Systems 200E-series driver for ATM on Linux.\n- Christophe Lizzi (lizzi@cnam.fr), October 1999-March 2003.\n-\n- Based on the PCA-200E driver from Uwe Dannowski (Uwe.Dannowski@inf.tu-dresden.de).\n-\n- This driver simultaneously supports PCA-200E and SBA-200E adapters\n- on i386, alpha (untested), powerpc, sparc and sparc64 architectures.\n-\n-*/\n-\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#ifdef CONFIG_SBUS\n-#include \n-#include \n-#include \n-#include \n-#include \n-#endif\n-\n-#if defined(CONFIG_ATM_FORE200E_USE_TASKLET) /* defer interrupt work to a tasklet */\n-#define FORE200E_USE_TASKLET\n-#endif\n-\n-#if 0 /* enable the debugging code of the buffer supply queues */\n-#define FORE200E_BSQ_DEBUG\n-#endif\n-\n-#if 1 /* ensure correct handling of 52-byte AAL0 SDUs expected by atmdump-like apps */\n-#define FORE200E_52BYTE_AAL0_SDU\n-#endif\n-\n-#include \"fore200e.h\"\n-#include \"suni.h\"\n-\n-#define FORE200E_VERSION \"0.3e\"\n-\n-#define FORE200E \"fore200e: \"\n-\n-#if 0 /* override .config */\n-#define CONFIG_ATM_FORE200E_DEBUG 1\n-#endif\n-#if defined(CONFIG_ATM_FORE200E_DEBUG) && (CONFIG_ATM_FORE200E_DEBUG > 0)\n-#define DPRINTK(level, format, args...) do { if (CONFIG_ATM_FORE200E_DEBUG >= (level)) \\\n- printk(FORE200E format, ##args); } while (0)\n-#else\n-#define DPRINTK(level, format, args...) do {} while (0)\n-#endif\n-\n-\n-#define FORE200E_ALIGN(addr, alignment) \\\n- ((((unsigned long)(addr) + (alignment - 1)) & ~(alignment - 1)) - (unsigned long)(addr))\n-\n-#define FORE200E_DMA_INDEX(dma_addr, type, index) ((dma_addr) + (index) * sizeof(type))\n-\n-#define FORE200E_INDEX(virt_addr, type, index) (&((type *)(virt_addr))[ index ])\n-\n-#define FORE200E_NEXT_ENTRY(index, modulo) (index = ((index) + 1) % (modulo))\n-\n-#if 1\n-#define ASSERT(expr) if (!(expr)) { \\\n-\t\t\t printk(FORE200E \"assertion failed! %s[%d]: %s\\n\", \\\n-\t\t\t\t __func__, __LINE__, #expr); \\\n-\t\t\t panic(FORE200E \"%s\", __func__); \\\n-\t\t\t }\n-#else\n-#define ASSERT(expr) do {} while (0)\n-#endif\n-\n-\n-static const struct atmdev_ops fore200e_ops;\n-\n-MODULE_AUTHOR(\"Christophe Lizzi - credits to Uwe Dannowski and Heikki Vatiainen\");\n-MODULE_DESCRIPTION(\"FORE Systems 200E-series ATM driver - version \" FORE200E_VERSION);\n-\n-static const int fore200e_rx_buf_nbr[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ] = {\n- { BUFFER_S1_NBR, BUFFER_L1_NBR },\n- { BUFFER_S2_NBR, BUFFER_L2_NBR }\n-};\n-\n-static const int fore200e_rx_buf_size[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ] = {\n- { BUFFER_S1_SIZE, BUFFER_L1_SIZE },\n- { BUFFER_S2_SIZE, BUFFER_L2_SIZE }\n-};\n-\n-\n-#if defined(CONFIG_ATM_FORE200E_DEBUG) && (CONFIG_ATM_FORE200E_DEBUG > 0)\n-static const char* fore200e_traffic_class[] = { \"NONE\", \"UBR\", \"CBR\", \"VBR\", \"ABR\", \"ANY\" };\n-#endif\n-\n-\n-#if 0 /* currently unused */\n-static int \n-fore200e_fore2atm_aal(enum fore200e_aal aal)\n-{\n- switch(aal) {\n- case FORE200E_AAL0: return ATM_AAL0;\n- case FORE200E_AAL34: return ATM_AAL34;\n- case FORE200E_AAL5: return ATM_AAL5;\n- }\n-\n- return -EINVAL;\n-}\n-#endif\n-\n-\n-static enum fore200e_aal\n-fore200e_atm2fore_aal(int aal)\n-{\n- switch(aal) {\n- case ATM_AAL0: return FORE200E_AAL0;\n- case ATM_AAL34: return FORE200E_AAL34;\n- case ATM_AAL1:\n- case ATM_AAL2:\n- case ATM_AAL5: return FORE200E_AAL5;\n- }\n-\n- return -EINVAL;\n-}\n-\n-\n-static char*\n-fore200e_irq_itoa(int irq)\n-{\n- static char str[8];\n- sprintf(str, \"%d\", irq);\n- return str;\n-}\n-\n-\n-/* allocate and align a chunk of memory intended to hold the data behing exchanged\n- between the driver and the adapter (using streaming DVMA) */\n-\n-static int\n-fore200e_chunk_alloc(struct fore200e* fore200e, struct chunk* chunk, int size, int alignment, int direction)\n-{\n- unsigned long offset = 0;\n-\n- if (alignment <= sizeof(int))\n-\talignment = 0;\n-\n- chunk->alloc_size = size + alignment;\n- chunk->direction = direction;\n-\n- chunk->alloc_addr = kzalloc(chunk->alloc_size, GFP_KERNEL);\n- if (chunk->alloc_addr == NULL)\n-\treturn -ENOMEM;\n-\n- if (alignment > 0)\n-\toffset = FORE200E_ALIGN(chunk->alloc_addr, alignment); \n- \n- chunk->align_addr = chunk->alloc_addr + offset;\n-\n- chunk->dma_addr = dma_map_single(fore200e->dev, chunk->align_addr,\n-\t\t\t\t size, direction);\n- if (dma_mapping_error(fore200e->dev, chunk->dma_addr)) {\n-\tkfree(chunk->alloc_addr);\n-\treturn -ENOMEM;\n- }\n- return 0;\n-}\n-\n-\n-/* free a chunk of memory */\n-\n-static void\n-fore200e_chunk_free(struct fore200e* fore200e, struct chunk* chunk)\n-{\n- dma_unmap_single(fore200e->dev, chunk->dma_addr, chunk->dma_size,\n-\t\t chunk->direction);\n- kfree(chunk->alloc_addr);\n-}\n-\n-/*\n- * Allocate a DMA consistent chunk of memory intended to act as a communication\n- * mechanism (to hold descriptors, status, queues, etc.) shared by the driver\n- * and the adapter.\n- */\n-static int\n-fore200e_dma_chunk_alloc(struct fore200e *fore200e, struct chunk *chunk,\n-\t\tint size, int nbr, int alignment)\n-{\n-\t/* returned chunks are page-aligned */\n-\tchunk->alloc_size = size * nbr;\n-\tchunk->alloc_addr = dma_alloc_coherent(fore200e->dev, chunk->alloc_size,\n-\t\t\t\t\t &chunk->dma_addr, GFP_KERNEL);\n-\tif (!chunk->alloc_addr)\n-\t\treturn -ENOMEM;\n-\tchunk->align_addr = chunk->alloc_addr;\n-\treturn 0;\n-}\n-\n-/*\n- * Free a DMA consistent chunk of memory.\n- */\n-static void\n-fore200e_dma_chunk_free(struct fore200e* fore200e, struct chunk* chunk)\n-{\n-\tdma_free_coherent(fore200e->dev, chunk->alloc_size, chunk->alloc_addr,\n-\t\t\t chunk->dma_addr);\n-}\n-\n-static void\n-fore200e_spin(int msecs)\n-{\n- unsigned long timeout = jiffies + msecs_to_jiffies(msecs);\n- while (time_before(jiffies, timeout));\n-}\n-\n-\n-static int\n-fore200e_poll(struct fore200e* fore200e, volatile u32* addr, u32 val, int msecs)\n-{\n- unsigned long timeout = jiffies + msecs_to_jiffies(msecs);\n- int ok;\n-\n- mb();\n- do {\n-\tif ((ok = (*addr == val)) || (*addr & STATUS_ERROR))\n-\t break;\n-\n- } while (time_before(jiffies, timeout));\n-\n-#if 1\n- if (!ok) {\n-\tprintk(FORE200E \"cmd polling failed, got status 0x%08x, expected 0x%08x\\n\",\n-\t *addr, val);\n- }\n-#endif\n-\n- return ok;\n-}\n-\n-\n-static int\n-fore200e_io_poll(struct fore200e* fore200e, volatile u32 __iomem *addr, u32 val, int msecs)\n-{\n- unsigned long timeout = jiffies + msecs_to_jiffies(msecs);\n- int ok;\n-\n- do {\n-\tif ((ok = (fore200e->bus->read(addr) == val)))\n-\t break;\n-\n- } while (time_before(jiffies, timeout));\n-\n-#if 1\n- if (!ok) {\n-\tprintk(FORE200E \"I/O polling failed, got status 0x%08x, expected 0x%08x\\n\",\n-\t fore200e->bus->read(addr), val);\n- }\n-#endif\n-\n- return ok;\n-}\n-\n-\n-static void\n-fore200e_free_rx_buf(struct fore200e* fore200e)\n-{\n- int scheme, magn, nbr;\n- struct buffer* buffer;\n-\n- for (scheme = 0; scheme < BUFFER_SCHEME_NBR; scheme++) {\n-\tfor (magn = 0; magn < BUFFER_MAGN_NBR; magn++) {\n-\n-\t if ((buffer = fore200e->host_bsq[ scheme ][ magn ].buffer) != NULL) {\n-\n-\t\tfor (nbr = 0; nbr < fore200e_rx_buf_nbr[ scheme ][ magn ]; nbr++) {\n-\n-\t\t struct chunk* data = &buffer[ nbr ].data;\n-\n-\t\t if (data->alloc_addr != NULL)\n-\t\t\tfore200e_chunk_free(fore200e, data);\n-\t\t}\n-\t }\n-\t}\n- }\n-}\n-\n-\n-static void\n-fore200e_uninit_bs_queue(struct fore200e* fore200e)\n-{\n- int scheme, magn;\n- \n- for (scheme = 0; scheme < BUFFER_SCHEME_NBR; scheme++) {\n-\tfor (magn = 0; magn < BUFFER_MAGN_NBR; magn++) {\n-\n-\t struct chunk* status = &fore200e->host_bsq[ scheme ][ magn ].status;\n-\t struct chunk* rbd_block = &fore200e->host_bsq[ scheme ][ magn ].rbd_block;\n-\t \n-\t if (status->alloc_addr)\n-\t\tfore200e_dma_chunk_free(fore200e, status);\n-\t \n-\t if (rbd_block->alloc_addr)\n-\t\tfore200e_dma_chunk_free(fore200e, rbd_block);\n-\t}\n- }\n-}\n-\n-\n-static int\n-fore200e_reset(struct fore200e* fore200e, int diag)\n-{\n- int ok;\n-\n- fore200e->cp_monitor = fore200e->virt_base + FORE200E_CP_MONITOR_OFFSET;\n- \n- fore200e->bus->write(BSTAT_COLD_START, &fore200e->cp_monitor->bstat);\n-\n- fore200e->bus->reset(fore200e);\n-\n- if (diag) {\n-\tok = fore200e_io_poll(fore200e, &fore200e->cp_monitor->bstat, BSTAT_SELFTEST_OK, 1000);\n-\tif (ok == 0) {\n-\t \n-\t printk(FORE200E \"device %s self-test failed\\n\", fore200e->name);\n-\t return -ENODEV;\n-\t}\n-\n-\tprintk(FORE200E \"device %s self-test passed\\n\", fore200e->name);\n-\t\n-\tfore200e->state = FORE200E_STATE_RESET;\n- }\n-\n- return 0;\n-}\n-\n-\n-static void\n-fore200e_shutdown(struct fore200e* fore200e)\n-{\n- printk(FORE200E \"removing device %s at 0x%lx, IRQ %s\\n\",\n-\t fore200e->name, fore200e->phys_base, \n-\t fore200e_irq_itoa(fore200e->irq));\n- \n- if (fore200e->state > FORE200E_STATE_RESET) {\n-\t/* first, reset the board to prevent further interrupts or data transfers */\n-\tfore200e_reset(fore200e, 0);\n- }\n- \n- /* then, release all allocated resources */\n- switch(fore200e->state) {\n-\n- case FORE200E_STATE_COMPLETE:\n-\tkfree(fore200e->stats);\n-\n-\tfallthrough;\n- case FORE200E_STATE_IRQ:\n-\tfree_irq(fore200e->irq, fore200e->atm_dev);\n-#ifdef FORE200E_USE_TASKLET\n-\ttasklet_kill(&fore200e->tx_tasklet);\n-\ttasklet_kill(&fore200e->rx_tasklet);\n-#endif\n-\n-\tfallthrough;\n- case FORE200E_STATE_ALLOC_BUF:\n-\tfore200e_free_rx_buf(fore200e);\n-\n-\tfallthrough;\n- case FORE200E_STATE_INIT_BSQ:\n-\tfore200e_uninit_bs_queue(fore200e);\n-\n-\tfallthrough;\n- case FORE200E_STATE_INIT_RXQ:\n-\tfore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.status);\n-\tfore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.rpd);\n-\n-\tfallthrough;\n- case FORE200E_STATE_INIT_TXQ:\n-\tfore200e_dma_chunk_free(fore200e, &fore200e->host_txq.status);\n-\tfore200e_dma_chunk_free(fore200e, &fore200e->host_txq.tpd);\n-\n-\tfallthrough;\n- case FORE200E_STATE_INIT_CMDQ:\n-\tfore200e_dma_chunk_free(fore200e, &fore200e->host_cmdq.status);\n-\n-\tfallthrough;\n- case FORE200E_STATE_INITIALIZE:\n-\t/* nothing to do for that state */\n-\n- case FORE200E_STATE_START_FW:\n-\t/* nothing to do for that state */\n-\n- case FORE200E_STATE_RESET:\n-\t/* nothing to do for that state */\n-\n- case FORE200E_STATE_MAP:\n-\tfore200e->bus->unmap(fore200e);\n-\n-\tfallthrough;\n- case FORE200E_STATE_CONFIGURE:\n-\t/* nothing to do for that state */\n-\n- case FORE200E_STATE_REGISTER:\n-\t/* XXX shouldn't we *start* by deregistering the device? */\n-\tatm_dev_deregister(fore200e->atm_dev);\n-\n-\tfallthrough;\n- case FORE200E_STATE_BLANK:\n-\t/* nothing to do for that state */\n-\tbreak;\n- }\n-}\n-\n-\n-#ifdef CONFIG_PCI\n-\n-static u32 fore200e_pca_read(volatile u32 __iomem *addr)\n-{\n- /* on big-endian hosts, the board is configured to convert\n- the endianess of slave RAM accesses */\n- return le32_to_cpu(readl(addr));\n-}\n-\n-\n-static void fore200e_pca_write(u32 val, volatile u32 __iomem *addr)\n-{\n- /* on big-endian hosts, the board is configured to convert\n- the endianess of slave RAM accesses */\n- writel(cpu_to_le32(val), addr);\n-}\n-\n-static int\n-fore200e_pca_irq_check(struct fore200e* fore200e)\n-{\n- /* this is a 1 bit register */\n- int irq_posted = readl(fore200e->regs.pca.psr);\n-\n-#if defined(CONFIG_ATM_FORE200E_DEBUG) && (CONFIG_ATM_FORE200E_DEBUG == 2)\n- if (irq_posted && (readl(fore200e->regs.pca.hcr) & PCA200E_HCR_OUTFULL)) {\n-\tDPRINTK(2,\"FIFO OUT full, device %d\\n\", fore200e->atm_dev->number);\n- }\n-#endif\n-\n- return irq_posted;\n-}\n-\n-\n-static void\n-fore200e_pca_irq_ack(struct fore200e* fore200e)\n-{\n- writel(PCA200E_HCR_CLRINTR, fore200e->regs.pca.hcr);\n-}\n-\n-\n-static void\n-fore200e_pca_reset(struct fore200e* fore200e)\n-{\n- writel(PCA200E_HCR_RESET, fore200e->regs.pca.hcr);\n- fore200e_spin(10);\n- writel(0, fore200e->regs.pca.hcr);\n-}\n-\n-\n-static int fore200e_pca_map(struct fore200e* fore200e)\n-{\n- DPRINTK(2, \"device %s being mapped in memory\\n\", fore200e->name);\n-\n- fore200e->virt_base = ioremap(fore200e->phys_base, PCA200E_IOSPACE_LENGTH);\n- \n- if (fore200e->virt_base == NULL) {\n-\tprintk(FORE200E \"can't map device %s\\n\", fore200e->name);\n-\treturn -EFAULT;\n- }\n-\n- DPRINTK(1, \"device %s mapped to 0x%p\\n\", fore200e->name, fore200e->virt_base);\n-\n- /* gain access to the PCA specific registers */\n- fore200e->regs.pca.hcr = fore200e->virt_base + PCA200E_HCR_OFFSET;\n- fore200e->regs.pca.imr = fore200e->virt_base + PCA200E_IMR_OFFSET;\n- fore200e->regs.pca.psr = fore200e->virt_base + PCA200E_PSR_OFFSET;\n-\n- fore200e->state = FORE200E_STATE_MAP;\n- return 0;\n-}\n-\n-\n-static void\n-fore200e_pca_unmap(struct fore200e* fore200e)\n-{\n- DPRINTK(2, \"device %s being unmapped from memory\\n\", fore200e->name);\n-\n- if (fore200e->virt_base != NULL)\n-\tiounmap(fore200e->virt_base);\n-}\n-\n-\n-static int fore200e_pca_configure(struct fore200e *fore200e)\n-{\n- struct pci_dev *pci_dev = to_pci_dev(fore200e->dev);\n- u8 master_ctrl, latency;\n-\n- DPRINTK(2, \"device %s being configured\\n\", fore200e->name);\n-\n- if ((pci_dev->irq == 0) || (pci_dev->irq == 0xFF)) {\n-\tprintk(FORE200E \"incorrect IRQ setting - misconfigured PCI-PCI bridge?\\n\");\n-\treturn -EIO;\n- }\n-\n- pci_read_config_byte(pci_dev, PCA200E_PCI_MASTER_CTRL, &master_ctrl);\n-\n- master_ctrl = master_ctrl\n-#if defined(__BIG_ENDIAN)\n-\t/* request the PCA board to convert the endianess of slave RAM accesses */\n-\t| PCA200E_CTRL_CONVERT_ENDIAN\n-#endif\n-#if 0\n- | PCA200E_CTRL_DIS_CACHE_RD\n- | PCA200E_CTRL_DIS_WRT_INVAL\n- | PCA200E_CTRL_ENA_CONT_REQ_MODE\n- | PCA200E_CTRL_2_CACHE_WRT_INVAL\n-#endif\n-\t| PCA200E_CTRL_LARGE_PCI_BURSTS;\n- \n- pci_write_config_byte(pci_dev, PCA200E_PCI_MASTER_CTRL, master_ctrl);\n-\n- /* raise latency from 32 (default) to 192, as this seems to prevent NIC\n- lockups (under heavy rx loads) due to continuous 'FIFO OUT full' condition.\n- this may impact the performances of other PCI devices on the same bus, though */\n- latency = 192;\n- pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);\n-\n- fore200e->state = FORE200E_STATE_CONFIGURE;\n- return 0;\n-}\n-\n-\n-static int __init\n-fore200e_pca_prom_read(struct fore200e* fore200e, struct prom_data* prom)\n-{\n- struct host_cmdq* cmdq = &fore200e->host_cmdq;\n- struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ];\n- struct prom_opcode opcode;\n- int ok;\n- u32 prom_dma;\n-\n- FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD);\n-\n- opcode.opcode = OPCODE_GET_PROM;\n- opcode.pad = 0;\n-\n- prom_dma = dma_map_single(fore200e->dev, prom, sizeof(struct prom_data),\n-\t\t\t DMA_FROM_DEVICE);\n- if (dma_mapping_error(fore200e->dev, prom_dma))\n-\treturn -ENOMEM;\n-\n- fore200e->bus->write(prom_dma, &entry->cp_entry->cmd.prom_block.prom_haddr);\n- \n- *entry->status = STATUS_PENDING;\n-\n- fore200e->bus->write(*(u32*)&opcode, (u32 __iomem *)&entry->cp_entry->cmd.prom_block.opcode);\n-\n- ok = fore200e_poll(fore200e, entry->status, STATUS_COMPLETE, 400);\n-\n- *entry->status = STATUS_FREE;\n-\n- dma_unmap_single(fore200e->dev, prom_dma, sizeof(struct prom_data), DMA_FROM_DEVICE);\n-\n- if (ok == 0) {\n-\tprintk(FORE200E \"unable to get PROM data from device %s\\n\", fore200e->name);\n-\treturn -EIO;\n- }\n-\n-#if defined(__BIG_ENDIAN)\n- \n-#define swap_here(addr) (*((u32*)(addr)) = swab32( *((u32*)(addr)) ))\n-\n- /* MAC address is stored as little-endian */\n- swap_here(&prom->mac_addr[0]);\n- swap_here(&prom->mac_addr[4]);\n-#endif\n- \n- return 0;\n-}\n-\n-\n-static int\n-fore200e_pca_proc_read(struct fore200e* fore200e, char *page)\n-{\n- struct pci_dev *pci_dev = to_pci_dev(fore200e->dev);\n-\n- return sprintf(page, \" PCI bus/slot/function:\\t%d/%d/%d\\n\",\n-\t\t pci_dev->bus->number, PCI_SLOT(pci_dev->devfn), PCI_FUNC(pci_dev->devfn));\n-}\n-\n-static const struct fore200e_bus fore200e_pci_ops = {\n-\t.model_name\t\t= \"PCA-200E\",\n-\t.proc_name\t\t= \"pca200e\",\n-\t.descr_alignment\t= 32,\n-\t.buffer_alignment\t= 4,\n-\t.status_alignment\t= 32,\n-\t.read\t\t\t= fore200e_pca_read,\n-\t.write\t\t\t= fore200e_pca_write,\n-\t.configure\t\t= fore200e_pca_configure,\n-\t.map\t\t\t= fore200e_pca_map,\n-\t.reset\t\t\t= fore200e_pca_reset,\n-\t.prom_read\t\t= fore200e_pca_prom_read,\n-\t.unmap\t\t\t= fore200e_pca_unmap,\n-\t.irq_check\t\t= fore200e_pca_irq_check,\n-\t.irq_ack\t\t= fore200e_pca_irq_ack,\n-\t.proc_read\t\t= fore200e_pca_proc_read,\n-};\n-#endif /* CONFIG_PCI */\n-\n-#ifdef CONFIG_SBUS\n-\n-static u32 fore200e_sba_read(volatile u32 __iomem *addr)\n-{\n- return sbus_readl(addr);\n-}\n-\n-static void fore200e_sba_write(u32 val, volatile u32 __iomem *addr)\n-{\n- sbus_writel(val, addr);\n-}\n-\n-static void fore200e_sba_irq_enable(struct fore200e *fore200e)\n-{\n-\tu32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY;\n-\tfore200e->bus->write(hcr | SBA200E_HCR_INTR_ENA, fore200e->regs.sba.hcr);\n-}\n-\n-static int fore200e_sba_irq_check(struct fore200e *fore200e)\n-{\n-\treturn fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_INTR_REQ;\n-}\n-\n-static void fore200e_sba_irq_ack(struct fore200e *fore200e)\n-{\n-\tu32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY;\n-\tfore200e->bus->write(hcr | SBA200E_HCR_INTR_CLR, fore200e->regs.sba.hcr);\n-}\n-\n-static void fore200e_sba_reset(struct fore200e *fore200e)\n-{\n-\tfore200e->bus->write(SBA200E_HCR_RESET, fore200e->regs.sba.hcr);\n-\tfore200e_spin(10);\n-\tfore200e->bus->write(0, fore200e->regs.sba.hcr);\n-}\n-\n-static int __init fore200e_sba_map(struct fore200e *fore200e)\n-{\n-\tstruct platform_device *op = to_platform_device(fore200e->dev);\n-\tunsigned int bursts;\n-\n-\t/* gain access to the SBA specific registers */\n-\tfore200e->regs.sba.hcr = of_ioremap(&op->resource[0], 0, SBA200E_HCR_LENGTH, \"SBA HCR\");\n-\tfore200e->regs.sba.bsr = of_ioremap(&op->resource[1], 0, SBA200E_BSR_LENGTH, \"SBA BSR\");\n-\tfore200e->regs.sba.isr = of_ioremap(&op->resource[2], 0, SBA200E_ISR_LENGTH, \"SBA ISR\");\n-\tfore200e->virt_base = of_ioremap(&op->resource[3], 0, SBA200E_RAM_LENGTH, \"SBA RAM\");\n-\n-\tif (!fore200e->virt_base) {\n-\t\tprintk(FORE200E \"unable to map RAM of device %s\\n\", fore200e->name);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tDPRINTK(1, \"device %s mapped to 0x%p\\n\", fore200e->name, fore200e->virt_base);\n- \n-\tfore200e->bus->write(0x02, fore200e->regs.sba.isr); /* XXX hardwired interrupt level */\n-\n-\t/* get the supported DVMA burst sizes */\n-\tbursts = of_getintprop_default(op->dev.of_node->parent, \"burst-sizes\", 0x00);\n-\n-\tif (sbus_can_dma_64bit())\n-\t\tsbus_set_sbus64(&op->dev, bursts);\n-\n-\tfore200e->state = FORE200E_STATE_MAP;\n-\treturn 0;\n-}\n-\n-static void fore200e_sba_unmap(struct fore200e *fore200e)\n-{\n-\tstruct platform_device *op = to_platform_device(fore200e->dev);\n-\n-\tof_iounmap(&op->resource[0], fore200e->regs.sba.hcr, SBA200E_HCR_LENGTH);\n-\tof_iounmap(&op->resource[1], fore200e->regs.sba.bsr, SBA200E_BSR_LENGTH);\n-\tof_iounmap(&op->resource[2], fore200e->regs.sba.isr, SBA200E_ISR_LENGTH);\n-\tof_iounmap(&op->resource[3], fore200e->virt_base, SBA200E_RAM_LENGTH);\n-}\n-\n-static int __init fore200e_sba_configure(struct fore200e *fore200e)\n-{\n-\tfore200e->state = FORE200E_STATE_CONFIGURE;\n-\treturn 0;\n-}\n-\n-static int __init fore200e_sba_prom_read(struct fore200e *fore200e, struct prom_data *prom)\n-{\n-\tstruct platform_device *op = to_platform_device(fore200e->dev);\n-\tconst u8 *prop;\n-\tint len;\n-\n-\tprop = of_get_property(op->dev.of_node, \"madaddrlo2\", &len);\n-\tif (!prop)\n-\t\treturn -ENODEV;\n-\tmemcpy(&prom->mac_addr[4], prop, 4);\n-\n-\tprop = of_get_property(op->dev.of_node, \"madaddrhi4\", &len);\n-\tif (!prop)\n-\t\treturn -ENODEV;\n-\tmemcpy(&prom->mac_addr[2], prop, 4);\n-\n-\tprom->serial_number = of_getintprop_default(op->dev.of_node,\n-\t\t\t\t\t\t \"serialnumber\", 0);\n-\tprom->hw_revision = of_getintprop_default(op->dev.of_node,\n-\t\t\t\t\t\t \"promversion\", 0);\n- \n-\treturn 0;\n-}\n-\n-static int fore200e_sba_proc_read(struct fore200e *fore200e, char *page)\n-{\n-\tstruct platform_device *op = to_platform_device(fore200e->dev);\n-\tconst struct linux_prom_registers *regs;\n-\n-\tregs = of_get_property(op->dev.of_node, \"reg\", NULL);\n-\n-\treturn sprintf(page, \" SBUS slot/device:\\t\\t%d/'%pOFn'\\n\",\n-\t\t (regs ? regs->which_io : 0), op->dev.of_node);\n-}\n-\n-static const struct fore200e_bus fore200e_sbus_ops = {\n-\t.model_name\t\t= \"SBA-200E\",\n-\t.proc_name\t\t= \"sba200e\",\n-\t.descr_alignment\t= 32,\n-\t.buffer_alignment\t= 64,\n-\t.status_alignment\t= 32,\n-\t.read\t\t\t= fore200e_sba_read,\n-\t.write\t\t\t= fore200e_sba_write,\n-\t.configure\t\t= fore200e_sba_configure,\n-\t.map\t\t\t= fore200e_sba_map,\n-\t.reset\t\t\t= fore200e_sba_reset,\n-\t.prom_read\t\t= fore200e_sba_prom_read,\n-\t.unmap\t\t\t= fore200e_sba_unmap,\n-\t.irq_enable\t\t= fore200e_sba_irq_enable,\n-\t.irq_check\t\t= fore200e_sba_irq_check,\n-\t.irq_ack\t\t= fore200e_sba_irq_ack,\n-\t.proc_read\t\t= fore200e_sba_proc_read,\n-};\n-#endif /* CONFIG_SBUS */\n-\n-static void\n-fore200e_tx_irq(struct fore200e* fore200e)\n-{\n- struct host_txq* txq = &fore200e->host_txq;\n- struct host_txq_entry* entry;\n- struct atm_vcc* vcc;\n- struct fore200e_vc_map* vc_map;\n-\n- if (fore200e->host_txq.txing == 0)\n-\treturn;\n-\n- for (;;) {\n-\t\n-\tentry = &txq->host_entry[ txq->tail ];\n-\n- if ((*entry->status & STATUS_COMPLETE) == 0) {\n-\t break;\n-\t}\n-\n-\tDPRINTK(3, \"TX COMPLETED: entry = %p [tail = %d], vc_map = %p, skb = %p\\n\", \n-\t\tentry, txq->tail, entry->vc_map, entry->skb);\n-\n-\t/* free copy of misaligned data */\n-\tkfree(entry->data);\n-\t\n-\t/* remove DMA mapping */\n-\tdma_unmap_single(fore200e->dev, entry->tpd->tsd[ 0 ].buffer, entry->tpd->tsd[ 0 ].length,\n-\t\t\t\t DMA_TO_DEVICE);\n-\n-\tvc_map = entry->vc_map;\n-\n-\t/* vcc closed since the time the entry was submitted for tx? */\n-\tif ((vc_map->vcc == NULL) ||\n-\t (test_bit(ATM_VF_READY, &vc_map->vcc->flags) == 0)) {\n-\n-\t DPRINTK(1, \"no ready vcc found for PDU sent on device %d\\n\",\n-\t\t fore200e->atm_dev->number);\n-\n-\t dev_kfree_skb_any(entry->skb);\n-\t}\n-\telse {\n-\t ASSERT(vc_map->vcc);\n-\n-\t /* vcc closed then immediately re-opened? */\n-\t if (vc_map->incarn != entry->incarn) {\n-\n-\t\t/* when a vcc is closed, some PDUs may be still pending in the tx queue.\n-\t\t if the same vcc is immediately re-opened, those pending PDUs must\n-\t\t not be popped after the completion of their emission, as they refer\n-\t\t to the prior incarnation of that vcc. otherwise, sk_atm(vcc)->sk_wmem_alloc\n-\t\t would be decremented by the size of the (unrelated) skb, possibly\n-\t\t leading to a negative sk->sk_wmem_alloc count, ultimately freezing the vcc.\n-\t\t we thus bind the tx entry to the current incarnation of the vcc\n-\t\t when the entry is submitted for tx. When the tx later completes,\n-\t\t if the incarnation number of the tx entry does not match the one\n-\t\t of the vcc, then this implies that the vcc has been closed then re-opened.\n-\t\t we thus just drop the skb here. */\n-\n-\t\tDPRINTK(1, \"vcc closed-then-re-opened; dropping PDU sent on device %d\\n\",\n-\t\t\tfore200e->atm_dev->number);\n-\n-\t\tdev_kfree_skb_any(entry->skb);\n-\t }\n-\t else {\n-\t\tvcc = vc_map->vcc;\n-\t\tASSERT(vcc);\n-\n-\t\t/* notify tx completion */\n-\t\tif (vcc->pop) {\n-\t\t vcc->pop(vcc, entry->skb);\n-\t\t}\n-\t\telse {\n-\t\t dev_kfree_skb_any(entry->skb);\n-\t\t}\n-\n-\t\t/* check error condition */\n-\t\tif (*entry->status & STATUS_ERROR)\n-\t\t atomic_inc(&vcc->stats->tx_err);\n-\t\telse\n-\t\t atomic_inc(&vcc->stats->tx);\n-\t }\n-\t}\n-\n-\t*entry->status = STATUS_FREE;\n-\n-\tfore200e->host_txq.txing--;\n-\n-\tFORE200E_NEXT_ENTRY(txq->tail, QUEUE_SIZE_TX);\n- }\n-}\n-\n-\n-#ifdef FORE200E_BSQ_DEBUG\n-int bsq_audit(int where, struct host_bsq* bsq, int scheme, int magn)\n-{\n- struct buffer* buffer;\n- int count = 0;\n-\n- buffer = bsq->freebuf;\n- while (buffer) {\n-\n-\tif (buffer->supplied) {\n-\t printk(FORE200E \"bsq_audit(%d): queue %d.%d, buffer %ld supplied but in free list!\\n\",\n-\t\t where, scheme, magn, buffer->index);\n-\t}\n-\n-\tif (buffer->magn != magn) {\n-\t printk(FORE200E \"bsq_audit(%d): queue %d.%d, buffer %ld, unexpected magn = %d\\n\",\n-\t\t where, scheme, magn, buffer->index, buffer->magn);\n-\t}\n-\n-\tif (buffer->scheme != scheme) {\n-\t printk(FORE200E \"bsq_audit(%d): queue %d.%d, buffer %ld, unexpected scheme = %d\\n\",\n-\t\t where, scheme, magn, buffer->index, buffer->scheme);\n-\t}\n-\n-\tif ((buffer->index < 0) || (buffer->index >= fore200e_rx_buf_nbr[ scheme ][ magn ])) {\n-\t printk(FORE200E \"bsq_audit(%d): queue %d.%d, out of range buffer index = %ld !\\n\",\n-\t\t where, scheme, magn, buffer->index);\n-\t}\n-\n-\tcount++;\n-\tbuffer = buffer->next;\n- }\n-\n- if (count != bsq->freebuf_count) {\n-\tprintk(FORE200E \"bsq_audit(%d): queue %d.%d, %d bufs in free list, but freebuf_count = %d\\n\",\n-\t where, scheme, magn, count, bsq->freebuf_count);\n- }\n- return 0;\n-}\n-#endif\n-\n-\n-static void\n-fore200e_supply(struct fore200e* fore200e)\n-{\n- int scheme, magn, i;\n-\n- struct host_bsq* bsq;\n- struct host_bsq_entry* entry;\n- struct buffer* buffer;\n-\n- for (scheme = 0; scheme < BUFFER_SCHEME_NBR; scheme++) {\n-\tfor (magn = 0; magn < BUFFER_MAGN_NBR; magn++) {\n-\n-\t bsq = &fore200e->host_bsq[ scheme ][ magn ];\n-\n-#ifdef FORE200E_BSQ_DEBUG\n-\t bsq_audit(1, bsq, scheme, magn);\n-#endif\n-\t while (bsq->freebuf_count >= RBD_BLK_SIZE) {\n-\n-\t\tDPRINTK(2, \"supplying %d rx buffers to queue %d / %d, freebuf_count = %d\\n\",\n-\t\t\tRBD_BLK_SIZE, scheme, magn, bsq->freebuf_count);\n-\n-\t\tentry = &bsq->host_entry[ bsq->head ];\n-\n-\t\tfor (i = 0; i < RBD_BLK_SIZE; i++) {\n-\n-\t\t /* take the first buffer in the free buffer list */\n-\t\t buffer = bsq->freebuf;\n-\t\t if (!buffer) {\n-\t\t\tprintk(FORE200E \"no more free bufs in queue %d.%d, but freebuf_count = %d\\n\",\n-\t\t\t scheme, magn, bsq->freebuf_count);\n-\t\t\treturn;\n-\t\t }\n-\t\t bsq->freebuf = buffer->next;\n-\t\t \n-#ifdef FORE200E_BSQ_DEBUG\n-\t\t if (buffer->supplied)\n-\t\t\tprintk(FORE200E \"queue %d.%d, buffer %lu already supplied\\n\",\n-\t\t\t scheme, magn, buffer->index);\n-\t\t buffer->supplied = 1;\n-#endif\n-\t\t entry->rbd_block->rbd[ i ].buffer_haddr = buffer->data.dma_addr;\n-\t\t entry->rbd_block->rbd[ i ].handle = FORE200E_BUF2HDL(buffer);\n-\t\t}\n-\n-\t\tFORE200E_NEXT_ENTRY(bsq->head, QUEUE_SIZE_BS);\n-\n- \t\t/* decrease accordingly the number of free rx buffers */\n-\t\tbsq->freebuf_count -= RBD_BLK_SIZE;\n-\n-\t\t*entry->status = STATUS_PENDING;\n-\t\tfore200e->bus->write(entry->rbd_block_dma, &entry->cp_entry->rbd_block_haddr);\n-\t }\n-\t}\n- }\n-}\n-\n-\n-static int\n-fore200e_push_rpd(struct fore200e* fore200e, struct atm_vcc* vcc, struct rpd* rpd)\n-{\n- struct sk_buff* skb;\n- struct buffer* buffer;\n- struct fore200e_vcc* fore200e_vcc;\n- int i, pdu_len = 0;\n-#ifdef FORE200E_52BYTE_AAL0_SDU\n- u32 cell_header = 0;\n-#endif\n-\n- ASSERT(vcc);\n- \n- fore200e_vcc = FORE200E_VCC(vcc);\n- ASSERT(fore200e_vcc);\n-\n-#ifdef FORE200E_52BYTE_AAL0_SDU\n- if ((vcc->qos.aal == ATM_AAL0) && (vcc->qos.rxtp.max_sdu == ATM_AAL0_SDU)) {\n-\n-\tcell_header = (rpd->atm_header.gfc << ATM_HDR_GFC_SHIFT) |\n-\t (rpd->atm_header.vpi << ATM_HDR_VPI_SHIFT) |\n- (rpd->atm_header.vci << ATM_HDR_VCI_SHIFT) |\n- (rpd->atm_header.plt << ATM_HDR_PTI_SHIFT) | \n- rpd->atm_header.clp;\n-\tpdu_len = 4;\n- }\n-#endif\n- \n- /* compute total PDU length */\n- for (i = 0; i < rpd->nseg; i++)\n-\tpdu_len += rpd->rsd[ i ].length;\n- \n- skb = alloc_skb(pdu_len, GFP_ATOMIC);\n- if (skb == NULL) {\n-\tDPRINTK(2, \"unable to alloc new skb, rx PDU length = %d\\n\", pdu_len);\n-\n-\tatomic_inc(&vcc->stats->rx_drop);\n-\treturn -ENOMEM;\n- } \n-\n- __net_timestamp(skb);\n- \n-#ifdef FORE200E_52BYTE_AAL0_SDU\n- if (cell_header) {\n-\t*((u32*)skb_put(skb, 4)) = cell_header;\n- }\n-#endif\n-\n- /* reassemble segments */\n- for (i = 0; i < rpd->nseg; i++) {\n-\t\n-\t/* rebuild rx buffer address from rsd handle */\n-\tbuffer = FORE200E_HDL2BUF(rpd->rsd[ i ].handle);\n-\t\n-\t/* Make device DMA transfer visible to CPU. */\n-\tdma_sync_single_for_cpu(fore200e->dev, buffer->data.dma_addr,\n-\t\t\t\trpd->rsd[i].length, DMA_FROM_DEVICE);\n-\t\n-\tskb_put_data(skb, buffer->data.align_addr, rpd->rsd[i].length);\n-\n-\t/* Now let the device get at it again. */\n-\tdma_sync_single_for_device(fore200e->dev, buffer->data.dma_addr,\n-\t\t\t\t rpd->rsd[i].length, DMA_FROM_DEVICE);\n- }\n-\n- DPRINTK(3, \"rx skb: len = %d, truesize = %d\\n\", skb->len, skb->truesize);\n- \n- if (pdu_len < fore200e_vcc->rx_min_pdu)\n-\tfore200e_vcc->rx_min_pdu = pdu_len;\n- if (pdu_len > fore200e_vcc->rx_max_pdu)\n-\tfore200e_vcc->rx_max_pdu = pdu_len;\n- fore200e_vcc->rx_pdu++;\n-\n- /* push PDU */\n- if (atm_charge(vcc, skb->truesize) == 0) {\n-\n-\tDPRINTK(2, \"receive buffers saturated for %d.%d.%d - PDU dropped\\n\",\n-\t\tvcc->itf, vcc->vpi, vcc->vci);\n-\n-\tdev_kfree_skb_any(skb);\n-\n-\tatomic_inc(&vcc->stats->rx_drop);\n-\treturn -ENOMEM;\n- }\n-\n- vcc->push(vcc, skb);\n- atomic_inc(&vcc->stats->rx);\n-\n- return 0;\n-}\n-\n-\n-static void\n-fore200e_collect_rpd(struct fore200e* fore200e, struct rpd* rpd)\n-{\n- struct host_bsq* bsq;\n- struct buffer* buffer;\n- int i;\n- \n- for (i = 0; i < rpd->nseg; i++) {\n-\n-\t/* rebuild rx buffer address from rsd handle */\n-\tbuffer = FORE200E_HDL2BUF(rpd->rsd[ i ].handle);\n-\n-\tbsq = &fore200e->host_bsq[ buffer->scheme ][ buffer->magn ];\n-\n-#ifdef FORE200E_BSQ_DEBUG\n-\tbsq_audit(2, bsq, buffer->scheme, buffer->magn);\n-\n-\tif (buffer->supplied == 0)\n-\t printk(FORE200E \"queue %d.%d, buffer %ld was not supplied\\n\",\n-\t\t buffer->scheme, buffer->magn, buffer->index);\n-\tbuffer->supplied = 0;\n-#endif\n-\n-\t/* re-insert the buffer into the free buffer list */\n-\tbuffer->next = bsq->freebuf;\n-\tbsq->freebuf = buffer;\n-\n-\t/* then increment the number of free rx buffers */\n-\tbsq->freebuf_count++;\n- }\n-}\n-\n-\n-static void\n-fore200e_rx_irq(struct fore200e* fore200e)\n-{\n- struct host_rxq* rxq = &fore200e->host_rxq;\n- struct host_rxq_entry* entry;\n- struct atm_vcc* vcc;\n- struct fore200e_vc_map* vc_map;\n-\n- for (;;) {\n-\t\n-\tentry = &rxq->host_entry[ rxq->head ];\n-\n-\t/* no more received PDUs */\n-\tif ((*entry->status & STATUS_COMPLETE) == 0)\n-\t break;\n-\n-\tvc_map = FORE200E_VC_MAP(fore200e, entry->rpd->atm_header.vpi, entry->rpd->atm_header.vci);\n-\n-\tif ((vc_map->vcc == NULL) ||\n-\t (test_bit(ATM_VF_READY, &vc_map->vcc->flags) == 0)) {\n-\n-\t DPRINTK(1, \"no ready VC found for PDU received on %d.%d.%d\\n\",\n-\t\t fore200e->atm_dev->number,\n-\t\t entry->rpd->atm_header.vpi, entry->rpd->atm_header.vci);\n-\t}\n-\telse {\n-\t vcc = vc_map->vcc;\n-\t ASSERT(vcc);\n-\n-\t if ((*entry->status & STATUS_ERROR) == 0) {\n-\n-\t\tfore200e_push_rpd(fore200e, vcc, entry->rpd);\n-\t }\n-\t else {\n-\t\tDPRINTK(2, \"damaged PDU on %d.%d.%d\\n\",\n-\t\t\tfore200e->atm_dev->number,\n-\t\t\tentry->rpd->atm_header.vpi, entry->rpd->atm_header.vci);\n-\t\tatomic_inc(&vcc->stats->rx_err);\n-\t }\n-\t}\n-\n-\tFORE200E_NEXT_ENTRY(rxq->head, QUEUE_SIZE_RX);\n-\n-\tfore200e_collect_rpd(fore200e, entry->rpd);\n-\n-\t/* rewrite the rpd address to ack the received PDU */\n-\tfore200e->bus->write(entry->rpd_dma, &entry->cp_entry->rpd_haddr);\n-\t*entry->status = STATUS_FREE;\n-\n-\tfore200e_supply(fore200e);\n- }\n-}\n-\n-\n-#ifndef FORE200E_USE_TASKLET\n-static void\n-fore200e_irq(struct fore200e* fore200e)\n-{\n- unsigned long flags;\n-\n- spin_lock_irqsave(&fore200e->q_lock, flags);\n- fore200e_rx_irq(fore200e);\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\n- spin_lock_irqsave(&fore200e->q_lock, flags);\n- fore200e_tx_irq(fore200e);\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-}\n-#endif\n-\n-\n-static irqreturn_t\n-fore200e_interrupt(int irq, void* dev)\n-{\n- struct fore200e* fore200e = FORE200E_DEV((struct atm_dev*)dev);\n-\n- if (fore200e->bus->irq_check(fore200e) == 0) {\n-\t\n-\tDPRINTK(3, \"interrupt NOT triggered by device %d\\n\", fore200e->atm_dev->number);\n-\treturn IRQ_NONE;\n- }\n- DPRINTK(3, \"interrupt triggered by device %d\\n\", fore200e->atm_dev->number);\n-\n-#ifdef FORE200E_USE_TASKLET\n- tasklet_schedule(&fore200e->tx_tasklet);\n- tasklet_schedule(&fore200e->rx_tasklet);\n-#else\n- fore200e_irq(fore200e);\n-#endif\n- \n- fore200e->bus->irq_ack(fore200e);\n- return IRQ_HANDLED;\n-}\n-\n-\n-#ifdef FORE200E_USE_TASKLET\n-static void\n-fore200e_tx_tasklet(unsigned long data)\n-{\n- struct fore200e* fore200e = (struct fore200e*) data;\n- unsigned long flags;\n-\n- DPRINTK(3, \"tx tasklet scheduled for device %d\\n\", fore200e->atm_dev->number);\n-\n- spin_lock_irqsave(&fore200e->q_lock, flags);\n- fore200e_tx_irq(fore200e);\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-}\n-\n-\n-static void\n-fore200e_rx_tasklet(unsigned long data)\n-{\n- struct fore200e* fore200e = (struct fore200e*) data;\n- unsigned long flags;\n-\n- DPRINTK(3, \"rx tasklet scheduled for device %d\\n\", fore200e->atm_dev->number);\n-\n- spin_lock_irqsave(&fore200e->q_lock, flags);\n- fore200e_rx_irq((struct fore200e*) data);\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-}\n-#endif\n-\n-\n-static int\n-fore200e_select_scheme(struct atm_vcc* vcc)\n-{\n- /* fairly balance the VCs over (identical) buffer schemes */\n- int scheme = vcc->vci % 2 ? BUFFER_SCHEME_ONE : BUFFER_SCHEME_TWO;\n-\n- DPRINTK(1, \"VC %d.%d.%d uses buffer scheme %d\\n\",\n-\t vcc->itf, vcc->vpi, vcc->vci, scheme);\n-\n- return scheme;\n-}\n-\n-\n-static int \n-fore200e_activate_vcin(struct fore200e* fore200e, int activate, struct atm_vcc* vcc, int mtu)\n-{\n- struct host_cmdq* cmdq = &fore200e->host_cmdq;\n- struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ];\n- struct activate_opcode activ_opcode;\n- struct deactivate_opcode deactiv_opcode;\n- struct vpvc vpvc;\n- int ok;\n- enum fore200e_aal aal = fore200e_atm2fore_aal(vcc->qos.aal);\n-\n- FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD);\n- \n- if (activate) {\n-\tFORE200E_VCC(vcc)->scheme = fore200e_select_scheme(vcc);\n-\t\n-\tactiv_opcode.opcode = OPCODE_ACTIVATE_VCIN;\n-\tactiv_opcode.aal = aal;\n-\tactiv_opcode.scheme = FORE200E_VCC(vcc)->scheme;\n-\tactiv_opcode.pad = 0;\n- }\n- else {\n-\tdeactiv_opcode.opcode = OPCODE_DEACTIVATE_VCIN;\n-\tdeactiv_opcode.pad = 0;\n- }\n-\n- vpvc.vci = vcc->vci;\n- vpvc.vpi = vcc->vpi;\n-\n- *entry->status = STATUS_PENDING;\n-\n- if (activate) {\n-\n-#ifdef FORE200E_52BYTE_AAL0_SDU\n-\tmtu = 48;\n-#endif\n-\t/* the MTU is not used by the cp, except in the case of AAL0 */\n-\tfore200e->bus->write(mtu, &entry->cp_entry->cmd.activate_block.mtu);\n-\tfore200e->bus->write(*(u32*)&vpvc, (u32 __iomem *)&entry->cp_entry->cmd.activate_block.vpvc);\n-\tfore200e->bus->write(*(u32*)&activ_opcode, (u32 __iomem *)&entry->cp_entry->cmd.activate_block.opcode);\n- }\n- else {\n-\tfore200e->bus->write(*(u32*)&vpvc, (u32 __iomem *)&entry->cp_entry->cmd.deactivate_block.vpvc);\n-\tfore200e->bus->write(*(u32*)&deactiv_opcode, (u32 __iomem *)&entry->cp_entry->cmd.deactivate_block.opcode);\n- }\n-\n- ok = fore200e_poll(fore200e, entry->status, STATUS_COMPLETE, 400);\n-\n- *entry->status = STATUS_FREE;\n-\n- if (ok == 0) {\n-\tprintk(FORE200E \"unable to %s VC %d.%d.%d\\n\",\n-\t activate ? \"open\" : \"close\", vcc->itf, vcc->vpi, vcc->vci);\n-\treturn -EIO;\n- }\n-\n- DPRINTK(1, \"VC %d.%d.%d %sed\\n\", vcc->itf, vcc->vpi, vcc->vci, \n-\t activate ? \"open\" : \"clos\");\n-\n- return 0;\n-}\n-\n-\n-#define FORE200E_MAX_BACK2BACK_CELLS 255 /* XXX depends on CDVT */\n-\n-static void\n-fore200e_rate_ctrl(struct atm_qos* qos, struct tpd_rate* rate)\n-{\n- if (qos->txtp.max_pcr < ATM_OC3_PCR) {\n- \n-\t/* compute the data cells to idle cells ratio from the tx PCR */\n-\trate->data_cells = qos->txtp.max_pcr * FORE200E_MAX_BACK2BACK_CELLS / ATM_OC3_PCR;\n-\trate->idle_cells = FORE200E_MAX_BACK2BACK_CELLS - rate->data_cells;\n- }\n- else {\n-\t/* disable rate control */\n-\trate->data_cells = rate->idle_cells = 0;\n- }\n-}\n-\n-\n-static int\n-fore200e_open(struct atm_vcc *vcc)\n-{\n- struct fore200e* fore200e = FORE200E_DEV(vcc->dev);\n- struct fore200e_vcc* fore200e_vcc;\n- struct fore200e_vc_map* vc_map;\n- unsigned long\t flags;\n- int\t\t\t vci = vcc->vci;\n- short\t\t vpi = vcc->vpi;\n-\n- ASSERT((vpi >= 0) && (vpi < 1<= 0) && (vci < 1<q_lock, flags);\n-\n- vc_map = FORE200E_VC_MAP(fore200e, vpi, vci);\n- if (vc_map->vcc) {\n-\n-\tspin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\n-\tprintk(FORE200E \"VC %d.%d.%d already in use\\n\",\n-\t fore200e->atm_dev->number, vpi, vci);\n-\n-\treturn -EINVAL;\n- }\n-\n- vc_map->vcc = vcc;\n-\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\n- fore200e_vcc = kzalloc_obj(struct fore200e_vcc, GFP_ATOMIC);\n- if (fore200e_vcc == NULL) {\n-\tvc_map->vcc = NULL;\n-\treturn -ENOMEM;\n- }\n-\n- DPRINTK(2, \"opening %d.%d.%d:%d QoS = (tx: cl=%s, pcr=%d-%d, cdv=%d, max_sdu=%d; \"\n-\t \"rx: cl=%s, pcr=%d-%d, cdv=%d, max_sdu=%d)\\n\",\n-\t vcc->itf, vcc->vpi, vcc->vci, fore200e_atm2fore_aal(vcc->qos.aal),\n-\t fore200e_traffic_class[ vcc->qos.txtp.traffic_class ],\n-\t vcc->qos.txtp.min_pcr, vcc->qos.txtp.max_pcr, vcc->qos.txtp.max_cdv, vcc->qos.txtp.max_sdu,\n-\t fore200e_traffic_class[ vcc->qos.rxtp.traffic_class ],\n-\t vcc->qos.rxtp.min_pcr, vcc->qos.rxtp.max_pcr, vcc->qos.rxtp.max_cdv, vcc->qos.rxtp.max_sdu);\n- \n- /* pseudo-CBR bandwidth requested? */\n- if ((vcc->qos.txtp.traffic_class == ATM_CBR) && (vcc->qos.txtp.max_pcr > 0)) {\n-\t\n-\tmutex_lock(&fore200e->rate_mtx);\n-\tif (fore200e->available_cell_rate < vcc->qos.txtp.max_pcr) {\n-\t mutex_unlock(&fore200e->rate_mtx);\n-\n-\t kfree(fore200e_vcc);\n-\t vc_map->vcc = NULL;\n-\t return -EAGAIN;\n-\t}\n-\n-\t/* reserve bandwidth */\n-\tfore200e->available_cell_rate -= vcc->qos.txtp.max_pcr;\n-\tmutex_unlock(&fore200e->rate_mtx);\n- }\n- \n- vcc->itf = vcc->dev->number;\n-\n- set_bit(ATM_VF_PARTIAL,&vcc->flags);\n- set_bit(ATM_VF_ADDR, &vcc->flags);\n-\n- vcc->dev_data = fore200e_vcc;\n- \n- if (fore200e_activate_vcin(fore200e, 1, vcc, vcc->qos.rxtp.max_sdu) < 0) {\n-\n-\tvc_map->vcc = NULL;\n-\n-\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\tclear_bit(ATM_VF_PARTIAL,&vcc->flags);\n-\n-\tvcc->dev_data = NULL;\n-\n-\tmutex_lock(&fore200e->rate_mtx);\n-\tfore200e->available_cell_rate += vcc->qos.txtp.max_pcr;\n-\tmutex_unlock(&fore200e->rate_mtx);\n-\n-\tkfree(fore200e_vcc);\n-\treturn -EINVAL;\n- }\n- \n- /* compute rate control parameters */\n- if ((vcc->qos.txtp.traffic_class == ATM_CBR) && (vcc->qos.txtp.max_pcr > 0)) {\n-\t\n-\tfore200e_rate_ctrl(&vcc->qos, &fore200e_vcc->rate);\n-\tset_bit(ATM_VF_HASQOS, &vcc->flags);\n-\n-\tDPRINTK(3, \"tx on %d.%d.%d:%d, tx PCR = %d, rx PCR = %d, data_cells = %u, idle_cells = %u\\n\",\n-\t\tvcc->itf, vcc->vpi, vcc->vci, fore200e_atm2fore_aal(vcc->qos.aal),\n-\t\tvcc->qos.txtp.max_pcr, vcc->qos.rxtp.max_pcr, \n-\t\tfore200e_vcc->rate.data_cells, fore200e_vcc->rate.idle_cells);\n- }\n- \n- fore200e_vcc->tx_min_pdu = fore200e_vcc->rx_min_pdu = MAX_PDU_SIZE + 1;\n- fore200e_vcc->tx_max_pdu = fore200e_vcc->rx_max_pdu = 0;\n- fore200e_vcc->tx_pdu = fore200e_vcc->rx_pdu = 0;\n-\n- /* new incarnation of the vcc */\n- vc_map->incarn = ++fore200e->incarn_count;\n-\n- /* VC unusable before this flag is set */\n- set_bit(ATM_VF_READY, &vcc->flags);\n-\n- return 0;\n-}\n-\n-\n-static void\n-fore200e_close(struct atm_vcc* vcc)\n-{\n- struct fore200e_vcc* fore200e_vcc;\n- struct fore200e* fore200e;\n- struct fore200e_vc_map* vc_map;\n- unsigned long flags;\n-\n- ASSERT(vcc);\n- fore200e = FORE200E_DEV(vcc->dev);\n-\n- ASSERT((vcc->vpi >= 0) && (vcc->vpi < 1<vci >= 0) && (vcc->vci < 1<itf, vcc->vpi, vcc->vci, fore200e_atm2fore_aal(vcc->qos.aal));\n-\n- clear_bit(ATM_VF_READY, &vcc->flags);\n-\n- fore200e_activate_vcin(fore200e, 0, vcc, 0);\n-\n- spin_lock_irqsave(&fore200e->q_lock, flags);\n-\n- vc_map = FORE200E_VC_MAP(fore200e, vcc->vpi, vcc->vci);\n-\n- /* the vc is no longer considered as \"in use\" by fore200e_open() */\n- vc_map->vcc = NULL;\n-\n- vcc->itf = vcc->vci = vcc->vpi = 0;\n-\n- fore200e_vcc = FORE200E_VCC(vcc);\n- vcc->dev_data = NULL;\n-\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\n- /* release reserved bandwidth, if any */\n- if ((vcc->qos.txtp.traffic_class == ATM_CBR) && (vcc->qos.txtp.max_pcr > 0)) {\n-\n-\tmutex_lock(&fore200e->rate_mtx);\n-\tfore200e->available_cell_rate += vcc->qos.txtp.max_pcr;\n-\tmutex_unlock(&fore200e->rate_mtx);\n-\n-\tclear_bit(ATM_VF_HASQOS, &vcc->flags);\n- }\n-\n- clear_bit(ATM_VF_ADDR, &vcc->flags);\n- clear_bit(ATM_VF_PARTIAL,&vcc->flags);\n-\n- ASSERT(fore200e_vcc);\n- kfree(fore200e_vcc);\n-}\n-\n-\n-static int\n-fore200e_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n- struct fore200e* fore200e;\n- struct fore200e_vcc* fore200e_vcc;\n- struct fore200e_vc_map* vc_map;\n- struct host_txq* txq;\n- struct host_txq_entry* entry;\n- struct tpd* tpd;\n- struct tpd_haddr tpd_haddr;\n- int retry = CONFIG_ATM_FORE200E_TX_RETRY;\n- int tx_copy = 0;\n- int tx_len = skb->len;\n- u32* cell_header = NULL;\n- unsigned char* skb_data;\n- int skb_len;\n- unsigned char* data;\n- unsigned long flags;\n-\n- if (!vcc)\n- return -EINVAL;\n-\n- fore200e = FORE200E_DEV(vcc->dev);\n- fore200e_vcc = FORE200E_VCC(vcc);\n-\n- if (!fore200e)\n- return -EINVAL;\n-\n- txq = &fore200e->host_txq;\n- if (!fore200e_vcc)\n- return -EINVAL;\n-\n- if (!test_bit(ATM_VF_READY, &vcc->flags)) {\n-\tDPRINTK(1, \"VC %d.%d.%d not ready for tx\\n\", vcc->itf, vcc->vpi, vcc->vpi);\n-\tdev_kfree_skb_any(skb);\n-\treturn -EINVAL;\n- }\n-\n-#ifdef FORE200E_52BYTE_AAL0_SDU\n- if ((vcc->qos.aal == ATM_AAL0) && (vcc->qos.txtp.max_sdu == ATM_AAL0_SDU)) {\n-\tcell_header = (u32*) skb->data;\n-\tskb_data = skb->data + 4; /* skip 4-byte cell header */\n-\tskb_len = tx_len = skb->len - 4;\n-\n-\tDPRINTK(3, \"user-supplied cell header = 0x%08x\\n\", *cell_header);\n- }\n- else \n-#endif\n- {\n-\tskb_data = skb->data;\n-\tskb_len = skb->len;\n- }\n- \n- if (((unsigned long)skb_data) & 0x3) {\n-\n-\tDPRINTK(2, \"misaligned tx PDU on device %s\\n\", fore200e->name);\n-\ttx_copy = 1;\n-\ttx_len = skb_len;\n- }\n-\n- if ((vcc->qos.aal == ATM_AAL0) && (skb_len % ATM_CELL_PAYLOAD)) {\n-\n- /* this simply NUKES the PCA board */\n-\tDPRINTK(2, \"incomplete tx AAL0 PDU on device %s\\n\", fore200e->name);\n-\ttx_copy = 1;\n-\ttx_len = ((skb_len / ATM_CELL_PAYLOAD) + 1) * ATM_CELL_PAYLOAD;\n- }\n- \n- if (tx_copy) {\n-\tdata = kmalloc(tx_len, GFP_ATOMIC);\n-\tif (data == NULL) {\n-\t if (vcc->pop) {\n-\t\tvcc->pop(vcc, skb);\n-\t }\n-\t else {\n-\t\tdev_kfree_skb_any(skb);\n-\t }\n-\t return -ENOMEM;\n-\t}\n-\n-\tmemcpy(data, skb_data, skb_len);\n-\tif (skb_len < tx_len)\n-\t memset(data + skb_len, 0x00, tx_len - skb_len);\n- }\n- else {\n-\tdata = skb_data;\n- }\n-\n- vc_map = FORE200E_VC_MAP(fore200e, vcc->vpi, vcc->vci);\n- ASSERT(vc_map->vcc == vcc);\n-\n- retry_here:\n-\n- spin_lock_irqsave(&fore200e->q_lock, flags);\n-\n- entry = &txq->host_entry[ txq->head ];\n-\n- if ((*entry->status != STATUS_FREE) || (txq->txing >= QUEUE_SIZE_TX - 2)) {\n-\n-\t/* try to free completed tx queue entries */\n-\tfore200e_tx_irq(fore200e);\n-\n-\tif (*entry->status != STATUS_FREE) {\n-\n-\t spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\n-\t /* retry once again? */\n-\t if (--retry > 0) {\n-\t\tudelay(50);\n-\t\tgoto retry_here;\n-\t }\n-\n-\t atomic_inc(&vcc->stats->tx_err);\n-\n-\t fore200e->tx_sat++;\n-\t DPRINTK(2, \"tx queue of device %s is saturated, PDU dropped - heartbeat is %08x\\n\",\n-\t\t fore200e->name, fore200e->cp_queues->heartbeat);\n-\t if (vcc->pop) {\n-\t\tvcc->pop(vcc, skb);\n-\t }\n-\t else {\n-\t\tdev_kfree_skb_any(skb);\n-\t }\n-\n-\t if (tx_copy)\n-\t\tkfree(data);\n-\n-\t return -ENOBUFS;\n-\t}\n- }\n-\n- entry->incarn = vc_map->incarn;\n- entry->vc_map = vc_map;\n- entry->skb = skb;\n- entry->data = tx_copy ? data : NULL;\n-\n- tpd = entry->tpd;\n- tpd->tsd[ 0 ].buffer = dma_map_single(fore200e->dev, data, tx_len,\n-\t\t\t\t\t DMA_TO_DEVICE);\n- if (dma_mapping_error(fore200e->dev, tpd->tsd[0].buffer)) {\n-\tif (tx_copy)\n-\t kfree(data);\n-\tspin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\treturn -ENOMEM;\n- }\n- tpd->tsd[ 0 ].length = tx_len;\n-\n- FORE200E_NEXT_ENTRY(txq->head, QUEUE_SIZE_TX);\n- txq->txing++;\n-\n- /* The dma_map call above implies a dma_sync so the device can use it,\n- * thus no explicit dma_sync call is necessary here.\n- */\n- \n- DPRINTK(3, \"tx on %d.%d.%d:%d, len = %u (%u)\\n\", \n-\t vcc->itf, vcc->vpi, vcc->vci, fore200e_atm2fore_aal(vcc->qos.aal),\n-\t tpd->tsd[0].length, skb_len);\n-\n- if (skb_len < fore200e_vcc->tx_min_pdu)\n-\tfore200e_vcc->tx_min_pdu = skb_len;\n- if (skb_len > fore200e_vcc->tx_max_pdu)\n-\tfore200e_vcc->tx_max_pdu = skb_len;\n- fore200e_vcc->tx_pdu++;\n-\n- /* set tx rate control information */\n- tpd->rate.data_cells = fore200e_vcc->rate.data_cells;\n- tpd->rate.idle_cells = fore200e_vcc->rate.idle_cells;\n-\n- if (cell_header) {\n-\ttpd->atm_header.clp = (*cell_header & ATM_HDR_CLP);\n-\ttpd->atm_header.plt = (*cell_header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;\n-\ttpd->atm_header.vci = (*cell_header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;\n-\ttpd->atm_header.vpi = (*cell_header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;\n-\ttpd->atm_header.gfc = (*cell_header & ATM_HDR_GFC_MASK) >> ATM_HDR_GFC_SHIFT;\n- }\n- else {\n-\t/* set the ATM header, common to all cells conveying the PDU */\n-\ttpd->atm_header.clp = 0;\n-\ttpd->atm_header.plt = 0;\n-\ttpd->atm_header.vci = vcc->vci;\n-\ttpd->atm_header.vpi = vcc->vpi;\n-\ttpd->atm_header.gfc = 0;\n- }\n-\n- tpd->spec.length = tx_len;\n- tpd->spec.nseg = 1;\n- tpd->spec.aal = fore200e_atm2fore_aal(vcc->qos.aal);\n- tpd->spec.intr = 1;\n-\n- tpd_haddr.size = sizeof(struct tpd) / (1<tpd_dma >> TPD_HADDR_SHIFT; /* shift the address, as we are in a bitfield */\n-\n- *entry->status = STATUS_PENDING;\n- fore200e->bus->write(*(u32*)&tpd_haddr, (u32 __iomem *)&entry->cp_entry->tpd_haddr);\n-\n- spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\n- return 0;\n-}\n-\n-\n-static int\n-fore200e_getstats(struct fore200e* fore200e)\n-{\n- struct host_cmdq* cmdq = &fore200e->host_cmdq;\n- struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ];\n- struct stats_opcode opcode;\n- int ok;\n- u32 stats_dma_addr;\n-\n- if (fore200e->stats == NULL) {\n-\tfore200e->stats = kzalloc_obj(struct stats);\n-\tif (fore200e->stats == NULL)\n-\t return -ENOMEM;\n- }\n- \n- stats_dma_addr = dma_map_single(fore200e->dev, fore200e->stats,\n-\t\t\t\t sizeof(struct stats), DMA_FROM_DEVICE);\n- if (dma_mapping_error(fore200e->dev, stats_dma_addr))\n- \treturn -ENOMEM;\n- \n- FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD);\n-\n- opcode.opcode = OPCODE_GET_STATS;\n- opcode.pad = 0;\n-\n- fore200e->bus->write(stats_dma_addr, &entry->cp_entry->cmd.stats_block.stats_haddr);\n- \n- *entry->status = STATUS_PENDING;\n-\n- fore200e->bus->write(*(u32*)&opcode, (u32 __iomem *)&entry->cp_entry->cmd.stats_block.opcode);\n-\n- ok = fore200e_poll(fore200e, entry->status, STATUS_COMPLETE, 400);\n-\n- *entry->status = STATUS_FREE;\n-\n- dma_unmap_single(fore200e->dev, stats_dma_addr, sizeof(struct stats), DMA_FROM_DEVICE);\n- \n- if (ok == 0) {\n-\tprintk(FORE200E \"unable to get statistics from device %s\\n\", fore200e->name);\n-\treturn -EIO;\n- }\n-\n- return 0;\n-}\n-\n-#if 0 /* currently unused */\n-static int\n-fore200e_get_oc3(struct fore200e* fore200e, struct oc3_regs* regs)\n-{\n- struct host_cmdq* cmdq = &fore200e->host_cmdq;\n- struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ];\n- struct oc3_opcode opcode;\n- int ok;\n- u32 oc3_regs_dma_addr;\n-\n- oc3_regs_dma_addr = fore200e->bus->dma_map(fore200e, regs, sizeof(struct oc3_regs), DMA_FROM_DEVICE);\n-\n- FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD);\n-\n- opcode.opcode = OPCODE_GET_OC3;\n- opcode.reg = 0;\n- opcode.value = 0;\n- opcode.mask = 0;\n-\n- fore200e->bus->write(oc3_regs_dma_addr, &entry->cp_entry->cmd.oc3_block.regs_haddr);\n- \n- *entry->status = STATUS_PENDING;\n-\n- fore200e->bus->write(*(u32*)&opcode, (u32*)&entry->cp_entry->cmd.oc3_block.opcode);\n-\n- ok = fore200e_poll(fore200e, entry->status, STATUS_COMPLETE, 400);\n-\n- *entry->status = STATUS_FREE;\n-\n- fore200e->bus->dma_unmap(fore200e, oc3_regs_dma_addr, sizeof(struct oc3_regs), DMA_FROM_DEVICE);\n- \n- if (ok == 0) {\n-\tprintk(FORE200E \"unable to get OC-3 regs of device %s\\n\", fore200e->name);\n-\treturn -EIO;\n- }\n-\n- return 0;\n-}\n-#endif\n-\n-\n-static int\n-fore200e_set_oc3(struct fore200e* fore200e, u32 reg, u32 value, u32 mask)\n-{\n- struct host_cmdq* cmdq = &fore200e->host_cmdq;\n- struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ];\n- struct oc3_opcode opcode;\n- int ok;\n-\n- DPRINTK(2, \"set OC-3 reg = 0x%02x, value = 0x%02x, mask = 0x%02x\\n\", reg, value, mask);\n-\n- FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD);\n-\n- opcode.opcode = OPCODE_SET_OC3;\n- opcode.reg = reg;\n- opcode.value = value;\n- opcode.mask = mask;\n-\n- fore200e->bus->write(0, &entry->cp_entry->cmd.oc3_block.regs_haddr);\n- \n- *entry->status = STATUS_PENDING;\n-\n- fore200e->bus->write(*(u32*)&opcode, (u32 __iomem *)&entry->cp_entry->cmd.oc3_block.opcode);\n-\n- ok = fore200e_poll(fore200e, entry->status, STATUS_COMPLETE, 400);\n-\n- *entry->status = STATUS_FREE;\n-\n- if (ok == 0) {\n-\tprintk(FORE200E \"unable to set OC-3 reg 0x%02x of device %s\\n\", reg, fore200e->name);\n-\treturn -EIO;\n- }\n-\n- return 0;\n-}\n-\n-\n-static int\n-fore200e_setloop(struct fore200e* fore200e, int loop_mode)\n-{\n- u32 mct_value, mct_mask;\n- int error;\n-\n- if (!capable(CAP_NET_ADMIN))\n-\treturn -EPERM;\n- \n- switch (loop_mode) {\n-\n- case ATM_LM_NONE:\n-\tmct_value = 0; \n-\tmct_mask = SUNI_MCT_DLE | SUNI_MCT_LLE;\n-\tbreak;\n-\t\n- case ATM_LM_LOC_PHY:\n-\tmct_value = mct_mask = SUNI_MCT_DLE;\n-\tbreak;\n-\n- case ATM_LM_RMT_PHY:\n-\tmct_value = mct_mask = SUNI_MCT_LLE;\n-\tbreak;\n-\n- default:\n-\treturn -EINVAL;\n- }\n-\n- error = fore200e_set_oc3(fore200e, SUNI_MCT, mct_value, mct_mask);\n- if (error == 0)\n-\tfore200e->loop_mode = loop_mode;\n-\n- return error;\n-}\n-\n-\n-static int\n-fore200e_fetch_stats(struct fore200e* fore200e, struct sonet_stats __user *arg)\n-{\n- struct sonet_stats tmp;\n-\n- if (fore200e_getstats(fore200e) < 0)\n-\treturn -EIO;\n-\n- tmp.section_bip = be32_to_cpu(fore200e->stats->oc3.section_bip8_errors);\n- tmp.line_bip = be32_to_cpu(fore200e->stats->oc3.line_bip24_errors);\n- tmp.path_bip = be32_to_cpu(fore200e->stats->oc3.path_bip8_errors);\n- tmp.line_febe = be32_to_cpu(fore200e->stats->oc3.line_febe_errors);\n- tmp.path_febe = be32_to_cpu(fore200e->stats->oc3.path_febe_errors);\n- tmp.corr_hcs = be32_to_cpu(fore200e->stats->oc3.corr_hcs_errors);\n- tmp.uncorr_hcs = be32_to_cpu(fore200e->stats->oc3.ucorr_hcs_errors);\n- tmp.tx_cells = be32_to_cpu(fore200e->stats->aal0.cells_transmitted) +\n-\t be32_to_cpu(fore200e->stats->aal34.cells_transmitted) +\n-\t be32_to_cpu(fore200e->stats->aal5.cells_transmitted);\n- tmp.rx_cells = be32_to_cpu(fore200e->stats->aal0.cells_received) +\n-\t be32_to_cpu(fore200e->stats->aal34.cells_received) +\n-\t be32_to_cpu(fore200e->stats->aal5.cells_received);\n-\n- if (arg)\n-\treturn copy_to_user(arg, &tmp, sizeof(struct sonet_stats)) ? -EFAULT : 0;\t\n- \n- return 0;\n-}\n-\n-\n-static int\n-fore200e_ioctl(struct atm_dev* dev, unsigned int cmd, void __user * arg)\n-{\n- struct fore200e* fore200e = FORE200E_DEV(dev);\n- \n- DPRINTK(2, \"ioctl cmd = 0x%x (%u), arg = 0x%p (%lu)\\n\", cmd, cmd, arg, (unsigned long)arg);\n-\n- switch (cmd) {\n-\n- case SONET_GETSTAT:\n-\treturn fore200e_fetch_stats(fore200e, (struct sonet_stats __user *)arg);\n-\n- case SONET_GETDIAG:\n-\treturn put_user(0, (int __user *)arg) ? -EFAULT : 0;\n-\n- case ATM_SETLOOP:\n-\treturn fore200e_setloop(fore200e, (int)(unsigned long)arg);\n-\n- case ATM_GETLOOP:\n-\treturn put_user(fore200e->loop_mode, (int __user *)arg) ? -EFAULT : 0;\n-\n- case ATM_QUERYLOOP:\n-\treturn put_user(ATM_LM_LOC_PHY | ATM_LM_RMT_PHY, (int __user *)arg) ? -EFAULT : 0;\n- }\n-\n- return -ENOSYS; /* not implemented */\n-}\n-\n-\n-static int\n-fore200e_change_qos(struct atm_vcc* vcc,struct atm_qos* qos, int flags)\n-{\n- struct fore200e_vcc* fore200e_vcc = FORE200E_VCC(vcc);\n- struct fore200e* fore200e = FORE200E_DEV(vcc->dev);\n-\n- if (!test_bit(ATM_VF_READY, &vcc->flags)) {\n-\tDPRINTK(1, \"VC %d.%d.%d not ready for QoS change\\n\", vcc->itf, vcc->vpi, vcc->vpi);\n-\treturn -EINVAL;\n- }\n-\n- DPRINTK(2, \"change_qos %d.%d.%d, \"\n-\t \"(tx: cl=%s, pcr=%d-%d, cdv=%d, max_sdu=%d; \"\n-\t \"rx: cl=%s, pcr=%d-%d, cdv=%d, max_sdu=%d), flags = 0x%x\\n\"\n-\t \"available_cell_rate = %u\",\n-\t vcc->itf, vcc->vpi, vcc->vci,\n-\t fore200e_traffic_class[ qos->txtp.traffic_class ],\n-\t qos->txtp.min_pcr, qos->txtp.max_pcr, qos->txtp.max_cdv, qos->txtp.max_sdu,\n-\t fore200e_traffic_class[ qos->rxtp.traffic_class ],\n-\t qos->rxtp.min_pcr, qos->rxtp.max_pcr, qos->rxtp.max_cdv, qos->rxtp.max_sdu,\n-\t flags, fore200e->available_cell_rate);\n-\n- if ((qos->txtp.traffic_class == ATM_CBR) && (qos->txtp.max_pcr > 0)) {\n-\n-\tmutex_lock(&fore200e->rate_mtx);\n-\tif (fore200e->available_cell_rate + vcc->qos.txtp.max_pcr < qos->txtp.max_pcr) {\n-\t mutex_unlock(&fore200e->rate_mtx);\n-\t return -EAGAIN;\n-\t}\n-\n-\tfore200e->available_cell_rate += vcc->qos.txtp.max_pcr;\n-\tfore200e->available_cell_rate -= qos->txtp.max_pcr;\n-\n-\tmutex_unlock(&fore200e->rate_mtx);\n-\t\n-\tmemcpy(&vcc->qos, qos, sizeof(struct atm_qos));\n-\t\n-\t/* update rate control parameters */\n-\tfore200e_rate_ctrl(qos, &fore200e_vcc->rate);\n-\n-\tset_bit(ATM_VF_HASQOS, &vcc->flags);\n-\n-\treturn 0;\n- }\n- \n- return -EINVAL;\n-}\n- \n-\n-static int fore200e_irq_request(struct fore200e *fore200e)\n-{\n- if (request_irq(fore200e->irq, fore200e_interrupt, IRQF_SHARED, fore200e->name, fore200e->atm_dev) < 0) {\n-\n-\tprintk(FORE200E \"unable to reserve IRQ %s for device %s\\n\",\n-\t fore200e_irq_itoa(fore200e->irq), fore200e->name);\n-\treturn -EBUSY;\n- }\n-\n- printk(FORE200E \"IRQ %s reserved for device %s\\n\",\n-\t fore200e_irq_itoa(fore200e->irq), fore200e->name);\n-\n-#ifdef FORE200E_USE_TASKLET\n- tasklet_init(&fore200e->tx_tasklet, fore200e_tx_tasklet, (unsigned long)fore200e);\n- tasklet_init(&fore200e->rx_tasklet, fore200e_rx_tasklet, (unsigned long)fore200e);\n-#endif\n-\n- fore200e->state = FORE200E_STATE_IRQ;\n- return 0;\n-}\n-\n-\n-static int fore200e_get_esi(struct fore200e *fore200e)\n-{\n- struct prom_data* prom = kzalloc_obj(struct prom_data);\n- int ok, i;\n-\n- if (!prom)\n-\treturn -ENOMEM;\n-\n- ok = fore200e->bus->prom_read(fore200e, prom);\n- if (ok < 0) {\n-\tkfree(prom);\n-\treturn -EBUSY;\n- }\n-\t\n- printk(FORE200E \"device %s, rev. %c, S/N: %d, ESI: %pM\\n\",\n-\t fore200e->name, \n-\t (prom->hw_revision & 0xFF) + '@', /* probably meaningless with SBA boards */\n-\t prom->serial_number & 0xFFFF, &prom->mac_addr[2]);\n-\t\n- for (i = 0; i < ESI_LEN; i++) {\n-\tfore200e->esi[ i ] = fore200e->atm_dev->esi[ i ] = prom->mac_addr[ i + 2 ];\n- }\n- \n- kfree(prom);\n-\n- return 0;\n-}\n-\n-\n-static int fore200e_alloc_rx_buf(struct fore200e *fore200e)\n-{\n- int scheme, magn, nbr, size, i;\n-\n- struct host_bsq* bsq;\n- struct buffer* buffer;\n-\n- for (scheme = 0; scheme < BUFFER_SCHEME_NBR; scheme++) {\n-\tfor (magn = 0; magn < BUFFER_MAGN_NBR; magn++) {\n-\n-\t bsq = &fore200e->host_bsq[ scheme ][ magn ];\n-\n-\t nbr = fore200e_rx_buf_nbr[ scheme ][ magn ];\n-\t size = fore200e_rx_buf_size[ scheme ][ magn ];\n-\n-\t DPRINTK(2, \"rx buffers %d / %d are being allocated\\n\", scheme, magn);\n-\n-\t /* allocate the array of receive buffers */\n-\t buffer = bsq->buffer = kzalloc_objs(struct buffer, nbr);\n-\n-\t if (buffer == NULL)\n-\t\treturn -ENOMEM;\n-\n-\t bsq->freebuf = NULL;\n-\n-\t for (i = 0; i < nbr; i++) {\n-\n-\t\tbuffer[ i ].scheme = scheme;\n-\t\tbuffer[ i ].magn = magn;\n-#ifdef FORE200E_BSQ_DEBUG\n-\t\tbuffer[ i ].index = i;\n-\t\tbuffer[ i ].supplied = 0;\n-#endif\n-\n-\t\t/* allocate the receive buffer body */\n-\t\tif (fore200e_chunk_alloc(fore200e,\n-\t\t\t\t\t &buffer[ i ].data, size, fore200e->bus->buffer_alignment,\n-\t\t\t\t\t DMA_FROM_DEVICE) < 0) {\n-\t\t \n-\t\t while (i > 0)\n-\t\t\tfore200e_chunk_free(fore200e, &buffer[ --i ].data);\n-\t\t kfree(buffer);\n-\t\t \n-\t\t return -ENOMEM;\n-\t\t}\n-\n-\t\t/* insert the buffer into the free buffer list */\n-\t\tbuffer[ i ].next = bsq->freebuf;\n-\t\tbsq->freebuf = &buffer[ i ];\n-\t }\n-\t /* all the buffers are free, initially */\n-\t bsq->freebuf_count = nbr;\n-\n-#ifdef FORE200E_BSQ_DEBUG\n-\t bsq_audit(3, bsq, scheme, magn);\n-#endif\n-\t}\n- }\n-\n- fore200e->state = FORE200E_STATE_ALLOC_BUF;\n- return 0;\n-}\n-\n-\n-static int fore200e_init_bs_queue(struct fore200e *fore200e)\n-{\n- int scheme, magn, i;\n-\n- struct host_bsq* bsq;\n- struct cp_bsq_entry __iomem * cp_entry;\n-\n- for (scheme = 0; scheme < BUFFER_SCHEME_NBR; scheme++) {\n-\tfor (magn = 0; magn < BUFFER_MAGN_NBR; magn++) {\n-\n-\t DPRINTK(2, \"buffer supply queue %d / %d is being initialized\\n\", scheme, magn);\n-\n-\t bsq = &fore200e->host_bsq[ scheme ][ magn ];\n-\n-\t /* allocate and align the array of status words */\n-\t if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t\t &bsq->status,\n-\t\t\t\t\t sizeof(enum status), \n-\t\t\t\t\t QUEUE_SIZE_BS,\n-\t\t\t\t\t fore200e->bus->status_alignment) < 0) {\n-\t\treturn -ENOMEM;\n-\t }\n-\n-\t /* allocate and align the array of receive buffer descriptors */\n-\t if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t\t &bsq->rbd_block,\n-\t\t\t\t\t sizeof(struct rbd_block),\n-\t\t\t\t\t QUEUE_SIZE_BS,\n-\t\t\t\t\t fore200e->bus->descr_alignment) < 0) {\n-\t\t\n-\t\tfore200e_dma_chunk_free(fore200e, &bsq->status);\n-\t\treturn -ENOMEM;\n-\t }\n-\t \n-\t /* get the base address of the cp resident buffer supply queue entries */\n-\t cp_entry = fore200e->virt_base + \n-\t\t fore200e->bus->read(&fore200e->cp_queues->cp_bsq[ scheme ][ magn ]);\n-\t \n-\t /* fill the host resident and cp resident buffer supply queue entries */\n-\t for (i = 0; i < QUEUE_SIZE_BS; i++) {\n-\t\t\n-\t\tbsq->host_entry[ i ].status = \n-\t\t FORE200E_INDEX(bsq->status.align_addr, enum status, i);\n-\t bsq->host_entry[ i ].rbd_block =\n-\t\t FORE200E_INDEX(bsq->rbd_block.align_addr, struct rbd_block, i);\n-\t\tbsq->host_entry[ i ].rbd_block_dma =\n-\t\t FORE200E_DMA_INDEX(bsq->rbd_block.dma_addr, struct rbd_block, i);\n-\t\tbsq->host_entry[ i ].cp_entry = &cp_entry[ i ];\n-\t\t\n-\t\t*bsq->host_entry[ i ].status = STATUS_FREE;\n-\t\t\n-\t\tfore200e->bus->write(FORE200E_DMA_INDEX(bsq->status.dma_addr, enum status, i), \n-\t\t\t\t &cp_entry[ i ].status_haddr);\n-\t }\n-\t}\n- }\n-\n- fore200e->state = FORE200E_STATE_INIT_BSQ;\n- return 0;\n-}\n-\n-\n-static int fore200e_init_rx_queue(struct fore200e *fore200e)\n-{\n- struct host_rxq* rxq = &fore200e->host_rxq;\n- struct cp_rxq_entry __iomem * cp_entry;\n- int i;\n-\n- DPRINTK(2, \"receive queue is being initialized\\n\");\n-\n- /* allocate and align the array of status words */\n- if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t &rxq->status,\n-\t\t\t\t sizeof(enum status), \n-\t\t\t\t QUEUE_SIZE_RX,\n-\t\t\t\t fore200e->bus->status_alignment) < 0) {\n-\treturn -ENOMEM;\n- }\n-\n- /* allocate and align the array of receive PDU descriptors */\n- if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t &rxq->rpd,\n-\t\t\t\t sizeof(struct rpd), \n-\t\t\t\t QUEUE_SIZE_RX,\n-\t\t\t\t fore200e->bus->descr_alignment) < 0) {\n-\t\n-\tfore200e_dma_chunk_free(fore200e, &rxq->status);\n-\treturn -ENOMEM;\n- }\n-\n- /* get the base address of the cp resident rx queue entries */\n- cp_entry = fore200e->virt_base + fore200e->bus->read(&fore200e->cp_queues->cp_rxq);\n-\n- /* fill the host resident and cp resident rx entries */\n- for (i=0; i < QUEUE_SIZE_RX; i++) {\n-\t\n-\trxq->host_entry[ i ].status = \n-\t FORE200E_INDEX(rxq->status.align_addr, enum status, i);\n-\trxq->host_entry[ i ].rpd = \n-\t FORE200E_INDEX(rxq->rpd.align_addr, struct rpd, i);\n-\trxq->host_entry[ i ].rpd_dma = \n-\t FORE200E_DMA_INDEX(rxq->rpd.dma_addr, struct rpd, i);\n-\trxq->host_entry[ i ].cp_entry = &cp_entry[ i ];\n-\n-\t*rxq->host_entry[ i ].status = STATUS_FREE;\n-\n-\tfore200e->bus->write(FORE200E_DMA_INDEX(rxq->status.dma_addr, enum status, i), \n-\t\t\t &cp_entry[ i ].status_haddr);\n-\n-\tfore200e->bus->write(FORE200E_DMA_INDEX(rxq->rpd.dma_addr, struct rpd, i),\n-\t\t\t &cp_entry[ i ].rpd_haddr);\n- }\n-\n- /* set the head entry of the queue */\n- rxq->head = 0;\n-\n- fore200e->state = FORE200E_STATE_INIT_RXQ;\n- return 0;\n-}\n-\n-\n-static int fore200e_init_tx_queue(struct fore200e *fore200e)\n-{\n- struct host_txq* txq = &fore200e->host_txq;\n- struct cp_txq_entry __iomem * cp_entry;\n- int i;\n-\n- DPRINTK(2, \"transmit queue is being initialized\\n\");\n-\n- /* allocate and align the array of status words */\n- if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t &txq->status,\n-\t\t\t\t sizeof(enum status), \n-\t\t\t\t QUEUE_SIZE_TX,\n-\t\t\t\t fore200e->bus->status_alignment) < 0) {\n-\treturn -ENOMEM;\n- }\n-\n- /* allocate and align the array of transmit PDU descriptors */\n- if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t &txq->tpd,\n-\t\t\t\t sizeof(struct tpd), \n-\t\t\t\t QUEUE_SIZE_TX,\n-\t\t\t\t fore200e->bus->descr_alignment) < 0) {\n-\t\n-\tfore200e_dma_chunk_free(fore200e, &txq->status);\n-\treturn -ENOMEM;\n- }\n-\n- /* get the base address of the cp resident tx queue entries */\n- cp_entry = fore200e->virt_base + fore200e->bus->read(&fore200e->cp_queues->cp_txq);\n-\n- /* fill the host resident and cp resident tx entries */\n- for (i=0; i < QUEUE_SIZE_TX; i++) {\n-\t\n-\ttxq->host_entry[ i ].status = \n-\t FORE200E_INDEX(txq->status.align_addr, enum status, i);\n-\ttxq->host_entry[ i ].tpd = \n-\t FORE200E_INDEX(txq->tpd.align_addr, struct tpd, i);\n-\ttxq->host_entry[ i ].tpd_dma = \n- FORE200E_DMA_INDEX(txq->tpd.dma_addr, struct tpd, i);\n-\ttxq->host_entry[ i ].cp_entry = &cp_entry[ i ];\n-\n-\t*txq->host_entry[ i ].status = STATUS_FREE;\n-\t\n-\tfore200e->bus->write(FORE200E_DMA_INDEX(txq->status.dma_addr, enum status, i), \n-\t\t\t &cp_entry[ i ].status_haddr);\n-\t\n- /* although there is a one-to-one mapping of tx queue entries and tpds,\n-\t we do not write here the DMA (physical) base address of each tpd into\n-\t the related cp resident entry, because the cp relies on this write\n-\t operation to detect that a new pdu has been submitted for tx */\n- }\n-\n- /* set the head and tail entries of the queue */\n- txq->head = 0;\n- txq->tail = 0;\n-\n- fore200e->state = FORE200E_STATE_INIT_TXQ;\n- return 0;\n-}\n-\n-\n-static int fore200e_init_cmd_queue(struct fore200e *fore200e)\n-{\n- struct host_cmdq* cmdq = &fore200e->host_cmdq;\n- struct cp_cmdq_entry __iomem * cp_entry;\n- int i;\n-\n- DPRINTK(2, \"command queue is being initialized\\n\");\n-\n- /* allocate and align the array of status words */\n- if (fore200e_dma_chunk_alloc(fore200e,\n-\t\t\t\t &cmdq->status,\n-\t\t\t\t sizeof(enum status), \n-\t\t\t\t QUEUE_SIZE_CMD,\n-\t\t\t\t fore200e->bus->status_alignment) < 0) {\n-\treturn -ENOMEM;\n- }\n- \n- /* get the base address of the cp resident cmd queue entries */\n- cp_entry = fore200e->virt_base + fore200e->bus->read(&fore200e->cp_queues->cp_cmdq);\n-\n- /* fill the host resident and cp resident cmd entries */\n- for (i=0; i < QUEUE_SIZE_CMD; i++) {\n-\t\n-\tcmdq->host_entry[ i ].status = \n- FORE200E_INDEX(cmdq->status.align_addr, enum status, i);\n-\tcmdq->host_entry[ i ].cp_entry = &cp_entry[ i ];\n-\n-\t*cmdq->host_entry[ i ].status = STATUS_FREE;\n-\n-\tfore200e->bus->write(FORE200E_DMA_INDEX(cmdq->status.dma_addr, enum status, i), \n- &cp_entry[ i ].status_haddr);\n- }\n-\n- /* set the head entry of the queue */\n- cmdq->head = 0;\n-\n- fore200e->state = FORE200E_STATE_INIT_CMDQ;\n- return 0;\n-}\n-\n-\n-static void fore200e_param_bs_queue(struct fore200e *fore200e,\n-\t\t\t\t enum buffer_scheme scheme,\n-\t\t\t\t enum buffer_magn magn, int queue_length,\n-\t\t\t\t int pool_size, int supply_blksize)\n-{\n- struct bs_spec __iomem * bs_spec = &fore200e->cp_queues->init.bs_spec[ scheme ][ magn ];\n-\n- fore200e->bus->write(queue_length, &bs_spec->queue_length);\n- fore200e->bus->write(fore200e_rx_buf_size[ scheme ][ magn ], &bs_spec->buffer_size);\n- fore200e->bus->write(pool_size, &bs_spec->pool_size);\n- fore200e->bus->write(supply_blksize, &bs_spec->supply_blksize);\n-}\n-\n-\n-static int fore200e_initialize(struct fore200e *fore200e)\n-{\n- struct cp_queues __iomem * cpq;\n- int ok, scheme, magn;\n-\n- DPRINTK(2, \"device %s being initialized\\n\", fore200e->name);\n-\n- mutex_init(&fore200e->rate_mtx);\n- spin_lock_init(&fore200e->q_lock);\n-\n- cpq = fore200e->cp_queues = fore200e->virt_base + FORE200E_CP_QUEUES_OFFSET;\n-\n- /* enable cp to host interrupts */\n- fore200e->bus->write(1, &cpq->imask);\n-\n- if (fore200e->bus->irq_enable)\n-\tfore200e->bus->irq_enable(fore200e);\n- \n- fore200e->bus->write(NBR_CONNECT, &cpq->init.num_connect);\n-\n- fore200e->bus->write(QUEUE_SIZE_CMD, &cpq->init.cmd_queue_len);\n- fore200e->bus->write(QUEUE_SIZE_RX, &cpq->init.rx_queue_len);\n- fore200e->bus->write(QUEUE_SIZE_TX, &cpq->init.tx_queue_len);\n-\n- fore200e->bus->write(RSD_EXTENSION, &cpq->init.rsd_extension);\n- fore200e->bus->write(TSD_EXTENSION, &cpq->init.tsd_extension);\n-\n- for (scheme = 0; scheme < BUFFER_SCHEME_NBR; scheme++)\n-\tfor (magn = 0; magn < BUFFER_MAGN_NBR; magn++)\n-\t fore200e_param_bs_queue(fore200e, scheme, magn,\n-\t\t\t\t QUEUE_SIZE_BS, \n-\t\t\t\t fore200e_rx_buf_nbr[ scheme ][ magn ],\n-\t\t\t\t RBD_BLK_SIZE);\n-\n- /* issue the initialize command */\n- fore200e->bus->write(STATUS_PENDING, &cpq->init.status);\n- fore200e->bus->write(OPCODE_INITIALIZE, &cpq->init.opcode);\n-\n- ok = fore200e_io_poll(fore200e, &cpq->init.status, STATUS_COMPLETE, 3000);\n- if (ok == 0) {\n-\tprintk(FORE200E \"device %s initialization failed\\n\", fore200e->name);\n-\treturn -ENODEV;\n- }\n-\n- printk(FORE200E \"device %s initialized\\n\", fore200e->name);\n-\n- fore200e->state = FORE200E_STATE_INITIALIZE;\n- return 0;\n-}\n-\n-\n-static void fore200e_monitor_putc(struct fore200e *fore200e, char c)\n-{\n- struct cp_monitor __iomem * monitor = fore200e->cp_monitor;\n-\n-#if 0\n- printk(\"%c\", c);\n-#endif\n- fore200e->bus->write(((u32) c) | FORE200E_CP_MONITOR_UART_AVAIL, &monitor->soft_uart.send);\n-}\n-\n-\n-static int fore200e_monitor_getc(struct fore200e *fore200e)\n-{\n- struct cp_monitor __iomem * monitor = fore200e->cp_monitor;\n- unsigned long timeout = jiffies + msecs_to_jiffies(50);\n- int c;\n-\n- while (time_before(jiffies, timeout)) {\n-\n-\tc = (int) fore200e->bus->read(&monitor->soft_uart.recv);\n-\n-\tif (c & FORE200E_CP_MONITOR_UART_AVAIL) {\n-\n-\t fore200e->bus->write(FORE200E_CP_MONITOR_UART_FREE, &monitor->soft_uart.recv);\n-#if 0\n-\t printk(\"%c\", c & 0xFF);\n-#endif\n-\t return c & 0xFF;\n-\t}\n- }\n-\n- return -1;\n-}\n-\n-\n-static void fore200e_monitor_puts(struct fore200e *fore200e, char *str)\n-{\n- while (*str) {\n-\n-\t/* the i960 monitor doesn't accept any new character if it has something to say */\n-\twhile (fore200e_monitor_getc(fore200e) >= 0);\n-\t\n-\tfore200e_monitor_putc(fore200e, *str++);\n- }\n-\n- while (fore200e_monitor_getc(fore200e) >= 0);\n-}\n-\n-#ifdef __LITTLE_ENDIAN\n-#define FW_EXT \".bin\"\n-#else\n-#define FW_EXT \"_ecd.bin2\"\n-#endif\n-\n-static int fore200e_load_and_start_fw(struct fore200e *fore200e)\n-{\n- const struct firmware *firmware;\n- const struct fw_header *fw_header;\n- const __le32 *fw_data;\n- u32 fw_size;\n- u32 __iomem *load_addr;\n- char buf[48];\n- int err;\n-\n- sprintf(buf, \"%s%s\", fore200e->bus->proc_name, FW_EXT);\n- if ((err = request_firmware(&firmware, buf, fore200e->dev)) < 0) {\n-\tprintk(FORE200E \"problem loading firmware image %s\\n\", fore200e->bus->model_name);\n-\treturn err;\n- }\n-\n- fw_data = (const __le32 *)firmware->data;\n- fw_size = firmware->size / sizeof(u32);\n- fw_header = (const struct fw_header *)firmware->data;\n- load_addr = fore200e->virt_base + le32_to_cpu(fw_header->load_offset);\n-\n- DPRINTK(2, \"device %s firmware being loaded at 0x%p (%d words)\\n\",\n-\t fore200e->name, load_addr, fw_size);\n-\n- if (le32_to_cpu(fw_header->magic) != FW_HEADER_MAGIC) {\n-\tprintk(FORE200E \"corrupted %s firmware image\\n\", fore200e->bus->model_name);\n-\tgoto release;\n- }\n-\n- for (; fw_size--; fw_data++, load_addr++)\n-\tfore200e->bus->write(le32_to_cpu(*fw_data), load_addr);\n-\n- DPRINTK(2, \"device %s firmware being started\\n\", fore200e->name);\n-\n-#if defined(__sparc_v9__)\n- /* reported to be required by SBA cards on some sparc64 hosts */\n- fore200e_spin(100);\n-#endif\n-\n- sprintf(buf, \"\\rgo %x\\r\", le32_to_cpu(fw_header->start_offset));\n- fore200e_monitor_puts(fore200e, buf);\n-\n- if (fore200e_io_poll(fore200e, &fore200e->cp_monitor->bstat, BSTAT_CP_RUNNING, 1000) == 0) {\n-\tprintk(FORE200E \"device %s firmware didn't start\\n\", fore200e->name);\n-\tgoto release;\n- }\n-\n- printk(FORE200E \"device %s firmware started\\n\", fore200e->name);\n-\n- fore200e->state = FORE200E_STATE_START_FW;\n- err = 0;\n-\n-release:\n- release_firmware(firmware);\n- return err;\n-}\n-\n-\n-static int fore200e_register(struct fore200e *fore200e, struct device *parent)\n-{\n- struct atm_dev* atm_dev;\n-\n- DPRINTK(2, \"device %s being registered\\n\", fore200e->name);\n-\n- atm_dev = atm_dev_register(fore200e->bus->proc_name, parent, &fore200e_ops,\n- -1, NULL);\n- if (atm_dev == NULL) {\n-\tprintk(FORE200E \"unable to register device %s\\n\", fore200e->name);\n-\treturn -ENODEV;\n- }\n-\n- atm_dev->dev_data = fore200e;\n- fore200e->atm_dev = atm_dev;\n-\n- atm_dev->ci_range.vpi_bits = FORE200E_VPI_BITS;\n- atm_dev->ci_range.vci_bits = FORE200E_VCI_BITS;\n-\n- fore200e->available_cell_rate = ATM_OC3_PCR;\n-\n- fore200e->state = FORE200E_STATE_REGISTER;\n- return 0;\n-}\n-\n-\n-static int fore200e_init(struct fore200e *fore200e, struct device *parent)\n-{\n- if (fore200e_register(fore200e, parent) < 0)\n-\treturn -ENODEV;\n- \n- if (fore200e->bus->configure(fore200e) < 0)\n-\treturn -ENODEV;\n-\n- if (fore200e->bus->map(fore200e) < 0)\n-\treturn -ENODEV;\n-\n- if (fore200e_reset(fore200e, 1) < 0)\n-\treturn -ENODEV;\n-\n- if (fore200e_load_and_start_fw(fore200e) < 0)\n-\treturn -ENODEV;\n-\n- if (fore200e_initialize(fore200e) < 0)\n-\treturn -ENODEV;\n-\n- if (fore200e_init_cmd_queue(fore200e) < 0)\n-\treturn -ENOMEM;\n-\n- if (fore200e_init_tx_queue(fore200e) < 0)\n-\treturn -ENOMEM;\n-\n- if (fore200e_init_rx_queue(fore200e) < 0)\n-\treturn -ENOMEM;\n-\n- if (fore200e_init_bs_queue(fore200e) < 0)\n-\treturn -ENOMEM;\n-\n- if (fore200e_alloc_rx_buf(fore200e) < 0)\n-\treturn -ENOMEM;\n-\n- if (fore200e_get_esi(fore200e) < 0)\n-\treturn -EIO;\n-\n- if (fore200e_irq_request(fore200e) < 0)\n-\treturn -EBUSY;\n-\n- fore200e_supply(fore200e);\n-\n- /* all done, board initialization is now complete */\n- fore200e->state = FORE200E_STATE_COMPLETE;\n- return 0;\n-}\n-\n-#ifdef CONFIG_SBUS\n-static int fore200e_sba_probe(struct platform_device *op)\n-{\n-\tstruct fore200e *fore200e;\n-\tstatic int index = 0;\n-\tint err;\n-\n-\tfore200e = kzalloc_obj(struct fore200e);\n-\tif (!fore200e)\n-\t\treturn -ENOMEM;\n-\n-\tfore200e->bus = &fore200e_sbus_ops;\n-\tfore200e->dev = &op->dev;\n-\tfore200e->irq = op->archdata.irqs[0];\n-\tfore200e->phys_base = op->resource[0].start;\n-\n-\tsprintf(fore200e->name, \"SBA-200E-%d\", index);\n-\n-\terr = fore200e_init(fore200e, &op->dev);\n-\tif (err < 0) {\n-\t\tfore200e_shutdown(fore200e);\n-\t\tkfree(fore200e);\n-\t\treturn err;\n-\t}\n-\n-\tindex++;\n-\tdev_set_drvdata(&op->dev, fore200e);\n-\n-\treturn 0;\n-}\n-\n-static void fore200e_sba_remove(struct platform_device *op)\n-{\n-\tstruct fore200e *fore200e = dev_get_drvdata(&op->dev);\n-\n-\tfore200e_shutdown(fore200e);\n-\tkfree(fore200e);\n-}\n-\n-static const struct of_device_id fore200e_sba_match[] = {\n-\t{\n-\t\t.name = SBA200E_PROM_NAME,\n-\t},\n-\t{},\n-};\n-MODULE_DEVICE_TABLE(of, fore200e_sba_match);\n-\n-static struct platform_driver fore200e_sba_driver = {\n-\t.driver = {\n-\t\t.name = \"fore_200e\",\n-\t\t.of_match_table = fore200e_sba_match,\n-\t},\n-\t.probe\t\t= fore200e_sba_probe,\n-\t.remove\t\t= fore200e_sba_remove,\n-};\n-#endif\n-\n-#ifdef CONFIG_PCI\n-static int fore200e_pca_detect(struct pci_dev *pci_dev,\n-\t\t\t const struct pci_device_id *pci_ent)\n-{\n- struct fore200e* fore200e;\n- int err = 0;\n- static int index = 0;\n-\n- if (pci_enable_device(pci_dev)) {\n-\terr = -EINVAL;\n-\tgoto out;\n- }\n-\n- if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32))) {\n-\terr = -EINVAL;\n-\tgoto out;\n- }\n- \n- fore200e = kzalloc_obj(struct fore200e);\n- if (fore200e == NULL) {\n-\terr = -ENOMEM;\n-\tgoto out_disable;\n- }\n-\n- fore200e->bus = &fore200e_pci_ops;\n- fore200e->dev\t= &pci_dev->dev;\n- fore200e->irq = pci_dev->irq;\n- fore200e->phys_base = pci_resource_start(pci_dev, 0);\n-\n- sprintf(fore200e->name, \"PCA-200E-%d\", index - 1);\n-\n- pci_set_master(pci_dev);\n-\n- printk(FORE200E \"device PCA-200E found at 0x%lx, IRQ %s\\n\",\n-\t fore200e->phys_base, fore200e_irq_itoa(fore200e->irq));\n-\n- sprintf(fore200e->name, \"PCA-200E-%d\", index);\n-\n- err = fore200e_init(fore200e, &pci_dev->dev);\n- if (err < 0) {\n-\tfore200e_shutdown(fore200e);\n-\tgoto out_free;\n- }\n-\n- ++index;\n- pci_set_drvdata(pci_dev, fore200e);\n-\n-out:\n- return err;\n-\n-out_free:\n- kfree(fore200e);\n-out_disable:\n- pci_disable_device(pci_dev);\n- goto out;\n-}\n-\n-\n-static void fore200e_pca_remove_one(struct pci_dev *pci_dev)\n-{\n- struct fore200e *fore200e;\n-\n- fore200e = pci_get_drvdata(pci_dev);\n-\n- fore200e_shutdown(fore200e);\n- kfree(fore200e);\n- pci_disable_device(pci_dev);\n-}\n-\n-\n-static const struct pci_device_id fore200e_pca_tbl[] = {\n- { PCI_VENDOR_ID_FORE, PCI_DEVICE_ID_FORE_PCA200E, PCI_ANY_ID, PCI_ANY_ID },\n- { 0, }\n-};\n-\n-MODULE_DEVICE_TABLE(pci, fore200e_pca_tbl);\n-\n-static struct pci_driver fore200e_pca_driver = {\n- .name = \"fore_200e\",\n- .probe = fore200e_pca_detect,\n- .remove = fore200e_pca_remove_one,\n- .id_table = fore200e_pca_tbl,\n-};\n-#endif\n-\n-static int __init fore200e_module_init(void)\n-{\n-\tint err = 0;\n-\n-\tprintk(FORE200E \"FORE Systems 200E-series ATM driver - version \" FORE200E_VERSION \"\\n\");\n-\n-#ifdef CONFIG_SBUS\n-\terr = platform_driver_register(&fore200e_sba_driver);\n-\tif (err)\n-\t\treturn err;\n-#endif\n-\n-#ifdef CONFIG_PCI\n-\terr = pci_register_driver(&fore200e_pca_driver);\n-#endif\n-\n-#ifdef CONFIG_SBUS\n-\tif (err)\n-\t\tplatform_driver_unregister(&fore200e_sba_driver);\n-#endif\n-\n-\treturn err;\n-}\n-\n-static void __exit fore200e_module_cleanup(void)\n-{\n-#ifdef CONFIG_PCI\n-\tpci_unregister_driver(&fore200e_pca_driver);\n-#endif\n-#ifdef CONFIG_SBUS\n-\tplatform_driver_unregister(&fore200e_sba_driver);\n-#endif\n-}\n-\n-static int\n-fore200e_proc_read(struct atm_dev *dev, loff_t* pos, char* page)\n-{\n- struct fore200e* fore200e = FORE200E_DEV(dev);\n- struct fore200e_vcc* fore200e_vcc;\n- struct atm_vcc* vcc;\n- int i, len, left = *pos;\n- unsigned long flags;\n-\n- if (!left--) {\n-\n-\tif (fore200e_getstats(fore200e) < 0)\n-\t return -EIO;\n-\n-\tlen = sprintf(page,\"\\n\"\n-\t\t \" device:\\n\"\n-\t\t \" internal name:\\t\\t%s\\n\", fore200e->name);\n-\n-\t/* print bus-specific information */\n-\tif (fore200e->bus->proc_read)\n-\t len += fore200e->bus->proc_read(fore200e, page + len);\n-\t\n-\tlen += sprintf(page + len,\n-\t\t\" interrupt line:\\t\\t%s\\n\"\n-\t\t\" physical base address:\\t0x%p\\n\"\n-\t\t\" virtual base address:\\t0x%p\\n\"\n-\t\t\" factory address (ESI):\\t%pM\\n\"\n-\t\t\" board serial number:\\t\\t%d\\n\\n\",\n-\t\tfore200e_irq_itoa(fore200e->irq),\n-\t\t(void*)fore200e->phys_base,\n-\t\tfore200e->virt_base,\n-\t\tfore200e->esi,\n-\t\tfore200e->esi[4] * 256 + fore200e->esi[5]);\n-\n-\treturn len;\n- }\n-\n- if (!left--)\n-\treturn sprintf(page,\n-\t\t \" free small bufs, scheme 1:\\t%d\\n\"\n-\t\t \" free large bufs, scheme 1:\\t%d\\n\"\n-\t\t \" free small bufs, scheme 2:\\t%d\\n\"\n-\t\t \" free large bufs, scheme 2:\\t%d\\n\",\n-\t\t fore200e->host_bsq[ BUFFER_SCHEME_ONE ][ BUFFER_MAGN_SMALL ].freebuf_count,\n-\t\t fore200e->host_bsq[ BUFFER_SCHEME_ONE ][ BUFFER_MAGN_LARGE ].freebuf_count,\n-\t\t fore200e->host_bsq[ BUFFER_SCHEME_TWO ][ BUFFER_MAGN_SMALL ].freebuf_count,\n-\t\t fore200e->host_bsq[ BUFFER_SCHEME_TWO ][ BUFFER_MAGN_LARGE ].freebuf_count);\n-\n- if (!left--) {\n-\tu32 hb = fore200e->bus->read(&fore200e->cp_queues->heartbeat);\n-\n-\tlen = sprintf(page,\"\\n\\n\"\n-\t\t \" cell processor:\\n\"\n-\t\t \" heartbeat state:\\t\\t\");\n-\t\n-\tif (hb >> 16 != 0xDEAD)\n-\t len += sprintf(page + len, \"0x%08x\\n\", hb);\n-\telse\n-\t len += sprintf(page + len, \"*** FATAL ERROR %04x ***\\n\", hb & 0xFFFF);\n-\n-\treturn len;\n- }\n-\n- if (!left--) {\n-\tstatic const char* media_name[] = {\n-\t \"unshielded twisted pair\",\n-\t \"multimode optical fiber ST\",\n-\t \"multimode optical fiber SC\",\n-\t \"single-mode optical fiber ST\",\n-\t \"single-mode optical fiber SC\",\n-\t \"unknown\"\n-\t};\n-\n-\tstatic const char* oc3_mode[] = {\n-\t \"normal operation\",\n-\t \"diagnostic loopback\",\n-\t \"line loopback\",\n-\t \"unknown\"\n-\t};\n-\n-\tu32 fw_release = fore200e->bus->read(&fore200e->cp_queues->fw_release);\n-\tu32 mon960_release = fore200e->bus->read(&fore200e->cp_queues->mon960_release);\n-\tu32 oc3_revision = fore200e->bus->read(&fore200e->cp_queues->oc3_revision);\n-\tu32 media_index = FORE200E_MEDIA_INDEX(fore200e->bus->read(&fore200e->cp_queues->media_type));\n-\tu32 oc3_index;\n-\n-\tif (media_index > 4)\n-\t\tmedia_index = 5;\n-\t\n-\tswitch (fore200e->loop_mode) {\n-\t case ATM_LM_NONE: oc3_index = 0;\n-\t\t break;\n-\t case ATM_LM_LOC_PHY: oc3_index = 1;\n-\t\t break;\n-\t case ATM_LM_RMT_PHY: oc3_index = 2;\n-\t\t break;\n-\t default: oc3_index = 3;\n-\t}\n-\n-\treturn sprintf(page,\n-\t\t \" firmware release:\\t\\t%d.%d.%d\\n\"\n-\t\t \" monitor release:\\t\\t%d.%d\\n\"\n-\t\t \" media type:\\t\\t\\t%s\\n\"\n-\t\t \" OC-3 revision:\\t\\t0x%x\\n\"\n- \" OC-3 mode:\\t\\t\\t%s\",\n-\t\t fw_release >> 16, fw_release << 16 >> 24, fw_release << 24 >> 24,\n-\t\t mon960_release >> 16, mon960_release << 16 >> 16,\n-\t\t media_name[ media_index ],\n-\t\t oc3_revision,\n-\t\t oc3_mode[ oc3_index ]);\n- }\n-\n- if (!left--) {\n-\tstruct cp_monitor __iomem * cp_monitor = fore200e->cp_monitor;\n-\n-\treturn sprintf(page,\n-\t\t \"\\n\\n\"\n-\t\t \" monitor:\\n\"\n-\t\t \" version number:\\t\\t%d\\n\"\n-\t\t \" boot status word:\\t\\t0x%08x\\n\",\n-\t\t fore200e->bus->read(&cp_monitor->mon_version),\n-\t\t fore200e->bus->read(&cp_monitor->bstat));\n- }\n-\n- if (!left--)\n-\treturn sprintf(page,\n-\t\t \"\\n\"\n-\t\t \" device statistics:\\n\"\n-\t\t \" 4b5b:\\n\"\n-\t\t \" crc_header_errors:\\t\\t%10u\\n\"\n-\t\t \" framing_errors:\\t\\t%10u\\n\",\n-\t\t be32_to_cpu(fore200e->stats->phy.crc_header_errors),\n-\t\t be32_to_cpu(fore200e->stats->phy.framing_errors));\n- \n- if (!left--)\n-\treturn sprintf(page, \"\\n\"\n-\t\t \" OC-3:\\n\"\n-\t\t \" section_bip8_errors:\\t%10u\\n\"\n-\t\t \" path_bip8_errors:\\t\\t%10u\\n\"\n-\t\t \" line_bip24_errors:\\t\\t%10u\\n\"\n-\t\t \" line_febe_errors:\\t\\t%10u\\n\"\n-\t\t \" path_febe_errors:\\t\\t%10u\\n\"\n-\t\t \" corr_hcs_errors:\\t\\t%10u\\n\"\n-\t\t \" ucorr_hcs_errors:\\t\\t%10u\\n\",\n-\t\t be32_to_cpu(fore200e->stats->oc3.section_bip8_errors),\n-\t\t be32_to_cpu(fore200e->stats->oc3.path_bip8_errors),\n-\t\t be32_to_cpu(fore200e->stats->oc3.line_bip24_errors),\n-\t\t be32_to_cpu(fore200e->stats->oc3.line_febe_errors),\n-\t\t be32_to_cpu(fore200e->stats->oc3.path_febe_errors),\n-\t\t be32_to_cpu(fore200e->stats->oc3.corr_hcs_errors),\n-\t\t be32_to_cpu(fore200e->stats->oc3.ucorr_hcs_errors));\n-\n- if (!left--)\n-\treturn sprintf(page,\"\\n\"\n-\t\t \" ATM:\\t\\t\\t\\t cells\\n\"\n-\t\t \" TX:\\t\\t\\t%10u\\n\"\n-\t\t \" RX:\\t\\t\\t%10u\\n\"\n-\t\t \" vpi out of range:\\t\\t%10u\\n\"\n-\t\t \" vpi no conn:\\t\\t%10u\\n\"\n-\t\t \" vci out of range:\\t\\t%10u\\n\"\n-\t\t \" vci no conn:\\t\\t%10u\\n\",\n-\t\t be32_to_cpu(fore200e->stats->atm.cells_transmitted),\n-\t\t be32_to_cpu(fore200e->stats->atm.cells_received),\n-\t\t be32_to_cpu(fore200e->stats->atm.vpi_bad_range),\n-\t\t be32_to_cpu(fore200e->stats->atm.vpi_no_conn),\n-\t\t be32_to_cpu(fore200e->stats->atm.vci_bad_range),\n-\t\t be32_to_cpu(fore200e->stats->atm.vci_no_conn));\n- \n- if (!left--)\n-\treturn sprintf(page,\"\\n\"\n-\t\t \" AAL0:\\t\\t\\t cells\\n\"\n-\t\t \" TX:\\t\\t\\t%10u\\n\"\n-\t\t \" RX:\\t\\t\\t%10u\\n\"\n-\t\t \" dropped:\\t\\t\\t%10u\\n\",\n-\t\t be32_to_cpu(fore200e->stats->aal0.cells_transmitted),\n-\t\t be32_to_cpu(fore200e->stats->aal0.cells_received),\n-\t\t be32_to_cpu(fore200e->stats->aal0.cells_dropped));\n- \n- if (!left--)\n-\treturn sprintf(page,\"\\n\"\n-\t\t \" AAL3/4:\\n\"\n-\t\t \" SAR sublayer:\\t\\t cells\\n\"\n-\t\t \" TX:\\t\\t\\t%10u\\n\"\n-\t\t \" RX:\\t\\t\\t%10u\\n\"\n-\t\t \" dropped:\\t\\t\\t%10u\\n\"\n-\t\t \" CRC errors:\\t\\t%10u\\n\"\n-\t\t \" protocol errors:\\t\\t%10u\\n\\n\"\n-\t\t \" CS sublayer:\\t\\t PDUs\\n\"\n-\t\t \" TX:\\t\\t\\t%10u\\n\"\n-\t\t \" RX:\\t\\t\\t%10u\\n\"\n-\t\t \" dropped:\\t\\t\\t%10u\\n\"\n-\t\t \" protocol errors:\\t\\t%10u\\n\",\n-\t\t be32_to_cpu(fore200e->stats->aal34.cells_transmitted),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cells_received),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cells_dropped),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cells_crc_errors),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cells_protocol_errors),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cspdus_transmitted),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cspdus_received),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cspdus_dropped),\n-\t\t be32_to_cpu(fore200e->stats->aal34.cspdus_protocol_errors));\n- \n- if (!left--)\n-\treturn sprintf(page,\"\\n\"\n-\t\t \" AAL5:\\n\"\n-\t\t \" SAR sublayer:\\t\\t cells\\n\"\n-\t\t \" TX:\\t\\t\\t%10u\\n\"\n-\t\t \" RX:\\t\\t\\t%10u\\n\"\n-\t\t \" dropped:\\t\\t\\t%10u\\n\"\n-\t\t \" congestions:\\t\\t%10u\\n\\n\"\n-\t\t \" CS sublayer:\\t\\t PDUs\\n\"\n-\t\t \" TX:\\t\\t\\t%10u\\n\"\n-\t\t \" RX:\\t\\t\\t%10u\\n\"\n-\t\t \" dropped:\\t\\t\\t%10u\\n\"\n-\t\t \" CRC errors:\\t\\t%10u\\n\"\n-\t\t \" protocol errors:\\t\\t%10u\\n\",\n-\t\t be32_to_cpu(fore200e->stats->aal5.cells_transmitted),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cells_received),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cells_dropped),\n-\t\t be32_to_cpu(fore200e->stats->aal5.congestion_experienced),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cspdus_transmitted),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cspdus_received),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cspdus_dropped),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cspdus_crc_errors),\n-\t\t be32_to_cpu(fore200e->stats->aal5.cspdus_protocol_errors));\n- \n- if (!left--)\n-\treturn sprintf(page,\"\\n\"\n-\t\t \" AUX:\\t\\t allocation failures\\n\"\n-\t\t \" small b1:\\t\\t\\t%10u\\n\"\n-\t\t \" large b1:\\t\\t\\t%10u\\n\"\n-\t\t \" small b2:\\t\\t\\t%10u\\n\"\n-\t\t \" large b2:\\t\\t\\t%10u\\n\"\n-\t\t \" RX PDUs:\\t\\t\\t%10u\\n\"\n-\t\t \" TX PDUs:\\t\\t\\t%10lu\\n\",\n-\t\t be32_to_cpu(fore200e->stats->aux.small_b1_failed),\n-\t\t be32_to_cpu(fore200e->stats->aux.large_b1_failed),\n-\t\t be32_to_cpu(fore200e->stats->aux.small_b2_failed),\n-\t\t be32_to_cpu(fore200e->stats->aux.large_b2_failed),\n-\t\t be32_to_cpu(fore200e->stats->aux.rpd_alloc_failed),\n-\t\t fore200e->tx_sat);\n- \n- if (!left--)\n-\treturn sprintf(page,\"\\n\"\n-\t\t \" receive carrier:\\t\\t\\t%s\\n\",\n-\t\t fore200e->stats->aux.receive_carrier ? \"ON\" : \"OFF!\");\n- \n- if (!left--) {\n- return sprintf(page,\"\\n\"\n-\t\t \" VCCs:\\n address VPI VCI AAL \"\n-\t\t \"TX PDUs TX min/max size RX PDUs RX min/max size\\n\");\n- }\n-\n- for (i = 0; i < NBR_CONNECT; i++) {\n-\n-\tvcc = fore200e->vc_map[i].vcc;\n-\n-\tif (vcc == NULL)\n-\t continue;\n-\n-\tspin_lock_irqsave(&fore200e->q_lock, flags);\n-\n-\tif (vcc && test_bit(ATM_VF_READY, &vcc->flags) && !left--) {\n-\n-\t fore200e_vcc = FORE200E_VCC(vcc);\n-\t ASSERT(fore200e_vcc);\n-\n-\t len = sprintf(page,\n-\t\t\t \" %pK %03d %05d %1d %09lu %05d/%05d %09lu %05d/%05d\\n\",\n-\t\t\t vcc,\n-\t\t\t vcc->vpi, vcc->vci, fore200e_atm2fore_aal(vcc->qos.aal),\n-\t\t\t fore200e_vcc->tx_pdu,\n-\t\t\t fore200e_vcc->tx_min_pdu > 0xFFFF ? 0 : fore200e_vcc->tx_min_pdu,\n-\t\t\t fore200e_vcc->tx_max_pdu,\n-\t\t\t fore200e_vcc->rx_pdu,\n-\t\t\t fore200e_vcc->rx_min_pdu > 0xFFFF ? 0 : fore200e_vcc->rx_min_pdu,\n-\t\t\t fore200e_vcc->rx_max_pdu);\n-\n-\t spin_unlock_irqrestore(&fore200e->q_lock, flags);\n-\t return len;\n-\t}\n-\n-\tspin_unlock_irqrestore(&fore200e->q_lock, flags);\n- }\n- \n- return 0;\n-}\n-\n-module_init(fore200e_module_init);\n-module_exit(fore200e_module_cleanup);\n-\n-\n-static const struct atmdev_ops fore200e_ops = {\n-\t.open = fore200e_open,\n-\t.close = fore200e_close,\n-\t.ioctl = fore200e_ioctl,\n-\t.send = fore200e_send,\n-\t.change_qos = fore200e_change_qos,\n-\t.proc_read = fore200e_proc_read,\n-\t.owner = THIS_MODULE\n-};\n-\n-MODULE_LICENSE(\"GPL\");\n-#ifdef CONFIG_PCI\n-#ifdef __LITTLE_ENDIAN__\n-MODULE_FIRMWARE(\"pca200e.bin\");\n-#else\n-MODULE_FIRMWARE(\"pca200e_ecd.bin2\");\n-#endif\n-#endif /* CONFIG_PCI */\n-#ifdef CONFIG_SBUS\n-MODULE_FIRMWARE(\"sba200e_ecd.bin2\");\n-#endif\ndiff --git a/drivers/atm/he.c b/drivers/atm/he.c\ndeleted file mode 100644\nindex bb9cb00f9585..000000000000\n--- a/drivers/atm/he.c\n+++ /dev/null\n@@ -1,2861 +0,0 @@\n-/*\n-\n- he.c\n-\n- ForeRunnerHE ATM Adapter driver for ATM on Linux\n- Copyright (C) 1999-2001 Naval Research Laboratory\n-\n- This library is free software; you can redistribute it and/or\n- modify it under the terms of the GNU Lesser General Public\n- License as published by the Free Software Foundation; either\n- version 2.1 of the License, or (at your option) any later version.\n-\n- This library is distributed in the hope that it will be useful,\n- but WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n- Lesser General Public License for more details.\n-\n- You should have received a copy of the GNU Lesser General Public\n- License along with this library; if not, write to the Free Software\n- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n-\n-*/\n-\n-/*\n-\n- he.c\n-\n- ForeRunnerHE ATM Adapter driver for ATM on Linux\n- Copyright (C) 1999-2001 Naval Research Laboratory\n-\n- Permission to use, copy, modify and distribute this software and its\n- documentation is hereby granted, provided that both the copyright\n- notice and this permission notice appear in all copies of the software,\n- derivative works or modified versions, and any portions thereof, and\n- that both notices appear in supporting documentation.\n-\n- NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS \"AS IS\" CONDITION AND\n- DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER\n- RESULTING FROM THE USE OF THIS SOFTWARE.\n-\n- This driver was written using the \"Programmer's Reference Manual for\n- ForeRunnerHE(tm)\", MANU0361-01 - Rev. A, 08/21/98.\n-\n- AUTHORS:\n-\tchas williams \n-\teric kinzie \n-\n- NOTES:\n-\t4096 supported 'connections'\n-\tgroup 0 is used for all traffic\n-\tinterrupt queue 0 is used for all interrupts\n-\taal0 support (based on work from ulrich.u.muller@nokia.com)\n-\n- */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \n-#include \n-#include \n-\n-#undef USE_SCATTERGATHER\n-#undef USE_CHECKSUM_HW\t\t\t/* still confused about this */\n-/* #undef HE_DEBUG */\n-\n-#include \"he.h\"\n-#include \"suni.h\"\n-#include \n-\n-#define hprintk(fmt,args...)\tprintk(KERN_ERR DEV_LABEL \"%d: \" fmt, he_dev->number , ##args)\n-\n-#ifdef HE_DEBUG\n-#define HPRINTK(fmt,args...)\tprintk(KERN_DEBUG DEV_LABEL \"%d: \" fmt, he_dev->number , ##args)\n-#else /* !HE_DEBUG */\n-#define HPRINTK(fmt,args...)\tdo { } while (0)\n-#endif /* HE_DEBUG */\n-\n-/* declarations */\n-\n-static int he_open(struct atm_vcc *vcc);\n-static void he_close(struct atm_vcc *vcc);\n-static int he_send(struct atm_vcc *vcc, struct sk_buff *skb);\n-static int he_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg);\n-static irqreturn_t he_irq_handler(int irq, void *dev_id);\n-static void he_tasklet(unsigned long data);\n-static int he_proc_read(struct atm_dev *dev,loff_t *pos,char *page);\n-static int he_start(struct atm_dev *dev);\n-static void he_stop(struct he_dev *dev);\n-static void he_phy_put(struct atm_dev *, unsigned char, unsigned long);\n-static unsigned char he_phy_get(struct atm_dev *, unsigned long);\n-\n-static u8 read_prom_byte(struct he_dev *he_dev, int addr);\n-\n-/* globals */\n-\n-static struct he_dev *he_devs;\n-static bool disable64;\n-static short nvpibits = -1;\n-static short nvcibits = -1;\n-static short rx_skb_reserve = 16;\n-static bool irq_coalesce = true;\n-static bool sdh;\n-\n-/* Read from EEPROM = 0000 0011b */\n-static unsigned int readtab[] = {\n-\tCS_HIGH | CLK_HIGH,\n-\tCS_LOW | CLK_LOW,\n-\tCLK_HIGH, /* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH, /* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH, /* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH, /* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH, /* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH, /* 0 */\n-\tCLK_LOW | SI_HIGH,\n-\tCLK_HIGH | SI_HIGH, /* 1 */\n-\tCLK_LOW | SI_HIGH,\n-\tCLK_HIGH | SI_HIGH /* 1 */\n-}; \n- \n-/* Clock to read from/write to the EEPROM */\n-static unsigned int clocktab[] = {\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW\n-}; \n-\n-static const struct atmdev_ops he_ops =\n-{\n-\t.open =\t\the_open,\n-\t.close =\the_close,\t\n-\t.ioctl =\the_ioctl,\t\n-\t.send =\t\the_send,\n-\t.phy_put =\the_phy_put,\n-\t.phy_get =\the_phy_get,\n-\t.proc_read =\the_proc_read,\n-\t.owner =\tTHIS_MODULE\n-};\n-\n-#define he_writel(dev, val, reg)\tdo { writel(val, (dev)->membase + (reg)); wmb(); } while (0)\n-#define he_readl(dev, reg)\t\treadl((dev)->membase + (reg))\n-\n-/* section 2.12 connection memory access */\n-\n-static __inline__ void\n-he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,\n-\t\t\t\t\t\t\t\tunsigned flags)\n-{\n-\the_writel(he_dev, val, CON_DAT);\n-\t(void) he_readl(he_dev, CON_DAT);\t\t/* flush posted writes */\n-\the_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);\n-\twhile (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);\n-}\n-\n-#define he_writel_rcm(dev, val, reg) \t\t\t\t\\\n-\t\t\the_writel_internal(dev, val, reg, CON_CTL_RCM)\n-\n-#define he_writel_tcm(dev, val, reg) \t\t\t\t\\\n-\t\t\the_writel_internal(dev, val, reg, CON_CTL_TCM)\n-\n-#define he_writel_mbox(dev, val, reg) \t\t\t\t\\\n-\t\t\the_writel_internal(dev, val, reg, CON_CTL_MBOX)\n-\n-static unsigned\n-he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)\n-{\n-\the_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);\n-\twhile (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);\n-\treturn he_readl(he_dev, CON_DAT);\n-}\n-\n-#define he_readl_rcm(dev, reg) \\\n-\t\t\the_readl_internal(dev, reg, CON_CTL_RCM)\n-\n-#define he_readl_tcm(dev, reg) \\\n-\t\t\the_readl_internal(dev, reg, CON_CTL_TCM)\n-\n-#define he_readl_mbox(dev, reg) \\\n-\t\t\the_readl_internal(dev, reg, CON_CTL_MBOX)\n-\n-\n-/* figure 2.2 connection id */\n-\n-#define he_mkcid(dev, vpi, vci)\t\t(((vpi << (dev)->vcibits) | vci) & 0x1fff)\n-\n-/* 2.5.1 per connection transmit state registers */\n-\n-#define he_writel_tsr0(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)\n-#define he_readl_tsr0(dev, cid) \\\n-\t\the_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)\n-\n-#define he_writel_tsr1(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)\n-\n-#define he_writel_tsr2(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)\n-\n-#define he_writel_tsr3(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)\n-\n-#define he_writel_tsr4(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)\n-\n-\t/* from page 2-20\n-\t *\n-\t * NOTE While the transmit connection is active, bits 23 through 0\n-\t * of this register must not be written by the host. Byte\n-\t * enables should be used during normal operation when writing\n-\t * the most significant byte.\n-\t */\n-\n-#define he_writel_tsr4_upper(dev, val, cid) \\\n-\t\the_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \\\n-\t\t\t\t\t\t\tCON_CTL_TCM \\\n-\t\t\t\t\t\t\t| CON_BYTE_DISABLE_2 \\\n-\t\t\t\t\t\t\t| CON_BYTE_DISABLE_1 \\\n-\t\t\t\t\t\t\t| CON_BYTE_DISABLE_0)\n-\n-#define he_readl_tsr4(dev, cid) \\\n-\t\the_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)\n-\n-#define he_writel_tsr5(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)\n-\n-#define he_writel_tsr6(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)\n-\n-#define he_writel_tsr7(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)\n-\n-\n-#define he_writel_tsr8(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)\n-\n-#define he_writel_tsr9(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)\n-\n-#define he_writel_tsr10(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)\n-\n-#define he_writel_tsr11(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)\n-\n-\n-#define he_writel_tsr12(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)\n-\n-#define he_writel_tsr13(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)\n-\n-\n-#define he_writel_tsr14(dev, val, cid) \\\n-\t\the_writel_tcm(dev, val, CONFIG_TSRD | cid)\n-\n-#define he_writel_tsr14_upper(dev, val, cid) \\\n-\t\the_writel_internal(dev, val, CONFIG_TSRD | cid, \\\n-\t\t\t\t\t\t\tCON_CTL_TCM \\\n-\t\t\t\t\t\t\t| CON_BYTE_DISABLE_2 \\\n-\t\t\t\t\t\t\t| CON_BYTE_DISABLE_1 \\\n-\t\t\t\t\t\t\t| CON_BYTE_DISABLE_0)\n-\n-/* 2.7.1 per connection receive state registers */\n-\n-#define he_writel_rsr0(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)\n-#define he_readl_rsr0(dev, cid) \\\n-\t\the_readl_rcm(dev, 0x00000 | (cid << 3) | 0)\n-\n-#define he_writel_rsr1(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)\n-\n-#define he_writel_rsr2(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)\n-\n-#define he_writel_rsr3(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)\n-\n-#define he_writel_rsr4(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)\n-\n-#define he_writel_rsr5(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)\n-\n-#define he_writel_rsr6(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)\n-\n-#define he_writel_rsr7(dev, val, cid) \\\n-\t\the_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)\n-\n-static __inline__ struct atm_vcc*\n-__find_vcc(struct he_dev *he_dev, unsigned cid)\n-{\n-\tstruct hlist_head *head;\n-\tstruct atm_vcc *vcc;\n-\tstruct sock *s;\n-\tshort vpi;\n-\tint vci;\n-\n-\tvpi = cid >> he_dev->vcibits;\n-\tvci = cid & ((1 << he_dev->vcibits) - 1);\n-\thead = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];\n-\n-\tsk_for_each(s, head) {\n-\t\tvcc = atm_sk(s);\n-\t\tif (vcc->dev == he_dev->atm_dev &&\n-\t\t vcc->vci == vci && vcc->vpi == vpi &&\n-\t\t vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\t\t\treturn vcc;\n-\t\t}\n-\t}\n-\treturn NULL;\n-}\n-\n-static int he_init_one(struct pci_dev *pci_dev,\n-\t\t const struct pci_device_id *pci_ent)\n-{\n-\tstruct atm_dev *atm_dev = NULL;\n-\tstruct he_dev *he_dev = NULL;\n-\tint err = 0;\n-\n-\tprintk(KERN_INFO \"ATM he driver\\n\");\n-\n-\tif (pci_enable_device(pci_dev))\n-\t\treturn -EIO;\n-\tif (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)) != 0) {\n-\t\tprintk(KERN_WARNING \"he: no suitable dma available\\n\");\n-\t\terr = -EIO;\n-\t\tgoto init_one_failure;\n-\t}\n-\n-\tatm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &he_ops, -1, NULL);\n-\tif (!atm_dev) {\n-\t\terr = -ENODEV;\n-\t\tgoto init_one_failure;\n-\t}\n-\tpci_set_drvdata(pci_dev, atm_dev);\n-\n-\the_dev = kzalloc_obj(struct he_dev);\n-\tif (!he_dev) {\n-\t\terr = -ENOMEM;\n-\t\tgoto init_one_failure;\n-\t}\n-\the_dev->pci_dev = pci_dev;\n-\the_dev->atm_dev = atm_dev;\n-\the_dev->atm_dev->dev_data = he_dev;\n-\tatm_dev->dev_data = he_dev;\n-\the_dev->number = atm_dev->number;\n-\ttasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);\n-\tspin_lock_init(&he_dev->global_lock);\n-\n-\tif (he_start(atm_dev)) {\n-\t\the_stop(he_dev);\n-\t\terr = -ENODEV;\n-\t\tgoto init_one_failure;\n-\t}\n-\the_dev->next = NULL;\n-\tif (he_devs)\n-\t\the_dev->next = he_devs;\n-\the_devs = he_dev;\n-\treturn 0;\n-\n-init_one_failure:\n-\tif (atm_dev)\n-\t\tatm_dev_deregister(atm_dev);\n-\tkfree(he_dev);\n-\tpci_disable_device(pci_dev);\n-\treturn err;\n-}\n-\n-static void he_remove_one(struct pci_dev *pci_dev)\n-{\n-\tstruct atm_dev *atm_dev;\n-\tstruct he_dev *he_dev;\n-\n-\tatm_dev = pci_get_drvdata(pci_dev);\n-\the_dev = HE_DEV(atm_dev);\n-\n-\t/* need to remove from he_devs */\n-\n-\the_stop(he_dev);\n-\tatm_dev_deregister(atm_dev);\n-\tkfree(he_dev);\n-\n-\tpci_disable_device(pci_dev);\n-}\n-\n-\n-static unsigned\n-rate_to_atmf(unsigned rate)\t\t/* cps to atm forum format */\n-{\n-#define NONZERO (1 << 14)\n-\n-\tunsigned exp = 0;\n-\n-\tif (rate == 0)\n-\t\treturn 0;\n-\n-\trate <<= 9;\n-\twhile (rate > 0x3ff) {\n-\t\t++exp;\n-\t\trate >>= 1;\n-\t}\n-\n-\treturn (NONZERO | (exp << 9) | (rate & 0x1ff));\n-}\n-\n-static void he_init_rx_lbfp0(struct he_dev *he_dev)\n-{\n-\tunsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;\n-\tunsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;\n-\tunsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;\n-\tunsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;\n-\t\n-\tlbufd_index = 0;\n-\tlbm_offset = he_readl(he_dev, RCMLBM_BA);\n-\n-\the_writel(he_dev, lbufd_index, RLBF0_H);\n-\n-\tfor (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {\n-\t\tlbufd_index += 2;\n-\t\tlbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;\n-\n-\t\the_writel_rcm(he_dev, lbuf_addr, lbm_offset);\n-\t\the_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);\n-\n-\t\tif (++lbuf_count == lbufs_per_row) {\n-\t\t\tlbuf_count = 0;\n-\t\t\trow_offset += he_dev->bytes_per_row;\n-\t\t}\n-\t\tlbm_offset += 4;\n-\t}\n-\t\t\n-\the_writel(he_dev, lbufd_index - 2, RLBF0_T);\n-\the_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);\n-}\n-\n-static void he_init_rx_lbfp1(struct he_dev *he_dev)\n-{\n-\tunsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;\n-\tunsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;\n-\tunsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;\n-\tunsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;\n-\t\n-\tlbufd_index = 1;\n-\tlbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);\n-\n-\the_writel(he_dev, lbufd_index, RLBF1_H);\n-\n-\tfor (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {\n-\t\tlbufd_index += 2;\n-\t\tlbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;\n-\n-\t\the_writel_rcm(he_dev, lbuf_addr, lbm_offset);\n-\t\the_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);\n-\n-\t\tif (++lbuf_count == lbufs_per_row) {\n-\t\t\tlbuf_count = 0;\n-\t\t\trow_offset += he_dev->bytes_per_row;\n-\t\t}\n-\t\tlbm_offset += 4;\n-\t}\n-\t\t\n-\the_writel(he_dev, lbufd_index - 2, RLBF1_T);\n-\the_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);\n-}\n-\n-static void he_init_tx_lbfp(struct he_dev *he_dev)\n-{\n-\tunsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;\n-\tunsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;\n-\tunsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;\n-\tunsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;\n-\t\n-\tlbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;\n-\tlbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);\n-\n-\the_writel(he_dev, lbufd_index, TLBF_H);\n-\n-\tfor (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {\n-\t\tlbufd_index += 1;\n-\t\tlbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;\n-\n-\t\the_writel_rcm(he_dev, lbuf_addr, lbm_offset);\n-\t\the_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);\n-\n-\t\tif (++lbuf_count == lbufs_per_row) {\n-\t\t\tlbuf_count = 0;\n-\t\t\trow_offset += he_dev->bytes_per_row;\n-\t\t}\n-\t\tlbm_offset += 2;\n-\t}\n-\t\t\n-\the_writel(he_dev, lbufd_index - 1, TLBF_T);\n-}\n-\n-static int he_init_tpdrq(struct he_dev *he_dev)\n-{\n-\the_dev->tpdrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t\t\tCONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq),\n-\t\t\t\t\t\t&he_dev->tpdrq_phys,\n-\t\t\t\t\t\tGFP_KERNEL);\n-\tif (he_dev->tpdrq_base == NULL) {\n-\t\thprintk(\"failed to alloc tpdrq\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\the_dev->tpdrq_tail = he_dev->tpdrq_base;\n-\the_dev->tpdrq_head = he_dev->tpdrq_base;\n-\n-\the_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);\n-\the_writel(he_dev, 0, TPDRQ_T);\t\n-\the_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);\n-\n-\treturn 0;\n-}\n-\n-static void he_init_cs_block(struct he_dev *he_dev)\n-{\n-\tunsigned clock, rate, delta;\n-\tint reg;\n-\n-\t/* 5.1.7 cs block initialization */\n-\n-\tfor (reg = 0; reg < 0x20; ++reg)\n-\t\the_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);\n-\n-\t/* rate grid timer reload values */\n-\n-\tclock = he_is622(he_dev) ? 66667000 : 50000000;\n-\trate = he_dev->atm_dev->link_rate;\n-\tdelta = rate / 16 / 2;\n-\n-\tfor (reg = 0; reg < 0x10; ++reg) {\n-\t\t/* 2.4 internal transmit function\n-\t\t *\n-\t \t * we initialize the first row in the rate grid.\n-\t\t * values are period (in clock cycles) of timer\n-\t\t */\n-\t\tunsigned period = clock / rate;\n-\n-\t\the_writel_mbox(he_dev, period, CS_TGRLD0 + reg);\n-\t\trate -= delta;\n-\t}\n-\n-\tif (he_is622(he_dev)) {\n-\t\t/* table 5.2 (4 cells per lbuf) */\n-\t\the_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);\n-\t\the_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);\n-\t\the_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);\n-\t\the_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);\n-\t\the_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);\n-\n-\t\t/* table 5.3, 5.4, 5.5, 5.6, 5.7 */\n-\t\the_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);\n-\t\the_writel_mbox(he_dev, 0x1801, CS_ERCTL1);\n-\t\the_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);\n-\t\the_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);\n-\t\the_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);\n-\t\the_writel_mbox(he_dev, 0x14585, CS_RTFWR);\n-\n-\t\the_writel_mbox(he_dev, 0x4680, CS_RTATR);\n-\n-\t\t/* table 5.8 */\n-\t\the_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);\n-\t\the_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);\n-\t\the_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);\n-\t\the_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);\n-\t\the_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);\n-\t\the_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);\n-\n-\t\t/* table 5.9 */\n-\t\the_writel_mbox(he_dev, 0x5, CS_OTPPER);\n-\t\the_writel_mbox(he_dev, 0x14, CS_OTWPER);\n-\t} else {\n-\t\t/* table 5.1 (4 cells per lbuf) */\n-\t\the_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);\n-\t\the_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);\n-\t\the_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);\n-\t\the_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);\n-\t\the_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);\n-\n-\t\t/* table 5.3, 5.4, 5.5, 5.6, 5.7 */\n-\t\the_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);\n-\t\the_writel_mbox(he_dev, 0x4701, CS_ERCTL1);\n-\t\the_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);\n-\t\the_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);\n-\t\the_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);\n-\t\the_writel_mbox(he_dev, 0xf424, CS_RTFWR);\n-\n-\t\the_writel_mbox(he_dev, 0x4680, CS_RTATR);\n-\n-\t\t/* table 5.8 */\n-\t\the_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);\n-\t\the_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);\n-\t\the_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);\n-\t\the_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);\n-\t\the_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);\n-\t\the_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);\n-\n-\t\t/* table 5.9 */\n-\t\the_writel_mbox(he_dev, 0x6, CS_OTPPER);\n-\t\the_writel_mbox(he_dev, 0x1e, CS_OTWPER);\n-\t}\n-\n-\the_writel_mbox(he_dev, 0x8, CS_OTTLIM);\n-\n-\tfor (reg = 0; reg < 0x8; ++reg)\n-\t\the_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);\n-\n-}\n-\n-static int he_init_cs_block_rcm(struct he_dev *he_dev)\n-{\n-\tunsigned (*rategrid)[16][16];\n-\tunsigned rate, delta;\n-\tint i, j, reg;\n-\n-\tunsigned rate_atmf, exp, man;\n-\tunsigned long long rate_cps;\n-\tint mult, buf, buf_limit = 4;\n-\n-\trategrid = kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL);\n-\tif (!rategrid)\n-\t\treturn -ENOMEM;\n-\n-\t/* initialize rate grid group table */\n-\n-\tfor (reg = 0x0; reg < 0xff; ++reg)\n-\t\the_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);\n-\n-\t/* initialize rate controller groups */\n-\n-\tfor (reg = 0x100; reg < 0x1ff; ++reg)\n-\t\the_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);\n-\t\n-\t/* initialize tNrm lookup table */\n-\n-\t/* the manual makes reference to a routine in a sample driver\n-\t for proper configuration; fortunately, we only need this\n-\t in order to support abr connection */\n-\t\n-\t/* initialize rate to group table */\n-\n-\trate = he_dev->atm_dev->link_rate;\n-\tdelta = rate / 32;\n-\n-\t/*\n-\t * 2.4 transmit internal functions\n-\t * \n-\t * we construct a copy of the rate grid used by the scheduler\n-\t * in order to construct the rate to group table below\n-\t */\n-\n-\tfor (j = 0; j < 16; j++) {\n-\t\t(*rategrid)[0][j] = rate;\n-\t\trate -= delta;\n-\t}\n-\n-\tfor (i = 1; i < 16; i++)\n-\t\tfor (j = 0; j < 16; j++)\n-\t\t\tif (i > 14)\n-\t\t\t\t(*rategrid)[i][j] = (*rategrid)[i - 1][j] / 4;\n-\t\t\telse\n-\t\t\t\t(*rategrid)[i][j] = (*rategrid)[i - 1][j] / 2;\n-\n-\t/*\n-\t * 2.4 transmit internal function\n-\t *\n-\t * this table maps the upper 5 bits of exponent and mantissa\n-\t * of the atm forum representation of the rate into an index\n-\t * on rate grid \n-\t */\n-\n-\trate_atmf = 0;\n-\twhile (rate_atmf < 0x400) {\n-\t\tman = (rate_atmf & 0x1f) << 4;\n-\t\texp = rate_atmf >> 5;\n-\n-\t\t/* \n-\t\t\tinstead of '/ 512', use '>> 9' to prevent a call\n-\t\t\tto divdu3 on x86 platforms\n-\t\t*/\n-\t\trate_cps = (unsigned long long) (1UL << exp) * (man + 512) >> 9;\n-\n-\t\tif (rate_cps < 10)\n-\t\t\trate_cps = 10;\t/* 2.2.1 minimum payload rate is 10 cps */\n-\n-\t\tfor (i = 255; i > 0; i--)\n-\t\t\tif ((*rategrid)[i/16][i%16] >= rate_cps)\n-\t\t\t\tbreak;\t /* pick nearest rate instead? */\n-\n-\t\t/*\n-\t\t * each table entry is 16 bits: (rate grid index (8 bits)\n-\t\t * and a buffer limit (8 bits)\n-\t\t * there are two table entries in each 32-bit register\n-\t\t */\n-\n-#ifdef notdef\n-\t\tbuf = rate_cps * he_dev->tx_numbuffs /\n-\t\t\t\t(he_dev->atm_dev->link_rate * 2);\n-#else\n-\t\t/* this is pretty, but avoids _divdu3 and is mostly correct */\n-\t\tmult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;\n-\t\tif (rate_cps > (272ULL * mult))\n-\t\t\tbuf = 4;\n-\t\telse if (rate_cps > (204ULL * mult))\n-\t\t\tbuf = 3;\n-\t\telse if (rate_cps > (136ULL * mult))\n-\t\t\tbuf = 2;\n-\t\telse if (rate_cps > (68ULL * mult))\n-\t\t\tbuf = 1;\n-\t\telse\n-\t\t\tbuf = 0;\n-#endif\n-\t\tif (buf > buf_limit)\n-\t\t\tbuf = buf_limit;\n-\t\treg = (reg << 16) | ((i << 8) | buf);\n-\n-#define RTGTBL_OFFSET 0x400\n-\t \n-\t\tif (rate_atmf & 0x1)\n-\t\t\the_writel_rcm(he_dev, reg,\n-\t\t\t\tCONFIG_RCMABR + RTGTBL_OFFSET + (rate_atmf >> 1));\n-\n-\t\t++rate_atmf;\n-\t}\n-\n-\tkfree(rategrid);\n-\treturn 0;\n-}\n-\n-static int he_init_group(struct he_dev *he_dev, int group)\n-{\n-\tstruct he_buff *heb, *next;\n-\tdma_addr_t mapping;\n-\tint i;\n-\n-\the_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));\n-\the_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));\n-\the_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));\n-\the_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),\n-\t\t G0_RBPS_BS + (group * 32));\n-\n-\t/* bitmap table */\n-\the_dev->rbpl_table = bitmap_zalloc(RBPL_TABLE_SIZE, GFP_KERNEL);\n-\tif (!he_dev->rbpl_table) {\n-\t\thprintk(\"unable to allocate rbpl bitmap table\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\t/* rbpl_virt 64-bit pointers */\n-\the_dev->rbpl_virt = kmalloc_objs(*he_dev->rbpl_virt, RBPL_TABLE_SIZE);\n-\tif (!he_dev->rbpl_virt) {\n-\t\thprintk(\"unable to allocate rbpl virt table\\n\");\n-\t\tgoto out_free_rbpl_table;\n-\t}\n-\n-\t/* large buffer pool */\n-\the_dev->rbpl_pool = dma_pool_create(\"rbpl\", &he_dev->pci_dev->dev,\n-\t\t\t\t\t CONFIG_RBPL_BUFSIZE, 64, 0);\n-\tif (he_dev->rbpl_pool == NULL) {\n-\t\thprintk(\"unable to create rbpl pool\\n\");\n-\t\tgoto out_free_rbpl_virt;\n-\t}\n-\n-\the_dev->rbpl_base = dma_alloc_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t\t CONFIG_RBPL_SIZE * sizeof(struct he_rbp),\n-\t\t\t\t\t &he_dev->rbpl_phys, GFP_KERNEL);\n-\tif (he_dev->rbpl_base == NULL) {\n-\t\thprintk(\"failed to alloc rbpl_base\\n\");\n-\t\tgoto out_destroy_rbpl_pool;\n-\t}\n-\n-\tINIT_LIST_HEAD(&he_dev->rbpl_outstanding);\n-\n-\tfor (i = 0; i < CONFIG_RBPL_SIZE; ++i) {\n-\n-\t\theb = dma_pool_alloc(he_dev->rbpl_pool, GFP_KERNEL, &mapping);\n-\t\tif (!heb)\n-\t\t\tgoto out_free_rbpl;\n-\t\theb->mapping = mapping;\n-\t\tlist_add(&heb->entry, &he_dev->rbpl_outstanding);\n-\n-\t\tset_bit(i, he_dev->rbpl_table);\n-\t\the_dev->rbpl_virt[i] = heb;\n-\t\the_dev->rbpl_hint = i + 1;\n-\t\the_dev->rbpl_base[i].idx = i << RBP_IDX_OFFSET;\n-\t\the_dev->rbpl_base[i].phys = mapping + offsetof(struct he_buff, data);\n-\t}\n-\the_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];\n-\n-\the_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));\n-\the_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),\n-\t\t\t\t\t\tG0_RBPL_T + (group * 32));\n-\the_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,\n-\t\t\t\t\t\tG0_RBPL_BS + (group * 32));\n-\the_writel(he_dev,\n-\t\t\tRBP_THRESH(CONFIG_RBPL_THRESH) |\n-\t\t\tRBP_QSIZE(CONFIG_RBPL_SIZE - 1) |\n-\t\t\tRBP_INT_ENB,\n-\t\t\t\t\t\tG0_RBPL_QI + (group * 32));\n-\n-\t/* rx buffer ready queue */\n-\n-\the_dev->rbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t\t CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),\n-\t\t\t\t\t &he_dev->rbrq_phys, GFP_KERNEL);\n-\tif (he_dev->rbrq_base == NULL) {\n-\t\thprintk(\"failed to allocate rbrq\\n\");\n-\t\tgoto out_free_rbpl;\n-\t}\n-\n-\the_dev->rbrq_head = he_dev->rbrq_base;\n-\the_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));\n-\the_writel(he_dev, 0, G0_RBRQ_H + (group * 16));\n-\the_writel(he_dev,\n-\t\tRBRQ_THRESH(CONFIG_RBRQ_THRESH) | RBRQ_SIZE(CONFIG_RBRQ_SIZE - 1),\n-\t\t\t\t\t\tG0_RBRQ_Q + (group * 16));\n-\tif (irq_coalesce) {\n-\t\thprintk(\"coalescing interrupts\\n\");\n-\t\the_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),\n-\t\t\t\t\t\tG0_RBRQ_I + (group * 16));\n-\t} else\n-\t\the_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),\n-\t\t\t\t\t\tG0_RBRQ_I + (group * 16));\n-\n-\t/* tx buffer ready queue */\n-\n-\the_dev->tbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t\t CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),\n-\t\t\t\t\t &he_dev->tbrq_phys, GFP_KERNEL);\n-\tif (he_dev->tbrq_base == NULL) {\n-\t\thprintk(\"failed to allocate tbrq\\n\");\n-\t\tgoto out_free_rbpq_base;\n-\t}\n-\n-\the_dev->tbrq_head = he_dev->tbrq_base;\n-\n-\the_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));\n-\the_writel(he_dev, 0, G0_TBRQ_H + (group * 16));\n-\the_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));\n-\the_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));\n-\n-\treturn 0;\n-\n-out_free_rbpq_base:\n-\tdma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE *\n-\t\t\t sizeof(struct he_rbrq), he_dev->rbrq_base,\n-\t\t\t he_dev->rbrq_phys);\n-out_free_rbpl:\n-\tlist_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)\n-\t\tdma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);\n-\n-\tdma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE *\n-\t\t\t sizeof(struct he_rbp), he_dev->rbpl_base,\n-\t\t\t he_dev->rbpl_phys);\n-out_destroy_rbpl_pool:\n-\tdma_pool_destroy(he_dev->rbpl_pool);\n-out_free_rbpl_virt:\n-\tkfree(he_dev->rbpl_virt);\n-out_free_rbpl_table:\n-\tbitmap_free(he_dev->rbpl_table);\n-\n-\treturn -ENOMEM;\n-}\n-\n-static int he_init_irq(struct he_dev *he_dev)\n-{\n-\tint i;\n-\n-\t/* 2.9.3.5 tail offset for each interrupt queue is located after the\n-\t\t end of the interrupt queue */\n-\n-\the_dev->irq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t\t (CONFIG_IRQ_SIZE + 1) * sizeof(struct he_irq),\n-\t\t\t\t\t &he_dev->irq_phys, GFP_KERNEL);\n-\tif (he_dev->irq_base == NULL) {\n-\t\thprintk(\"failed to allocate irq\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\the_dev->irq_tailoffset = (unsigned *)\n-\t\t\t\t\t&he_dev->irq_base[CONFIG_IRQ_SIZE];\n-\t*he_dev->irq_tailoffset = 0;\n-\the_dev->irq_head = he_dev->irq_base;\n-\the_dev->irq_tail = he_dev->irq_base;\n-\n-\tfor (i = 0; i < CONFIG_IRQ_SIZE; ++i)\n-\t\the_dev->irq_base[i].isw = ITYPE_INVALID;\n-\n-\the_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);\n-\the_writel(he_dev,\n-\t\tIRQ_SIZE(CONFIG_IRQ_SIZE) | IRQ_THRESH(CONFIG_IRQ_THRESH),\n-\t\t\t\t\t\t\t\tIRQ0_HEAD);\n-\the_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);\n-\the_writel(he_dev, 0x0, IRQ0_DATA);\n-\n-\the_writel(he_dev, 0x0, IRQ1_BASE);\n-\the_writel(he_dev, 0x0, IRQ1_HEAD);\n-\the_writel(he_dev, 0x0, IRQ1_CNTL);\n-\the_writel(he_dev, 0x0, IRQ1_DATA);\n-\n-\the_writel(he_dev, 0x0, IRQ2_BASE);\n-\the_writel(he_dev, 0x0, IRQ2_HEAD);\n-\the_writel(he_dev, 0x0, IRQ2_CNTL);\n-\the_writel(he_dev, 0x0, IRQ2_DATA);\n-\n-\the_writel(he_dev, 0x0, IRQ3_BASE);\n-\the_writel(he_dev, 0x0, IRQ3_HEAD);\n-\the_writel(he_dev, 0x0, IRQ3_CNTL);\n-\the_writel(he_dev, 0x0, IRQ3_DATA);\n-\n-\t/* 2.9.3.2 interrupt queue mapping registers */\n-\n-\the_writel(he_dev, 0x0, GRP_10_MAP);\n-\the_writel(he_dev, 0x0, GRP_32_MAP);\n-\the_writel(he_dev, 0x0, GRP_54_MAP);\n-\the_writel(he_dev, 0x0, GRP_76_MAP);\n-\n-\tif (request_irq(he_dev->pci_dev->irq,\n-\t\t\the_irq_handler, IRQF_SHARED, DEV_LABEL, he_dev)) {\n-\t\thprintk(\"irq %d already in use\\n\", he_dev->pci_dev->irq);\n-\t\treturn -EINVAL;\n-\t} \n-\n-\the_dev->irq = he_dev->pci_dev->irq;\n-\n-\treturn 0;\n-}\n-\n-static int he_start(struct atm_dev *dev)\n-{\n-\tstruct he_dev *he_dev;\n-\tstruct pci_dev *pci_dev;\n-\tunsigned long membase;\n-\n-\tu16 command;\n-\tu32 gen_cntl_0, host_cntl, lb_swap;\n-\tu8 cache_size, timer;\n-\t\n-\tunsigned err;\n-\tunsigned int status, reg;\n-\tint i, group;\n-\n-\the_dev = HE_DEV(dev);\n-\tpci_dev = he_dev->pci_dev;\n-\n-\tmembase = pci_resource_start(pci_dev, 0);\n-\tHPRINTK(\"membase = 0x%lx irq = %d.\\n\", membase, pci_dev->irq);\n-\n-\t/*\n-\t * pci bus controller initialization \n-\t */\n-\n-\t/* 4.3 pci bus controller-specific initialization */\n-\tif (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) {\n-\t\thprintk(\"can't read GEN_CNTL_0\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\tgen_cntl_0 |= (MRL_ENB | MRM_ENB | IGNORE_TIMEOUT);\n-\tif (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) {\n-\t\thprintk(\"can't write GEN_CNTL_0.\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (pci_read_config_word(pci_dev, PCI_COMMAND, &command) != 0) {\n-\t\thprintk(\"can't read PCI_COMMAND.\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tcommand |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);\n-\tif (pci_write_config_word(pci_dev, PCI_COMMAND, command) != 0) {\n-\t\thprintk(\"can't enable memory.\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (pci_read_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, &cache_size)) {\n-\t\thprintk(\"can't read cache line size?\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (cache_size < 16) {\n-\t\tcache_size = 16;\n-\t\tif (pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, cache_size))\n-\t\t\thprintk(\"can't set cache line size to %d\\n\", cache_size);\n-\t}\n-\n-\tif (pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &timer)) {\n-\t\thprintk(\"can't read latency timer?\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* from table 3.9\n-\t *\n-\t * LAT_TIMER = 1 + AVG_LAT + BURST_SIZE/BUS_SIZE\n-\t * \n-\t * AVG_LAT: The average first data read/write latency [maximum 16 clock cycles]\n-\t * BURST_SIZE: 1536 bytes (read) for 622, 768 bytes (read) for 155 [192 clock cycles]\n-\t *\n-\t */ \n-#define LAT_TIMER 209\n-\tif (timer < LAT_TIMER) {\n-\t\tHPRINTK(\"latency timer was %d, setting to %d\\n\", timer, LAT_TIMER);\n-\t\ttimer = LAT_TIMER;\n-\t\tif (pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, timer))\n-\t\t\thprintk(\"can't set latency timer to %d\\n\", timer);\n-\t}\n-\n-\tif (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) {\n-\t\thprintk(\"can't set up page mapping\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* 4.4 card reset */\n-\the_writel(he_dev, 0x0, RESET_CNTL);\n-\the_writel(he_dev, 0xff, RESET_CNTL);\n-\n-\tmsleep(16);\t/* 16 ms */\n-\tstatus = he_readl(he_dev, RESET_CNTL);\n-\tif ((status & BOARD_RST_STATUS) == 0) {\n-\t\thprintk(\"reset failed\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* 4.5 set bus width */\n-\thost_cntl = he_readl(he_dev, HOST_CNTL);\n-\tif (host_cntl & PCI_BUS_SIZE64)\n-\t\tgen_cntl_0 |= ENBL_64;\n-\telse\n-\t\tgen_cntl_0 &= ~ENBL_64;\n-\n-\tif (disable64 == 1) {\n-\t\thprintk(\"disabling 64-bit pci bus transfers\\n\");\n-\t\tgen_cntl_0 &= ~ENBL_64;\n-\t}\n-\n-\tif (gen_cntl_0 & ENBL_64)\n-\t\thprintk(\"64-bit transfers enabled\\n\");\n-\n-\tpci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);\n-\n-\t/* 4.7 read prom contents */\n-\tfor (i = 0; i < PROD_ID_LEN; ++i)\n-\t\the_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);\n-\n-\the_dev->media = read_prom_byte(he_dev, MEDIA);\n-\n-\tfor (i = 0; i < 6; ++i)\n-\t\tdev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);\n-\n-\thprintk(\"%s%s, %pM\\n\", he_dev->prod_id,\n-\t\the_dev->media & 0x40 ? \"SM\" : \"MM\", dev->esi);\n-\the_dev->atm_dev->link_rate = he_is622(he_dev) ?\n-\t\t\t\t\t\tATM_OC12_PCR : ATM_OC3_PCR;\n-\n-\t/* 4.6 set host endianess */\n-\tlb_swap = he_readl(he_dev, LB_SWAP);\n-\tif (he_is622(he_dev))\n-\t\tlb_swap &= ~XFER_SIZE;\t\t/* 4 cells */\n-\telse\n-\t\tlb_swap |= XFER_SIZE;\t\t/* 8 cells */\n-#ifdef __BIG_ENDIAN\n-\tlb_swap |= DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST;\n-#else\n-\tlb_swap &= ~(DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST |\n-\t\t\tDATA_WR_SWAP | DATA_RD_SWAP | DESC_RD_SWAP);\n-#endif /* __BIG_ENDIAN */\n-\the_writel(he_dev, lb_swap, LB_SWAP);\n-\n-\t/* 4.8 sdram controller initialization */\n-\the_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);\n-\n-\t/* 4.9 initialize rnum value */\n-\tlb_swap |= SWAP_RNUM_MAX(0xf);\n-\the_writel(he_dev, lb_swap, LB_SWAP);\n-\n-\t/* 4.10 initialize the interrupt queues */\n-\tif ((err = he_init_irq(he_dev)) != 0)\n-\t\treturn err;\n-\n-\t/* 4.11 enable pci bus controller state machines */\n-\thost_cntl |= (OUTFF_ENB | CMDFF_ENB |\n-\t\t\t\tQUICK_RD_RETRY | QUICK_WR_RETRY | PERR_INT_ENB);\n-\the_writel(he_dev, host_cntl, HOST_CNTL);\n-\n-\tgen_cntl_0 |= INT_PROC_ENBL|INIT_ENB;\n-\tpci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);\n-\n-\t/*\n-\t * atm network controller initialization\n-\t */\n-\n-\t/* 5.1.1 generic configuration state */\n-\n-\t/*\n-\t *\t\tlocal (cell) buffer memory map\n-\t * \n-\t * HE155 HE622\n-\t * \n-\t * 0 ____________1023 bytes 0 _______________________2047 bytes\n-\t * | | | | |\n-\t * | utility | | rx0 | |\n-\t * 5|____________| 255|___________________| u |\n-\t * 6| | 256| | t |\n-\t * | | | | i |\n-\t * | rx0 | row | tx | l |\n-\t * | | | | i |\n-\t * | | 767|___________________| t |\n-\t * 517|____________| 768| | y |\n-\t * row 518| | | rx1 | |\n-\t * | | 1023|___________________|___|\n-\t * | |\n-\t * | tx |\n-\t * | |\n-\t * | |\n-\t * 1535|____________|\n-\t * 1536| |\n-\t * | rx1 |\n-\t * 2047|____________|\n-\t *\n-\t */\n-\n-\t/* total 4096 connections */\n-\the_dev->vcibits = CONFIG_DEFAULT_VCIBITS;\n-\the_dev->vpibits = CONFIG_DEFAULT_VPIBITS;\n-\n-\tif (nvpibits != -1 && nvcibits != -1 && nvpibits+nvcibits != HE_MAXCIDBITS) {\n-\t\thprintk(\"nvpibits + nvcibits != %d\\n\", HE_MAXCIDBITS);\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (nvpibits != -1) {\n-\t\the_dev->vpibits = nvpibits;\n-\t\the_dev->vcibits = HE_MAXCIDBITS - nvpibits;\n-\t}\n-\n-\tif (nvcibits != -1) {\n-\t\the_dev->vcibits = nvcibits;\n-\t\the_dev->vpibits = HE_MAXCIDBITS - nvcibits;\n-\t}\n-\n-\n-\tif (he_is622(he_dev)) {\n-\t\the_dev->cells_per_row = 40;\n-\t\the_dev->bytes_per_row = 2048;\n-\t\the_dev->r0_numrows = 256;\n-\t\the_dev->tx_numrows = 512;\n-\t\the_dev->r1_numrows = 256;\n-\t\the_dev->r0_startrow = 0;\n-\t\the_dev->tx_startrow = 256;\n-\t\the_dev->r1_startrow = 768;\n-\t} else {\n-\t\the_dev->cells_per_row = 20;\n-\t\the_dev->bytes_per_row = 1024;\n-\t\the_dev->r0_numrows = 512;\n-\t\the_dev->tx_numrows = 1018;\n-\t\the_dev->r1_numrows = 512;\n-\t\the_dev->r0_startrow = 6;\n-\t\the_dev->tx_startrow = 518;\n-\t\the_dev->r1_startrow = 1536;\n-\t}\n-\n-\the_dev->cells_per_lbuf = 4;\n-\the_dev->buffer_limit = 4;\n-\the_dev->r0_numbuffs = he_dev->r0_numrows *\n-\t\t\t\the_dev->cells_per_row / he_dev->cells_per_lbuf;\n-\tif (he_dev->r0_numbuffs > 2560)\n-\t\the_dev->r0_numbuffs = 2560;\n-\n-\the_dev->r1_numbuffs = he_dev->r1_numrows *\n-\t\t\t\the_dev->cells_per_row / he_dev->cells_per_lbuf;\n-\tif (he_dev->r1_numbuffs > 2560)\n-\t\the_dev->r1_numbuffs = 2560;\n-\n-\the_dev->tx_numbuffs = he_dev->tx_numrows *\n-\t\t\t\the_dev->cells_per_row / he_dev->cells_per_lbuf;\n-\tif (he_dev->tx_numbuffs > 5120)\n-\t\the_dev->tx_numbuffs = 5120;\n-\n-\t/* 5.1.2 configure hardware dependent registers */\n-\n-\the_writel(he_dev, \n-\t\tSLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) |\n-\t\tRH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) |\n-\t\t(he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |\n-\t\t(he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),\n-\t\t\t\t\t\t\t\tLBARB);\n-\n-\the_writel(he_dev, BANK_ON |\n-\t\t(he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),\n-\t\t\t\t\t\t\t\tSDRAMCON);\n-\n-\the_writel(he_dev,\n-\t\t(he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |\n-\t\t\t\t\t\tRM_RW_WAIT(1), RCMCONFIG);\n-\the_writel(he_dev,\n-\t\t(he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |\n-\t\t\t\t\t\tTM_RW_WAIT(1), TCMCONFIG);\n-\n-\the_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);\n-\n-\the_writel(he_dev, \n-\t\t(he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |\n-\t\t(he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |\n-\t\tRX_VALVP(he_dev->vpibits) |\n-\t\tRX_VALVC(he_dev->vcibits),\t\t\t RC_CONFIG);\n-\n-\the_writel(he_dev, DRF_THRESH(0x20) |\n-\t\t(he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |\n-\t\tTX_VCI_MASK(he_dev->vcibits) |\n-\t\tLBFREE_CNT(he_dev->tx_numbuffs), \t\tTX_CONFIG);\n-\n-\the_writel(he_dev, 0x0, TXAAL5_PROTO);\n-\n-\the_writel(he_dev, PHY_INT_ENB |\n-\t\t(he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),\n-\t\t\t\t\t\t\t\tRH_CONFIG);\n-\n-\t/* 5.1.3 initialize connection memory */\n-\n-\tfor (i = 0; i < TCM_MEM_SIZE; ++i)\n-\t\the_writel_tcm(he_dev, 0, i);\n-\n-\tfor (i = 0; i < RCM_MEM_SIZE; ++i)\n-\t\the_writel_rcm(he_dev, 0, i);\n-\n-\t/*\n-\t *\ttransmit connection memory map\n-\t *\n-\t * tx memory\n-\t * 0x0 ___________________\n-\t * | |\n-\t * | |\n-\t * | TSRa |\n-\t * | |\n-\t * | |\n-\t * 0x8000|___________________|\n-\t * | |\n-\t * | TSRb |\n-\t * 0xc000|___________________|\n-\t * | |\n-\t * | TSRc |\n-\t * 0xe000|___________________|\n-\t * | TSRd |\n-\t * 0xf000|___________________|\n-\t * | tmABR |\n-\t * 0x10000|___________________|\n-\t * | |\n-\t * | tmTPD |\n-\t * |___________________|\n-\t * | |\n-\t * ....\n-\t * 0x1ffff|___________________|\n-\t *\n-\t *\n-\t */\n-\n-\the_writel(he_dev, CONFIG_TSRB, TSRB_BA);\n-\the_writel(he_dev, CONFIG_TSRC, TSRC_BA);\n-\the_writel(he_dev, CONFIG_TSRD, TSRD_BA);\n-\the_writel(he_dev, CONFIG_TMABR, TMABR_BA);\n-\the_writel(he_dev, CONFIG_TPDBA, TPD_BA);\n-\n-\n-\t/*\n-\t *\treceive connection memory map\n-\t *\n-\t * 0x0 ___________________\n-\t * | |\n-\t * | |\n-\t * | RSRa |\n-\t * | |\n-\t * | |\n-\t * 0x8000|___________________|\n-\t * | |\n-\t * | rx0/1 |\n-\t * | LBM | link lists of local\n-\t * | tx | buffer memory \n-\t * | |\n-\t * 0xd000|___________________|\n-\t * | |\n-\t * | rmABR |\n-\t * 0xe000|___________________|\n-\t * | |\n-\t * | RSRb |\n-\t * |___________________|\n-\t * | |\n-\t * ....\n-\t * 0xffff|___________________|\n-\t */\n-\n-\the_writel(he_dev, 0x08000, RCMLBM_BA);\n-\the_writel(he_dev, 0x0e000, RCMRSRB_BA);\n-\the_writel(he_dev, 0x0d800, RCMABR_BA);\n-\n-\t/* 5.1.4 initialize local buffer free pools linked lists */\n-\n-\the_init_rx_lbfp0(he_dev);\n-\the_init_rx_lbfp1(he_dev);\n-\n-\the_writel(he_dev, 0x0, RLBC_H);\n-\the_writel(he_dev, 0x0, RLBC_T);\n-\the_writel(he_dev, 0x0, RLBC_H2);\n-\n-\the_writel(he_dev, 512, RXTHRSH);\t/* 10% of r0+r1 buffers */\n-\the_writel(he_dev, 256, LITHRSH); \t/* 5% of r0+r1 buffers */\n-\n-\the_init_tx_lbfp(he_dev);\n-\n-\the_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);\n-\n-\t/* 5.1.5 initialize intermediate receive queues */\n-\n-\tif (he_is622(he_dev)) {\n-\t\the_writel(he_dev, 0x000f, G0_INMQ_S);\n-\t\the_writel(he_dev, 0x200f, G0_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x001f, G1_INMQ_S);\n-\t\the_writel(he_dev, 0x201f, G1_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x002f, G2_INMQ_S);\n-\t\the_writel(he_dev, 0x202f, G2_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x003f, G3_INMQ_S);\n-\t\the_writel(he_dev, 0x203f, G3_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x004f, G4_INMQ_S);\n-\t\the_writel(he_dev, 0x204f, G4_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x005f, G5_INMQ_S);\n-\t\the_writel(he_dev, 0x205f, G5_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x006f, G6_INMQ_S);\n-\t\the_writel(he_dev, 0x206f, G6_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x007f, G7_INMQ_S);\n-\t\the_writel(he_dev, 0x207f, G7_INMQ_L);\n-\t} else {\n-\t\the_writel(he_dev, 0x0000, G0_INMQ_S);\n-\t\the_writel(he_dev, 0x0008, G0_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0001, G1_INMQ_S);\n-\t\the_writel(he_dev, 0x0009, G1_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0002, G2_INMQ_S);\n-\t\the_writel(he_dev, 0x000a, G2_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0003, G3_INMQ_S);\n-\t\the_writel(he_dev, 0x000b, G3_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0004, G4_INMQ_S);\n-\t\the_writel(he_dev, 0x000c, G4_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0005, G5_INMQ_S);\n-\t\the_writel(he_dev, 0x000d, G5_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0006, G6_INMQ_S);\n-\t\the_writel(he_dev, 0x000e, G6_INMQ_L);\n-\n-\t\the_writel(he_dev, 0x0007, G7_INMQ_S);\n-\t\the_writel(he_dev, 0x000f, G7_INMQ_L);\n-\t}\n-\n-\t/* 5.1.6 application tunable parameters */\n-\n-\the_writel(he_dev, 0x0, MCC);\n-\the_writel(he_dev, 0x0, OEC);\n-\the_writel(he_dev, 0x0, DCC);\n-\the_writel(he_dev, 0x0, CEC);\n-\t\n-\t/* 5.1.7 cs block initialization */\n-\n-\the_init_cs_block(he_dev);\n-\n-\t/* 5.1.8 cs block connection memory initialization */\n-\t\n-\tif (he_init_cs_block_rcm(he_dev) < 0)\n-\t\treturn -ENOMEM;\n-\n-\t/* 5.1.10 initialize host structures */\n-\n-\the_init_tpdrq(he_dev);\n-\n-\the_dev->tpd_pool = dma_pool_create(\"tpd\", &he_dev->pci_dev->dev,\n-\t\t\t\t\t sizeof(struct he_tpd), TPD_ALIGNMENT, 0);\n-\tif (he_dev->tpd_pool == NULL) {\n-\t\thprintk(\"unable to create tpd dma_pool\\n\");\n-\t\treturn -ENOMEM; \n-\t}\n-\n-\tINIT_LIST_HEAD(&he_dev->outstanding_tpds);\n-\n-\tif (he_init_group(he_dev, 0) != 0)\n-\t\treturn -ENOMEM;\n-\n-\tfor (group = 1; group < HE_NUM_GROUPS; ++group) {\n-\t\the_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));\n-\t\the_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));\n-\t\the_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));\n-\t\the_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),\n-\t\t\t\t\t\tG0_RBPS_BS + (group * 32));\n-\n-\t\the_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));\n-\t\the_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));\n-\t\the_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),\n-\t\t\t\t\t\tG0_RBPL_QI + (group * 32));\n-\t\the_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));\n-\n-\t\the_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));\n-\t\the_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));\n-\t\the_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),\n-\t\t\t\t\t\tG0_RBRQ_Q + (group * 16));\n-\t\the_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));\n-\n-\t\the_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));\n-\t\the_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));\n-\t\the_writel(he_dev, TBRQ_THRESH(0x1),\n-\t\t\t\t\t\tG0_TBRQ_THRESH + (group * 16));\n-\t\the_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));\n-\t}\n-\n-\t/* host status page */\n-\n-\the_dev->hsp = dma_alloc_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t\t sizeof(struct he_hsp),\n-\t\t\t\t\t &he_dev->hsp_phys, GFP_KERNEL);\n-\tif (he_dev->hsp == NULL) {\n-\t\thprintk(\"failed to allocate host status page\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\the_writel(he_dev, he_dev->hsp_phys, HSP_BA);\n-\n-\t/* initialize framer */\n-\n-#ifdef CONFIG_ATM_HE_USE_SUNI\n-\tif (he_isMM(he_dev))\n-\t\tsuni_init(he_dev->atm_dev);\n-\tif (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)\n-\t\the_dev->atm_dev->phy->start(he_dev->atm_dev);\n-#endif /* CONFIG_ATM_HE_USE_SUNI */\n-\n-\tif (sdh) {\n-\t\t/* this really should be in suni.c but for now... */\n-\t\tint val;\n-\n-\t\tval = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);\n-\t\tval = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT);\n-\t\the_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);\n-\t\the_phy_put(he_dev->atm_dev, SUNI_TACP_IUCHP_CLP, SUNI_TACP_IUCHP);\n-\t}\n-\n-\t/* 5.1.12 enable transmit and receive */\n-\n-\treg = he_readl_mbox(he_dev, CS_ERCTL0);\n-\treg |= TX_ENABLE|ER_ENABLE;\n-\the_writel_mbox(he_dev, reg, CS_ERCTL0);\n-\n-\treg = he_readl(he_dev, RC_CONFIG);\n-\treg |= RX_ENABLE;\n-\the_writel(he_dev, reg, RC_CONFIG);\n-\n-\tfor (i = 0; i < HE_NUM_CS_STPER; ++i) {\n-\t\the_dev->cs_stper[i].inuse = 0;\n-\t\the_dev->cs_stper[i].pcr = -1;\n-\t}\n-\the_dev->total_bw = 0;\n-\n-\n-\t/* atm linux initialization */\n-\n-\the_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;\n-\the_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;\n-\n-\the_dev->irq_peak = 0;\n-\the_dev->rbrq_peak = 0;\n-\the_dev->rbpl_peak = 0;\n-\the_dev->tbrq_peak = 0;\n-\n-\tHPRINTK(\"hell bent for leather!\\n\");\n-\n-\treturn 0;\n-}\n-\n-static void\n-he_stop(struct he_dev *he_dev)\n-{\n-\tstruct he_buff *heb, *next;\n-\tstruct pci_dev *pci_dev;\n-\tu32 gen_cntl_0, reg;\n-\tu16 command;\n-\n-\tpci_dev = he_dev->pci_dev;\n-\n-\t/* disable interrupts */\n-\n-\tif (he_dev->membase) {\n-\t\tpci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0);\n-\t\tgen_cntl_0 &= ~(INT_PROC_ENBL | INIT_ENB);\n-\t\tpci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);\n-\n-\t\ttasklet_disable(&he_dev->tasklet);\n-\n-\t\t/* disable recv and transmit */\n-\n-\t\treg = he_readl_mbox(he_dev, CS_ERCTL0);\n-\t\treg &= ~(TX_ENABLE|ER_ENABLE);\n-\t\the_writel_mbox(he_dev, reg, CS_ERCTL0);\n-\n-\t\treg = he_readl(he_dev, RC_CONFIG);\n-\t\treg &= ~(RX_ENABLE);\n-\t\the_writel(he_dev, reg, RC_CONFIG);\n-\t}\n-\n-#ifdef CONFIG_ATM_HE_USE_SUNI\n-\tif (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)\n-\t\the_dev->atm_dev->phy->stop(he_dev->atm_dev);\n-#endif /* CONFIG_ATM_HE_USE_SUNI */\n-\n-\tif (he_dev->irq)\n-\t\tfree_irq(he_dev->irq, he_dev);\n-\n-\tif (he_dev->irq_base)\n-\t\tdma_free_coherent(&he_dev->pci_dev->dev, (CONFIG_IRQ_SIZE + 1)\n-\t\t\t\t * sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);\n-\n-\tif (he_dev->hsp)\n-\t\tdma_free_coherent(&he_dev->pci_dev->dev, sizeof(struct he_hsp),\n-\t\t\t\t he_dev->hsp, he_dev->hsp_phys);\n-\n-\tif (he_dev->rbpl_base) {\n-\t\tlist_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)\n-\t\t\tdma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);\n-\n-\t\tdma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE\n-\t\t\t\t * sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);\n-\t}\n-\n-\tkfree(he_dev->rbpl_virt);\n-\tbitmap_free(he_dev->rbpl_table);\n-\tdma_pool_destroy(he_dev->rbpl_pool);\n-\n-\tif (he_dev->rbrq_base)\n-\t\tdma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),\n-\t\t\t\t he_dev->rbrq_base, he_dev->rbrq_phys);\n-\n-\tif (he_dev->tbrq_base)\n-\t\tdma_free_coherent(&he_dev->pci_dev->dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),\n-\t\t\t\t he_dev->tbrq_base, he_dev->tbrq_phys);\n-\n-\tif (he_dev->tpdrq_base)\n-\t\tdma_free_coherent(&he_dev->pci_dev->dev,\n-\t\t\t\t CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq),\n-\t\t\t\t he_dev->tpdrq_base, he_dev->tpdrq_phys);\n-\n-\tdma_pool_destroy(he_dev->tpd_pool);\n-\n-\tif (he_dev->pci_dev) {\n-\t\tpci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);\n-\t\tcommand &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n-\t\tpci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);\n-\t}\n-\t\n-\tif (he_dev->membase)\n-\t\tiounmap(he_dev->membase);\n-}\n-\n-static struct he_tpd *\n-__alloc_tpd(struct he_dev *he_dev)\n-{\n-\tstruct he_tpd *tpd;\n-\tdma_addr_t mapping;\n-\n-\ttpd = dma_pool_alloc(he_dev->tpd_pool, GFP_ATOMIC, &mapping);\n-\tif (tpd == NULL)\n-\t\treturn NULL;\n-\t\t\t\n-\ttpd->status = TPD_ADDR(mapping);\n-\ttpd->reserved = 0; \n-\ttpd->iovec[0].addr = 0; tpd->iovec[0].len = 0;\n-\ttpd->iovec[1].addr = 0; tpd->iovec[1].len = 0;\n-\ttpd->iovec[2].addr = 0; tpd->iovec[2].len = 0;\n-\n-\treturn tpd;\n-}\n-\n-#define AAL5_LEN(buf,len) \t\t\t\t\t\t\\\n-\t\t\t((((unsigned char *)(buf))[(len)-6] << 8) |\t\\\n-\t\t\t\t(((unsigned char *)(buf))[(len)-5]))\n-\n-/* 2.10.1.2 receive\n- *\n- * aal5 packets can optionally return the tcp checksum in the lower\n- * 16 bits of the crc (RSR0_TCP_CKSUM)\n- */\n-\n-#define TCP_CKSUM(buf,len) \t\t\t\t\t\t\\\n-\t\t\t((((unsigned char *)(buf))[(len)-2] << 8) |\t\\\n-\t\t\t\t(((unsigned char *)(buf))[(len-1)]))\n-\n-static int\n-he_service_rbrq(struct he_dev *he_dev, int group)\n-{\n-\tstruct he_rbrq *rbrq_tail = (struct he_rbrq *)\n-\t\t\t\t((unsigned long)he_dev->rbrq_base |\n-\t\t\t\t\the_dev->hsp->group[group].rbrq_tail);\n-\tunsigned cid, lastcid = -1;\n-\tstruct sk_buff *skb;\n-\tstruct atm_vcc *vcc = NULL;\n-\tstruct he_vcc *he_vcc;\n-\tstruct he_buff *heb, *next;\n-\tint i;\n-\tint pdus_assembled = 0;\n-\tint updated = 0;\n-\n-\tread_lock(&vcc_sklist_lock);\n-\twhile (he_dev->rbrq_head != rbrq_tail) {\n-\t\t++updated;\n-\n-\t\tHPRINTK(\"%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\\n\",\n-\t\t\the_dev->rbrq_head, group,\n-\t\t\tRBRQ_ADDR(he_dev->rbrq_head),\n-\t\t\tRBRQ_BUFLEN(he_dev->rbrq_head),\n-\t\t\tRBRQ_CID(he_dev->rbrq_head),\n-\t\t\tRBRQ_CRC_ERR(he_dev->rbrq_head) ? \" CRC_ERR\" : \"\",\n-\t\t\tRBRQ_LEN_ERR(he_dev->rbrq_head) ? \" LEN_ERR\" : \"\",\n-\t\t\tRBRQ_END_PDU(he_dev->rbrq_head) ? \" END_PDU\" : \"\",\n-\t\t\tRBRQ_AAL5_PROT(he_dev->rbrq_head) ? \" AAL5_PROT\" : \"\",\n-\t\t\tRBRQ_CON_CLOSED(he_dev->rbrq_head) ? \" CON_CLOSED\" : \"\",\n-\t\t\tRBRQ_HBUF_ERR(he_dev->rbrq_head) ? \" HBUF_ERR\" : \"\");\n-\n-\t\ti = RBRQ_ADDR(he_dev->rbrq_head) >> RBP_IDX_OFFSET;\n-\t\theb = he_dev->rbpl_virt[i];\n-\n-\t\tcid = RBRQ_CID(he_dev->rbrq_head);\n-\t\tif (cid != lastcid)\n-\t\t\tvcc = __find_vcc(he_dev, cid);\n-\t\tlastcid = cid;\n-\n-\t\tif (vcc == NULL || (he_vcc = HE_VCC(vcc)) == NULL) {\n-\t\t\thprintk(\"vcc/he_vcc == NULL (cid 0x%x)\\n\", cid);\n-\t\t\tif (!RBRQ_HBUF_ERR(he_dev->rbrq_head)) {\n-\t\t\t\tclear_bit(i, he_dev->rbpl_table);\n-\t\t\t\tlist_del(&heb->entry);\n-\t\t\t\tdma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);\n-\t\t\t}\n-\t\t\t\t\t\n-\t\t\tgoto next_rbrq_entry;\n-\t\t}\n-\n-\t\tif (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {\n-\t\t\thprintk(\"HBUF_ERR! (cid 0x%x)\\n\", cid);\n-\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\tgoto return_host_buffers;\n-\t\t}\n-\n-\t\theb->len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;\n-\t\tclear_bit(i, he_dev->rbpl_table);\n-\t\tlist_move_tail(&heb->entry, &he_vcc->buffers);\n-\t\the_vcc->pdu_len += heb->len;\n-\n-\t\tif (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {\n-\t\t\tlastcid = -1;\n-\t\t\tHPRINTK(\"wake_up rx_waitq (cid 0x%x)\\n\", cid);\n-\t\t\twake_up(&he_vcc->rx_waitq);\n-\t\t\tgoto return_host_buffers;\n-\t\t}\n-\n-\t\tif (!RBRQ_END_PDU(he_dev->rbrq_head))\n-\t\t\tgoto next_rbrq_entry;\n-\n-\t\tif (RBRQ_LEN_ERR(he_dev->rbrq_head)\n-\t\t\t\t|| RBRQ_CRC_ERR(he_dev->rbrq_head)) {\n-\t\t\tHPRINTK(\"%s%s (%d.%d)\\n\",\n-\t\t\t\tRBRQ_CRC_ERR(he_dev->rbrq_head)\n-\t\t\t\t\t\t\t? \"CRC_ERR \" : \"\",\n-\t\t\t\tRBRQ_LEN_ERR(he_dev->rbrq_head)\n-\t\t\t\t\t\t\t? \"LEN_ERR\" : \"\",\n-\t\t\t\t\t\t\tvcc->vpi, vcc->vci);\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\tgoto return_host_buffers;\n-\t\t}\n-\n-\t\tskb = atm_alloc_charge(vcc, he_vcc->pdu_len + rx_skb_reserve,\n-\t\t\t\t\t\t\tGFP_ATOMIC);\n-\t\tif (!skb) {\n-\t\t\tHPRINTK(\"charge failed (%d.%d)\\n\", vcc->vpi, vcc->vci);\n-\t\t\tgoto return_host_buffers;\n-\t\t}\n-\n-\t\tif (rx_skb_reserve > 0)\n-\t\t\tskb_reserve(skb, rx_skb_reserve);\n-\n-\t\t__net_timestamp(skb);\n-\n-\t\tlist_for_each_entry(heb, &he_vcc->buffers, entry)\n-\t\t\tskb_put_data(skb, &heb->data, heb->len);\n-\n-\t\tswitch (vcc->qos.aal) {\n-\t\t\tcase ATM_AAL0:\n-\t\t\t\t/* 2.10.1.5 raw cell receive */\n-\t\t\t\tskb->len = ATM_AAL0_SDU;\n-\t\t\t\tskb_set_tail_pointer(skb, skb->len);\n-\t\t\t\tbreak;\n-\t\t\tcase ATM_AAL5:\n-\t\t\t\t/* 2.10.1.2 aal5 receive */\n-\n-\t\t\t\tskb->len = AAL5_LEN(skb->data, he_vcc->pdu_len);\n-\t\t\t\tskb_set_tail_pointer(skb, skb->len);\n-#ifdef USE_CHECKSUM_HW\n-\t\t\t\tif (vcc->vpi == 0 && vcc->vci >= ATM_NOT_RSV_VCI) {\n-\t\t\t\t\tskb->ip_summed = CHECKSUM_COMPLETE;\n-\t\t\t\t\tskb->csum = TCP_CKSUM(skb->data,\n-\t\t\t\t\t\t\the_vcc->pdu_len);\n-\t\t\t\t}\n-#endif\n-\t\t\t\tbreak;\n-\t\t}\n-\n-#ifdef should_never_happen\n-\t\tif (skb->len > vcc->qos.rxtp.max_sdu)\n-\t\t\thprintk(\"pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)! cid 0x%x\\n\", skb->len, vcc->qos.rxtp.max_sdu, cid);\n-#endif\n-\n-#ifdef notdef\n-\t\tATM_SKB(skb)->vcc = vcc;\n-#endif\n-\t\tspin_unlock(&he_dev->global_lock);\n-\t\tvcc->push(vcc, skb);\n-\t\tspin_lock(&he_dev->global_lock);\n-\n-\t\tatomic_inc(&vcc->stats->rx);\n-\n-return_host_buffers:\n-\t\t++pdus_assembled;\n-\n-\t\tlist_for_each_entry_safe(heb, next, &he_vcc->buffers, entry)\n-\t\t\tdma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);\n-\t\tINIT_LIST_HEAD(&he_vcc->buffers);\n-\t\the_vcc->pdu_len = 0;\n-\n-next_rbrq_entry:\n-\t\the_dev->rbrq_head = (struct he_rbrq *)\n-\t\t\t\t((unsigned long) he_dev->rbrq_base |\n-\t\t\t\t\tRBRQ_MASK(he_dev->rbrq_head + 1));\n-\n-\t}\n-\tread_unlock(&vcc_sklist_lock);\n-\n-\tif (updated) {\n-\t\tif (updated > he_dev->rbrq_peak)\n-\t\t\the_dev->rbrq_peak = updated;\n-\n-\t\the_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),\n-\t\t\t\t\t\tG0_RBRQ_H + (group * 16));\n-\t}\n-\n-\treturn pdus_assembled;\n-}\n-\n-static void\n-he_service_tbrq(struct he_dev *he_dev, int group)\n-{\n-\tstruct he_tbrq *tbrq_tail = (struct he_tbrq *)\n-\t\t\t\t((unsigned long)he_dev->tbrq_base |\n-\t\t\t\t\the_dev->hsp->group[group].tbrq_tail);\n-\tstruct he_tpd *tpd;\n-\tint slot, updated = 0;\n-\tstruct he_tpd *__tpd;\n-\n-\t/* 2.1.6 transmit buffer return queue */\n-\n-\twhile (he_dev->tbrq_head != tbrq_tail) {\n-\t\t++updated;\n-\n-\t\tHPRINTK(\"tbrq%d 0x%x%s%s\\n\",\n-\t\t\tgroup,\n-\t\t\tTBRQ_TPD(he_dev->tbrq_head), \n-\t\t\tTBRQ_EOS(he_dev->tbrq_head) ? \" EOS\" : \"\",\n-\t\t\tTBRQ_MULTIPLE(he_dev->tbrq_head) ? \" MULTIPLE\" : \"\");\n-\t\ttpd = NULL;\n-\t\tlist_for_each_entry(__tpd, &he_dev->outstanding_tpds, entry) {\n-\t\t\tif (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {\n-\t\t\t\ttpd = __tpd;\n-\t\t\t\tlist_del(&__tpd->entry);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\tif (tpd == NULL) {\n-\t\t\thprintk(\"unable to locate tpd for dma buffer %x\\n\",\n-\t\t\t\t\t\tTBRQ_TPD(he_dev->tbrq_head));\n-\t\t\tgoto next_tbrq_entry;\n-\t\t}\n-\n-\t\tif (TBRQ_EOS(he_dev->tbrq_head)) {\n-\t\t\tHPRINTK(\"wake_up(tx_waitq) cid 0x%x\\n\",\n-\t\t\t\the_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));\n-\t\t\tif (tpd->vcc)\n-\t\t\t\twake_up(&HE_VCC(tpd->vcc)->tx_waitq);\n-\n-\t\t\tgoto next_tbrq_entry;\n-\t\t}\n-\n-\t\tfor (slot = 0; slot < TPD_MAXIOV; ++slot) {\n-\t\t\tif (tpd->iovec[slot].addr)\n-\t\t\t\tdma_unmap_single(&he_dev->pci_dev->dev,\n-\t\t\t\t\ttpd->iovec[slot].addr,\n-\t\t\t\t\ttpd->iovec[slot].len & TPD_LEN_MASK,\n-\t\t\t\t\t\t\tDMA_TO_DEVICE);\n-\t\t\tif (tpd->iovec[slot].len & TPD_LST)\n-\t\t\t\tbreak;\n-\t\t\t\t\n-\t\t}\n-\n-\t\tif (tpd->skb) {\t/* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */\n-\t\t\tif (tpd->vcc && tpd->vcc->pop)\n-\t\t\t\ttpd->vcc->pop(tpd->vcc, tpd->skb);\n-\t\t\telse\n-\t\t\t\tdev_kfree_skb_any(tpd->skb);\n-\t\t}\n-\n-next_tbrq_entry:\n-\t\tif (tpd)\n-\t\t\tdma_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));\n-\t\the_dev->tbrq_head = (struct he_tbrq *)\n-\t\t\t\t((unsigned long) he_dev->tbrq_base |\n-\t\t\t\t\tTBRQ_MASK(he_dev->tbrq_head + 1));\n-\t}\n-\n-\tif (updated) {\n-\t\tif (updated > he_dev->tbrq_peak)\n-\t\t\the_dev->tbrq_peak = updated;\n-\n-\t\the_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),\n-\t\t\t\t\t\tG0_TBRQ_H + (group * 16));\n-\t}\n-}\n-\n-static void\n-he_service_rbpl(struct he_dev *he_dev, int group)\n-{\n-\tstruct he_rbp *new_tail;\n-\tstruct he_rbp *rbpl_head;\n-\tstruct he_buff *heb;\n-\tdma_addr_t mapping;\n-\tint i;\n-\tint moved = 0;\n-\n-\trbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |\n-\t\t\t\t\tRBPL_MASK(he_readl(he_dev, G0_RBPL_S)));\n-\n-\tfor (;;) {\n-\t\tnew_tail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |\n-\t\t\t\t\t\tRBPL_MASK(he_dev->rbpl_tail+1));\n-\n-\t\t/* table 3.42 -- rbpl_tail should never be set to rbpl_head */\n-\t\tif (new_tail == rbpl_head)\n-\t\t\tbreak;\n-\n-\t\ti = find_next_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE, he_dev->rbpl_hint);\n-\t\tif (i > (RBPL_TABLE_SIZE - 1)) {\n-\t\t\ti = find_first_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE);\n-\t\t\tif (i > (RBPL_TABLE_SIZE - 1))\n-\t\t\t\tbreak;\n-\t\t}\n-\t\the_dev->rbpl_hint = i + 1;\n-\n-\t\theb = dma_pool_alloc(he_dev->rbpl_pool, GFP_ATOMIC, &mapping);\n-\t\tif (!heb)\n-\t\t\tbreak;\n-\t\theb->mapping = mapping;\n-\t\tlist_add(&heb->entry, &he_dev->rbpl_outstanding);\n-\t\the_dev->rbpl_virt[i] = heb;\n-\t\tset_bit(i, he_dev->rbpl_table);\n-\t\tnew_tail->idx = i << RBP_IDX_OFFSET;\n-\t\tnew_tail->phys = mapping + offsetof(struct he_buff, data);\n-\n-\t\the_dev->rbpl_tail = new_tail;\n-\t\t++moved;\n-\t} \n-\n-\tif (moved)\n-\t\the_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);\n-}\n-\n-static void\n-he_tasklet(unsigned long data)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = (struct he_dev *) data;\n-\tint group, type;\n-\tint updated = 0;\n-\n-\tHPRINTK(\"tasklet (0x%lx)\\n\", data);\n-\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\n-\twhile (he_dev->irq_head != he_dev->irq_tail) {\n-\t\t++updated;\n-\n-\t\ttype = ITYPE_TYPE(he_dev->irq_head->isw);\n-\t\tgroup = ITYPE_GROUP(he_dev->irq_head->isw);\n-\n-\t\tswitch (type) {\n-\t\t\tcase ITYPE_RBRQ_THRESH:\n-\t\t\t\tHPRINTK(\"rbrq%d threshold\\n\", group);\n-\t\t\t\tfallthrough;\n-\t\t\tcase ITYPE_RBRQ_TIMER:\n-\t\t\t\tif (he_service_rbrq(he_dev, group))\n-\t\t\t\t\the_service_rbpl(he_dev, group);\n-\t\t\t\tbreak;\n-\t\t\tcase ITYPE_TBRQ_THRESH:\n-\t\t\t\tHPRINTK(\"tbrq%d threshold\\n\", group);\n-\t\t\t\tfallthrough;\n-\t\t\tcase ITYPE_TPD_COMPLETE:\n-\t\t\t\the_service_tbrq(he_dev, group);\n-\t\t\t\tbreak;\n-\t\t\tcase ITYPE_RBPL_THRESH:\n-\t\t\t\the_service_rbpl(he_dev, group);\n-\t\t\t\tbreak;\n-\t\t\tcase ITYPE_RBPS_THRESH:\n-\t\t\t\t/* shouldn't happen unless small buffers enabled */\n-\t\t\t\tbreak;\n-\t\t\tcase ITYPE_PHY:\n-\t\t\t\tHPRINTK(\"phy interrupt\\n\");\n-#ifdef CONFIG_ATM_HE_USE_SUNI\n-\t\t\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t\t\t\tif (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)\n-\t\t\t\t\the_dev->atm_dev->phy->interrupt(he_dev->atm_dev);\n-\t\t\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-#endif\n-\t\t\t\tbreak;\n-\t\t\tcase ITYPE_OTHER:\n-\t\t\t\tswitch (type|group) {\n-\t\t\t\t\tcase ITYPE_PARITY:\n-\t\t\t\t\t\thprintk(\"parity error\\n\");\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t\tcase ITYPE_ABORT:\n-\t\t\t\t\t\thprintk(\"abort 0x%x\\n\", he_readl(he_dev, ABORT_ADDR));\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t\tbreak;\n-\t\t\tcase ITYPE_TYPE(ITYPE_INVALID):\n-\t\t\t\t/* see 8.1.1 -- check all queues */\n-\n-\t\t\t\tHPRINTK(\"isw not updated 0x%x\\n\", he_dev->irq_head->isw);\n-\n-\t\t\t\the_service_rbrq(he_dev, 0);\n-\t\t\t\the_service_rbpl(he_dev, 0);\n-\t\t\t\the_service_tbrq(he_dev, 0);\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\thprintk(\"bad isw 0x%x?\\n\", he_dev->irq_head->isw);\n-\t\t}\n-\n-\t\the_dev->irq_head->isw = ITYPE_INVALID;\n-\n-\t\the_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);\n-\t}\n-\n-\tif (updated) {\n-\t\tif (updated > he_dev->irq_peak)\n-\t\t\the_dev->irq_peak = updated;\n-\n-\t\the_writel(he_dev,\n-\t\t\tIRQ_SIZE(CONFIG_IRQ_SIZE) |\n-\t\t\tIRQ_THRESH(CONFIG_IRQ_THRESH) |\n-\t\t\tIRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);\n-\t\t(void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */\n-\t}\n-\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-}\n-\n-static irqreturn_t\n-he_irq_handler(int irq, void *dev_id)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = (struct he_dev * )dev_id;\n-\tint handled = 0;\n-\n-\tif (he_dev == NULL)\n-\t\treturn IRQ_NONE;\n-\n-\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\n-\the_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |\n-\t\t\t\t\t\t(*he_dev->irq_tailoffset << 2));\n-\n-\tif (he_dev->irq_tail == he_dev->irq_head) {\n-\t\tHPRINTK(\"tailoffset not updated?\\n\");\n-\t\the_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |\n-\t\t\t((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));\n-\t\t(void) he_readl(he_dev, INT_FIFO);\t/* 8.1.2 controller errata */\n-\t}\n-\n-#ifdef DEBUG\n-\tif (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)\n-\t\thprintk(\"spurious (or shared) interrupt?\\n\");\n-#endif\n-\n-\tif (he_dev->irq_head != he_dev->irq_tail) {\n-\t\thandled = 1;\n-\t\ttasklet_schedule(&he_dev->tasklet);\n-\t\the_writel(he_dev, INT_CLEAR_A, INT_FIFO);\t/* clear interrupt */\n-\t\t(void) he_readl(he_dev, INT_FIFO);\t\t/* flush posted writes */\n-\t}\n-\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\treturn IRQ_RETVAL(handled);\n-\n-}\n-\n-static __inline__ void\n-__enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)\n-{\n-\tstruct he_tpdrq *new_tail;\n-\n-\tHPRINTK(\"tpdrq %p cid 0x%x -> tpdrq_tail %p\\n\",\n-\t\t\t\t\ttpd, cid, he_dev->tpdrq_tail);\n-\n-\t/* new_tail = he_dev->tpdrq_tail; */\n-\tnew_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |\n-\t\t\t\t\tTPDRQ_MASK(he_dev->tpdrq_tail+1));\n-\n-\t/*\n-\t * check to see if we are about to set the tail == head\n-\t * if true, update the head pointer from the adapter\n-\t * to see if this is really the case (reading the queue\n-\t * head for every enqueue would be unnecessarily slow)\n-\t */\n-\n-\tif (new_tail == he_dev->tpdrq_head) {\n-\t\the_dev->tpdrq_head = (struct he_tpdrq *)\n-\t\t\t(((unsigned long)he_dev->tpdrq_base) |\n-\t\t\t\tTPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));\n-\n-\t\tif (new_tail == he_dev->tpdrq_head) {\n-\t\t\tint slot;\n-\n-\t\t\thprintk(\"tpdrq full (cid 0x%x)\\n\", cid);\n-\t\t\t/*\n-\t\t\t * FIXME\n-\t\t\t * push tpd onto a transmit backlog queue\n-\t\t\t * after service_tbrq, service the backlog\n-\t\t\t * for now, we just drop the pdu\n-\t\t\t */\n-\t\t\tfor (slot = 0; slot < TPD_MAXIOV; ++slot) {\n-\t\t\t\tif (tpd->iovec[slot].addr)\n-\t\t\t\t\tdma_unmap_single(&he_dev->pci_dev->dev,\n-\t\t\t\t\t\ttpd->iovec[slot].addr,\n-\t\t\t\t\t\ttpd->iovec[slot].len & TPD_LEN_MASK,\n-\t\t\t\t\t\t\t\tDMA_TO_DEVICE);\n-\t\t\t}\n-\t\t\tif (tpd->skb) {\n-\t\t\t\tif (tpd->vcc->pop)\n-\t\t\t\t\ttpd->vcc->pop(tpd->vcc, tpd->skb);\n-\t\t\t\telse\n-\t\t\t\t\tdev_kfree_skb_any(tpd->skb);\n-\t\t\t\tatomic_inc(&tpd->vcc->stats->tx_err);\n-\t\t\t}\n-\t\t\tdma_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));\n-\t\t\treturn;\n-\t\t}\n-\t}\n-\n-\t/* 2.1.5 transmit packet descriptor ready queue */\n-\tlist_add_tail(&tpd->entry, &he_dev->outstanding_tpds);\n-\the_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);\n-\the_dev->tpdrq_tail->cid = cid;\n-\twmb();\n-\n-\the_dev->tpdrq_tail = new_tail;\n-\n-\the_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);\n-\t(void) he_readl(he_dev, TPDRQ_T);\t\t/* flush posted writes */\n-}\n-\n-static int\n-he_open(struct atm_vcc *vcc)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = HE_DEV(vcc->dev);\n-\tstruct he_vcc *he_vcc;\n-\tint err = 0;\n-\tunsigned cid, rsr0, rsr1, rsr4, tsr0, tsr0_aal, tsr4, period, reg, clock;\n-\tshort vpi = vcc->vpi;\n-\tint vci = vcc->vci;\n-\n-\tif (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)\n-\t\treturn 0;\n-\n-\tHPRINTK(\"open vcc %p %d.%d\\n\", vcc, vpi, vci);\n-\n-\tset_bit(ATM_VF_ADDR, &vcc->flags);\n-\n-\tcid = he_mkcid(he_dev, vpi, vci);\n-\n-\the_vcc = kmalloc_obj(struct he_vcc, GFP_ATOMIC);\n-\tif (he_vcc == NULL) {\n-\t\thprintk(\"unable to allocate he_vcc during open\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tINIT_LIST_HEAD(&he_vcc->buffers);\n-\the_vcc->pdu_len = 0;\n-\the_vcc->rc_index = -1;\n-\n-\tinit_waitqueue_head(&he_vcc->rx_waitq);\n-\tinit_waitqueue_head(&he_vcc->tx_waitq);\n-\n-\tvcc->dev_data = he_vcc;\n-\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\tint pcr_goal;\n-\n-\t\tpcr_goal = atm_pcr_goal(&vcc->qos.txtp);\n-\t\tif (pcr_goal == 0)\n-\t\t\tpcr_goal = he_dev->atm_dev->link_rate;\n-\t\tif (pcr_goal < 0)\t/* means round down, technically */\n-\t\t\tpcr_goal = -pcr_goal;\n-\n-\t\tHPRINTK(\"open tx cid 0x%x pcr_goal %d\\n\", cid, pcr_goal);\n-\n-\t\tswitch (vcc->qos.aal) {\n-\t\t\tcase ATM_AAL5:\n-\t\t\t\ttsr0_aal = TSR0_AAL5;\n-\t\t\t\ttsr4 = TSR4_AAL5;\n-\t\t\t\tbreak;\n-\t\t\tcase ATM_AAL0:\n-\t\t\t\ttsr0_aal = TSR0_AAL0_SDU;\n-\t\t\t\ttsr4 = TSR4_AAL0_SDU;\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\terr = -EINVAL;\n-\t\t\t\tgoto open_failed;\n-\t\t}\n-\n-\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\t\ttsr0 = he_readl_tsr0(he_dev, cid);\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\t\tif (TSR0_CONN_STATE(tsr0) != 0) {\n-\t\t\thprintk(\"cid 0x%x not idle (tsr0 = 0x%x)\\n\", cid, tsr0);\n-\t\t\terr = -EBUSY;\n-\t\t\tgoto open_failed;\n-\t\t}\n-\n-\t\tswitch (vcc->qos.txtp.traffic_class) {\n-\t\t\tcase ATM_UBR:\n-\t\t\t\t/* 2.3.3.1 open connection ubr */\n-\n-\t\t\t\ttsr0 = TSR0_UBR | TSR0_GROUP(0) | tsr0_aal |\n-\t\t\t\t\tTSR0_USE_WMIN | TSR0_UPDATE_GER;\n-\t\t\t\tbreak;\n-\n-\t\t\tcase ATM_CBR:\n-\t\t\t\t/* 2.3.3.2 open connection cbr */\n-\n-\t\t\t\t/* 8.2.3 cbr scheduler wrap problem -- limit to 90% total link rate */\n-\t\t\t\tif ((he_dev->total_bw + pcr_goal)\n-\t\t\t\t\t> (he_dev->atm_dev->link_rate * 9 / 10))\n-\t\t\t\t{\n-\t\t\t\t\terr = -EBUSY;\n-\t\t\t\t\tgoto open_failed;\n-\t\t\t\t}\n-\n-\t\t\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\t\t\t/* also protects he_dev->cs_stper[] */\n-\n-\t\t\t\t/* find an unused cs_stper register */\n-\t\t\t\tfor (reg = 0; reg < HE_NUM_CS_STPER; ++reg)\n-\t\t\t\t\tif (he_dev->cs_stper[reg].inuse == 0 || \n-\t\t\t\t\t he_dev->cs_stper[reg].pcr == pcr_goal)\n-\t\t\t\t\t\t\tbreak;\n-\n-\t\t\t\tif (reg == HE_NUM_CS_STPER) {\n-\t\t\t\t\terr = -EBUSY;\n-\t\t\t\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t\t\t\t\tgoto open_failed;\n-\t\t\t\t}\n-\n-\t\t\t\the_dev->total_bw += pcr_goal;\n-\n-\t\t\t\the_vcc->rc_index = reg;\n-\t\t\t\t++he_dev->cs_stper[reg].inuse;\n-\t\t\t\the_dev->cs_stper[reg].pcr = pcr_goal;\n-\n-\t\t\t\tclock = he_is622(he_dev) ? 66667000 : 50000000;\n-\t\t\t\tperiod = clock / pcr_goal;\n-\t\t\t\t\n-\t\t\t\tHPRINTK(\"rc_index = %d period = %d\\n\",\n-\t\t\t\t\t\t\t\treg, period);\n-\n-\t\t\t\the_writel_mbox(he_dev, rate_to_atmf(period/2),\n-\t\t\t\t\t\t\tCS_STPER0 + reg);\n-\t\t\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\t\t\t\ttsr0 = TSR0_CBR | TSR0_GROUP(0) | tsr0_aal |\n-\t\t\t\t\t\t\tTSR0_RC_INDEX(reg);\n-\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\terr = -EINVAL;\n-\t\t\t\tgoto open_failed;\n-\t\t}\n-\n-\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\n-\t\the_writel_tsr0(he_dev, tsr0, cid);\n-\t\the_writel_tsr4(he_dev, tsr4 | 1, cid);\n-\t\the_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |\n-\t\t\t\t\tTSR1_PCR(rate_to_atmf(pcr_goal)), cid);\n-\t\the_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);\n-\t\the_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);\n-\n-\t\the_writel_tsr3(he_dev, 0x0, cid);\n-\t\the_writel_tsr5(he_dev, 0x0, cid);\n-\t\the_writel_tsr6(he_dev, 0x0, cid);\n-\t\the_writel_tsr7(he_dev, 0x0, cid);\n-\t\the_writel_tsr8(he_dev, 0x0, cid);\n-\t\the_writel_tsr10(he_dev, 0x0, cid);\n-\t\the_writel_tsr11(he_dev, 0x0, cid);\n-\t\the_writel_tsr12(he_dev, 0x0, cid);\n-\t\the_writel_tsr13(he_dev, 0x0, cid);\n-\t\the_writel_tsr14(he_dev, 0x0, cid);\n-\t\t(void) he_readl_tsr0(he_dev, cid);\t\t/* flush posted writes */\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t}\n-\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\tunsigned aal;\n-\n-\t\tHPRINTK(\"open rx cid 0x%x (rx_waitq %p)\\n\", cid,\n-\t\t \t\t\t\t&HE_VCC(vcc)->rx_waitq);\n-\n-\t\tswitch (vcc->qos.aal) {\n-\t\t\tcase ATM_AAL5:\n-\t\t\t\taal = RSR0_AAL5;\n-\t\t\t\tbreak;\n-\t\t\tcase ATM_AAL0:\n-\t\t\t\taal = RSR0_RAWCELL;\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\terr = -EINVAL;\n-\t\t\t\tgoto open_failed;\n-\t\t}\n-\n-\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\n-\t\trsr0 = he_readl_rsr0(he_dev, cid);\n-\t\tif (rsr0 & RSR0_OPEN_CONN) {\n-\t\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\t\t\thprintk(\"cid 0x%x not idle (rsr0 = 0x%x)\\n\", cid, rsr0);\n-\t\t\terr = -EBUSY;\n-\t\t\tgoto open_failed;\n-\t\t}\n-\n-\t\trsr1 = RSR1_GROUP(0) | RSR1_RBPL_ONLY;\n-\t\trsr4 = RSR4_GROUP(0) | RSR4_RBPL_ONLY;\n-\t\trsr0 = vcc->qos.rxtp.traffic_class == ATM_UBR ? \n-\t\t\t\t(RSR0_EPD_ENABLE|RSR0_PPD_ENABLE) : 0;\n-\n-#ifdef USE_CHECKSUM_HW\n-\t\tif (vpi == 0 && vci >= ATM_NOT_RSV_VCI)\n-\t\t\trsr0 |= RSR0_TCP_CKSUM;\n-#endif\n-\n-\t\the_writel_rsr4(he_dev, rsr4, cid);\n-\t\the_writel_rsr1(he_dev, rsr1, cid);\n-\t\t/* 5.1.11 last parameter initialized should be\n-\t\t\t the open/closed indication in rsr0 */\n-\t\the_writel_rsr0(he_dev,\n-\t\t\trsr0 | RSR0_START_PDU | RSR0_OPEN_CONN | aal, cid);\n-\t\t(void) he_readl_rsr0(he_dev, cid);\t\t/* flush posted writes */\n-\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t}\n-\n-open_failed:\n-\n-\tif (err) {\n-\t\tkfree(he_vcc);\n-\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t}\n-\telse\n-\t\tset_bit(ATM_VF_READY, &vcc->flags);\n-\n-\treturn err;\n-}\n-\n-static void\n-he_close(struct atm_vcc *vcc)\n-{\n-\tunsigned long flags;\n-\tDECLARE_WAITQUEUE(wait, current);\n-\tstruct he_dev *he_dev = HE_DEV(vcc->dev);\n-\tstruct he_tpd *tpd;\n-\tunsigned cid;\n-\tstruct he_vcc *he_vcc = HE_VCC(vcc);\n-#define MAX_RETRY 30\n-\tint retry = 0, sleep = 1, tx_inuse;\n-\n-\tHPRINTK(\"close vcc %p %d.%d\\n\", vcc, vcc->vpi, vcc->vci);\n-\n-\tclear_bit(ATM_VF_READY, &vcc->flags);\n-\tcid = he_mkcid(he_dev, vcc->vpi, vcc->vci);\n-\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\tint timeout;\n-\n-\t\tHPRINTK(\"close rx cid 0x%x\\n\", cid);\n-\n-\t\t/* 2.7.2.2 close receive operation */\n-\n-\t\t/* wait for previous close (if any) to finish */\n-\n-\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\t\twhile (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {\n-\t\t\tHPRINTK(\"close cid 0x%x RCC_BUSY\\n\", cid);\n-\t\t\tudelay(250);\n-\t\t}\n-\n-\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t\tadd_wait_queue(&he_vcc->rx_waitq, &wait);\n-\n-\t\the_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);\n-\t\t(void) he_readl_rsr0(he_dev, cid);\t\t/* flush posted writes */\n-\t\the_writel_mbox(he_dev, cid, RXCON_CLOSE);\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\t\ttimeout = schedule_timeout(30*HZ);\n-\n-\t\tremove_wait_queue(&he_vcc->rx_waitq, &wait);\n-\t\tset_current_state(TASK_RUNNING);\n-\n-\t\tif (timeout == 0)\n-\t\t\thprintk(\"close rx timeout cid 0x%x\\n\", cid);\n-\n-\t\tHPRINTK(\"close rx cid 0x%x complete\\n\", cid);\n-\n-\t}\n-\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\tvolatile unsigned tsr4, tsr0;\n-\t\tint timeout;\n-\n-\t\tHPRINTK(\"close tx cid 0x%x\\n\", cid);\n-\t\t\n-\t\t/* 2.1.2\n-\t\t *\n-\t\t * ... the host must first stop queueing packets to the TPDRQ\n-\t\t * on the connection to be closed, then wait for all outstanding\n-\t\t * packets to be transmitted and their buffers returned to the\n-\t\t * TBRQ. When the last packet on the connection arrives in the\n-\t\t * TBRQ, the host issues the close command to the adapter.\n-\t\t */\n-\n-\t\twhile (((tx_inuse = refcount_read(&sk_atm(vcc)->sk_wmem_alloc)) > 1) &&\n-\t\t (retry < MAX_RETRY)) {\n-\t\t\tmsleep(sleep);\n-\t\t\tif (sleep < 250)\n-\t\t\t\tsleep = sleep * 2;\n-\n-\t\t\t++retry;\n-\t\t}\n-\n-\t\tif (tx_inuse > 1)\n-\t\t\thprintk(\"close tx cid 0x%x tx_inuse = %d\\n\", cid, tx_inuse);\n-\n-\t\t/* 2.3.1.1 generic close operations with flush */\n-\n-\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\t\the_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);\n-\t\t\t\t\t/* also clears TSR4_SESSION_ENDED */\n-\n-\t\tswitch (vcc->qos.txtp.traffic_class) {\n-\t\t\tcase ATM_UBR:\n-\t\t\t\the_writel_tsr1(he_dev, \n-\t\t\t\t\tTSR1_MCR(rate_to_atmf(200000))\n-\t\t\t\t\t| TSR1_PCR(0), cid);\n-\t\t\t\tbreak;\n-\t\t\tcase ATM_CBR:\n-\t\t\t\the_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);\n-\t\t\t\tbreak;\n-\t\t}\n-\t\t(void) he_readl_tsr4(he_dev, cid);\t\t/* flush posted writes */\n-\n-\t\ttpd = __alloc_tpd(he_dev);\n-\t\tif (tpd == NULL) {\n-\t\t\thprintk(\"close tx he_alloc_tpd failed cid 0x%x\\n\", cid);\n-\t\t\tgoto close_tx_incomplete;\n-\t\t}\n-\t\ttpd->status |= TPD_EOS | TPD_INT;\n-\t\ttpd->skb = NULL;\n-\t\ttpd->vcc = vcc;\n-\t\twmb();\n-\n-\t\tset_current_state(TASK_UNINTERRUPTIBLE);\n-\t\tadd_wait_queue(&he_vcc->tx_waitq, &wait);\n-\t\t__enqueue_tpd(he_dev, tpd, cid);\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\t\ttimeout = schedule_timeout(30*HZ);\n-\n-\t\tremove_wait_queue(&he_vcc->tx_waitq, &wait);\n-\t\tset_current_state(TASK_RUNNING);\n-\n-\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\n-\t\tif (timeout == 0) {\n-\t\t\thprintk(\"close tx timeout cid 0x%x\\n\", cid);\n-\t\t\tgoto close_tx_incomplete;\n-\t\t}\n-\n-\t\twhile (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {\n-\t\t\tHPRINTK(\"close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\\n\", cid, tsr4);\n-\t\t\tudelay(250);\n-\t\t}\n-\n-\t\twhile (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {\n-\t\t\tHPRINTK(\"close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\\n\", cid, tsr0);\n-\t\t\tudelay(250);\n-\t\t}\n-\n-close_tx_incomplete:\n-\n-\t\tif (vcc->qos.txtp.traffic_class == ATM_CBR) {\n-\t\t\tint reg = he_vcc->rc_index;\n-\n-\t\t\tHPRINTK(\"cs_stper reg = %d\\n\", reg);\n-\n-\t\t\tif (he_dev->cs_stper[reg].inuse == 0)\n-\t\t\t\thprintk(\"cs_stper[%d].inuse = 0!\\n\", reg);\n-\t\t\telse\n-\t\t\t\t--he_dev->cs_stper[reg].inuse;\n-\n-\t\t\the_dev->total_bw -= he_dev->cs_stper[reg].pcr;\n-\t\t}\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\t\tHPRINTK(\"close tx cid 0x%x complete\\n\", cid);\n-\t}\n-\n-\tkfree(he_vcc);\n-\n-\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-}\n-\n-static int\n-he_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = HE_DEV(vcc->dev);\n-\tunsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);\n-\tstruct he_tpd *tpd;\n-#ifdef USE_SCATTERGATHER\n-\tint i, slot = 0;\n-#endif\n-\n-#define HE_TPD_BUFSIZE 0xffff\n-\n-\tHPRINTK(\"send %d.%d\\n\", vcc->vpi, vcc->vci);\n-\n-\tif ((skb->len > HE_TPD_BUFSIZE) ||\n-\t ((vcc->qos.aal == ATM_AAL0) && (skb->len != ATM_AAL0_SDU))) {\n-\t\thprintk(\"buffer too large (or small) -- %d bytes\\n\", skb->len );\n-\t\tif (vcc->pop)\n-\t\t\tvcc->pop(vcc, skb);\n-\t\telse\n-\t\t\tdev_kfree_skb_any(skb);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\treturn -EINVAL;\n-\t}\n-\n-#ifndef USE_SCATTERGATHER\n-\tif (skb_shinfo(skb)->nr_frags) {\n-\t\thprintk(\"no scatter/gather support\\n\");\n-\t\tif (vcc->pop)\n-\t\t\tvcc->pop(vcc, skb);\n-\t\telse\n-\t\t\tdev_kfree_skb_any(skb);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\treturn -EINVAL;\n-\t}\n-#endif\n-\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\n-\ttpd = __alloc_tpd(he_dev);\n-\tif (tpd == NULL) {\n-\t\tif (vcc->pop)\n-\t\t\tvcc->pop(vcc, skb);\n-\t\telse\n-\t\t\tdev_kfree_skb_any(skb);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tif (vcc->qos.aal == ATM_AAL5)\n-\t\ttpd->status |= TPD_CELLTYPE(TPD_USERCELL);\n-\telse {\n-\t\tchar *pti_clp = (void *) (skb->data + 3);\n-\t\tint clp, pti;\n-\n-\t\tpti = (*pti_clp & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; \n-\t\tclp = (*pti_clp & ATM_HDR_CLP);\n-\t\ttpd->status |= TPD_CELLTYPE(pti);\n-\t\tif (clp)\n-\t\t\ttpd->status |= TPD_CLP;\n-\n-\t\tskb_pull(skb, ATM_AAL0_SDU - ATM_CELL_PAYLOAD);\n-\t}\n-\n-#ifdef USE_SCATTERGATHER\n-\ttpd->iovec[slot].addr = dma_map_single(&he_dev->pci_dev->dev, skb->data,\n-\t\t\t\tskb_headlen(skb), DMA_TO_DEVICE);\n-\ttpd->iovec[slot].len = skb_headlen(skb);\n-\t++slot;\n-\n-\tfor (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {\n-\t\tskb_frag_t *frag = &skb_shinfo(skb)->frags[i];\n-\n-\t\tif (slot == TPD_MAXIOV) {\t/* queue tpd; start new tpd */\n-\t\t\ttpd->vcc = vcc;\n-\t\t\ttpd->skb = NULL;\t/* not the last fragment\n-\t\t\t\t\t\t so dont ->push() yet */\n-\t\t\twmb();\n-\n-\t\t\t__enqueue_tpd(he_dev, tpd, cid);\n-\t\t\ttpd = __alloc_tpd(he_dev);\n-\t\t\tif (tpd == NULL) {\n-\t\t\t\tif (vcc->pop)\n-\t\t\t\t\tvcc->pop(vcc, skb);\n-\t\t\t\telse\n-\t\t\t\t\tdev_kfree_skb_any(skb);\n-\t\t\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\t\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t\t\t\treturn -ENOMEM;\n-\t\t\t}\n-\t\t\ttpd->status |= TPD_USERCELL;\n-\t\t\tslot = 0;\n-\t\t}\n-\n-\t\ttpd->iovec[slot].addr = skb_frag_dma_map(&he_dev->pci_dev->dev,\n-\t\t\t\tfrag, 0, skb_frag_size(frag), DMA_TO_DEVICE);\n-\t\ttpd->iovec[slot].len = skb_frag_size(frag);\n-\t\t++slot;\n-\n-\t}\n-\n-\ttpd->iovec[slot - 1].len |= TPD_LST;\n-#else\n-\ttpd->address0 = dma_map_single(&he_dev->pci_dev->dev, skb->data, skb->len, DMA_TO_DEVICE);\n-\ttpd->length0 = skb->len | TPD_LST;\n-#endif\n-\ttpd->status |= TPD_INT;\n-\n-\ttpd->vcc = vcc;\n-\ttpd->skb = skb;\n-\twmb();\n-\tATM_SKB(skb)->vcc = vcc;\n-\n-\t__enqueue_tpd(he_dev, tpd, cid);\n-\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\tatomic_inc(&vcc->stats->tx);\n-\n-\treturn 0;\n-}\n-\n-static int\n-he_ioctl(struct atm_dev *atm_dev, unsigned int cmd, void __user *arg)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = HE_DEV(atm_dev);\n-\tstruct he_ioctl_reg reg;\n-\tint err = 0;\n-\n-\tswitch (cmd) {\n-\t\tcase HE_GET_REG:\n-\t\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\t\treturn -EPERM;\n-\n-\t\t\tif (copy_from_user(®, arg,\n-\t\t\t\t\t sizeof(struct he_ioctl_reg)))\n-\t\t\t\treturn -EFAULT;\n-\n-\t\t\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\t\t\tswitch (reg.type) {\n-\t\t\t\tcase HE_REGTYPE_PCI:\n-\t\t\t\t\tif (reg.addr >= HE_REGMAP_SIZE) {\n-\t\t\t\t\t\terr = -EINVAL;\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t\t}\n-\n-\t\t\t\t\treg.val = he_readl(he_dev, reg.addr);\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase HE_REGTYPE_RCM:\n-\t\t\t\t\treg.val =\n-\t\t\t\t\t\the_readl_rcm(he_dev, reg.addr);\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase HE_REGTYPE_TCM:\n-\t\t\t\t\treg.val =\n-\t\t\t\t\t\the_readl_tcm(he_dev, reg.addr);\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase HE_REGTYPE_MBOX:\n-\t\t\t\t\treg.val =\n-\t\t\t\t\t\the_readl_mbox(he_dev, reg.addr);\n-\t\t\t\t\tbreak;\n-\t\t\t\tdefault:\n-\t\t\t\t\terr = -EINVAL;\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\t\t\tif (err == 0)\n-\t\t\t\tif (copy_to_user(arg, ®,\n-\t\t\t\t\t\t\tsizeof(struct he_ioctl_reg)))\n-\t\t\t\t\treturn -EFAULT;\n-\t\t\tbreak;\n-\t\tdefault:\n-#ifdef CONFIG_ATM_HE_USE_SUNI\n-\t\t\tif (atm_dev->phy && atm_dev->phy->ioctl)\n-\t\t\t\terr = atm_dev->phy->ioctl(atm_dev, cmd, arg);\n-#else /* CONFIG_ATM_HE_USE_SUNI */\n-\t\t\terr = -EINVAL;\n-#endif /* CONFIG_ATM_HE_USE_SUNI */\n-\t\t\tbreak;\n-\t}\n-\n-\treturn err;\n-}\n-\n-static void\n-he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = HE_DEV(atm_dev);\n-\n-\tHPRINTK(\"phy_put(val 0x%x, addr 0x%lx)\\n\", val, addr);\n-\n-\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\the_writel(he_dev, val, FRAMER + (addr*4));\n-\t(void) he_readl(he_dev, FRAMER + (addr*4));\t\t/* flush posted writes */\n-\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-}\n- \n-\t\n-static unsigned char\n-he_phy_get(struct atm_dev *atm_dev, unsigned long addr)\n-{ \n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = HE_DEV(atm_dev);\n-\tunsigned reg;\n-\n-\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\treg = he_readl(he_dev, FRAMER + (addr*4));\n-\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\tHPRINTK(\"phy_get(addr 0x%lx) =0x%x\\n\", addr, reg);\n-\treturn reg;\n-}\n-\n-static int\n-he_proc_read(struct atm_dev *dev, loff_t *pos, char *page)\n-{\n-\tunsigned long flags;\n-\tstruct he_dev *he_dev = HE_DEV(dev);\n-\tint left, i;\n-#ifdef notdef\n-\tstruct he_rbrq *rbrq_tail;\n-\tstruct he_tpdrq *tpdrq_head;\n-\tint rbpl_head, rbpl_tail;\n-#endif\n-\tstatic long mcc = 0, oec = 0, dcc = 0, cec = 0;\n-\n-\n-\tleft = *pos;\n-\tif (!left--)\n-\t\treturn sprintf(page, \"ATM he driver\\n\");\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"%s%s\\n\\n\",\n-\t\t\the_dev->prod_id, he_dev->media & 0x40 ? \"SM\" : \"MM\");\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"Mismatched Cells VPI/VCI Not Open Dropped Cells RCM Dropped Cells\\n\");\n-\n-\tspin_lock_irqsave(&he_dev->global_lock, flags);\n-\tmcc += he_readl(he_dev, MCC);\n-\toec += he_readl(he_dev, OEC);\n-\tdcc += he_readl(he_dev, DCC);\n-\tcec += he_readl(he_dev, CEC);\n-\tspin_unlock_irqrestore(&he_dev->global_lock, flags);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"%16ld %16ld %13ld %17ld\\n\\n\", \n-\t\t\t\t\t\t\tmcc, oec, dcc, cec);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"irq_size = %d inuse = ? peak = %d\\n\",\n-\t\t\t\tCONFIG_IRQ_SIZE, he_dev->irq_peak);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"tpdrq_size = %d inuse = ?\\n\",\n-\t\t\t\t\t\tCONFIG_TPDRQ_SIZE);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"rbrq_size = %d inuse = ? peak = %d\\n\",\n-\t\t\t\tCONFIG_RBRQ_SIZE, he_dev->rbrq_peak);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"tbrq_size = %d peak = %d\\n\",\n-\t\t\t\t\tCONFIG_TBRQ_SIZE, he_dev->tbrq_peak);\n-\n-\n-#ifdef notdef\n-\trbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));\n-\trbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));\n-\n-\tinuse = rbpl_head - rbpl_tail;\n-\tif (inuse < 0)\n-\t\tinuse += CONFIG_RBPL_SIZE * sizeof(struct he_rbp);\n-\tinuse /= sizeof(struct he_rbp);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"rbpl_size = %d inuse = %d\\n\\n\",\n-\t\t\t\t\t\tCONFIG_RBPL_SIZE, inuse);\n-#endif\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"rate controller periods (cbr)\\n pcr #vc\\n\");\n-\n-\tfor (i = 0; i < HE_NUM_CS_STPER; ++i)\n-\t\tif (!left--)\n-\t\t\treturn sprintf(page, \"cs_stper%-2d %8ld %3d\\n\", i,\n-\t\t\t\t\t\the_dev->cs_stper[i].pcr,\n-\t\t\t\t\t\the_dev->cs_stper[i].inuse);\n-\n-\tif (!left--)\n-\t\treturn sprintf(page, \"total bw (cbr): %d (limit %d)\\n\",\n-\t\t\the_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);\n-\n-\treturn 0;\n-}\n-\n-/* eeprom routines -- see 4.7 */\n-\n-static u8 read_prom_byte(struct he_dev *he_dev, int addr)\n-{\n-\tu32 val = 0, tmp_read = 0;\n-\tint i, j = 0;\n-\tu8 byte_read = 0;\n-\n-\tval = readl(he_dev->membase + HOST_CNTL);\n-\tval &= 0xFFFFE0FF;\n- \n-\t/* Turn on write enable */\n-\tval |= 0x800;\n-\the_writel(he_dev, val, HOST_CNTL);\n- \n-\t/* Send READ instruction */\n-\tfor (i = 0; i < ARRAY_SIZE(readtab); i++) {\n-\t\the_writel(he_dev, val | readtab[i], HOST_CNTL);\n-\t\tudelay(EEPROM_DELAY);\n-\t}\n- \n-\t/* Next, we need to send the byte address to read from */\n-\tfor (i = 7; i >= 0; i--) {\n-\t\the_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);\n-\t\tudelay(EEPROM_DELAY);\n-\t\the_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);\n-\t\tudelay(EEPROM_DELAY);\n-\t}\n- \n-\tj = 0;\n-\n-\tval &= 0xFFFFF7FF; /* Turn off write enable */\n-\the_writel(he_dev, val, HOST_CNTL);\n- \n-\t/* Now, we can read data from the EEPROM by clocking it in */\n-\tfor (i = 7; i >= 0; i--) {\n-\t\the_writel(he_dev, val | clocktab[j++], HOST_CNTL);\n-\t\tudelay(EEPROM_DELAY);\n-\t\ttmp_read = he_readl(he_dev, HOST_CNTL);\n-\t\tbyte_read |= (unsigned char)\n-\t\t\t ((tmp_read & ID_DOUT) >> ID_DOFFSET << i);\n-\t\the_writel(he_dev, val | clocktab[j++], HOST_CNTL);\n-\t\tudelay(EEPROM_DELAY);\n-\t}\n- \n-\the_writel(he_dev, val | ID_CS, HOST_CNTL);\n-\tudelay(EEPROM_DELAY);\n-\n-\treturn byte_read;\n-}\n-\n-MODULE_LICENSE(\"GPL\");\n-MODULE_AUTHOR(\"chas williams \");\n-MODULE_DESCRIPTION(\"ForeRunnerHE ATM Adapter driver\");\n-module_param(disable64, bool, 0);\n-MODULE_PARM_DESC(disable64, \"disable 64-bit pci bus transfers\");\n-module_param(nvpibits, short, 0);\n-MODULE_PARM_DESC(nvpibits, \"numbers of bits for vpi (default 0)\");\n-module_param(nvcibits, short, 0);\n-MODULE_PARM_DESC(nvcibits, \"numbers of bits for vci (default 12)\");\n-module_param(rx_skb_reserve, short, 0);\n-MODULE_PARM_DESC(rx_skb_reserve, \"padding for receive skb (default 16)\");\n-module_param(irq_coalesce, bool, 0);\n-MODULE_PARM_DESC(irq_coalesce, \"use interrupt coalescing (default 1)\");\n-module_param(sdh, bool, 0);\n-MODULE_PARM_DESC(sdh, \"use SDH framing (default 0)\");\n-\n-static const struct pci_device_id he_pci_tbl[] = {\n-\t{ PCI_VDEVICE(FORE, PCI_DEVICE_ID_FORE_HE), 0 },\n-\t{ 0, }\n-};\n-\n-MODULE_DEVICE_TABLE(pci, he_pci_tbl);\n-\n-static struct pci_driver he_driver = {\n-\t.name =\t\t\"he\",\n-\t.probe =\the_init_one,\n-\t.remove =\the_remove_one,\n-\t.id_table =\the_pci_tbl,\n-};\n-\n-module_pci_driver(he_driver);\ndiff --git a/drivers/atm/idt77105.c b/drivers/atm/idt77105.c\ndeleted file mode 100644\nindex 4bbcca7f77c8..000000000000\n--- a/drivers/atm/idt77105.c\n+++ /dev/null\n@@ -1,376 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/* drivers/atm/idt77105.c - IDT77105 (PHY) driver */\n- \n-/* Written 1999 by Greg Banks, NEC Australia . Based on suni.c */\n-\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \"idt77105.h\"\n-\n-#undef GENERAL_DEBUG\n-\n-#ifdef GENERAL_DEBUG\n-#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)\n-#else\n-#define DPRINTK(format,args...)\n-#endif\n-\n-\n-struct idt77105_priv {\n-\tstruct idt77105_stats stats; /* link diagnostics */\n-\tstruct atm_dev *dev;\t\t/* device back-pointer */\n-\tstruct idt77105_priv *next;\n- int loop_mode;\n- unsigned char old_mcr; /* storage of MCR reg while signal lost */\n-};\n-\n-static DEFINE_SPINLOCK(idt77105_priv_lock);\n-\n-#define PRIV(dev) ((struct idt77105_priv *) dev->phy_data)\n-\n-#define PUT(val,reg) dev->ops->phy_put(dev,val,IDT77105_##reg)\n-#define GET(reg) dev->ops->phy_get(dev,IDT77105_##reg)\n-\n-static void idt77105_stats_timer_func(struct timer_list *);\n-static void idt77105_restart_timer_func(struct timer_list *);\n-\n-\n-static DEFINE_TIMER(stats_timer, idt77105_stats_timer_func);\n-static DEFINE_TIMER(restart_timer, idt77105_restart_timer_func);\n-static int start_timer = 1;\n-static struct idt77105_priv *idt77105_all = NULL;\n-\n-/*\n- * Retrieve the value of one of the IDT77105's counters.\n- * `counter' is one of the IDT77105_CTRSEL_* constants.\n- */\n-static u16 get_counter(struct atm_dev *dev, int counter)\n-{\n- u16 val;\n- \n- /* write the counter bit into PHY register 6 */\n- PUT(counter, CTRSEL);\n- /* read the low 8 bits from register 4 */\n- val = GET(CTRLO);\n- /* read the high 8 bits from register 5 */\n- val |= GET(CTRHI)<<8;\n- \n- return val;\n-}\n-\n-/*\n- * Timer function called every second to gather statistics\n- * from the 77105. This is done because the h/w registers\n- * will overflow if not read at least once per second. The\n- * kernel's stats are much higher precision. Also, having\n- * a separate copy of the stats allows implementation of\n- * an ioctl which gathers the stats *without* zero'ing them.\n- */\n-static void idt77105_stats_timer_func(struct timer_list *unused)\n-{\n-\tstruct idt77105_priv *walk;\n-\tstruct atm_dev *dev;\n-\tstruct idt77105_stats *stats;\n-\n- DPRINTK(\"IDT77105 gathering statistics\\n\");\n-\tfor (walk = idt77105_all; walk; walk = walk->next) {\n-\t\tdev = walk->dev;\n- \n-\t\tstats = &walk->stats;\n- stats->symbol_errors += get_counter(dev, IDT77105_CTRSEL_SEC);\n- stats->tx_cells += get_counter(dev, IDT77105_CTRSEL_TCC);\n- stats->rx_cells += get_counter(dev, IDT77105_CTRSEL_RCC);\n- stats->rx_hec_errors += get_counter(dev, IDT77105_CTRSEL_RHEC);\n-\t}\n- if (!start_timer) mod_timer(&stats_timer,jiffies+IDT77105_STATS_TIMER_PERIOD);\n-}\n-\n-\n-/*\n- * A separate timer func which handles restarting PHY chips which\n- * have had the cable re-inserted after being pulled out. This is\n- * done by polling the Good Signal Bit in the Interrupt Status\n- * register every 5 seconds. The other technique (checking Good\n- * Signal Bit in the interrupt handler) cannot be used because PHY\n- * interrupts need to be disabled when the cable is pulled out\n- * to avoid lots of spurious cell error interrupts.\n- */\n-static void idt77105_restart_timer_func(struct timer_list *unused)\n-{\n-\tstruct idt77105_priv *walk;\n-\tstruct atm_dev *dev;\n- unsigned char istat;\n-\n- DPRINTK(\"IDT77105 checking for cable re-insertion\\n\");\n-\tfor (walk = idt77105_all; walk; walk = walk->next) {\n-\t\tdev = walk->dev;\n- \n- if (dev->signal != ATM_PHY_SIG_LOST)\n- continue;\n- \n- istat = GET(ISTAT); /* side effect: clears all interrupt status bits */\n- if (istat & IDT77105_ISTAT_GOODSIG) {\n- /* Found signal again */\n- atm_dev_signal_change(dev, ATM_PHY_SIG_FOUND);\n-\t printk(KERN_NOTICE \"%s(itf %d): signal detected again\\n\",\n- dev->type,dev->number);\n- /* flush the receive FIFO */\n- PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG);\n- /* re-enable interrupts */\n-\t PUT( walk->old_mcr ,MCR);\n- }\n-\t}\n- if (!start_timer) mod_timer(&restart_timer,jiffies+IDT77105_RESTART_TIMER_PERIOD);\n-}\n-\n-\n-static int fetch_stats(struct atm_dev *dev,struct idt77105_stats __user *arg,int zero)\n-{\n-\tunsigned long flags;\n-\tstruct idt77105_stats stats;\n-\n-\tspin_lock_irqsave(&idt77105_priv_lock, flags);\n-\tmemcpy(&stats, &PRIV(dev)->stats, sizeof(struct idt77105_stats));\n-\tif (zero)\n-\t\tmemset(&PRIV(dev)->stats, 0, sizeof(struct idt77105_stats));\n-\tspin_unlock_irqrestore(&idt77105_priv_lock, flags);\n-\tif (arg == NULL)\n-\t\treturn 0;\n-\treturn copy_to_user(arg, &stats,\n-\t\t sizeof(struct idt77105_stats)) ? -EFAULT : 0;\n-}\n-\n-\n-static int set_loopback(struct atm_dev *dev,int mode)\n-{\n-\tint diag;\n-\n-\tdiag = GET(DIAG) & ~IDT77105_DIAG_LCMASK;\n-\tswitch (mode) {\n-\t\tcase ATM_LM_NONE:\n-\t\t\tbreak;\n-\t\tcase ATM_LM_LOC_ATM:\n-\t\t\tdiag |= IDT77105_DIAG_LC_PHY_LOOPBACK;\n-\t\t\tbreak;\n-\t\tcase ATM_LM_RMT_ATM:\n-\t\t\tdiag |= IDT77105_DIAG_LC_LINE_LOOPBACK;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t}\n-\tPUT(diag,DIAG);\n-\tprintk(KERN_NOTICE \"%s(%d) Loopback mode is: %s\\n\", dev->type,\n-\t dev->number,\n-\t (mode == ATM_LM_NONE ? \"NONE\" : \n-\t (mode == ATM_LM_LOC_ATM ? \"DIAG (local)\" :\n-\t\t(mode == IDT77105_DIAG_LC_LINE_LOOPBACK ? \"LOOP (remote)\" :\n-\t\t \"unknown\")))\n-\t\t );\n-\tPRIV(dev)->loop_mode = mode;\n-\treturn 0;\n-}\n-\n-\n-static int idt77105_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)\n-{\n- printk(KERN_NOTICE \"%s(%d) idt77105_ioctl() called\\n\",dev->type,dev->number);\n-\tswitch (cmd) {\n-\t\tcase IDT77105_GETSTATZ:\n-\t\t\tif (!capable(CAP_NET_ADMIN)) return -EPERM;\n-\t\t\tfallthrough;\n-\t\tcase IDT77105_GETSTAT:\n-\t\t\treturn fetch_stats(dev, arg, cmd == IDT77105_GETSTATZ);\n-\t\tcase ATM_SETLOOP:\n-\t\t\treturn set_loopback(dev,(int)(unsigned long) arg);\n-\t\tcase ATM_GETLOOP:\n-\t\t\treturn put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?\n-\t\t\t -EFAULT : 0;\n-\t\tcase ATM_QUERYLOOP:\n-\t\t\treturn put_user(ATM_LM_LOC_ATM | ATM_LM_RMT_ATM,\n-\t\t\t (int __user *) arg) ? -EFAULT : 0;\n-\t\tdefault:\n-\t\t\treturn -ENOIOCTLCMD;\n-\t}\n-}\n-\n-\n-\n-static void idt77105_int(struct atm_dev *dev)\n-{\n- unsigned char istat;\n- \n- istat = GET(ISTAT); /* side effect: clears all interrupt status bits */\n- \n- DPRINTK(\"IDT77105 generated an interrupt, istat=%02x\\n\", (unsigned)istat);\n- \n- if (istat & IDT77105_ISTAT_RSCC) {\n- /* Rx Signal Condition Change - line went up or down */\n- if (istat & IDT77105_ISTAT_GOODSIG) { /* signal detected again */\n- /* This should not happen (restart timer does it) but JIC */\n-\t\tatm_dev_signal_change(dev, ATM_PHY_SIG_FOUND);\n- } else { /* signal lost */\n- /*\n- * Disable interrupts and stop all transmission and\n- * reception - the restart timer will restore these.\n- */\n- PRIV(dev)->old_mcr = GET(MCR);\n-\t PUT(\n- (PRIV(dev)->old_mcr|\n- IDT77105_MCR_DREC|\n- IDT77105_MCR_DRIC|\n- IDT77105_MCR_HALTTX\n- ) & ~IDT77105_MCR_EIP, MCR);\n-\t\tatm_dev_signal_change(dev, ATM_PHY_SIG_LOST);\n-\t printk(KERN_NOTICE \"%s(itf %d): signal lost\\n\",\n- dev->type,dev->number);\n- }\n- }\n- \n- if (istat & IDT77105_ISTAT_RFO) {\n- /* Rx FIFO Overrun -- perform a FIFO flush */\n- PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG);\n-\t printk(KERN_NOTICE \"%s(itf %d): receive FIFO overrun\\n\",\n- dev->type,dev->number);\n- }\n-#ifdef GENERAL_DEBUG\n- if (istat & (IDT77105_ISTAT_HECERR | IDT77105_ISTAT_SCR |\n- IDT77105_ISTAT_RSE)) {\n- /* normally don't care - just report in stats */\n-\t printk(KERN_NOTICE \"%s(itf %d): received cell with error\\n\",\n- dev->type,dev->number);\n- }\n-#endif\n-}\n-\n-\n-static int idt77105_start(struct atm_dev *dev)\n-{\n-\tunsigned long flags;\n-\n-\tif (!(dev->phy_data = kmalloc_obj(struct idt77105_priv)))\n-\t\treturn -ENOMEM;\n-\tPRIV(dev)->dev = dev;\n-\tspin_lock_irqsave(&idt77105_priv_lock, flags);\n-\tPRIV(dev)->next = idt77105_all;\n-\tidt77105_all = PRIV(dev);\n-\tspin_unlock_irqrestore(&idt77105_priv_lock, flags);\n-\tmemset(&PRIV(dev)->stats,0,sizeof(struct idt77105_stats));\n- \n- /* initialise dev->signal from Good Signal Bit */\n-\tatm_dev_signal_change(dev,\n-\t\tGET(ISTAT) & IDT77105_ISTAT_GOODSIG ?\n-\t\tATM_PHY_SIG_FOUND : ATM_PHY_SIG_LOST);\n-\tif (dev->signal == ATM_PHY_SIG_LOST)\n-\t\tprintk(KERN_WARNING \"%s(itf %d): no signal\\n\",dev->type,\n-\t\t dev->number);\n-\n- /* initialise loop mode from hardware */\n- switch ( GET(DIAG) & IDT77105_DIAG_LCMASK ) {\n- case IDT77105_DIAG_LC_NORMAL:\n- PRIV(dev)->loop_mode = ATM_LM_NONE;\n- break;\n- case IDT77105_DIAG_LC_PHY_LOOPBACK:\n- PRIV(dev)->loop_mode = ATM_LM_LOC_ATM;\n- break;\n- case IDT77105_DIAG_LC_LINE_LOOPBACK:\n- PRIV(dev)->loop_mode = ATM_LM_RMT_ATM;\n- break;\n- }\n- \n- /* enable interrupts, e.g. on loss of signal */\n- PRIV(dev)->old_mcr = GET(MCR);\n- if (dev->signal == ATM_PHY_SIG_FOUND) {\n- PRIV(dev)->old_mcr |= IDT77105_MCR_EIP;\n-\t PUT(PRIV(dev)->old_mcr, MCR);\n- }\n-\n- \n-\tidt77105_stats_timer_func(0); /* clear 77105 counters */\n-\t(void) fetch_stats(dev,NULL,1); /* clear kernel counters */\n- \n-\tspin_lock_irqsave(&idt77105_priv_lock, flags);\n-\tif (start_timer) {\n-\t\tstart_timer = 0;\n- \n-\t\tstats_timer.expires = jiffies+IDT77105_STATS_TIMER_PERIOD;\n-\t\tadd_timer(&stats_timer);\n- \n-\t\trestart_timer.expires = jiffies+IDT77105_RESTART_TIMER_PERIOD;\n-\t\tadd_timer(&restart_timer);\n-\t}\n-\tspin_unlock_irqrestore(&idt77105_priv_lock, flags);\n-\treturn 0;\n-}\n-\n-\n-static int idt77105_stop(struct atm_dev *dev)\n-{\n-\tstruct idt77105_priv *walk, *prev;\n-\n- DPRINTK(\"%s(itf %d): stopping IDT77105\\n\",dev->type,dev->number);\n- \n- /* disable interrupts */\n-\tPUT( GET(MCR) & ~IDT77105_MCR_EIP, MCR );\n- \n- /* detach private struct from atm_dev & free */\n-\tfor (prev = NULL, walk = idt77105_all ;\n- walk != NULL;\n- prev = walk, walk = walk->next) {\n- if (walk->dev == dev) {\n- if (prev != NULL)\n- prev->next = walk->next;\n- else\n- idt77105_all = walk->next;\n-\t dev->phy = NULL;\n- dev->phy_data = NULL;\n- kfree(walk);\n- break;\n- }\n- }\n-\n-\treturn 0;\n-}\n-\n-\n-static const struct atmphy_ops idt77105_ops = {\n-\t.start = \tidt77105_start,\n-\t.ioctl =\tidt77105_ioctl,\n-\t.interrupt =\tidt77105_int,\n-\t.stop =\t\tidt77105_stop,\n-};\n-\n-\n-int idt77105_init(struct atm_dev *dev)\n-{\n-\tdev->phy = &idt77105_ops;\n-\treturn 0;\n-}\n-\n-EXPORT_SYMBOL(idt77105_init);\n-\n-static void __exit idt77105_exit(void)\n-{\n-\t/* turn off timers */\n-\ttimer_delete_sync(&stats_timer);\n-\ttimer_delete_sync(&restart_timer);\n-}\n-\n-module_exit(idt77105_exit);\n-\n-MODULE_DESCRIPTION(\"IDT77105 PHY driver\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c\ndeleted file mode 100644\nindex 7f8aaf5e6e43..000000000000\n--- a/drivers/atm/idt77252.c\n+++ /dev/null\n@@ -1,3797 +0,0 @@\n-/******************************************************************* \n- *\n- * Copyright (c) 2000 ATecoM GmbH \n- *\n- * The author may be reached at ecd@atecom.com.\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; either version 2 of the License, or (at your\n- * option) any later version.\n- *\n- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED\n- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN\n- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF\n- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- *\n- * You should have received a copy of the GNU General Public License along\n- * with this program; if not, write to the Free Software Foundation, Inc.,\n- * 675 Mass Ave, Cambridge, MA 02139, USA.\n- *\n- *******************************************************************/\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \n-#include \n-#include \n-#include \n-\n-#ifdef CONFIG_ATM_IDT77252_USE_SUNI\n-#include \"suni.h\"\n-#endif /* CONFIG_ATM_IDT77252_USE_SUNI */\n-\n-\n-#include \"idt77252.h\"\n-#include \"idt77252_tables.h\"\n-\n-static unsigned int vpibits = 1;\n-\n-\n-#define ATM_IDT77252_SEND_IDLE 1\n-\n-\n-/*\n- * Debug HACKs.\n- */\n-#define DEBUG_MODULE 1\n-#undef HAVE_EEPROM\t/* does not work, yet. */\n-\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-static unsigned long debug = DBG_GENERAL;\n-#endif\n-\n-\n-#define SAR_RX_DELAY\t(SAR_CFG_RXINT_NODELAY)\n-\n-\n-/*\n- * SCQ Handling.\n- */\n-static struct scq_info *alloc_scq(struct idt77252_dev *, int);\n-static void free_scq(struct idt77252_dev *, struct scq_info *);\n-static int queue_skb(struct idt77252_dev *, struct vc_map *,\n-\t\t struct sk_buff *, int oam);\n-static void drain_scq(struct idt77252_dev *, struct vc_map *);\n-static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);\n-static void fill_scd(struct idt77252_dev *, struct scq_info *, int);\n-\n-/*\n- * FBQ Handling.\n- */\n-static int push_rx_skb(struct idt77252_dev *,\n-\t\t struct sk_buff *, int queue);\n-static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);\n-static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);\n-static void recycle_rx_pool_skb(struct idt77252_dev *,\n-\t\t\t\tstruct rx_pool *);\n-static void add_rx_skb(struct idt77252_dev *, int queue,\n-\t\t unsigned int size, unsigned int count);\n-\n-/*\n- * RSQ Handling.\n- */\n-static int init_rsq(struct idt77252_dev *);\n-static void deinit_rsq(struct idt77252_dev *);\n-static void idt77252_rx(struct idt77252_dev *);\n-\n-/*\n- * TSQ handling.\n- */\n-static int init_tsq(struct idt77252_dev *);\n-static void deinit_tsq(struct idt77252_dev *);\n-static void idt77252_tx(struct idt77252_dev *);\n-\n-\n-/*\n- * ATM Interface.\n- */\n-static void idt77252_dev_close(struct atm_dev *dev);\n-static int idt77252_open(struct atm_vcc *vcc);\n-static void idt77252_close(struct atm_vcc *vcc);\n-static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);\n-static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,\n-\t\t\t int flags);\n-static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,\n-\t\t\t unsigned long addr);\n-static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);\n-static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,\n-\t\t\t int flags);\n-static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,\n-\t\t\t char *page);\n-static void idt77252_softint(struct work_struct *work);\n-\n-\n-static const struct atmdev_ops idt77252_ops =\n-{\n-\t.dev_close\t= idt77252_dev_close,\n-\t.open\t\t= idt77252_open,\n-\t.close\t\t= idt77252_close,\n-\t.send\t\t= idt77252_send,\n-\t.send_oam\t= idt77252_send_oam,\n-\t.phy_put\t= idt77252_phy_put,\n-\t.phy_get\t= idt77252_phy_get,\n-\t.change_qos\t= idt77252_change_qos,\n-\t.proc_read\t= idt77252_proc_read,\n-\t.owner\t\t= THIS_MODULE\n-};\n-\n-static struct idt77252_dev *idt77252_chain = NULL;\n-static unsigned int idt77252_sram_write_errors = 0;\n-\n-/*****************************************************************************/\n-/* */\n-/* I/O and Utility Bus */\n-/* */\n-/*****************************************************************************/\n-\n-static void\n-waitfor_idle(struct idt77252_dev *card)\n-{\n-\tu32 stat;\n-\n-\tstat = readl(SAR_REG_STAT);\n-\twhile (stat & SAR_STAT_CMDBZ)\n-\t\tstat = readl(SAR_REG_STAT);\n-}\n-\n-static u32\n-read_sram(struct idt77252_dev *card, unsigned long addr)\n-{\n-\tunsigned long flags;\n-\tu32 value;\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twritel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);\n-\twaitfor_idle(card);\n-\tvalue = readl(SAR_REG_DR0);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\treturn value;\n-}\n-\n-static void\n-write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)\n-{\n-\tunsigned long flags;\n-\n-\tif ((idt77252_sram_write_errors == 0) &&\n-\t (((addr > card->tst[0] + card->tst_size - 2) &&\n-\t (addr < card->tst[0] + card->tst_size)) ||\n-\t ((addr > card->tst[1] + card->tst_size - 2) &&\n-\t (addr < card->tst[1] + card->tst_size)))) {\n-\t\tprintk(\"%s: ERROR: TST JMP section at %08lx written: %08x\\n\",\n-\t\t card->name, addr, value);\n-\t}\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twritel(value, SAR_REG_DR0);\n-\twritel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);\n-\twaitfor_idle(card);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-}\n-\n-static u8\n-read_utility(void *dev, unsigned long ubus_addr)\n-{\n-\tstruct idt77252_dev *card = dev;\n-\tunsigned long flags;\n-\tu8 value;\n-\n-\tif (!card) {\n-\t\tprintk(\"Error: No such device.\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twritel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);\n-\twaitfor_idle(card);\n-\tvalue = readl(SAR_REG_DR0);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\treturn value;\n-}\n-\n-static void\n-write_utility(void *dev, unsigned long ubus_addr, u8 value)\n-{\n-\tstruct idt77252_dev *card = dev;\n-\tunsigned long flags;\n-\n-\tif (!card) {\n-\t\tprintk(\"Error: No such device.\\n\");\n-\t\treturn;\n-\t}\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twritel((u32) value, SAR_REG_DR0);\n-\twritel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);\n-\twaitfor_idle(card);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-}\n-\n-#ifdef HAVE_EEPROM\n-static u32 rdsrtab[] =\n-{\n-\tSAR_GP_EECS | SAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO,\t/* 1 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO\t/* 1 */\n-};\n-\n-static u32 wrentab[] =\n-{\n-\tSAR_GP_EECS | SAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO,\t/* 1 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO,\t/* 1 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK\t\t\t/* 0 */\n-};\n-\n-static u32 rdtab[] =\n-{\n-\tSAR_GP_EECS | SAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO,\t/* 1 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO\t/* 1 */\n-};\n-\n-static u32 wrtab[] =\n-{\n-\tSAR_GP_EECS | SAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\t0,\n-\tSAR_GP_EESCLK,\t\t\t/* 0 */\n-\tSAR_GP_EEDO,\n-\tSAR_GP_EESCLK | SAR_GP_EEDO,\t/* 1 */\n-\t0,\n-\tSAR_GP_EESCLK\t\t\t/* 0 */\n-};\n-\n-static u32 clktab[] =\n-{\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0,\n-\tSAR_GP_EESCLK,\n-\t0\n-};\n-\n-static u32\n-idt77252_read_gp(struct idt77252_dev *card)\n-{\n-\tu32 gp;\n-\n-\tgp = readl(SAR_REG_GP);\n-#if 0\n-\tprintk(\"RD: %s\\n\", gp & SAR_GP_EEDI ? \"1\" : \"0\");\n-#endif\n-\treturn gp;\n-}\n-\n-static void\n-idt77252_write_gp(struct idt77252_dev *card, u32 value)\n-{\n-\tunsigned long flags;\n-\n-#if 0\n-\tprintk(\"WR: %s %s %s\\n\", value & SAR_GP_EECS ? \" \" : \"/CS\",\n-\t value & SAR_GP_EESCLK ? \"HIGH\" : \"LOW \",\n-\t value & SAR_GP_EEDO ? \"1\" : \"0\");\n-#endif\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twaitfor_idle(card);\n-\twritel(value, SAR_REG_GP);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-}\n-\n-static u8\n-idt77252_eeprom_read_status(struct idt77252_dev *card)\n-{\n-\tu8 byte;\n-\tu32 gp;\n-\tint i, j;\n-\n-\tgp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);\n-\n-\tfor (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {\n-\t\tidt77252_write_gp(card, gp | rdsrtab[i]);\n-\t\tudelay(5);\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\tbyte = 0;\n-\tfor (i = 0, j = 0; i < 8; i++) {\n-\t\tbyte <<= 1;\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++]);\n-\t\tudelay(5);\n-\n-\t\tbyte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++]);\n-\t\tudelay(5);\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\treturn byte;\n-}\n-\n-static u8\n-idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)\n-{\n-\tu8 byte;\n-\tu32 gp;\n-\tint i, j;\n-\n-\tgp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);\n-\n-\tfor (i = 0; i < ARRAY_SIZE(rdtab); i++) {\n-\t\tidt77252_write_gp(card, gp | rdtab[i]);\n-\t\tudelay(5);\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\tfor (i = 0, j = 0; i < 8; i++) {\n-\t\tidt77252_write_gp(card, gp | clktab[j++] |\n-\t\t\t\t\t(offset & 1 ? SAR_GP_EEDO : 0));\n-\t\tudelay(5);\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++] |\n-\t\t\t\t\t(offset & 1 ? SAR_GP_EEDO : 0));\n-\t\tudelay(5);\n-\n-\t\toffset >>= 1;\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\tbyte = 0;\n-\tfor (i = 0, j = 0; i < 8; i++) {\n-\t\tbyte <<= 1;\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++]);\n-\t\tudelay(5);\n-\n-\t\tbyte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++]);\n-\t\tudelay(5);\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\treturn byte;\n-}\n-\n-static void\n-idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)\n-{\n-\tu32 gp;\n-\tint i, j;\n-\n-\tgp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);\n-\n-\tfor (i = 0; i < ARRAY_SIZE(wrentab); i++) {\n-\t\tidt77252_write_gp(card, gp | wrentab[i]);\n-\t\tudelay(5);\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\tfor (i = 0; i < ARRAY_SIZE(wrtab); i++) {\n-\t\tidt77252_write_gp(card, gp | wrtab[i]);\n-\t\tudelay(5);\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\tfor (i = 0, j = 0; i < 8; i++) {\n-\t\tidt77252_write_gp(card, gp | clktab[j++] |\n-\t\t\t\t\t(offset & 1 ? SAR_GP_EEDO : 0));\n-\t\tudelay(5);\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++] |\n-\t\t\t\t\t(offset & 1 ? SAR_GP_EEDO : 0));\n-\t\tudelay(5);\n-\n-\t\toffset >>= 1;\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\n-\tfor (i = 0, j = 0; i < 8; i++) {\n-\t\tidt77252_write_gp(card, gp | clktab[j++] |\n-\t\t\t\t\t(data & 1 ? SAR_GP_EEDO : 0));\n-\t\tudelay(5);\n-\n-\t\tidt77252_write_gp(card, gp | clktab[j++] |\n-\t\t\t\t\t(data & 1 ? SAR_GP_EEDO : 0));\n-\t\tudelay(5);\n-\n-\t\tdata >>= 1;\n-\t}\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-}\n-\n-static void\n-idt77252_eeprom_init(struct idt77252_dev *card)\n-{\n-\tu32 gp;\n-\n-\tgp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);\n-\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);\n-\tudelay(5);\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);\n-\tudelay(5);\n-\tidt77252_write_gp(card, gp | SAR_GP_EECS);\n-\tudelay(5);\n-}\n-#endif /* HAVE_EEPROM */\n-\n-\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-static void\n-dump_tct(struct idt77252_dev *card, int index)\n-{\n-\tunsigned long tct;\n-\tint i;\n-\n-\ttct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);\n-\n-\tprintk(\"%s: TCT %x:\", card->name, index);\n-\tfor (i = 0; i < 8; i++) {\n-\t\tprintk(\" %08x\", read_sram(card, tct + i));\n-\t}\n-\tprintk(\"\\n\");\n-}\n-\n-static void\n-idt77252_tx_dump(struct idt77252_dev *card)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct vc_map *vc;\n-\tint i;\n-\n-\tprintk(\"%s\\n\", __func__);\n-\tfor (i = 0; i < card->tct_size; i++) {\n-\t\tvc = card->vcs[i];\n-\t\tif (!vc)\n-\t\t\tcontinue;\n-\n-\t\tvcc = NULL;\n-\t\tif (vc->rx_vcc)\n-\t\t\tvcc = vc->rx_vcc;\n-\t\telse if (vc->tx_vcc)\n-\t\t\tvcc = vc->tx_vcc;\n-\n-\t\tif (!vcc)\n-\t\t\tcontinue;\n-\n-\t\tprintk(\"%s: Connection %d:\\n\", card->name, vc->index);\n-\t\tdump_tct(card, vc->index);\n-\t}\n-}\n-#endif\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* SCQ Handling */\n-/* */\n-/*****************************************************************************/\n-\n-static int\n-sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)\n-{\n-\tstruct sb_pool *pool = &card->sbpool[queue];\n-\tint index;\n-\n-\tindex = pool->index;\n-\twhile (pool->skb[index]) {\n-\t\tindex = (index + 1) & FBQ_MASK;\n-\t\tif (index == pool->index)\n-\t\t\treturn -ENOBUFS;\n-\t}\n-\n-\tpool->skb[index] = skb;\n-\tIDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);\n-\n-\tpool->index = (index + 1) & FBQ_MASK;\n-\treturn 0;\n-}\n-\n-static void\n-sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)\n-{\n-\tunsigned int queue, index;\n-\tu32 handle;\n-\n-\thandle = IDT77252_PRV_POOL(skb);\n-\n-\tqueue = POOL_QUEUE(handle);\n-\tif (queue > 3)\n-\t\treturn;\n-\n-\tindex = POOL_INDEX(handle);\n-\tif (index > FBQ_SIZE - 1)\n-\t\treturn;\n-\n-\tcard->sbpool[queue].skb[index] = NULL;\n-}\n-\n-static struct sk_buff *\n-sb_pool_skb(struct idt77252_dev *card, u32 handle)\n-{\n-\tunsigned int queue, index;\n-\n-\tqueue = POOL_QUEUE(handle);\n-\tif (queue > 3)\n-\t\treturn NULL;\n-\n-\tindex = POOL_INDEX(handle);\n-\tif (index > FBQ_SIZE - 1)\n-\t\treturn NULL;\n-\n-\treturn card->sbpool[queue].skb[index];\n-}\n-\n-static struct scq_info *\n-alloc_scq(struct idt77252_dev *card, int class)\n-{\n-\tstruct scq_info *scq;\n-\n-\tscq = kzalloc_obj(struct scq_info);\n-\tif (!scq)\n-\t\treturn NULL;\n-\tscq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,\n-\t\t\t\t &scq->paddr, GFP_KERNEL);\n-\tif (scq->base == NULL) {\n-\t\tkfree(scq);\n-\t\treturn NULL;\n-\t}\n-\n-\tscq->next = scq->base;\n-\tscq->last = scq->base + (SCQ_ENTRIES - 1);\n-\tatomic_set(&scq->used, 0);\n-\n-\tspin_lock_init(&scq->lock);\n-\tspin_lock_init(&scq->skblock);\n-\n-\tskb_queue_head_init(&scq->transmit);\n-\tskb_queue_head_init(&scq->pending);\n-\n-\tTXPRINTK(\"idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\\n\",\n-\t\t scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);\n-\n-\treturn scq;\n-}\n-\n-static void\n-free_scq(struct idt77252_dev *card, struct scq_info *scq)\n-{\n-\tstruct sk_buff *skb;\n-\tstruct atm_vcc *vcc;\n-\n-\tdma_free_coherent(&card->pcidev->dev, SCQ_SIZE,\n-\t\t\t scq->base, scq->paddr);\n-\n-\twhile ((skb = skb_dequeue(&scq->transmit))) {\n-\t\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\n-\t\tvcc = ATM_SKB(skb)->vcc;\n-\t\tif (vcc->pop)\n-\t\t\tvcc->pop(vcc, skb);\n-\t\telse\n-\t\t\tdev_kfree_skb(skb);\n-\t}\n-\n-\twhile ((skb = skb_dequeue(&scq->pending))) {\n-\t\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\n-\t\tvcc = ATM_SKB(skb)->vcc;\n-\t\tif (vcc->pop)\n-\t\t\tvcc->pop(vcc, skb);\n-\t\telse\n-\t\t\tdev_kfree_skb(skb);\n-\t}\n-\n-\tkfree(scq);\n-}\n-\n-\n-static int\n-push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)\n-{\n-\tstruct scq_info *scq = vc->scq;\n-\tunsigned long flags;\n-\tstruct scqe *tbd;\n-\tint entries;\n-\n-\tTXPRINTK(\"%s: SCQ: next 0x%p\\n\", card->name, scq->next);\n-\n-\tatomic_inc(&scq->used);\n-\tentries = atomic_read(&scq->used);\n-\tif (entries > (SCQ_ENTRIES - 1)) {\n-\t\tatomic_dec(&scq->used);\n-\t\tgoto out;\n-\t}\n-\n-\tskb_queue_tail(&scq->transmit, skb);\n-\n-\tspin_lock_irqsave(&vc->lock, flags);\n-\tif (vc->estimator) {\n-\t\tstruct atm_vcc *vcc = vc->tx_vcc;\n-\t\tstruct sock *sk = sk_atm(vcc);\n-\n-\t\tvc->estimator->cells += (skb->len + 47) / 48;\n-\t\tif (refcount_read(&sk->sk_wmem_alloc) >\n-\t\t (sk->sk_sndbuf >> 1)) {\n-\t\t\tu32 cps = vc->estimator->maxcps;\n-\n-\t\t\tvc->estimator->cps = cps;\n-\t\t\tvc->estimator->avcps = cps << 5;\n-\t\t\tif (vc->lacr < vc->init_er) {\n-\t\t\t\tvc->lacr = vc->init_er;\n-\t\t\t\twritel(TCMDQ_LACR | (vc->lacr << 16) |\n-\t\t\t\t vc->index, SAR_REG_TCMDQ);\n-\t\t\t}\n-\t\t}\n-\t}\n-\tspin_unlock_irqrestore(&vc->lock, flags);\n-\n-\ttbd = &IDT77252_PRV_TBD(skb);\n-\n-\tspin_lock_irqsave(&scq->lock, flags);\n-\tscq->next->word_1 = cpu_to_le32(tbd->word_1 |\n-\t\t\t\t\tSAR_TBD_TSIF | SAR_TBD_GTSI);\n-\tscq->next->word_2 = cpu_to_le32(tbd->word_2);\n-\tscq->next->word_3 = cpu_to_le32(tbd->word_3);\n-\tscq->next->word_4 = cpu_to_le32(tbd->word_4);\n-\n-\tif (scq->next == scq->last)\n-\t\tscq->next = scq->base;\n-\telse\n-\t\tscq->next++;\n-\n-\twrite_sram(card, scq->scd,\n-\t\t scq->paddr +\n-\t\t (u32)((unsigned long)scq->next - (unsigned long)scq->base));\n-\tspin_unlock_irqrestore(&scq->lock, flags);\n-\n-\tscq->trans_start = jiffies;\n-\n-\tif (test_and_clear_bit(VCF_IDLE, &vc->flags)) {\n-\t\twritel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,\n-\t\t SAR_REG_TCMDQ);\n-\t}\n-\n-\tTXPRINTK(\"%d entries in SCQ used (push).\\n\", atomic_read(&scq->used));\n-\n-\tXPRINTK(\"%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\\n\",\n-\t\tcard->name, atomic_read(&scq->used),\n-\t\tread_sram(card, scq->scd + 1), scq->next);\n-\n-\treturn 0;\n-\n-out:\n-\tif (time_after(jiffies, scq->trans_start + HZ)) {\n-\t\tprintk(\"%s: Error pushing TBD for %d.%d\\n\",\n-\t\t card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-\t\tidt77252_tx_dump(card);\n-#endif\n-\t\tscq->trans_start = jiffies;\n-\t}\n-\n-\treturn -ENOBUFS;\n-}\n-\n-\n-static void\n-drain_scq(struct idt77252_dev *card, struct vc_map *vc)\n-{\n-\tstruct scq_info *scq = vc->scq;\n-\tstruct sk_buff *skb;\n-\tstruct atm_vcc *vcc;\n-\n-\tTXPRINTK(\"%s: SCQ (before drain %2d) next = 0x%p.\\n\",\n-\t\t card->name, atomic_read(&scq->used), scq->next);\n-\n-\tskb = skb_dequeue(&scq->transmit);\n-\tif (skb) {\n-\t\tTXPRINTK(\"%s: freeing skb at %p.\\n\", card->name, skb);\n-\n-\t\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\n-\t\tvcc = ATM_SKB(skb)->vcc;\n-\n-\t\tif (vcc->pop)\n-\t\t\tvcc->pop(vcc, skb);\n-\t\telse\n-\t\t\tdev_kfree_skb(skb);\n-\n-\t\tatomic_inc(&vcc->stats->tx);\n-\t}\n-\n-\tatomic_dec(&scq->used);\n-\n-\tspin_lock(&scq->skblock);\n-\twhile ((skb = skb_dequeue(&scq->pending))) {\n-\t\tif (push_on_scq(card, vc, skb)) {\n-\t\t\tskb_queue_head(&vc->scq->pending, skb);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\tspin_unlock(&scq->skblock);\n-}\n-\n-static int\n-queue_skb(struct idt77252_dev *card, struct vc_map *vc,\n-\t struct sk_buff *skb, int oam)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct scqe *tbd;\n-\tunsigned long flags;\n-\tint error;\n-\tint aal;\n-\tu32 word4;\n-\n-\tif (skb->len == 0) {\n-\t\tprintk(\"%s: invalid skb->len (%d)\\n\", card->name, skb->len);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tTXPRINTK(\"%s: Sending %d bytes of data.\\n\",\n-\t\t card->name, skb->len);\n-\n-\ttbd = &IDT77252_PRV_TBD(skb);\n-\tvcc = ATM_SKB(skb)->vcc;\n-\tword4 = (skb->data[0] << 24) | (skb->data[1] << 16) |\n-\t\t\t(skb->data[2] << 8) | (skb->data[3] << 0);\n-\n-\tIDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,\n-\t\t\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\tif (dma_mapping_error(&card->pcidev->dev, IDT77252_PRV_PADDR(skb)))\n-\t\treturn -ENOMEM;\n-\n-\terror = -EINVAL;\n-\n-\tif (oam) {\n-\t\tif (skb->len != 52)\n-\t\t\tgoto errout;\n-\n-\t\ttbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;\n-\t\ttbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;\n-\t\ttbd->word_3 = 0x00000000;\n-\t\ttbd->word_4 = word4;\n-\n-\t\tif (test_bit(VCF_RSV, &vc->flags))\n-\t\t\tvc = card->vcs[0];\n-\n-\t\tgoto done;\n-\t}\n-\n-\tif (test_bit(VCF_RSV, &vc->flags)) {\n-\t\tprintk(\"%s: Trying to transmit on reserved VC\\n\", card->name);\n-\t\tgoto errout;\n-\t}\n-\n-\taal = vcc->qos.aal;\n-\n-\tswitch (aal) {\n-\tcase ATM_AAL0:\n-\tcase ATM_AAL34:\n-\t\tif (skb->len > 52)\n-\t\t\tgoto errout;\n-\n-\t\tif (aal == ATM_AAL0)\n-\t\t\ttbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |\n-\t\t\t\t ATM_CELL_PAYLOAD;\n-\t\telse\n-\t\t\ttbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |\n-\t\t\t\t ATM_CELL_PAYLOAD;\n-\n-\t\ttbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;\n-\t\ttbd->word_3 = 0x00000000;\n-\t\ttbd->word_4 = word4;\n-\t\tbreak;\n-\n-\tcase ATM_AAL5:\n-\t\ttbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;\n-\t\ttbd->word_2 = IDT77252_PRV_PADDR(skb);\n-\t\ttbd->word_3 = skb->len;\n-\t\ttbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |\n-\t\t\t (vcc->vci << SAR_TBD_VCI_SHIFT);\n-\t\tbreak;\n-\n-\tcase ATM_AAL1:\n-\tcase ATM_AAL2:\n-\tdefault:\n-\t\tprintk(\"%s: Traffic type not supported.\\n\", card->name);\n-\t\terror = -EPROTONOSUPPORT;\n-\t\tgoto errout;\n-\t}\n-\n-done:\n-\tspin_lock_irqsave(&vc->scq->skblock, flags);\n-\tskb_queue_tail(&vc->scq->pending, skb);\n-\n-\twhile ((skb = skb_dequeue(&vc->scq->pending))) {\n-\t\tif (push_on_scq(card, vc, skb)) {\n-\t\t\tskb_queue_head(&vc->scq->pending, skb);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\tspin_unlock_irqrestore(&vc->scq->skblock, flags);\n-\n-\treturn 0;\n-\n-errout:\n-\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t skb->len, DMA_TO_DEVICE);\n-\treturn error;\n-}\n-\n-static unsigned long\n-get_free_scd(struct idt77252_dev *card, struct vc_map *vc)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < card->scd_size; i++) {\n-\t\tif (!card->scd2vc[i]) {\n-\t\t\tcard->scd2vc[i] = vc;\n-\t\t\tvc->scd_index = i;\n-\t\t\treturn card->scd_base + i * SAR_SRAM_SCD_SIZE;\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n-static void\n-fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)\n-{\n-\twrite_sram(card, scq->scd, scq->paddr);\n-\twrite_sram(card, scq->scd + 1, 0x00000000);\n-\twrite_sram(card, scq->scd + 2, 0xffffffff);\n-\twrite_sram(card, scq->scd + 3, 0x00000000);\n-}\n-\n-static void\n-clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)\n-{\n-\treturn;\n-}\n-\n-/*****************************************************************************/\n-/* */\n-/* RSQ Handling */\n-/* */\n-/*****************************************************************************/\n-\n-static int\n-init_rsq(struct idt77252_dev *card)\n-{\n-\tstruct rsq_entry *rsqe;\n-\n-\tcard->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,\n-\t\t\t\t\t &card->rsq.paddr, GFP_KERNEL);\n-\tif (card->rsq.base == NULL) {\n-\t\tprintk(\"%s: can't allocate RSQ.\\n\", card->name);\n-\t\treturn -1;\n-\t}\n-\n-\tcard->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;\n-\tcard->rsq.next = card->rsq.last;\n-\tfor (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)\n-\t\trsqe->word_4 = 0;\n-\n-\twritel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,\n-\t SAR_REG_RSQH);\n-\twritel(card->rsq.paddr, SAR_REG_RSQB);\n-\n-\tIPRINTK(\"%s: RSQ base at 0x%lx (0x%x).\\n\", card->name,\n-\t\t(unsigned long) card->rsq.base,\n-\t\treadl(SAR_REG_RSQB));\n-\tIPRINTK(\"%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\\n\",\n-\t\tcard->name,\n-\t\treadl(SAR_REG_RSQH),\n-\t\treadl(SAR_REG_RSQB),\n-\t\treadl(SAR_REG_RSQT));\n-\n-\treturn 0;\n-}\n-\n-static void\n-deinit_rsq(struct idt77252_dev *card)\n-{\n-\tdma_free_coherent(&card->pcidev->dev, RSQSIZE,\n-\t\t\t card->rsq.base, card->rsq.paddr);\n-}\n-\n-static void\n-dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct sk_buff *skb;\n-\tstruct rx_pool *rpp;\n-\tstruct vc_map *vc;\n-\tu32 header, vpi, vci;\n-\tu32 stat;\n-\tint i;\n-\n-\tstat = le32_to_cpu(rsqe->word_4);\n-\n-\tif (stat & SAR_RSQE_IDLE) {\n-\t\tRXPRINTK(\"%s: message about inactive connection.\\n\",\n-\t\t\t card->name);\n-\t\treturn;\n-\t}\n-\n-\tskb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));\n-\tif (skb == NULL) {\n-\t\tprintk(\"%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\\n\",\n-\t\t card->name, __func__,\n-\t\t le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),\n-\t\t le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));\n-\t\treturn;\n-\t}\n-\n-\theader = le32_to_cpu(rsqe->word_1);\n-\tvpi = (header >> 16) & 0x00ff;\n-\tvci = (header >> 0) & 0xffff;\n-\n-\tRXPRINTK(\"%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\\n\",\n-\t\t card->name, vpi, vci, skb, skb->data);\n-\n-\tif ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {\n-\t\tprintk(\"%s: SDU received for out-of-range vc %u.%u\\n\",\n-\t\t card->name, vpi, vci);\n-\t\trecycle_rx_skb(card, skb);\n-\t\treturn;\n-\t}\n-\n-\tvc = card->vcs[VPCI2VC(card, vpi, vci)];\n-\tif (!vc || !test_bit(VCF_RX, &vc->flags)) {\n-\t\tprintk(\"%s: SDU received on non RX vc %u.%u\\n\",\n-\t\t card->name, vpi, vci);\n-\t\trecycle_rx_skb(card, skb);\n-\t\treturn;\n-\t}\n-\n-\tvcc = vc->rx_vcc;\n-\n-\tdma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\tskb_end_pointer(skb) - skb->data,\n-\t\t\t\tDMA_FROM_DEVICE);\n-\n-\tif ((vcc->qos.aal == ATM_AAL0) ||\n-\t (vcc->qos.aal == ATM_AAL34)) {\n-\t\tstruct sk_buff *sb;\n-\t\tunsigned char *cell;\n-\t\tu32 aal0;\n-\n-\t\tcell = skb->data;\n-\t\tfor (i = (stat & SAR_RSQE_CELLCNT); i; i--) {\n-\t\t\tif ((sb = dev_alloc_skb(64)) == NULL) {\n-\t\t\t\tprintk(\"%s: Can't allocate buffers for aal0.\\n\",\n-\t\t\t\t card->name);\n-\t\t\t\tatomic_add(i, &vcc->stats->rx_drop);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (!atm_charge(vcc, sb->truesize)) {\n-\t\t\t\tRXPRINTK(\"%s: atm_charge() dropped aal0 packets.\\n\",\n-\t\t\t\t\t card->name);\n-\t\t\t\tatomic_add(i - 1, &vcc->stats->rx_drop);\n-\t\t\t\tdev_kfree_skb(sb);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\taal0 = (vpi << ATM_HDR_VPI_SHIFT) |\n-\t\t\t (vci << ATM_HDR_VCI_SHIFT);\n-\t\t\taal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;\n-\t\t\taal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;\n-\n-\t\t\t*((u32 *) sb->data) = aal0;\n-\t\t\tskb_put(sb, sizeof(u32));\n-\t\t\tskb_put_data(sb, cell, ATM_CELL_PAYLOAD);\n-\n-\t\t\tATM_SKB(sb)->vcc = vcc;\n-\t\t\t__net_timestamp(sb);\n-\t\t\tvcc->push(vcc, sb);\n-\t\t\tatomic_inc(&vcc->stats->rx);\n-\n-\t\t\tcell += ATM_CELL_PAYLOAD;\n-\t\t}\n-\n-\t\trecycle_rx_skb(card, skb);\n-\t\treturn;\n-\t}\n-\tif (vcc->qos.aal != ATM_AAL5) {\n-\t\tprintk(\"%s: Unexpected AAL type in dequeue_rx(): %d.\\n\",\n-\t\t card->name, vcc->qos.aal);\n-\t\trecycle_rx_skb(card, skb);\n-\t\treturn;\n-\t}\n-\tskb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;\n-\n-\trpp = &vc->rcv.rx_pool;\n-\n-\t__skb_queue_tail(&rpp->queue, skb);\n-\trpp->len += skb->len;\n-\n-\tif (stat & SAR_RSQE_EPDU) {\n-\t\tunsigned int len, truesize;\n-\t\tunsigned char *l1l2;\n-\n-\t\tl1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);\n-\n-\t\tlen = (l1l2[0] << 8) | l1l2[1];\n-\t\tlen = len ? len : 0x10000;\n-\n-\t\tRXPRINTK(\"%s: PDU has %d bytes.\\n\", card->name, len);\n-\n-\t\tif ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {\n-\t\t\tRXPRINTK(\"%s: AAL5 PDU size mismatch: %d != %d. \"\n-\t\t\t \"(CDC: %08x)\\n\",\n-\t\t\t card->name, len, rpp->len, readl(SAR_REG_CDC));\n-\t\t\trecycle_rx_pool_skb(card, rpp);\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\treturn;\n-\t\t}\n-\t\tif (stat & SAR_RSQE_CRC) {\n-\t\t\tRXPRINTK(\"%s: AAL5 CRC error.\\n\", card->name);\n-\t\t\trecycle_rx_pool_skb(card, rpp);\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\treturn;\n-\t\t}\n-\t\tif (skb_queue_len(&rpp->queue) > 1) {\n-\t\t\tstruct sk_buff *sb;\n-\n-\t\t\tskb = dev_alloc_skb(rpp->len);\n-\t\t\tif (!skb) {\n-\t\t\t\tRXPRINTK(\"%s: Can't alloc RX skb.\\n\",\n-\t\t\t\t\t card->name);\n-\t\t\t\trecycle_rx_pool_skb(card, rpp);\n-\t\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\t\treturn;\n-\t\t\t}\n-\t\t\tif (!atm_charge(vcc, skb->truesize)) {\n-\t\t\t\trecycle_rx_pool_skb(card, rpp);\n-\t\t\t\tdev_kfree_skb(skb);\n-\t\t\t\treturn;\n-\t\t\t}\n-\t\t\tskb_queue_walk(&rpp->queue, sb)\n-\t\t\t\tskb_put_data(skb, sb->data, sb->len);\n-\n-\t\t\trecycle_rx_pool_skb(card, rpp);\n-\n-\t\t\tskb_trim(skb, len);\n-\t\t\tATM_SKB(skb)->vcc = vcc;\n-\t\t\t__net_timestamp(skb);\n-\n-\t\t\tvcc->push(vcc, skb);\n-\t\t\tatomic_inc(&vcc->stats->rx);\n-\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tflush_rx_pool(card, rpp);\n-\n-\t\tif (!atm_charge(vcc, skb->truesize)) {\n-\t\t\trecycle_rx_skb(card, skb);\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\t skb_end_pointer(skb) - skb->data,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tsb_pool_remove(card, skb);\n-\n-\t\tskb_trim(skb, len);\n-\t\tATM_SKB(skb)->vcc = vcc;\n-\t\t__net_timestamp(skb);\n-\n-\t\ttruesize = skb->truesize;\n-\t\tvcc->push(vcc, skb);\n-\t\tatomic_inc(&vcc->stats->rx);\n-\n-\t\tif (truesize > SAR_FB_SIZE_3)\n-\t\t\tadd_rx_skb(card, 3, SAR_FB_SIZE_3, 1);\n-\t\telse if (truesize > SAR_FB_SIZE_2)\n-\t\t\tadd_rx_skb(card, 2, SAR_FB_SIZE_2, 1);\n-\t\telse if (truesize > SAR_FB_SIZE_1)\n-\t\t\tadd_rx_skb(card, 1, SAR_FB_SIZE_1, 1);\n-\t\telse\n-\t\t\tadd_rx_skb(card, 0, SAR_FB_SIZE_0, 1);\n-\t\treturn;\n-\t}\n-}\n-\n-static void\n-idt77252_rx(struct idt77252_dev *card)\n-{\n-\tstruct rsq_entry *rsqe;\n-\n-\tif (card->rsq.next == card->rsq.last)\n-\t\trsqe = card->rsq.base;\n-\telse\n-\t\trsqe = card->rsq.next + 1;\n-\n-\tif (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {\n-\t\tRXPRINTK(\"%s: no entry in RSQ.\\n\", card->name);\n-\t\treturn;\n-\t}\n-\n-\tdo {\n-\t\tdequeue_rx(card, rsqe);\n-\t\trsqe->word_4 = 0;\n-\t\tcard->rsq.next = rsqe;\n-\t\tif (card->rsq.next == card->rsq.last)\n-\t\t\trsqe = card->rsq.base;\n-\t\telse\n-\t\t\trsqe = card->rsq.next + 1;\n-\t} while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);\n-\n-\twritel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,\n-\t SAR_REG_RSQH);\n-}\n-\n-static void\n-idt77252_rx_raw(struct idt77252_dev *card)\n-{\n-\tstruct sk_buff\t*queue;\n-\tu32\t\thead, tail;\n-\tstruct atm_vcc\t*vcc;\n-\tstruct vc_map\t*vc;\n-\tstruct sk_buff\t*sb;\n-\n-\tif (card->raw_cell_head == NULL) {\n-\t\tu32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));\n-\t\tcard->raw_cell_head = sb_pool_skb(card, handle);\n-\t}\n-\n-\tqueue = card->raw_cell_head;\n-\tif (!queue)\n-\t\treturn;\n-\n-\thead = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);\n-\ttail = readl(SAR_REG_RAWCT);\n-\n-\tdma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),\n-\t\t\t\tskb_end_offset(queue) - 16,\n-\t\t\t\tDMA_FROM_DEVICE);\n-\n-\twhile (head != tail) {\n-\t\tunsigned int vpi, vci;\n-\t\tu32 header;\n-\n-\t\theader = le32_to_cpu(*(u32 *) &queue->data[0]);\n-\n-\t\tvpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;\n-\t\tvci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;\n-\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-\t\tif (debug & DBG_RAW_CELL) {\n-\t\t\tint i;\n-\n-\t\t\tprintk(\"%s: raw cell %x.%02x.%04x.%x.%x\\n\",\n-\t\t\t card->name, (header >> 28) & 0x000f,\n-\t\t\t (header >> 20) & 0x00ff,\n-\t\t\t (header >> 4) & 0xffff,\n-\t\t\t (header >> 1) & 0x0007,\n-\t\t\t (header >> 0) & 0x0001);\n-\t\t\tfor (i = 16; i < 64; i++)\n-\t\t\t\tprintk(\" %02x\", queue->data[i]);\n-\t\t\tprintk(\"\\n\");\n-\t\t}\n-#endif\n-\n-\t\tif (vpi >= (1<vpibits) || vci >= (1<vcibits)) {\n-\t\t\tRPRINTK(\"%s: SDU received for out-of-range vc %u.%u\\n\",\n-\t\t\t\tcard->name, vpi, vci);\n-\t\t\tgoto drop;\n-\t\t}\n-\n-\t\tvc = card->vcs[VPCI2VC(card, vpi, vci)];\n-\t\tif (!vc || !test_bit(VCF_RX, &vc->flags)) {\n-\t\t\tRPRINTK(\"%s: SDU received on non RX vc %u.%u\\n\",\n-\t\t\t\tcard->name, vpi, vci);\n-\t\t\tgoto drop;\n-\t\t}\n-\n-\t\tvcc = vc->rx_vcc;\n-\n-\t\tif (vcc->qos.aal != ATM_AAL0) {\n-\t\t\tRPRINTK(\"%s: raw cell for non AAL0 vc %u.%u\\n\",\n-\t\t\t\tcard->name, vpi, vci);\n-\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\tgoto drop;\n-\t\t}\n-\t\n-\t\tif ((sb = dev_alloc_skb(64)) == NULL) {\n-\t\t\tprintk(\"%s: Can't allocate buffers for AAL0.\\n\",\n-\t\t\t card->name);\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\tgoto drop;\n-\t\t}\n-\n-\t\tif (!atm_charge(vcc, sb->truesize)) {\n-\t\t\tRXPRINTK(\"%s: atm_charge() dropped AAL0 packets.\\n\",\n-\t\t\t\t card->name);\n-\t\t\tdev_kfree_skb(sb);\n-\t\t\tgoto drop;\n-\t\t}\n-\n-\t\t*((u32 *) sb->data) = header;\n-\t\tskb_put(sb, sizeof(u32));\n-\t\tskb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);\n-\n-\t\tATM_SKB(sb)->vcc = vcc;\n-\t\t__net_timestamp(sb);\n-\t\tvcc->push(vcc, sb);\n-\t\tatomic_inc(&vcc->stats->rx);\n-\n-drop:\n-\t\tskb_pull(queue, 64);\n-\n-\t\thead = IDT77252_PRV_PADDR(queue)\n-\t\t\t\t\t+ (queue->data - queue->head - 16);\n-\n-\t\tif (queue->len < 128) {\n-\t\t\tstruct sk_buff *next;\n-\t\t\tu32 handle;\n-\n-\t\t\thead = le32_to_cpu(*(u32 *) &queue->data[0]);\n-\t\t\thandle = le32_to_cpu(*(u32 *) &queue->data[4]);\n-\n-\t\t\tnext = sb_pool_skb(card, handle);\n-\t\t\trecycle_rx_skb(card, queue);\n-\n-\t\t\tif (next) {\n-\t\t\t\tcard->raw_cell_head = next;\n-\t\t\t\tqueue = card->raw_cell_head;\n-\t\t\t\tdma_sync_single_for_cpu(&card->pcidev->dev,\n-\t\t\t\t\t\t\tIDT77252_PRV_PADDR(queue),\n-\t\t\t\t\t\t\t(skb_end_pointer(queue) -\n-\t\t\t\t\t\t\t queue->data),\n-\t\t\t\t\t\t\tDMA_FROM_DEVICE);\n-\t\t\t} else {\n-\t\t\t\tcard->raw_cell_head = NULL;\n-\t\t\t\tprintk(\"%s: raw cell queue overrun\\n\",\n-\t\t\t\t card->name);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t}\n-}\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* TSQ Handling */\n-/* */\n-/*****************************************************************************/\n-\n-static int\n-init_tsq(struct idt77252_dev *card)\n-{\n-\tstruct tsq_entry *tsqe;\n-\n-\tcard->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,\n-\t\t\t\t\t &card->tsq.paddr, GFP_KERNEL);\n-\tif (card->tsq.base == NULL) {\n-\t\tprintk(\"%s: can't allocate TSQ.\\n\", card->name);\n-\t\treturn -1;\n-\t}\n-\n-\tcard->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;\n-\tcard->tsq.next = card->tsq.last;\n-\tfor (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)\n-\t\ttsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);\n-\n-\twritel(card->tsq.paddr, SAR_REG_TSQB);\n-\twritel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,\n-\t SAR_REG_TSQH);\n-\n-\treturn 0;\n-}\n-\n-static void\n-deinit_tsq(struct idt77252_dev *card)\n-{\n-\tdma_free_coherent(&card->pcidev->dev, TSQSIZE,\n-\t\t\t card->tsq.base, card->tsq.paddr);\n-}\n-\n-static void\n-idt77252_tx(struct idt77252_dev *card)\n-{\n-\tstruct tsq_entry *tsqe;\n-\tunsigned int vpi, vci;\n-\tstruct vc_map *vc;\n-\tu32 conn, stat;\n-\n-\tif (card->tsq.next == card->tsq.last)\n-\t\ttsqe = card->tsq.base;\n-\telse\n-\t\ttsqe = card->tsq.next + 1;\n-\n-\tTXPRINTK(\"idt77252_tx: tsq %p: base %p, next %p, last %p\\n\", tsqe,\n-\t\t card->tsq.base, card->tsq.next, card->tsq.last);\n-\tTXPRINTK(\"idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \\n\",\n-\t\t readl(SAR_REG_TSQB),\n-\t\t readl(SAR_REG_TSQT),\n-\t\t readl(SAR_REG_TSQH));\n-\n-\tstat = le32_to_cpu(tsqe->word_2);\n-\n-\tif (stat & SAR_TSQE_INVALID)\n-\t\treturn;\n-\n-\tdo {\n-\t\tTXPRINTK(\"tsqe: 0x%p [0x%08x 0x%08x]\\n\", tsqe,\n-\t\t\t le32_to_cpu(tsqe->word_1),\n-\t\t\t le32_to_cpu(tsqe->word_2));\n-\n-\t\tswitch (stat & SAR_TSQE_TYPE) {\n-\t\tcase SAR_TSQE_TYPE_TIMER:\n-\t\t\tTXPRINTK(\"%s: Timer RollOver detected.\\n\", card->name);\n-\t\t\tbreak;\n-\n-\t\tcase SAR_TSQE_TYPE_IDLE:\n-\n-\t\t\tconn = le32_to_cpu(tsqe->word_1);\n-\n-\t\t\tif (SAR_TSQE_TAG(stat) == 0x10) {\n-#ifdef\tNOTDEF\n-\t\t\t\tprintk(\"%s: Connection %d halted.\\n\",\n-\t\t\t\t card->name,\n-\t\t\t\t le32_to_cpu(tsqe->word_1) & 0x1fff);\n-#endif\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tvc = card->vcs[conn & 0x1fff];\n-\t\t\tif (!vc) {\n-\t\t\t\tprintk(\"%s: could not find VC from conn %d\\n\",\n-\t\t\t\t card->name, conn & 0x1fff);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tprintk(\"%s: Connection %d IDLE.\\n\",\n-\t\t\t card->name, vc->index);\n-\n-\t\t\tset_bit(VCF_IDLE, &vc->flags);\n-\t\t\tbreak;\n-\n-\t\tcase SAR_TSQE_TYPE_TSR:\n-\n-\t\t\tconn = le32_to_cpu(tsqe->word_1);\n-\n-\t\t\tvc = card->vcs[conn & 0x1fff];\n-\t\t\tif (!vc) {\n-\t\t\t\tprintk(\"%s: no VC at index %d\\n\",\n-\t\t\t\t card->name,\n-\t\t\t\t le32_to_cpu(tsqe->word_1) & 0x1fff);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tdrain_scq(card, vc);\n-\t\t\tbreak;\n-\n-\t\tcase SAR_TSQE_TYPE_TBD_COMP:\n-\n-\t\t\tconn = le32_to_cpu(tsqe->word_1);\n-\n-\t\t\tvpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;\n-\t\t\tvci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;\n-\n-\t\t\tif (vpi >= (1 << card->vpibits) ||\n-\t\t\t vci >= (1 << card->vcibits)) {\n-\t\t\t\tprintk(\"%s: TBD complete: \"\n-\t\t\t\t \"out of range VPI.VCI %u.%u\\n\",\n-\t\t\t\t card->name, vpi, vci);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tvc = card->vcs[VPCI2VC(card, vpi, vci)];\n-\t\t\tif (!vc) {\n-\t\t\t\tprintk(\"%s: TBD complete: \"\n-\t\t\t\t \"no VC at VPI.VCI %u.%u\\n\",\n-\t\t\t\t card->name, vpi, vci);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tdrain_scq(card, vc);\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\ttsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);\n-\n-\t\tcard->tsq.next = tsqe;\n-\t\tif (card->tsq.next == card->tsq.last)\n-\t\t\ttsqe = card->tsq.base;\n-\t\telse\n-\t\t\ttsqe = card->tsq.next + 1;\n-\n-\t\tTXPRINTK(\"tsqe: %p: base %p, next %p, last %p\\n\", tsqe,\n-\t\t\t card->tsq.base, card->tsq.next, card->tsq.last);\n-\n-\t\tstat = le32_to_cpu(tsqe->word_2);\n-\n-\t} while (!(stat & SAR_TSQE_INVALID));\n-\n-\twritel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,\n-\t SAR_REG_TSQH);\n-\n-\tXPRINTK(\"idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\\n\",\n-\t\tcard->index, readl(SAR_REG_TSQH),\n-\t\treadl(SAR_REG_TSQT), card->tsq.next);\n-}\n-\n-\n-static void\n-tst_timer(struct timer_list *t)\n-{\n-\tstruct idt77252_dev *card = timer_container_of(card, t, tst_timer);\n-\tunsigned long base, idle, jump;\n-\tunsigned long flags;\n-\tu32 pc;\n-\tint e;\n-\n-\tspin_lock_irqsave(&card->tst_lock, flags);\n-\n-\tbase = card->tst[card->tst_index];\n-\tidle = card->tst[card->tst_index ^ 1];\n-\n-\tif (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {\n-\t\tjump = base + card->tst_size - 2;\n-\n-\t\tpc = readl(SAR_REG_NOW) >> 2;\n-\t\tif ((pc ^ idle) & ~(card->tst_size - 1)) {\n-\t\t\tmod_timer(&card->tst_timer, jiffies + 1);\n-\t\t\tgoto out;\n-\t\t}\n-\n-\t\tclear_bit(TST_SWITCH_WAIT, &card->tst_state);\n-\n-\t\tcard->tst_index ^= 1;\n-\t\twrite_sram(card, jump, TSTE_OPC_JMP | (base << 2));\n-\n-\t\tbase = card->tst[card->tst_index];\n-\t\tidle = card->tst[card->tst_index ^ 1];\n-\n-\t\tfor (e = 0; e < card->tst_size - 2; e++) {\n-\t\t\tif (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {\n-\t\t\t\twrite_sram(card, idle + e,\n-\t\t\t\t\t card->soft_tst[e].tste & TSTE_MASK);\n-\t\t\t\tcard->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tif (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {\n-\n-\t\tfor (e = 0; e < card->tst_size - 2; e++) {\n-\t\t\tif (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {\n-\t\t\t\twrite_sram(card, idle + e,\n-\t\t\t\t\t card->soft_tst[e].tste & TSTE_MASK);\n-\t\t\t\tcard->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);\n-\t\t\t\tcard->soft_tst[e].tste |= TSTE_PUSH_IDLE;\n-\t\t\t}\n-\t\t}\n-\n-\t\tjump = base + card->tst_size - 2;\n-\n-\t\twrite_sram(card, jump, TSTE_OPC_NULL);\n-\t\tset_bit(TST_SWITCH_WAIT, &card->tst_state);\n-\n-\t\tmod_timer(&card->tst_timer, jiffies + 1);\n-\t}\n-\n-out:\n-\tspin_unlock_irqrestore(&card->tst_lock, flags);\n-}\n-\n-static int\n-__fill_tst(struct idt77252_dev *card, struct vc_map *vc,\n-\t int n, unsigned int opc)\n-{\n-\tunsigned long cl, avail;\n-\tunsigned long idle;\n-\tint e, r;\n-\tu32 data;\n-\n-\tavail = card->tst_size - 2;\n-\tfor (e = 0; e < avail; e++) {\n-\t\tif (card->soft_tst[e].vc == NULL)\n-\t\t\tbreak;\n-\t}\n-\tif (e >= avail) {\n-\t\tprintk(\"%s: No free TST entries found\\n\", card->name);\n-\t\treturn -1;\n-\t}\n-\n-\tNPRINTK(\"%s: conn %d: first TST entry at %d.\\n\",\n-\t\tcard->name, vc ? vc->index : -1, e);\n-\n-\tr = n;\n-\tcl = avail;\n-\tdata = opc & TSTE_OPC_MASK;\n-\tif (vc && (opc != TSTE_OPC_NULL))\n-\t\tdata = opc | vc->index;\n-\n-\tidle = card->tst[card->tst_index ^ 1];\n-\n-\t/*\n-\t * Fill Soft TST.\n-\t */\n-\twhile (r > 0) {\n-\t\tif ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {\n-\t\t\tif (vc)\n-\t\t\t\tcard->soft_tst[e].vc = vc;\n-\t\t\telse\n-\t\t\t\tcard->soft_tst[e].vc = (void *)-1;\n-\n-\t\t\tcard->soft_tst[e].tste = data;\n-\t\t\tif (timer_pending(&card->tst_timer))\n-\t\t\t\tcard->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;\n-\t\t\telse {\n-\t\t\t\twrite_sram(card, idle + e, data);\n-\t\t\t\tcard->soft_tst[e].tste |= TSTE_PUSH_IDLE;\n-\t\t\t}\n-\n-\t\t\tcl -= card->tst_size;\n-\t\t\tr--;\n-\t\t}\n-\n-\t\tif (++e == avail)\n-\t\t\te = 0;\n-\t\tcl += n;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)\n-{\n-\tunsigned long flags;\n-\tint res;\n-\n-\tspin_lock_irqsave(&card->tst_lock, flags);\n-\n-\tres = __fill_tst(card, vc, n, opc);\n-\n-\tset_bit(TST_SWITCH_PENDING, &card->tst_state);\n-\tif (!timer_pending(&card->tst_timer))\n-\t\tmod_timer(&card->tst_timer, jiffies + 1);\n-\n-\tspin_unlock_irqrestore(&card->tst_lock, flags);\n-\treturn res;\n-}\n-\n-static int\n-__clear_tst(struct idt77252_dev *card, struct vc_map *vc)\n-{\n-\tunsigned long idle;\n-\tint e;\n-\n-\tidle = card->tst[card->tst_index ^ 1];\n-\n-\tfor (e = 0; e < card->tst_size - 2; e++) {\n-\t\tif (card->soft_tst[e].vc == vc) {\n-\t\t\tcard->soft_tst[e].vc = NULL;\n-\n-\t\t\tcard->soft_tst[e].tste = TSTE_OPC_VAR;\n-\t\t\tif (timer_pending(&card->tst_timer))\n-\t\t\t\tcard->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;\n-\t\t\telse {\n-\t\t\t\twrite_sram(card, idle + e, TSTE_OPC_VAR);\n-\t\t\t\tcard->soft_tst[e].tste |= TSTE_PUSH_IDLE;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-clear_tst(struct idt77252_dev *card, struct vc_map *vc)\n-{\n-\tunsigned long flags;\n-\tint res;\n-\n-\tspin_lock_irqsave(&card->tst_lock, flags);\n-\n-\tres = __clear_tst(card, vc);\n-\n-\tset_bit(TST_SWITCH_PENDING, &card->tst_state);\n-\tif (!timer_pending(&card->tst_timer))\n-\t\tmod_timer(&card->tst_timer, jiffies + 1);\n-\n-\tspin_unlock_irqrestore(&card->tst_lock, flags);\n-\treturn res;\n-}\n-\n-static int\n-change_tst(struct idt77252_dev *card, struct vc_map *vc,\n-\t int n, unsigned int opc)\n-{\n-\tunsigned long flags;\n-\tint res;\n-\n-\tspin_lock_irqsave(&card->tst_lock, flags);\n-\n-\t__clear_tst(card, vc);\n-\tres = __fill_tst(card, vc, n, opc);\n-\n-\tset_bit(TST_SWITCH_PENDING, &card->tst_state);\n-\tif (!timer_pending(&card->tst_timer))\n-\t\tmod_timer(&card->tst_timer, jiffies + 1);\n-\n-\tspin_unlock_irqrestore(&card->tst_lock, flags);\n-\treturn res;\n-}\n-\n-\n-static int\n-set_tct(struct idt77252_dev *card, struct vc_map *vc)\n-{\n-\tunsigned long tct;\n-\n-\ttct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);\n-\n-\tswitch (vc->class) {\n-\tcase SCHED_CBR:\n-\t\tOPRINTK(\"%s: writing TCT at 0x%lx, SCD 0x%lx.\\n\",\n-\t\t card->name, tct, vc->scq->scd);\n-\n-\t\twrite_sram(card, tct + 0, TCT_CBR | vc->scq->scd);\n-\t\twrite_sram(card, tct + 1, 0);\n-\t\twrite_sram(card, tct + 2, 0);\n-\t\twrite_sram(card, tct + 3, 0);\n-\t\twrite_sram(card, tct + 4, 0);\n-\t\twrite_sram(card, tct + 5, 0);\n-\t\twrite_sram(card, tct + 6, 0);\n-\t\twrite_sram(card, tct + 7, 0);\n-\t\tbreak;\n-\n-\tcase SCHED_UBR:\n-\t\tOPRINTK(\"%s: writing TCT at 0x%lx, SCD 0x%lx.\\n\",\n-\t\t card->name, tct, vc->scq->scd);\n-\n-\t\twrite_sram(card, tct + 0, TCT_UBR | vc->scq->scd);\n-\t\twrite_sram(card, tct + 1, 0);\n-\t\twrite_sram(card, tct + 2, TCT_TSIF);\n-\t\twrite_sram(card, tct + 3, TCT_HALT | TCT_IDLE);\n-\t\twrite_sram(card, tct + 4, 0);\n-\t\twrite_sram(card, tct + 5, vc->init_er);\n-\t\twrite_sram(card, tct + 6, 0);\n-\t\twrite_sram(card, tct + 7, TCT_FLAG_UBR);\n-\t\tbreak;\n-\n-\tcase SCHED_VBR:\n-\tcase SCHED_ABR:\n-\tdefault:\n-\t\treturn -ENOSYS;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/*****************************************************************************/\n-/* */\n-/* FBQ Handling */\n-/* */\n-/*****************************************************************************/\n-\n-static __inline__ int\n-idt77252_fbq_full(struct idt77252_dev *card, int queue)\n-{\n-\treturn (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;\n-}\n-\n-static int\n-push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)\n-{\n-\tunsigned long flags;\n-\tu32 handle;\n-\tu32 addr;\n-\n-\tskb->data = skb->head;\n-\tskb_reset_tail_pointer(skb);\n-\tskb->len = 0;\n-\n-\tskb_reserve(skb, 16);\n-\n-\tswitch (queue) {\n-\tcase 0:\n-\t\tskb_put(skb, SAR_FB_SIZE_0);\n-\t\tbreak;\n-\tcase 1:\n-\t\tskb_put(skb, SAR_FB_SIZE_1);\n-\t\tbreak;\n-\tcase 2:\n-\t\tskb_put(skb, SAR_FB_SIZE_2);\n-\t\tbreak;\n-\tcase 3:\n-\t\tskb_put(skb, SAR_FB_SIZE_3);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n-\t}\n-\n-\tif (idt77252_fbq_full(card, queue))\n-\t\treturn -1;\n-\n-\tmemset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));\n-\n-\thandle = IDT77252_PRV_POOL(skb);\n-\taddr = IDT77252_PRV_PADDR(skb);\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twritel(handle, card->fbq[queue]);\n-\twritel(addr, card->fbq[queue]);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\n-\treturn 0;\n-}\n-\n-static void\n-add_rx_skb(struct idt77252_dev *card, int queue,\n-\t unsigned int size, unsigned int count)\n-{\n-\tstruct sk_buff *skb;\n-\tdma_addr_t paddr;\n-\n-\twhile (count--) {\n-\t\tskb = dev_alloc_skb(size);\n-\t\tif (!skb)\n-\t\t\treturn;\n-\n-\t\tif (sb_pool_add(card, skb, queue)) {\n-\t\t\tprintk(\"%s: SB POOL full\\n\", __func__);\n-\t\t\tgoto outfree;\n-\t\t}\n-\n-\t\tpaddr = dma_map_single(&card->pcidev->dev, skb->data,\n-\t\t\t\t skb_end_pointer(skb) - skb->data,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tif (dma_mapping_error(&card->pcidev->dev, paddr))\n-\t\t\tgoto outpoolrm;\n-\t\tIDT77252_PRV_PADDR(skb) = paddr;\n-\n-\t\tif (push_rx_skb(card, skb, queue)) {\n-\t\t\tprintk(\"%s: FB QUEUE full\\n\", __func__);\n-\t\t\tgoto outunmap;\n-\t\t}\n-\t}\n-\n-\treturn;\n-\n-outunmap:\n-\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);\n-\n-outpoolrm:\n-\tsb_pool_remove(card, skb);\n-\n-outfree:\n-\tdev_kfree_skb(skb);\n-}\n-\n-\n-static void\n-recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)\n-{\n-\tu32 handle = IDT77252_PRV_POOL(skb);\n-\tint err;\n-\n-\tdma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\t skb_end_pointer(skb) - skb->data,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\n-\terr = push_rx_skb(card, skb, POOL_QUEUE(handle));\n-\tif (err) {\n-\t\tdma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),\n-\t\t\t\t skb_end_pointer(skb) - skb->data,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tsb_pool_remove(card, skb);\n-\t\tdev_kfree_skb(skb);\n-\t}\n-}\n-\n-static void\n-flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)\n-{\n-\tskb_queue_head_init(&rpp->queue);\n-\trpp->len = 0;\n-}\n-\n-static void\n-recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)\n-{\n-\tstruct sk_buff *skb, *tmp;\n-\n-\tskb_queue_walk_safe(&rpp->queue, skb, tmp)\n-\t\trecycle_rx_skb(card, skb);\n-\n-\tflush_rx_pool(card, rpp);\n-}\n-\n-/*****************************************************************************/\n-/* */\n-/* ATM Interface */\n-/* */\n-/*****************************************************************************/\n-\n-static void\n-idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)\n-{\n-\twrite_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);\n-}\n-\n-static unsigned char\n-idt77252_phy_get(struct atm_dev *dev, unsigned long addr)\n-{\n-\treturn read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));\n-}\n-\n-static inline int\n-idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)\n-{\n-\tstruct atm_dev *dev = vcc->dev;\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tstruct vc_map *vc = vcc->dev_data;\n-\tint err;\n-\n-\tif (vc == NULL) {\n-\t\tprintk(\"%s: NULL connection in send().\\n\", card->name);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\tif (!test_bit(VCF_TX, &vc->flags)) {\n-\t\tprintk(\"%s: Trying to transmit on a non-tx VC.\\n\", card->name);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tswitch (vcc->qos.aal) {\n-\tcase ATM_AAL0:\n-\tcase ATM_AAL1:\n-\tcase ATM_AAL5:\n-\t\tbreak;\n-\tdefault:\n-\t\tprintk(\"%s: Unsupported AAL: %d\\n\", card->name, vcc->qos.aal);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (skb_shinfo(skb)->nr_frags != 0) {\n-\t\tprintk(\"%s: No scatter-gather yet.\\n\", card->name);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\tATM_SKB(skb)->vcc = vcc;\n-\n-\terr = queue_skb(card, vc, skb, oam);\n-\tif (err) {\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb(skb);\n-\t\treturn err;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\treturn idt77252_send_skb(vcc, skb, 0);\n-}\n-\n-static int\n-idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)\n-{\n-\tstruct atm_dev *dev = vcc->dev;\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tstruct sk_buff *skb;\n-\n-\tskb = dev_alloc_skb(64);\n-\tif (!skb) {\n-\t\tprintk(\"%s: Out of memory in send_oam().\\n\", card->name);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\treturn -ENOMEM;\n-\t}\n-\trefcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);\n-\n-\tskb_put_data(skb, cell, 52);\n-\n-\treturn idt77252_send_skb(vcc, skb, 1);\n-}\n-\n-static __inline__ unsigned int\n-idt77252_fls(unsigned int x)\n-{\n-\tint r = 1;\n-\n-\tif (x == 0)\n-\t\treturn 0;\n-\tif (x & 0xffff0000) {\n-\t\tx >>= 16;\n-\t\tr += 16;\n-\t}\n-\tif (x & 0xff00) {\n-\t\tx >>= 8;\n-\t\tr += 8;\n-\t}\n-\tif (x & 0xf0) {\n-\t\tx >>= 4;\n-\t\tr += 4;\n-\t}\n-\tif (x & 0xc) {\n-\t\tx >>= 2;\n-\t\tr += 2;\n-\t}\n-\tif (x & 0x2)\n-\t\tr += 1;\n-\treturn r;\n-}\n-\n-static u16\n-idt77252_int_to_atmfp(unsigned int rate)\n-{\n-\tu16 m, e;\n-\n-\tif (rate == 0)\n-\t\treturn 0;\n-\te = idt77252_fls(rate) - 1;\n-\tif (e < 9)\n-\t\tm = (rate - (1 << e)) << (9 - e);\n-\telse if (e == 9)\n-\t\tm = (rate - (1 << e));\n-\telse /* e > 9 */\n-\t\tm = (rate - (1 << e)) >> (e - 9);\n-\treturn 0x4000 | (e << 9) | m;\n-}\n-\n-static u8\n-idt77252_rate_logindex(struct idt77252_dev *card, int pcr)\n-{\n-\tu16 afp;\n-\n-\tafp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);\n-\tif (pcr < 0)\n-\t\treturn rate_to_log[(afp >> 5) & 0x1ff];\n-\treturn rate_to_log[((afp >> 5) + 1) & 0x1ff];\n-}\n-\n-static void\n-idt77252_est_timer(struct timer_list *t)\n-{\n-\tstruct rate_estimator *est = timer_container_of(est, t, timer);\n-\tstruct vc_map *vc = est->vc;\n-\tstruct idt77252_dev *card = vc->card;\n-\tunsigned long flags;\n-\tu32 rate, cps;\n-\tu64 ncells;\n-\tu8 lacr;\n-\n-\tspin_lock_irqsave(&vc->lock, flags);\n-\tif (!vc->estimator)\n-\t\tgoto out;\n-\tncells = est->cells;\n-\n-\trate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);\n-\test->last_cells = ncells;\n-\test->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;\n-\test->cps = (est->avcps + 0x1f) >> 5;\n-\n-\tcps = est->cps;\n-\tif (cps < (est->maxcps >> 4))\n-\t\tcps = est->maxcps >> 4;\n-\n-\tlacr = idt77252_rate_logindex(card, cps);\n-\tif (lacr > vc->max_er)\n-\t\tlacr = vc->max_er;\n-\n-\tif (lacr != vc->lacr) {\n-\t\tvc->lacr = lacr;\n-\t\twritel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);\n-\t}\n-\n-\test->timer.expires = jiffies + ((HZ / 4) << est->interval);\n-\tadd_timer(&est->timer);\n-\n-out:\n-\tspin_unlock_irqrestore(&vc->lock, flags);\n-}\n-\n-static struct rate_estimator *\n-idt77252_init_est(struct vc_map *vc, int pcr)\n-{\n-\tstruct rate_estimator *est;\n-\n-\test = kzalloc_obj(struct rate_estimator);\n-\tif (!est)\n-\t\treturn NULL;\n-\test->maxcps = pcr < 0 ? -pcr : pcr;\n-\test->cps = est->maxcps;\n-\test->avcps = est->cps << 5;\n-\test->vc = vc;\n-\n-\test->interval = 2;\t\t/* XXX: make this configurable */\n-\test->ewma_log = 2;\t\t/* XXX: make this configurable */\n-\ttimer_setup(&est->timer, idt77252_est_timer, 0);\n-\tmod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));\n-\n-\treturn est;\n-}\n-\n-static int\n-idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,\n-\t\t struct atm_vcc *vcc, struct atm_qos *qos)\n-{\n-\tint tst_free, tst_used, tst_entries;\n-\tunsigned long tmpl, modl;\n-\tint tcr, tcra;\n-\n-\tif ((qos->txtp.max_pcr == 0) &&\n-\t (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {\n-\t\tprintk(\"%s: trying to open a CBR VC with cell rate = 0\\n\",\n-\t\t card->name);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\ttst_used = 0;\n-\ttst_free = card->tst_free;\n-\tif (test_bit(VCF_TX, &vc->flags))\n-\t\ttst_used = vc->ntste;\n-\ttst_free += tst_used;\n-\n-\ttcr = atm_pcr_goal(&qos->txtp);\n-\ttcra = tcr >= 0 ? tcr : -tcr;\n-\n-\tTXPRINTK(\"%s: CBR target cell rate = %d\\n\", card->name, tcra);\n-\n-\ttmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);\n-\tmodl = tmpl % (unsigned long)card->utopia_pcr;\n-\n-\ttst_entries = (int) (tmpl / card->utopia_pcr);\n-\tif (tcr > 0) {\n-\t\tif (modl > 0)\n-\t\t\ttst_entries++;\n-\t} else if (tcr == 0) {\n-\t\ttst_entries = tst_free - SAR_TST_RESERVED;\n-\t\tif (tst_entries <= 0) {\n-\t\t\tprintk(\"%s: no CBR bandwidth free.\\n\", card->name);\n-\t\t\treturn -ENOSR;\n-\t\t}\n-\t}\n-\n-\tif (tst_entries == 0) {\n-\t\tprintk(\"%s: selected CBR bandwidth < granularity.\\n\",\n-\t\t card->name);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (tst_entries > (tst_free - SAR_TST_RESERVED)) {\n-\t\tprintk(\"%s: not enough CBR bandwidth free.\\n\", card->name);\n-\t\treturn -ENOSR;\n-\t}\n-\n-\tvc->ntste = tst_entries;\n-\n-\tcard->tst_free = tst_free - tst_entries;\n-\tif (test_bit(VCF_TX, &vc->flags)) {\n-\t\tif (tst_used == tst_entries)\n-\t\t\treturn 0;\n-\n-\t\tOPRINTK(\"%s: modify %d -> %d entries in TST.\\n\",\n-\t\t\tcard->name, tst_used, tst_entries);\n-\t\tchange_tst(card, vc, tst_entries, TSTE_OPC_CBR);\n-\t\treturn 0;\n-\t}\n-\n-\tOPRINTK(\"%s: setting %d entries in TST.\\n\", card->name, tst_entries);\n-\tfill_tst(card, vc, tst_entries, TSTE_OPC_CBR);\n-\treturn 0;\n-}\n-\n-static int\n-idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,\n-\t\t struct atm_vcc *vcc, struct atm_qos *qos)\n-{\n-\tstruct rate_estimator *est = NULL;\n-\tunsigned long flags;\n-\tint tcr;\n-\n-\tspin_lock_irqsave(&vc->lock, flags);\n-\tif (vc->estimator) {\n-\t\test = vc->estimator;\n-\t\tvc->estimator = NULL;\n-\t}\n-\tspin_unlock_irqrestore(&vc->lock, flags);\n-\tif (est) {\n-\t\ttimer_shutdown_sync(&est->timer);\n-\t\tkfree(est);\n-\t}\n-\n-\ttcr = atm_pcr_goal(&qos->txtp);\n-\tif (tcr == 0)\n-\t\ttcr = card->link_pcr;\n-\n-\tvc->estimator = idt77252_init_est(vc, tcr);\n-\n-\tvc->class = SCHED_UBR;\n-\tvc->init_er = idt77252_rate_logindex(card, tcr);\n-\tvc->lacr = vc->init_er;\n-\tif (tcr < 0)\n-\t\tvc->max_er = vc->init_er;\n-\telse\n-\t\tvc->max_er = 0xff;\n-\n-\treturn 0;\n-}\n-\n-static int\n-idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,\n-\t\t struct atm_vcc *vcc, struct atm_qos *qos)\n-{\n-\tint error;\n-\n-\tif (test_bit(VCF_TX, &vc->flags))\n-\t\treturn -EBUSY;\n-\n-\tswitch (qos->txtp.traffic_class) {\n-\t\tcase ATM_CBR:\n-\t\t\tvc->class = SCHED_CBR;\n-\t\t\tbreak;\n-\n-\t\tcase ATM_UBR:\n-\t\t\tvc->class = SCHED_UBR;\n-\t\t\tbreak;\n-\n-\t\tcase ATM_VBR:\n-\t\tcase ATM_ABR:\n-\t\tdefault:\n-\t\t\treturn -EPROTONOSUPPORT;\n-\t}\n-\n-\tvc->scq = alloc_scq(card, vc->class);\n-\tif (!vc->scq) {\n-\t\tprintk(\"%s: can't get SCQ.\\n\", card->name);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tvc->scq->scd = get_free_scd(card, vc);\n-\tif (vc->scq->scd == 0) {\n-\t\tprintk(\"%s: no SCD available.\\n\", card->name);\n-\t\tfree_scq(card, vc->scq);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tfill_scd(card, vc->scq, vc->class);\n-\n-\tif (set_tct(card, vc)) {\n-\t\tprintk(\"%s: class %d not supported.\\n\",\n-\t\t card->name, qos->txtp.traffic_class);\n-\n-\t\tcard->scd2vc[vc->scd_index] = NULL;\n-\t\tfree_scq(card, vc->scq);\n-\t\treturn -EPROTONOSUPPORT;\n-\t}\n-\n-\tswitch (vc->class) {\n-\t\tcase SCHED_CBR:\n-\t\t\terror = idt77252_init_cbr(card, vc, vcc, qos);\n-\t\t\tif (error) {\n-\t\t\t\tcard->scd2vc[vc->scd_index] = NULL;\n-\t\t\t\tfree_scq(card, vc->scq);\n-\t\t\t\treturn error;\n-\t\t\t}\n-\n-\t\t\tclear_bit(VCF_IDLE, &vc->flags);\n-\t\t\twritel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);\n-\t\t\tbreak;\n-\n-\t\tcase SCHED_UBR:\n-\t\t\terror = idt77252_init_ubr(card, vc, vcc, qos);\n-\t\t\tif (error) {\n-\t\t\t\tcard->scd2vc[vc->scd_index] = NULL;\n-\t\t\t\tfree_scq(card, vc->scq);\n-\t\t\t\treturn error;\n-\t\t\t}\n-\n-\t\t\tset_bit(VCF_IDLE, &vc->flags);\n-\t\t\tbreak;\n-\t}\n-\n-\tvc->tx_vcc = vcc;\n-\tset_bit(VCF_TX, &vc->flags);\n-\treturn 0;\n-}\n-\n-static int\n-idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,\n-\t\t struct atm_vcc *vcc, struct atm_qos *qos)\n-{\n-\tunsigned long flags;\n-\tunsigned long addr;\n-\tu32 rcte = 0;\n-\n-\tif (test_bit(VCF_RX, &vc->flags))\n-\t\treturn -EBUSY;\n-\n-\tvc->rx_vcc = vcc;\n-\tset_bit(VCF_RX, &vc->flags);\n-\n-\tif ((vcc->vci == 3) || (vcc->vci == 4))\n-\t\treturn 0;\n-\n-\tflush_rx_pool(card, &vc->rcv.rx_pool);\n-\n-\trcte |= SAR_RCTE_CONNECTOPEN;\n-\trcte |= SAR_RCTE_RAWCELLINTEN;\n-\n-\tswitch (qos->aal) {\n-\t\tcase ATM_AAL0:\n-\t\t\trcte |= SAR_RCTE_RCQ;\n-\t\t\tbreak;\n-\t\tcase ATM_AAL1:\n-\t\t\trcte |= SAR_RCTE_OAM; /* Let SAR drop Video */\n-\t\t\tbreak;\n-\t\tcase ATM_AAL34:\n-\t\t\trcte |= SAR_RCTE_AAL34;\n-\t\t\tbreak;\n-\t\tcase ATM_AAL5:\n-\t\t\trcte |= SAR_RCTE_AAL5;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\trcte |= SAR_RCTE_RCQ;\n-\t\t\tbreak;\n-\t}\n-\n-\tif (qos->aal != ATM_AAL5)\n-\t\trcte |= SAR_RCTE_FBP_1;\n-\telse if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)\n-\t\trcte |= SAR_RCTE_FBP_3;\n-\telse if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)\n-\t\trcte |= SAR_RCTE_FBP_2;\n-\telse if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)\n-\t\trcte |= SAR_RCTE_FBP_1;\n-\telse\n-\t\trcte |= SAR_RCTE_FBP_01;\n-\n-\taddr = card->rct_base + (vc->index << 2);\n-\n-\tOPRINTK(\"%s: writing RCT at 0x%lx\\n\", card->name, addr);\n-\twrite_sram(card, addr, rcte);\n-\n-\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\twritel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);\n-\twaitfor_idle(card);\n-\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\n-\treturn 0;\n-}\n-\n-static int\n-idt77252_open(struct atm_vcc *vcc)\n-{\n-\tstruct atm_dev *dev = vcc->dev;\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tstruct vc_map *vc;\n-\tunsigned int index;\n-\tunsigned int inuse;\n-\tint error;\n-\tint vci = vcc->vci;\n-\tshort vpi = vcc->vpi;\n-\n-\tif (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)\n-\t\treturn 0;\n-\n-\tif (vpi >= (1 << card->vpibits)) {\n-\t\tprintk(\"%s: unsupported VPI: %d\\n\", card->name, vpi);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (vci >= (1 << card->vcibits)) {\n-\t\tprintk(\"%s: unsupported VCI: %d\\n\", card->name, vci);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tset_bit(ATM_VF_ADDR, &vcc->flags);\n-\n-\tmutex_lock(&card->mutex);\n-\n-\tOPRINTK(\"%s: opening vpi.vci: %d.%d\\n\", card->name, vpi, vci);\n-\n-\tswitch (vcc->qos.aal) {\n-\tcase ATM_AAL0:\n-\tcase ATM_AAL1:\n-\tcase ATM_AAL5:\n-\t\tbreak;\n-\tdefault:\n-\t\tprintk(\"%s: Unsupported AAL: %d\\n\", card->name, vcc->qos.aal);\n-\t\tmutex_unlock(&card->mutex);\n-\t\treturn -EPROTONOSUPPORT;\n-\t}\n-\n-\tindex = VPCI2VC(card, vpi, vci);\n-\tif (!card->vcs[index]) {\n-\t\tcard->vcs[index] = kzalloc_obj(struct vc_map);\n-\t\tif (!card->vcs[index]) {\n-\t\t\tprintk(\"%s: can't alloc vc in open()\\n\", card->name);\n-\t\t\tmutex_unlock(&card->mutex);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\tcard->vcs[index]->card = card;\n-\t\tcard->vcs[index]->index = index;\n-\n-\t\tspin_lock_init(&card->vcs[index]->lock);\n-\t}\n-\tvc = card->vcs[index];\n-\n-\tvcc->dev_data = vc;\n-\n-\tIPRINTK(\"%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\\n\",\n-\t card->name, vc->index, vcc->vpi, vcc->vci,\n-\t vcc->qos.rxtp.traffic_class != ATM_NONE ? \"rx\" : \"--\",\n-\t vcc->qos.txtp.traffic_class != ATM_NONE ? \"tx\" : \"--\",\n-\t vcc->qos.rxtp.max_sdu);\n-\n-\tinuse = 0;\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE &&\n-\t test_bit(VCF_TX, &vc->flags))\n-\t\tinuse = 1;\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE &&\n-\t test_bit(VCF_RX, &vc->flags))\n-\t\tinuse += 2;\n-\n-\tif (inuse) {\n-\t\tprintk(\"%s: %s vci already in use.\\n\", card->name,\n-\t\t inuse == 1 ? \"tx\" : inuse == 2 ? \"rx\" : \"tx and rx\");\n-\t\tmutex_unlock(&card->mutex);\n-\t\treturn -EADDRINUSE;\n-\t}\n-\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\terror = idt77252_init_tx(card, vc, vcc, &vcc->qos);\n-\t\tif (error) {\n-\t\t\tmutex_unlock(&card->mutex);\n-\t\t\treturn error;\n-\t\t}\n-\t}\n-\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\terror = idt77252_init_rx(card, vc, vcc, &vcc->qos);\n-\t\tif (error) {\n-\t\t\tmutex_unlock(&card->mutex);\n-\t\t\treturn error;\n-\t\t}\n-\t}\n-\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\n-\tmutex_unlock(&card->mutex);\n-\treturn 0;\n-}\n-\n-static void\n-idt77252_close(struct atm_vcc *vcc)\n-{\n-\tstruct atm_dev *dev = vcc->dev;\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tstruct vc_map *vc = vcc->dev_data;\n-\tunsigned long flags;\n-\tunsigned long addr;\n-\tunsigned long timeout;\n-\n-\tmutex_lock(&card->mutex);\n-\n-\tIPRINTK(\"%s: idt77252_close: vc = %d (%d.%d)\\n\",\n-\t\tcard->name, vc->index, vcc->vpi, vcc->vci);\n-\n-\tclear_bit(ATM_VF_READY, &vcc->flags);\n-\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\n-\t\tspin_lock_irqsave(&vc->lock, flags);\n-\t\tclear_bit(VCF_RX, &vc->flags);\n-\t\tvc->rx_vcc = NULL;\n-\t\tspin_unlock_irqrestore(&vc->lock, flags);\n-\n-\t\tif ((vcc->vci == 3) || (vcc->vci == 4))\n-\t\t\tgoto done;\n-\n-\t\taddr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;\n-\n-\t\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\t\twritel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);\n-\t\twaitfor_idle(card);\n-\t\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\n-\t\tif (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {\n-\t\t\tDPRINTK(\"%s: closing a VC with pending rx buffers.\\n\",\n-\t\t\t\tcard->name);\n-\n-\t\t\trecycle_rx_pool_skb(card, &vc->rcv.rx_pool);\n-\t\t}\n-\t}\n-\n-done:\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\n-\t\tspin_lock_irqsave(&vc->lock, flags);\n-\t\tclear_bit(VCF_TX, &vc->flags);\n-\t\tclear_bit(VCF_IDLE, &vc->flags);\n-\t\tclear_bit(VCF_RSV, &vc->flags);\n-\t\tvc->tx_vcc = NULL;\n-\n-\t\tif (vc->estimator) {\n-\t\t\ttimer_shutdown(&vc->estimator->timer);\n-\t\t\tkfree(vc->estimator);\n-\t\t\tvc->estimator = NULL;\n-\t\t}\n-\t\tspin_unlock_irqrestore(&vc->lock, flags);\n-\n-\t\ttimeout = 5 * 1000;\n-\t\twhile (atomic_read(&vc->scq->used) > 0) {\n-\t\t\ttimeout = msleep_interruptible(timeout);\n-\t\t\tif (!timeout) {\n-\t\t\t\tpr_warn(\"%s: SCQ drain timeout: %u used\\n\",\n-\t\t\t\t\tcard->name, atomic_read(&vc->scq->used));\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\twritel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);\n-\t\tclear_scd(card, vc->scq, vc->class);\n-\n-\t\tif (vc->class == SCHED_CBR) {\n-\t\t\tclear_tst(card, vc);\n-\t\t\tcard->tst_free += vc->ntste;\n-\t\t\tvc->ntste = 0;\n-\t\t}\n-\n-\t\tcard->scd2vc[vc->scd_index] = NULL;\n-\t\tfree_scq(card, vc->scq);\n-\t}\n-\n-\tmutex_unlock(&card->mutex);\n-}\n-\n-static int\n-idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)\n-{\n-\tstruct atm_dev *dev = vcc->dev;\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tstruct vc_map *vc = vcc->dev_data;\n-\tint error = 0;\n-\n-\tmutex_lock(&card->mutex);\n-\n-\tif (qos->txtp.traffic_class != ATM_NONE) {\n-\t \tif (!test_bit(VCF_TX, &vc->flags)) {\n-\t\t\terror = idt77252_init_tx(card, vc, vcc, qos);\n-\t\t\tif (error)\n-\t\t\t\tgoto out;\n-\t\t} else {\n-\t\t\tswitch (qos->txtp.traffic_class) {\n-\t\t\tcase ATM_CBR:\n-\t\t\t\terror = idt77252_init_cbr(card, vc, vcc, qos);\n-\t\t\t\tif (error)\n-\t\t\t\t\tgoto out;\n-\t\t\t\tbreak;\n-\n-\t\t\tcase ATM_UBR:\n-\t\t\t\terror = idt77252_init_ubr(card, vc, vcc, qos);\n-\t\t\t\tif (error)\n-\t\t\t\t\tgoto out;\n-\n-\t\t\t\tif (!test_bit(VCF_IDLE, &vc->flags)) {\n-\t\t\t\t\twritel(TCMDQ_LACR | (vc->lacr << 16) |\n-\t\t\t\t\t vc->index, SAR_REG_TCMDQ);\n-\t\t\t\t}\n-\t\t\t\tbreak;\n-\n-\t\t\tcase ATM_VBR:\n-\t\t\tcase ATM_ABR:\n-\t\t\t\terror = -EOPNOTSUPP;\n-\t\t\t\tgoto out;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tif ((qos->rxtp.traffic_class != ATM_NONE) &&\n-\t !test_bit(VCF_RX, &vc->flags)) {\n-\t\terror = idt77252_init_rx(card, vc, vcc, qos);\n-\t\tif (error)\n-\t\t\tgoto out;\n-\t}\n-\n-\tmemcpy(&vcc->qos, qos, sizeof(struct atm_qos));\n-\n-\tset_bit(ATM_VF_HASQOS, &vcc->flags);\n-\n-out:\n-\tmutex_unlock(&card->mutex);\n-\treturn error;\n-}\n-\n-static int\n-idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)\n-{\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tint i, left;\n-\n-\tleft = (int) *pos;\n-\tif (!left--)\n-\t\treturn sprintf(page, \"IDT77252 Interrupts:\\n\");\n-\tif (!left--)\n-\t\treturn sprintf(page, \"TSIF: %lu\\n\", card->irqstat[15]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"TXICP: %lu\\n\", card->irqstat[14]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"TSQF: %lu\\n\", card->irqstat[12]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"TMROF: %lu\\n\", card->irqstat[11]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"PHYI: %lu\\n\", card->irqstat[10]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"FBQ3A: %lu\\n\", card->irqstat[8]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"FBQ2A: %lu\\n\", card->irqstat[7]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"RSQF: %lu\\n\", card->irqstat[6]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"EPDU: %lu\\n\", card->irqstat[5]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"RAWCF: %lu\\n\", card->irqstat[4]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"FBQ1A: %lu\\n\", card->irqstat[3]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"FBQ0A: %lu\\n\", card->irqstat[2]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"RSQAF: %lu\\n\", card->irqstat[1]);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"IDT77252 Transmit Connection Table:\\n\");\n-\n-\tfor (i = 0; i < card->tct_size; i++) {\n-\t\tunsigned long tct;\n-\t\tstruct atm_vcc *vcc;\n-\t\tstruct vc_map *vc;\n-\t\tchar *p;\n-\n-\t\tvc = card->vcs[i];\n-\t\tif (!vc)\n-\t\t\tcontinue;\n-\n-\t\tvcc = NULL;\n-\t\tif (vc->tx_vcc)\n-\t\t\tvcc = vc->tx_vcc;\n-\t\tif (!vcc)\n-\t\t\tcontinue;\n-\t\tif (left--)\n-\t\t\tcontinue;\n-\n-\t\tp = page;\n-\t\tp += sprintf(p, \" %4u: %u.%u: \", i, vcc->vpi, vcc->vci);\n-\t\ttct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);\n-\n-\t\tfor (i = 0; i < 8; i++)\n-\t\t\tp += sprintf(p, \" %08x\", read_sram(card, tct + i));\n-\t\tp += sprintf(p, \"\\n\");\n-\t\treturn p - page;\n-\t}\n-\treturn 0;\n-}\n-\n-/*****************************************************************************/\n-/* */\n-/* Interrupt handler */\n-/* */\n-/*****************************************************************************/\n-\n-static void\n-idt77252_collect_stat(struct idt77252_dev *card)\n-{\n-\t(void) readl(SAR_REG_CDC);\n-\t(void) readl(SAR_REG_VPEC);\n-\t(void) readl(SAR_REG_ICC);\n-\n-}\n-\n-static irqreturn_t\n-idt77252_interrupt(int irq, void *dev_id)\n-{\n-\tstruct idt77252_dev *card = dev_id;\n-\tu32 stat;\n-\n-\tstat = readl(SAR_REG_STAT) & 0xffff;\n-\tif (!stat)\t/* no interrupt for us */\n-\t\treturn IRQ_NONE;\n-\n-\tif (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {\n-\t\tprintk(\"%s: Re-entering irq_handler()\\n\", card->name);\n-\t\tgoto out;\n-\t}\n-\n-\twritel(stat, SAR_REG_STAT);\t/* reset interrupt */\n-\n-\tif (stat & SAR_STAT_TSIF) {\t/* entry written to TSQ */\n-\t\tINTPRINTK(\"%s: TSIF\\n\", card->name);\n-\t\tcard->irqstat[15]++;\n-\t\tidt77252_tx(card);\n-\t}\n-\tif (stat & SAR_STAT_TXICP) {\t/* Incomplete CS-PDU has */\n-\t\tINTPRINTK(\"%s: TXICP\\n\", card->name);\n-\t\tcard->irqstat[14]++;\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-\t\tidt77252_tx_dump(card);\n-#endif\n-\t}\n-\tif (stat & SAR_STAT_TSQF) {\t/* TSQ 7/8 full */\n-\t\tINTPRINTK(\"%s: TSQF\\n\", card->name);\n-\t\tcard->irqstat[12]++;\n-\t\tidt77252_tx(card);\n-\t}\n-\tif (stat & SAR_STAT_TMROF) {\t/* Timer overflow */\n-\t\tINTPRINTK(\"%s: TMROF\\n\", card->name);\n-\t\tcard->irqstat[11]++;\n-\t\tidt77252_collect_stat(card);\n-\t}\n-\n-\tif (stat & SAR_STAT_EPDU) {\t/* Got complete CS-PDU */\n-\t\tINTPRINTK(\"%s: EPDU\\n\", card->name);\n-\t\tcard->irqstat[5]++;\n-\t\tidt77252_rx(card);\n-\t}\n-\tif (stat & SAR_STAT_RSQAF) {\t/* RSQ is 7/8 full */\n-\t\tINTPRINTK(\"%s: RSQAF\\n\", card->name);\n-\t\tcard->irqstat[1]++;\n-\t\tidt77252_rx(card);\n-\t}\n-\tif (stat & SAR_STAT_RSQF) {\t/* RSQ is full */\n-\t\tINTPRINTK(\"%s: RSQF\\n\", card->name);\n-\t\tcard->irqstat[6]++;\n-\t\tidt77252_rx(card);\n-\t}\n-\tif (stat & SAR_STAT_RAWCF) {\t/* Raw cell received */\n-\t\tINTPRINTK(\"%s: RAWCF\\n\", card->name);\n-\t\tcard->irqstat[4]++;\n-\t\tidt77252_rx_raw(card);\n-\t}\n-\n-\tif (stat & SAR_STAT_PHYI) {\t/* PHY device interrupt */\n-\t\tINTPRINTK(\"%s: PHYI\", card->name);\n-\t\tcard->irqstat[10]++;\n-\t\tif (card->atmdev->phy && card->atmdev->phy->interrupt)\n-\t\t\tcard->atmdev->phy->interrupt(card->atmdev);\n-\t}\n-\n-\tif (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |\n-\t\t SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {\n-\n-\t\twritel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);\n-\n-\t\tINTPRINTK(\"%s: FBQA: %04x\\n\", card->name, stat);\n-\n-\t\tif (stat & SAR_STAT_FBQ0A)\n-\t\t\tcard->irqstat[2]++;\n-\t\tif (stat & SAR_STAT_FBQ1A)\n-\t\t\tcard->irqstat[3]++;\n-\t\tif (stat & SAR_STAT_FBQ2A)\n-\t\t\tcard->irqstat[7]++;\n-\t\tif (stat & SAR_STAT_FBQ3A)\n-\t\t\tcard->irqstat[8]++;\n-\n-\t\tschedule_work(&card->tqueue);\n-\t}\n-\n-out:\n-\tclear_bit(IDT77252_BIT_INTERRUPT, &card->flags);\n-\treturn IRQ_HANDLED;\n-}\n-\n-static void\n-idt77252_softint(struct work_struct *work)\n-{\n-\tstruct idt77252_dev *card =\n-\t\tcontainer_of(work, struct idt77252_dev, tqueue);\n-\tu32 stat;\n-\tint done;\n-\n-\tfor (done = 1; ; done = 1) {\n-\t\tstat = readl(SAR_REG_STAT) >> 16;\n-\n-\t\tif ((stat & 0x0f) < SAR_FBQ0_HIGH) {\n-\t\t\tadd_rx_skb(card, 0, SAR_FB_SIZE_0, 32);\n-\t\t\tdone = 0;\n-\t\t}\n-\n-\t\tstat >>= 4;\n-\t\tif ((stat & 0x0f) < SAR_FBQ1_HIGH) {\n-\t\t\tadd_rx_skb(card, 1, SAR_FB_SIZE_1, 32);\n-\t\t\tdone = 0;\n-\t\t}\n-\n-\t\tstat >>= 4;\n-\t\tif ((stat & 0x0f) < SAR_FBQ2_HIGH) {\n-\t\t\tadd_rx_skb(card, 2, SAR_FB_SIZE_2, 32);\n-\t\t\tdone = 0;\n-\t\t}\n-\n-\t\tstat >>= 4;\n-\t\tif ((stat & 0x0f) < SAR_FBQ3_HIGH) {\n-\t\t\tadd_rx_skb(card, 3, SAR_FB_SIZE_3, 32);\n-\t\t\tdone = 0;\n-\t\t}\n-\n-\t\tif (done)\n-\t\t\tbreak;\n-\t}\n-\n-\twritel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);\n-}\n-\n-\n-static int\n-open_card_oam(struct idt77252_dev *card)\n-{\n-\tunsigned long flags;\n-\tunsigned long addr;\n-\tstruct vc_map *vc;\n-\tint vpi, vci;\n-\tint index;\n-\tu32 rcte;\n-\n-\tfor (vpi = 0; vpi < (1 << card->vpibits); vpi++) {\n-\t\tfor (vci = 3; vci < 5; vci++) {\n-\t\t\tindex = VPCI2VC(card, vpi, vci);\n-\n-\t\t\tvc = kzalloc_obj(struct vc_map);\n-\t\t\tif (!vc) {\n-\t\t\t\tprintk(\"%s: can't alloc vc\\n\", card->name);\n-\t\t\t\treturn -ENOMEM;\n-\t\t\t}\n-\t\t\tvc->index = index;\n-\t\t\tcard->vcs[index] = vc;\n-\n-\t\t\tflush_rx_pool(card, &vc->rcv.rx_pool);\n-\n-\t\t\trcte = SAR_RCTE_CONNECTOPEN |\n-\t\t\t SAR_RCTE_RAWCELLINTEN |\n-\t\t\t SAR_RCTE_RCQ |\n-\t\t\t SAR_RCTE_FBP_1;\n-\n-\t\t\taddr = card->rct_base + (vc->index << 2);\n-\t\t\twrite_sram(card, addr, rcte);\n-\n-\t\t\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\t\t\twritel(SAR_CMD_OPEN_CONNECTION | (addr << 2),\n-\t\t\t SAR_REG_CMD);\n-\t\t\twaitfor_idle(card);\n-\t\t\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void\n-close_card_oam(struct idt77252_dev *card)\n-{\n-\tunsigned long flags;\n-\tunsigned long addr;\n-\tstruct vc_map *vc;\n-\tint vpi, vci;\n-\tint index;\n-\n-\tfor (vpi = 0; vpi < (1 << card->vpibits); vpi++) {\n-\t\tfor (vci = 3; vci < 5; vci++) {\n-\t\t\tindex = VPCI2VC(card, vpi, vci);\n-\t\t\tvc = card->vcs[index];\n-\n-\t\t\taddr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;\n-\n-\t\t\tspin_lock_irqsave(&card->cmd_lock, flags);\n-\t\t\twritel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),\n-\t\t\t SAR_REG_CMD);\n-\t\t\twaitfor_idle(card);\n-\t\t\tspin_unlock_irqrestore(&card->cmd_lock, flags);\n-\n-\t\t\tif (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {\n-\t\t\t\tDPRINTK(\"%s: closing a VC \"\n-\t\t\t\t\t\"with pending rx buffers.\\n\",\n-\t\t\t\t\tcard->name);\n-\n-\t\t\t\trecycle_rx_pool_skb(card, &vc->rcv.rx_pool);\n-\t\t\t}\n-\t\t\tkfree(vc);\n-\t\t}\n-\t}\n-}\n-\n-static int\n-open_card_ubr0(struct idt77252_dev *card)\n-{\n-\tstruct vc_map *vc;\n-\n-\tvc = kzalloc_obj(struct vc_map);\n-\tif (!vc) {\n-\t\tprintk(\"%s: can't alloc vc\\n\", card->name);\n-\t\treturn -ENOMEM;\n-\t}\n-\tcard->vcs[0] = vc;\n-\tvc->class = SCHED_UBR0;\n-\n-\tvc->scq = alloc_scq(card, vc->class);\n-\tif (!vc->scq) {\n-\t\tprintk(\"%s: can't get SCQ.\\n\", card->name);\n-\t\tkfree(card->vcs[0]);\n-\t\tcard->vcs[0] = NULL;\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tcard->scd2vc[0] = vc;\n-\tvc->scd_index = 0;\n-\tvc->scq->scd = card->scd_base;\n-\n-\tfill_scd(card, vc->scq, vc->class);\n-\n-\twrite_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);\n-\twrite_sram(card, card->tct_base + 1, 0);\n-\twrite_sram(card, card->tct_base + 2, 0);\n-\twrite_sram(card, card->tct_base + 3, 0);\n-\twrite_sram(card, card->tct_base + 4, 0);\n-\twrite_sram(card, card->tct_base + 5, 0);\n-\twrite_sram(card, card->tct_base + 6, 0);\n-\twrite_sram(card, card->tct_base + 7, TCT_FLAG_UBR);\n-\n-\tclear_bit(VCF_IDLE, &vc->flags);\n-\twritel(TCMDQ_START | 0, SAR_REG_TCMDQ);\n-\treturn 0;\n-}\n-\n-static void\n-close_card_ubr0(struct idt77252_dev *card)\n-{\n-\tstruct vc_map *vc = card->vcs[0];\n-\n-\tfree_scq(card, vc->scq);\n-\tkfree(vc);\n-}\n-\n-static int\n-idt77252_dev_open(struct idt77252_dev *card)\n-{\n-\tu32 conf;\n-\n-\tif (!test_bit(IDT77252_BIT_INIT, &card->flags)) {\n-\t\tprintk(\"%s: SAR not yet initialized.\\n\", card->name);\n-\t\treturn -1;\n-\t}\n-\n-\tconf = SAR_CFG_RXPTH|\t/* enable receive path */\n-\t SAR_RX_DELAY |\t/* interrupt on complete PDU\t\t*/\n-\t SAR_CFG_RAWIE |\t/* interrupt enable on raw cells */\n-\t SAR_CFG_RQFIE |\t/* interrupt on RSQ almost full */\n-\t SAR_CFG_TMOIE |\t/* interrupt on timer overflow */\n-\t SAR_CFG_FBIE |\t/* interrupt on low free buffers */\n-\t SAR_CFG_TXEN |\t/* transmit operation enable */\n-\t SAR_CFG_TXINT |\t/* interrupt on transmit status */\n-\t SAR_CFG_TXUIE |\t/* interrupt on transmit underrun */\n-\t SAR_CFG_TXSFI |\t/* interrupt on TSQ almost full */\n-\t SAR_CFG_PHYIE\t/* enable PHY interrupts\t\t*/\n-\t ;\n-\n-#ifdef CONFIG_ATM_IDT77252_RCV_ALL\n-\t/* Test RAW cell receive. */\n-\tconf |= SAR_CFG_VPECA;\n-#endif\n-\n-\twritel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);\n-\n-\tif (open_card_oam(card)) {\n-\t\tprintk(\"%s: Error initializing OAM.\\n\", card->name);\n-\t\treturn -1;\n-\t}\n-\n-\tif (open_card_ubr0(card)) {\n-\t\tprintk(\"%s: Error initializing UBR0.\\n\", card->name);\n-\t\treturn -1;\n-\t}\n-\n-\tIPRINTK(\"%s: opened IDT77252 ABR SAR.\\n\", card->name);\n-\treturn 0;\n-}\n-\n-static void idt77252_dev_close(struct atm_dev *dev)\n-{\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tu32 conf;\n-\n-\tclose_card_ubr0(card);\n-\tclose_card_oam(card);\n-\n-\tconf = SAR_CFG_RXPTH |\t/* enable receive path */\n-\t SAR_RX_DELAY |\t/* interrupt on complete PDU */\n-\t SAR_CFG_RAWIE |\t/* interrupt enable on raw cells */\n-\t SAR_CFG_RQFIE |\t/* interrupt on RSQ almost full */\n-\t SAR_CFG_TMOIE |\t/* interrupt on timer overflow */\n-\t SAR_CFG_FBIE |\t/* interrupt on low free buffers */\n-\t SAR_CFG_TXEN |\t/* transmit operation enable */\n-\t SAR_CFG_TXINT |\t/* interrupt on transmit status */\n-\t SAR_CFG_TXUIE |\t/* interrupt on xmit underrun */\n-\t SAR_CFG_TXSFI\t/* interrupt on TSQ almost full */\n-\t ;\n-\n-\twritel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);\n-\n-\tDIPRINTK(\"%s: closed IDT77252 ABR SAR.\\n\", card->name);\n-}\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* Initialisation and Deinitialization of IDT77252 */\n-/* */\n-/*****************************************************************************/\n-\n-\n-static void\n-deinit_card(struct idt77252_dev *card)\n-{\n-\tstruct sk_buff *skb;\n-\tint i, j;\n-\n-\tif (!test_bit(IDT77252_BIT_INIT, &card->flags)) {\n-\t\tprintk(\"%s: SAR not yet initialized.\\n\", card->name);\n-\t\treturn;\n-\t}\n-\tDIPRINTK(\"idt77252: deinitialize card %u\\n\", card->index);\n-\n-\twritel(0, SAR_REG_CFG);\n-\n-\tif (card->atmdev)\n-\t\tatm_dev_deregister(card->atmdev);\n-\n-\tfor (i = 0; i < 4; i++) {\n-\t\tfor (j = 0; j < FBQ_SIZE; j++) {\n-\t\t\tskb = card->sbpool[i].skb[j];\n-\t\t\tif (skb) {\n-\t\t\t\tdma_unmap_single(&card->pcidev->dev,\n-\t\t\t\t\t\t IDT77252_PRV_PADDR(skb),\n-\t\t\t\t\t\t (skb_end_pointer(skb) -\n-\t\t\t\t\t\t skb->data),\n-\t\t\t\t\t\t DMA_FROM_DEVICE);\n-\t\t\t\tcard->sbpool[i].skb[j] = NULL;\n-\t\t\t\tdev_kfree_skb(skb);\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tvfree(card->soft_tst);\n-\n-\tvfree(card->scd2vc);\n-\n-\tvfree(card->vcs);\n-\n-\tif (card->raw_cell_hnd) {\n-\t\tdma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),\n-\t\t\t\t card->raw_cell_hnd, card->raw_cell_paddr);\n-\t}\n-\n-\tif (card->rsq.base) {\n-\t\tDIPRINTK(\"%s: Release RSQ ...\\n\", card->name);\n-\t\tdeinit_rsq(card);\n-\t}\n-\n-\tif (card->tsq.base) {\n-\t\tDIPRINTK(\"%s: Release TSQ ...\\n\", card->name);\n-\t\tdeinit_tsq(card);\n-\t}\n-\n-\tDIPRINTK(\"idt77252: Release IRQ.\\n\");\n-\tfree_irq(card->pcidev->irq, card);\n-\n-\tfor (i = 0; i < 4; i++) {\n-\t\tif (card->fbq[i])\n-\t\t\tiounmap(card->fbq[i]);\n-\t}\n-\n-\tif (card->membase)\n-\t\tiounmap(card->membase);\n-\n-\tclear_bit(IDT77252_BIT_INIT, &card->flags);\n-\tDIPRINTK(\"%s: Card deinitialized.\\n\", card->name);\n-}\n-\n-\n-static void init_sram(struct idt77252_dev *card)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < card->sramsize; i += 4)\n-\t\twrite_sram(card, (i >> 2), 0);\n-\n-\t/* set SRAM layout for THIS card */\n-\tif (card->sramsize == (512 * 1024)) {\n-\t\tcard->tct_base = SAR_SRAM_TCT_128_BASE;\n-\t\tcard->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)\n-\t\t / SAR_SRAM_TCT_SIZE;\n-\t\tcard->rct_base = SAR_SRAM_RCT_128_BASE;\n-\t\tcard->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)\n-\t\t / SAR_SRAM_RCT_SIZE;\n-\t\tcard->rt_base = SAR_SRAM_RT_128_BASE;\n-\t\tcard->scd_base = SAR_SRAM_SCD_128_BASE;\n-\t\tcard->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)\n-\t\t / SAR_SRAM_SCD_SIZE;\n-\t\tcard->tst[0] = SAR_SRAM_TST1_128_BASE;\n-\t\tcard->tst[1] = SAR_SRAM_TST2_128_BASE;\n-\t\tcard->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;\n-\t\tcard->abrst_base = SAR_SRAM_ABRSTD_128_BASE;\n-\t\tcard->abrst_size = SAR_ABRSTD_SIZE_8K;\n-\t\tcard->fifo_base = SAR_SRAM_FIFO_128_BASE;\n-\t\tcard->fifo_size = SAR_RXFD_SIZE_32K;\n-\t} else {\n-\t\tcard->tct_base = SAR_SRAM_TCT_32_BASE;\n-\t\tcard->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)\n-\t\t / SAR_SRAM_TCT_SIZE;\n-\t\tcard->rct_base = SAR_SRAM_RCT_32_BASE;\n-\t\tcard->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)\n-\t\t / SAR_SRAM_RCT_SIZE;\n-\t\tcard->rt_base = SAR_SRAM_RT_32_BASE;\n-\t\tcard->scd_base = SAR_SRAM_SCD_32_BASE;\n-\t\tcard->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)\n-\t\t / SAR_SRAM_SCD_SIZE;\n-\t\tcard->tst[0] = SAR_SRAM_TST1_32_BASE;\n-\t\tcard->tst[1] = SAR_SRAM_TST2_32_BASE;\n-\t\tcard->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);\n-\t\tcard->abrst_base = SAR_SRAM_ABRSTD_32_BASE;\n-\t\tcard->abrst_size = SAR_ABRSTD_SIZE_1K;\n-\t\tcard->fifo_base = SAR_SRAM_FIFO_32_BASE;\n-\t\tcard->fifo_size = SAR_RXFD_SIZE_4K;\n-\t}\n-\n-\t/* Initialize TCT */\n-\tfor (i = 0; i < card->tct_size; i++) {\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);\n-\t\twrite_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);\n-\t}\n-\n-\t/* Initialize RCT */\n-\tfor (i = 0; i < card->rct_size; i++) {\n-\t\twrite_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,\n-\t\t\t\t (u32) SAR_RCTE_RAWCELLINTEN);\n-\t\twrite_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,\n-\t\t\t\t (u32) 0);\n-\t\twrite_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,\n-\t\t\t\t (u32) 0);\n-\t\twrite_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,\n-\t\t\t\t (u32) 0xffffffff);\n-\t}\n-\n-\twritel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);\n-\twritel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);\n-\twritel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);\n-\twritel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);\n-\n-\t/* Initialize rate table */\n-\tfor (i = 0; i < 256; i++) {\n-\t\twrite_sram(card, card->rt_base + i, log_to_rate[i]);\n-\t}\n-\n-\tfor (i = 0; i < 128; i++) {\n-\t\tunsigned int tmp;\n-\n-\t\ttmp = rate_to_log[(i << 2) + 0] << 0;\n-\t\ttmp |= rate_to_log[(i << 2) + 1] << 8;\n-\t\ttmp |= rate_to_log[(i << 2) + 2] << 16;\n-\t\ttmp |= rate_to_log[(i << 2) + 3] << 24;\n-\t\twrite_sram(card, card->rt_base + 256 + i, tmp);\n-\t}\n-\n-#if 0 /* Fill RDF and AIR tables. */\n-\tfor (i = 0; i < 128; i++) {\n-\t\tunsigned int tmp;\n-\n-\t\ttmp = RDF[0][(i << 1) + 0] << 16;\n-\t\ttmp |= RDF[0][(i << 1) + 1] << 0;\n-\t\twrite_sram(card, card->rt_base + 512 + i, tmp);\n-\t}\n-\n-\tfor (i = 0; i < 128; i++) {\n-\t\tunsigned int tmp;\n-\n-\t\ttmp = AIR[0][(i << 1) + 0] << 16;\n-\t\ttmp |= AIR[0][(i << 1) + 1] << 0;\n-\t\twrite_sram(card, card->rt_base + 640 + i, tmp);\n-\t}\n-#endif\n-\n-\tIPRINTK(\"%s: initialize rate table ...\\n\", card->name);\n-\twritel(card->rt_base << 2, SAR_REG_RTBL);\n-\n-\t/* Initialize TSTs */\n-\tIPRINTK(\"%s: initialize TST ...\\n\", card->name);\n-\tcard->tst_free = card->tst_size - 2;\t/* last two are jumps */\n-\n-\tfor (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)\n-\t\twrite_sram(card, i, TSTE_OPC_VAR);\n-\twrite_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));\n-\tidt77252_sram_write_errors = 1;\n-\twrite_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));\n-\tidt77252_sram_write_errors = 0;\n-\tfor (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)\n-\t\twrite_sram(card, i, TSTE_OPC_VAR);\n-\twrite_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));\n-\tidt77252_sram_write_errors = 1;\n-\twrite_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));\n-\tidt77252_sram_write_errors = 0;\n-\n-\tcard->tst_index = 0;\n-\twritel(card->tst[0] << 2, SAR_REG_TSTB);\n-\n-\t/* Initialize ABRSTD and Receive FIFO */\n-\tIPRINTK(\"%s: initialize ABRSTD ...\\n\", card->name);\n-\twritel(card->abrst_size | (card->abrst_base << 2),\n-\t SAR_REG_ABRSTD);\n-\n-\tIPRINTK(\"%s: initialize receive fifo ...\\n\", card->name);\n-\twritel(card->fifo_size | (card->fifo_base << 2),\n-\t SAR_REG_RXFD);\n-\n-\tIPRINTK(\"%s: SRAM initialization complete.\\n\", card->name);\n-}\n-\n-static int init_card(struct atm_dev *dev)\n-{\n-\tstruct idt77252_dev *card = dev->dev_data;\n-\tstruct pci_dev *pcidev = card->pcidev;\n-\tunsigned long tmpl, modl;\n-\tunsigned int linkrate, rsvdcr;\n-\tunsigned int tst_entries;\n-\tstruct net_device *tmp;\n-\tchar tname[10];\n-\n-\tu32 size;\n-\tu_char pci_byte;\n-\tu32 conf;\n-\tint i, k;\n-\n-\tif (test_bit(IDT77252_BIT_INIT, &card->flags)) {\n-\t\tprintk(\"Error: SAR already initialized.\\n\");\n-\t\treturn -1;\n-\t}\n-\n-/*****************************************************************/\n-/* P C I C O N F I G U R A T I O N */\n-/*****************************************************************/\n-\n-\t/* Set PCI Retry-Timeout and TRDY timeout */\n-\tIPRINTK(\"%s: Checking PCI retries.\\n\", card->name);\n-\tif (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {\n-\t\tprintk(\"%s: can't read PCI retry timeout.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\tif (pci_byte != 0) {\n-\t\tIPRINTK(\"%s: PCI retry timeout: %d, set to 0.\\n\",\n-\t\t\tcard->name, pci_byte);\n-\t\tif (pci_write_config_byte(pcidev, 0x40, 0) != 0) {\n-\t\t\tprintk(\"%s: can't set PCI retry timeout.\\n\",\n-\t\t\t card->name);\n-\t\t\tdeinit_card(card);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\tIPRINTK(\"%s: Checking PCI TRDY.\\n\", card->name);\n-\tif (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {\n-\t\tprintk(\"%s: can't read PCI TRDY timeout.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\tif (pci_byte != 0) {\n-\t\tIPRINTK(\"%s: PCI TRDY timeout: %d, set to 0.\\n\",\n-\t\t card->name, pci_byte);\n-\t\tif (pci_write_config_byte(pcidev, 0x41, 0) != 0) {\n-\t\t\tprintk(\"%s: can't set PCI TRDY timeout.\\n\", card->name);\n-\t\t\tdeinit_card(card);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\t/* Reset Timer register */\n-\tif (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {\n-\t\tprintk(\"%s: resetting timer overflow.\\n\", card->name);\n-\t\twritel(SAR_STAT_TMROF, SAR_REG_STAT);\n-\t}\n-\tIPRINTK(\"%s: Request IRQ ... \", card->name);\n-\tif (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,\n-\t\t\tcard->name, card) != 0) {\n-\t\tprintk(\"%s: can't allocate IRQ.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\tIPRINTK(\"got %d.\\n\", pcidev->irq);\n-\n-/*****************************************************************/\n-/* C H E C K A N D I N I T S R A M */\n-/*****************************************************************/\n-\n-\tIPRINTK(\"%s: Initializing SRAM\\n\", card->name);\n-\n-\t/* preset size of connecton table, so that init_sram() knows about it */\n-\tconf =\tSAR_CFG_TX_FIFO_SIZE_9 |\t/* Use maximum fifo size */\n-\t\tSAR_CFG_RXSTQ_SIZE_8k |\t\t/* Receive Status Queue is 8k */\n-\t\tSAR_CFG_IDLE_CLP |\t\t/* Set CLP on idle cells */\n-#ifndef ATM_IDT77252_SEND_IDLE\n-\t\tSAR_CFG_NO_IDLE |\t\t/* Do not send idle cells */\n-#endif\n-\t\t0;\n-\n-\tif (card->sramsize == (512 * 1024))\n-\t\tconf |= SAR_CFG_CNTBL_1k;\n-\telse\n-\t\tconf |= SAR_CFG_CNTBL_512;\n-\n-\tswitch (vpibits) {\n-\tcase 0:\n-\t\tconf |= SAR_CFG_VPVCS_0;\n-\t\tbreak;\n-\tdefault:\n-\tcase 1:\n-\t\tconf |= SAR_CFG_VPVCS_1;\n-\t\tbreak;\n-\tcase 2:\n-\t\tconf |= SAR_CFG_VPVCS_2;\n-\t\tbreak;\n-\tcase 8:\n-\t\tconf |= SAR_CFG_VPVCS_8;\n-\t\tbreak;\n-\t}\n-\n-\twritel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);\n-\n-\tinit_sram(card);\n-\n-/********************************************************************/\n-/* A L L O C R A M A N D S E T V A R I O U S T H I N G S */\n-/********************************************************************/\n-\t/* Initialize TSQ */\n-\tif (0 != init_tsq(card)) {\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\t/* Initialize RSQ */\n-\tif (0 != init_rsq(card)) {\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\n-\tcard->vpibits = vpibits;\n-\tif (card->sramsize == (512 * 1024)) {\n-\t\tcard->vcibits = 10 - card->vpibits;\n-\t} else {\n-\t\tcard->vcibits = 9 - card->vpibits;\n-\t}\n-\n-\tcard->vcimask = 0;\n-\tfor (k = 0, i = 1; k < card->vcibits; k++) {\n-\t\tcard->vcimask |= i;\n-\t\ti <<= 1;\n-\t}\n-\n-\tIPRINTK(\"%s: Setting VPI/VCI mask to zero.\\n\", card->name);\n-\twritel(0, SAR_REG_VPM);\n-\n-\t/* Little Endian Order */\n-\twritel(0, SAR_REG_GP);\n-\n-\t/* Initialize RAW Cell Handle Register */\n-\tcard->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,\n-\t\t\t\t\t\t2 * sizeof(u32),\n-\t\t\t\t\t\t&card->raw_cell_paddr,\n-\t\t\t\t\t\tGFP_KERNEL);\n-\tif (!card->raw_cell_hnd) {\n-\t\tprintk(\"%s: memory allocation failure.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\twritel(card->raw_cell_paddr, SAR_REG_RAWHND);\n-\tIPRINTK(\"%s: raw cell handle is at 0x%p.\\n\", card->name,\n-\t\tcard->raw_cell_hnd);\n-\n-\tsize = sizeof(struct vc_map *) * card->tct_size;\n-\tIPRINTK(\"%s: allocate %d byte for VC map.\\n\", card->name, size);\n-\tcard->vcs = vzalloc(size);\n-\tif (!card->vcs) {\n-\t\tprintk(\"%s: memory allocation failure.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\n-\tsize = sizeof(struct vc_map *) * card->scd_size;\n-\tIPRINTK(\"%s: allocate %d byte for SCD to VC mapping.\\n\",\n-\t card->name, size);\n-\tcard->scd2vc = vzalloc(size);\n-\tif (!card->scd2vc) {\n-\t\tprintk(\"%s: memory allocation failure.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\n-\tsize = sizeof(struct tst_info) * (card->tst_size - 2);\n-\tIPRINTK(\"%s: allocate %d byte for TST to VC mapping.\\n\",\n-\t\tcard->name, size);\n-\tcard->soft_tst = vmalloc(size);\n-\tif (!card->soft_tst) {\n-\t\tprintk(\"%s: memory allocation failure.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\tfor (i = 0; i < card->tst_size - 2; i++) {\n-\t\tcard->soft_tst[i].tste = TSTE_OPC_VAR;\n-\t\tcard->soft_tst[i].vc = NULL;\n-\t}\n-\n-\tif (dev->phy == NULL) {\n-\t\tprintk(\"%s: No LT device defined.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\tif (dev->phy->ioctl == NULL) {\n-\t\tprintk(\"%s: LT had no IOCTL function defined.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\n-#ifdef\tCONFIG_ATM_IDT77252_USE_SUNI\n-\t/*\n-\t * this is a jhs hack to get around special functionality in the\n-\t * phy driver for the atecom hardware; the functionality doesn't\n-\t * exist in the linux atm suni driver\n-\t *\n-\t * it isn't the right way to do things, but as the guy from NIST\n-\t * said, talking about their measurement of the fine structure\n-\t * constant, \"it's good enough for government work.\"\n-\t */\n-\tlinkrate = 149760000;\n-#endif\n-\n-\tcard->link_pcr = (linkrate / 8 / 53);\n-\tprintk(\"%s: Linkrate on ATM line : %u bit/s, %u cell/s.\\n\",\n-\t card->name, linkrate, card->link_pcr);\n-\n-#ifdef ATM_IDT77252_SEND_IDLE\n-\tcard->utopia_pcr = card->link_pcr;\n-#else\n-\tcard->utopia_pcr = (160000000 / 8 / 54);\n-#endif\n-\n-\trsvdcr = 0;\n-\tif (card->utopia_pcr > card->link_pcr)\n-\t\trsvdcr = card->utopia_pcr - card->link_pcr;\n-\n-\ttmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);\n-\tmodl = tmpl % (unsigned long)card->utopia_pcr;\n-\ttst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);\n-\tif (modl)\n-\t\ttst_entries++;\n-\tcard->tst_free -= tst_entries;\n-\tfill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);\n-\n-#ifdef HAVE_EEPROM\n-\tidt77252_eeprom_init(card);\n-\tprintk(\"%s: EEPROM: %02x:\", card->name,\n-\t\tidt77252_eeprom_read_status(card));\n-\n-\tfor (i = 0; i < 0x80; i++) {\n-\t\tprintk(\" %02x\", \n-\t\tidt77252_eeprom_read_byte(card, i)\n-\t\t);\n-\t}\n-\tprintk(\"\\n\");\n-#endif /* HAVE_EEPROM */\n-\n-\t/*\n-\t * XXX: \n-\t */\n-\tsprintf(tname, \"eth%d\", card->index);\n-\ttmp = dev_get_by_name(&init_net, tname);\t/* jhs: was \"tmp = dev_get(tname);\" */\n-\tif (tmp) {\n-\t\tmemcpy(card->atmdev->esi, tmp->dev_addr, 6);\n-\t\tdev_put(tmp);\n-\t\tprintk(\"%s: ESI %pM\\n\", card->name, card->atmdev->esi);\n-\t}\n-\t/*\n-\t * XXX: \n-\t */\n-\n-\t/* Set Maximum Deficit Count for now. */\n-\twritel(0xffff, SAR_REG_MDFCT);\n-\n-\tset_bit(IDT77252_BIT_INIT, &card->flags);\n-\n-\tXPRINTK(\"%s: IDT77252 ABR SAR initialization complete.\\n\", card->name);\n-\treturn 0;\n-}\n-\n-\n-/*****************************************************************************/\n-/* */\n-/* Probing of IDT77252 ABR SAR */\n-/* */\n-/*****************************************************************************/\n-\n-\n-static int idt77252_preset(struct idt77252_dev *card)\n-{\n-\tu16 pci_command;\n-\n-/*****************************************************************/\n-/* P C I C O N F I G U R A T I O N */\n-/*****************************************************************/\n-\n-\tXPRINTK(\"%s: Enable PCI master and memory access for SAR.\\n\",\n-\t\tcard->name);\n-\tif (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {\n-\t\tprintk(\"%s: can't read PCI_COMMAND.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-\tif (!(pci_command & PCI_COMMAND_IO)) {\n-\t\tprintk(\"%s: PCI_COMMAND: %04x (?)\\n\",\n-\t\t card->name, pci_command);\n-\t\tdeinit_card(card);\n-\t\treturn (-1);\n-\t}\n-\tpci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n-\tif (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {\n-\t\tprintk(\"%s: can't write PCI_COMMAND.\\n\", card->name);\n-\t\tdeinit_card(card);\n-\t\treturn -1;\n-\t}\n-/*****************************************************************/\n-/* G E N E R I C R E S E T */\n-/*****************************************************************/\n-\n-\t/* Software reset */\n-\twritel(SAR_CFG_SWRST, SAR_REG_CFG);\n-\tmdelay(1);\n-\twritel(0, SAR_REG_CFG);\n-\n-\tIPRINTK(\"%s: Software resetted.\\n\", card->name);\n-\treturn 0;\n-}\n-\n-\n-static unsigned long probe_sram(struct idt77252_dev *card)\n-{\n-\tu32 data, addr;\n-\n-\twritel(0, SAR_REG_DR0);\n-\twritel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);\n-\n-\tfor (addr = 0x4000; addr < 0x80000; addr += 0x4000) {\n-\t\twritel(ATM_POISON, SAR_REG_DR0);\n-\t\twritel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);\n-\n-\t\twritel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);\n-\t\tdata = readl(SAR_REG_DR0);\n-\n-\t\tif (data != 0)\n-\t\t\tbreak;\n-\t}\n-\n-\treturn addr * sizeof(u32);\n-}\n-\n-static int idt77252_init_one(struct pci_dev *pcidev,\n-\t\t\t const struct pci_device_id *id)\n-{\n-\tstatic struct idt77252_dev **last = &idt77252_chain;\n-\tstatic int index = 0;\n-\n-\tunsigned long membase, srambase;\n-\tstruct idt77252_dev *card;\n-\tstruct atm_dev *dev;\n-\tint i, err;\n-\n-\n-\tif ((err = pci_enable_device(pcidev))) {\n-\t\tprintk(\"idt77252: can't enable PCI device at %s\\n\", pci_name(pcidev));\n-\t\treturn err;\n-\t}\n-\n-\tif ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {\n-\t\tprintk(\"idt77252: can't enable DMA for PCI device at %s\\n\", pci_name(pcidev));\n-\t\tgoto err_out_disable_pdev;\n-\t}\n-\n-\tcard = kzalloc_obj(struct idt77252_dev);\n-\tif (!card) {\n-\t\tprintk(\"idt77252-%d: can't allocate private data\\n\", index);\n-\t\terr = -ENOMEM;\n-\t\tgoto err_out_disable_pdev;\n-\t}\n-\tcard->revision = pcidev->revision;\n-\tcard->index = index;\n-\tcard->pcidev = pcidev;\n-\tsprintf(card->name, \"idt77252-%d\", card->index);\n-\n-\tINIT_WORK(&card->tqueue, idt77252_softint);\n-\n-\tmembase = pci_resource_start(pcidev, 1);\n-\tsrambase = pci_resource_start(pcidev, 2);\n-\n-\tmutex_init(&card->mutex);\n-\tspin_lock_init(&card->cmd_lock);\n-\tspin_lock_init(&card->tst_lock);\n-\n-\ttimer_setup(&card->tst_timer, tst_timer, 0);\n-\n-\t/* Do the I/O remapping... */\n-\tcard->membase = ioremap(membase, 1024);\n-\tif (!card->membase) {\n-\t\tprintk(\"%s: can't ioremap() membase\\n\", card->name);\n-\t\terr = -EIO;\n-\t\tgoto err_out_free_card;\n-\t}\n-\n-\tif (idt77252_preset(card)) {\n-\t\tprintk(\"%s: preset failed\\n\", card->name);\n-\t\terr = -EIO;\n-\t\tgoto err_out_iounmap;\n-\t}\n-\n-\tdev = atm_dev_register(\"idt77252\", &pcidev->dev, &idt77252_ops, -1,\n-\t\t\t NULL);\n-\tif (!dev) {\n-\t\tprintk(\"%s: can't register atm device\\n\", card->name);\n-\t\terr = -EIO;\n-\t\tgoto err_out_iounmap;\n-\t}\n-\tdev->dev_data = card;\n-\tcard->atmdev = dev;\n-\n-#ifdef\tCONFIG_ATM_IDT77252_USE_SUNI\n-\tsuni_init(dev);\n-\tif (!dev->phy) {\n-\t\tprintk(\"%s: can't init SUNI\\n\", card->name);\n-\t\terr = -EIO;\n-\t\tgoto err_out_deinit_card;\n-\t}\n-#endif\t/* CONFIG_ATM_IDT77252_USE_SUNI */\n-\n-\tcard->sramsize = probe_sram(card);\n-\n-\tfor (i = 0; i < 4; i++) {\n-\t\tcard->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);\n-\t\tif (!card->fbq[i]) {\n-\t\t\tprintk(\"%s: can't ioremap() FBQ%d\\n\", card->name, i);\n-\t\t\terr = -EIO;\n-\t\t\tgoto err_out_deinit_card;\n-\t\t}\n-\t}\n-\n-\tprintk(\"%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\\n\",\n-\t card->name, ((card->revision > 1) && (card->revision < 25)) ?\n-\t 'A' + card->revision - 1 : '?', membase, srambase,\n-\t card->sramsize / 1024);\n-\n-\tif (init_card(dev)) {\n-\t\tprintk(\"%s: init_card failed\\n\", card->name);\n-\t\terr = -EIO;\n-\t\tgoto err_out_deinit_card;\n-\t}\n-\n-\tdev->ci_range.vpi_bits = card->vpibits;\n-\tdev->ci_range.vci_bits = card->vcibits;\n-\tdev->link_rate = card->link_pcr;\n-\n-\tif (dev->phy->start)\n-\t\tdev->phy->start(dev);\n-\n-\tif (idt77252_dev_open(card)) {\n-\t\tprintk(\"%s: dev_open failed\\n\", card->name);\n-\t\terr = -EIO;\n-\t\tgoto err_out_stop;\n-\t}\n-\n-\t*last = card;\n-\tlast = &card->next;\n-\tindex++;\n-\n-\treturn 0;\n-\n-err_out_stop:\n-\tif (dev->phy->stop)\n-\t\tdev->phy->stop(dev);\n-\n-err_out_deinit_card:\n-\tdeinit_card(card);\n-\n-err_out_iounmap:\n-\tiounmap(card->membase);\n-\n-err_out_free_card:\n-\tkfree(card);\n-\n-err_out_disable_pdev:\n-\tpci_disable_device(pcidev);\n-\treturn err;\n-}\n-\n-static const struct pci_device_id idt77252_pci_tbl[] =\n-{\n-\t{ PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },\n-\t{ 0, }\n-};\n-\n-MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);\n-\n-static struct pci_driver idt77252_driver = {\n-\t.name\t\t= \"idt77252\",\n-\t.id_table\t= idt77252_pci_tbl,\n-\t.probe\t\t= idt77252_init_one,\n-};\n-\n-static int __init idt77252_init(void)\n-{\n-\tstruct sk_buff *skb;\n-\n-\tprintk(\"%s: at %p\\n\", __func__, idt77252_init);\n-\tBUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct idt77252_skb_prv) + sizeof(struct atm_skb_data));\n-\treturn pci_register_driver(&idt77252_driver);\n-}\n-\n-static void __exit idt77252_exit(void)\n-{\n-\tstruct idt77252_dev *card;\n-\tstruct atm_dev *dev;\n-\n-\tpci_unregister_driver(&idt77252_driver);\n-\n-\twhile (idt77252_chain) {\n-\t\tcard = idt77252_chain;\n-\t\tdev = card->atmdev;\n-\t\tidt77252_chain = card->next;\n-\t\ttimer_shutdown_sync(&card->tst_timer);\n-\n-\t\tif (dev->phy->stop)\n-\t\t\tdev->phy->stop(dev);\n-\t\tdeinit_card(card);\n-\t\tpci_disable_device(card->pcidev);\n-\t\tkfree(card);\n-\t}\n-\n-\tDIPRINTK(\"idt77252: finished cleanup-module().\\n\");\n-}\n-\n-module_init(idt77252_init);\n-module_exit(idt77252_exit);\n-\n-MODULE_LICENSE(\"GPL\");\n-\n-module_param(vpibits, uint, 0);\n-MODULE_PARM_DESC(vpibits, \"number of VPI bits supported (0, 1, or 2)\");\n-#ifdef CONFIG_ATM_IDT77252_DEBUG\n-module_param(debug, ulong, 0644);\n-MODULE_PARM_DESC(debug, \"debug bitmap, see drivers/atm/idt77252.h\");\n-#endif\n-\n-MODULE_AUTHOR(\"Eddie C. Dost \");\n-MODULE_DESCRIPTION(\"IDT77252 ABR SAR Driver\");\ndiff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c\ndeleted file mode 100644\nindex 0d38e93772c2..000000000000\n--- a/drivers/atm/iphase.c\n+++ /dev/null\n@@ -1,3283 +0,0 @@\n-/******************************************************************************\n- iphase.c: Device driver for Interphase ATM PCI adapter cards \n- Author: Peter Wang \n-\t\t Some fixes: Arnaldo Carvalho de Melo \n- Interphase Corporation \n- Version: 1.0 \n-*******************************************************************************\n- \n- This software may be used and distributed according to the terms\n- of the GNU General Public License (GPL), incorporated herein by reference.\n- Drivers based on this skeleton fall under the GPL and must retain\n- the authorship (implicit copyright) notice.\n-\n- This program is distributed in the hope that it will be useful, but\n- WITHOUT ANY WARRANTY; without even the implied warranty of\n- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n- General Public License for more details.\n- \n- Modified from an incomplete driver for Interphase 5575 1KVC 1M card which \n- was originally written by Monalisa Agrawal at UNH. Now this driver \n- supports a variety of varients of Interphase ATM PCI (i)Chip adapter \n- card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM) \n- in terms of PHY type, the size of control memory and the size of \n- packet memory. The following are the change log and history:\n- \n- Bugfix the Mona's UBR driver.\n- Modify the basic memory allocation and dma logic.\n- Port the driver to the latest kernel from 2.0.46.\n- Complete the ABR logic of the driver, and added the ABR work-\n- around for the hardware anormalies.\n- Add the CBR support.\n-\t Add the flow control logic to the driver to allow rate-limit VC.\n- Add 4K VC support to the board with 512K control memory.\n- Add the support of all the variants of the Interphase ATM PCI \n- (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525\n- (25M UTP25) and x531 (DS3 and E3).\n- Add SMP support.\n-\n- Support and updates available at: ftp://ftp.iphase.com/pub/atm\n-\n-*******************************************************************************/\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \"iphase.h\"\t\t \n-#include \"suni.h\"\t\t \n-#define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))\n-\n-#define PRIV(dev) ((struct suni_priv *) dev->phy_data)\n-\n-static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr);\n-static void desc_dbg(IADEV *iadev);\n-\n-static IADEV *ia_dev[8];\n-static struct atm_dev *_ia_dev[8];\n-static int iadev_count;\n-static void ia_led_timer(struct timer_list *unused);\n-static DEFINE_TIMER(ia_timer, ia_led_timer);\n-static int IA_TX_BUF = DFL_TX_BUFFERS, IA_TX_BUF_SZ = DFL_TX_BUF_SZ;\n-static int IA_RX_BUF = DFL_RX_BUFFERS, IA_RX_BUF_SZ = DFL_RX_BUF_SZ;\n-static uint IADebugFlag = /* IF_IADBG_ERR | IF_IADBG_CBR| IF_IADBG_INIT_ADAPTER\n- |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0; \n-\n-module_param(IA_TX_BUF, int, 0);\n-module_param(IA_TX_BUF_SZ, int, 0);\n-module_param(IA_RX_BUF, int, 0);\n-module_param(IA_RX_BUF_SZ, int, 0);\n-module_param(IADebugFlag, uint, 0644);\n-\n-MODULE_DESCRIPTION(\"Driver for Interphase ATM PCI NICs\");\n-MODULE_LICENSE(\"GPL\");\n-\n-/**************************** IA_LIB **********************************/\n-\n-static void ia_init_rtn_q (IARTN_Q *que) \n-{ \n- que->next = NULL; \n- que->tail = NULL; \n-}\n-\n-static void ia_enque_head_rtn_q (IARTN_Q *que, IARTN_Q * data) \n-{\n- data->next = NULL;\n- if (que->next == NULL) \n- que->next = que->tail = data;\n- else {\n- data->next = que->next;\n- que->next = data;\n- } \n- return;\n-}\n-\n-static int ia_enque_rtn_q (IARTN_Q *que, struct desc_tbl_t data) {\n- IARTN_Q *entry = kmalloc_obj(*entry, GFP_ATOMIC);\n- if (!entry)\n- return -ENOMEM;\n- entry->data = data;\n- entry->next = NULL;\n- if (que->next == NULL) \n- que->next = que->tail = entry;\n- else {\n- que->tail->next = entry;\n- que->tail = que->tail->next;\n- } \n- return 1;\n-}\n-\n-static IARTN_Q * ia_deque_rtn_q (IARTN_Q *que) {\n- IARTN_Q *tmpdata;\n- if (que->next == NULL)\n- return NULL;\n- tmpdata = que->next;\n- if ( que->next == que->tail) \n- que->next = que->tail = NULL;\n- else \n- que->next = que->next->next;\n- return tmpdata;\n-}\n-\n-static void ia_hack_tcq(IADEV *dev) {\n-\n- u_short \t\tdesc1;\n- u_short\t\ttcq_wr;\n- struct ia_vcc *iavcc_r = NULL; \n-\n- tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff;\n- while (dev->host_tcq_wr != tcq_wr) {\n- desc1 = *(u_short *)(dev->seg_ram + dev->host_tcq_wr);\n- if (!desc1) ;\n- else if (!dev->desc_tbl[desc1 -1].timestamp) {\n- IF_ABR(printk(\" Desc %d is reset at %ld\\n\", desc1 -1, jiffies);)\n- *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0;\n- } \n- else if (dev->desc_tbl[desc1 -1].timestamp) {\n- if (!(iavcc_r = dev->desc_tbl[desc1 -1].iavcc)) { \n- printk(\"IA: Fatal err in get_desc\\n\");\n- continue;\n- }\n- iavcc_r->vc_desc_cnt--;\n- dev->desc_tbl[desc1 -1].timestamp = 0;\n- IF_EVENT(printk(\"ia_hack: return_q skb = 0x%p desc = %d\\n\",\n- dev->desc_tbl[desc1 -1].txskb, desc1);)\n- if (iavcc_r->pcr < dev->rate_limit) {\n- IA_SKB_STATE (dev->desc_tbl[desc1-1].txskb) |= IA_TX_DONE;\n- if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0)\n- printk(\"ia_hack_tcq: No memory available\\n\");\n- } \n- dev->desc_tbl[desc1 -1].iavcc = NULL;\n- dev->desc_tbl[desc1 -1].txskb = NULL;\n- }\n- dev->host_tcq_wr += 2;\n- if (dev->host_tcq_wr > dev->ffL.tcq_ed) \n- dev->host_tcq_wr = dev->ffL.tcq_st;\n- }\n-} /* ia_hack_tcq */\n-\n-static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) {\n- u_short \t\tdesc_num, i;\n- struct ia_vcc *iavcc_r = NULL; \n- unsigned long delta;\n- static unsigned long timer = 0;\n- int ltimeout;\n-\n- ia_hack_tcq (dev);\n- if((time_after(jiffies,timer+50)) || ((dev->ffL.tcq_rd==dev->host_tcq_wr))) {\n- timer = jiffies; \n- i=0;\n- while (i < dev->num_tx_desc) {\n- if (!dev->desc_tbl[i].timestamp) {\n- i++;\n- continue;\n- }\n- ltimeout = dev->desc_tbl[i].iavcc->ltimeout; \n- delta = jiffies - dev->desc_tbl[i].timestamp;\n- if (delta >= ltimeout) {\n- IF_ABR(printk(\"RECOVER run!! desc_tbl %d = %d delta = %ld, time = %ld\\n\", i,dev->desc_tbl[i].timestamp, delta, jiffies);)\n- if (dev->ffL.tcq_rd == dev->ffL.tcq_st) \n- dev->ffL.tcq_rd = dev->ffL.tcq_ed;\n- else \n- dev->ffL.tcq_rd -= 2;\n- *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd) = i+1;\n- if (!dev->desc_tbl[i].txskb || !(iavcc_r = dev->desc_tbl[i].iavcc))\n- printk(\"Fatal err, desc table vcc or skb is NULL\\n\");\n- else \n- iavcc_r->vc_desc_cnt--;\n- dev->desc_tbl[i].timestamp = 0;\n- dev->desc_tbl[i].iavcc = NULL;\n- dev->desc_tbl[i].txskb = NULL;\n- }\n- i++;\n- } /* while */\n- }\n- if (dev->ffL.tcq_rd == dev->host_tcq_wr) \n- return 0xFFFF;\n- \n- /* Get the next available descriptor number from TCQ */\n- desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);\n-\n- while (!desc_num || (dev->desc_tbl[desc_num -1]).timestamp) {\n- dev->ffL.tcq_rd += 2;\n- if (dev->ffL.tcq_rd > dev->ffL.tcq_ed) \n-\tdev->ffL.tcq_rd = dev->ffL.tcq_st;\n- if (dev->ffL.tcq_rd == dev->host_tcq_wr) \n- return 0xFFFF; \n- desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);\n- }\n-\n- /* get system time */\n- dev->desc_tbl[desc_num -1].timestamp = jiffies;\n- return desc_num;\n-}\n-\n-static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) {\n- u_char \tfoundLockUp;\n- vcstatus_t\t\t*vcstatus;\n- u_short *shd_tbl;\n- u_short tempCellSlot, tempFract;\n- struct main_vc *abr_vc = (struct main_vc *)dev->MAIN_VC_TABLE_ADDR;\n- struct ext_vc *eabr_vc = (struct ext_vc *)dev->EXT_VC_TABLE_ADDR;\n- u_int i;\n-\n- if (vcc->qos.txtp.traffic_class == ATM_ABR) {\n- vcstatus = (vcstatus_t *) &(dev->testTable[vcc->vci]->vc_status);\n- vcstatus->cnt++;\n- foundLockUp = 0;\n- if( vcstatus->cnt == 0x05 ) {\n- abr_vc += vcc->vci;\n-\teabr_vc += vcc->vci;\n-\tif( eabr_vc->last_desc ) {\n-\t if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) {\n- /* Wait for 10 Micro sec */\n- udelay(10);\n-\t if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE))\n-\t\t foundLockUp = 1;\n- }\n-\t else {\n-\t tempCellSlot = abr_vc->last_cell_slot;\n- tempFract = abr_vc->fraction;\n- if((tempCellSlot == dev->testTable[vcc->vci]->lastTime)\n- && (tempFract == dev->testTable[vcc->vci]->fract))\n-\t foundLockUp = 1; \t\t \n- dev->testTable[vcc->vci]->lastTime = tempCellSlot; \n- dev->testTable[vcc->vci]->fract = tempFract; \n-\t } \t \n- } /* last descriptor */\t \t \n- vcstatus->cnt = 0; \t\n- } /* vcstatus->cnt */\n-\t\n- if (foundLockUp) {\n- IF_ABR(printk(\"LOCK UP found\\n\");) \n-\twritew(0xFFFD, dev->seg_reg+MODE_REG_0);\n- /* Wait for 10 Micro sec */\n- udelay(10); \n- abr_vc->status &= 0xFFF8;\n- abr_vc->status |= 0x0001; /* state is idle */\n-\tshd_tbl = (u_short *)dev->ABR_SCHED_TABLE_ADDR; \n-\tfor( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ );\n-\tif (i < dev->num_vc)\n- shd_tbl[i] = vcc->vci;\n- else\n- IF_ERR(printk(\"ABR Seg. may not continue on VC %x\\n\",vcc->vci);)\n- writew(T_ONLINE, dev->seg_reg+MODE_REG_0);\n- writew(~(TRANSMIT_DONE|TCQ_NOT_EMPTY), dev->seg_reg+SEG_MASK_REG);\n- writew(TRANSMIT_DONE, dev->seg_reg+SEG_INTR_STATUS_REG); \n-\tvcstatus->cnt = 0;\n- } /* foundLockUp */\n-\n- } /* if an ABR VC */\n-\n-\n-}\n- \n-/*\n-** Conversion of 24-bit cellrate (cells/sec) to 16-bit floating point format.\n-**\n-** +----+----+------------------+-------------------------------+\n-** | R | NZ | 5-bit exponent | 9-bit mantissa |\n-** +----+----+------------------+-------------------------------+\n-** \n-** R = reserved (written as 0)\n-** NZ = 0 if 0 cells/sec; 1 otherwise\n-**\n-** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec\n-*/\n-static u16\n-cellrate_to_float(u32 cr)\n-{\n-\n-#define\tNZ \t\t0x4000\n-#define\tM_BITS\t\t9\t\t/* Number of bits in mantissa */\n-#define\tE_BITS\t\t5\t\t/* Number of bits in exponent */\n-#define\tM_MASK\t\t0x1ff\t\t\n-#define\tE_MASK\t\t0x1f\n- u16 flot;\n- u32\ttmp = cr & 0x00ffffff;\n- int \ti = 0;\n- if (cr == 0)\n- return 0;\n- while (tmp != 1) {\n- tmp >>= 1;\n- i++;\n- }\n- if (i == M_BITS)\n- flot = NZ | (i << M_BITS) | (cr & M_MASK);\n- else if (i < M_BITS)\n- flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK);\n- else\n- flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK);\n- return flot;\n-}\n-\n-#if 0\n-/*\n-** Conversion of 16-bit floating point format to 24-bit cellrate (cells/sec).\n-*/\n-static u32\n-float_to_cellrate(u16 rate)\n-{\n- u32 exp, mantissa, cps;\n- if ((rate & NZ) == 0)\n- return 0;\n- exp = (rate >> M_BITS) & E_MASK;\n- mantissa = rate & M_MASK;\n- if (exp == 0)\n- return 1;\n- cps = (1 << M_BITS) | mantissa;\n- if (exp == M_BITS)\n- cps = cps;\n- else if (exp > M_BITS)\n- cps <<= (exp - M_BITS);\n- else\n- cps >>= (M_BITS - exp);\n- return cps;\n-}\n-#endif \n-\n-static void init_abr_vc (IADEV *dev, srv_cls_param_t *srv_p) {\n- srv_p->class_type = ATM_ABR;\n- srv_p->pcr = dev->LineRate;\n- srv_p->mcr = 0;\n- srv_p->icr = 0x055cb7;\n- srv_p->tbe = 0xffffff;\n- srv_p->frtt = 0x3a;\n- srv_p->rif = 0xf;\n- srv_p->rdf = 0xb;\n- srv_p->nrm = 0x4;\n- srv_p->trm = 0x7;\n- srv_p->cdf = 0x3;\n- srv_p->adtf = 50;\n-}\n-\n-static int\n-ia_open_abr_vc(IADEV *dev, srv_cls_param_t *srv_p, \n- struct atm_vcc *vcc, u8 flag)\n-{\n- f_vc_abr_entry *f_abr_vc;\n- r_vc_abr_entry *r_abr_vc;\n- u32\t\ticr;\n- u8\t\ttrm, nrm, crm;\n- u16\t\tadtf, air, *ptr16;\t\n- f_abr_vc =(f_vc_abr_entry *)dev->MAIN_VC_TABLE_ADDR;\n- f_abr_vc += vcc->vci; \n- switch (flag) {\n- case 1: /* FFRED initialization */\n-#if 0 /* sanity check */\n- if (srv_p->pcr == 0)\n- return INVALID_PCR;\n- if (srv_p->pcr > dev->LineRate)\n- srv_p->pcr = dev->LineRate;\n- if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate)\n-\t return MCR_UNAVAILABLE;\n- if (srv_p->mcr > srv_p->pcr)\n-\t return INVALID_MCR;\n- if (!(srv_p->icr))\n-\t srv_p->icr = srv_p->pcr;\n- if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr))\n-\t return INVALID_ICR;\n- if ((srv_p->tbe < MIN_TBE) || (srv_p->tbe > MAX_TBE))\n-\t return INVALID_TBE;\n- if ((srv_p->frtt < MIN_FRTT) || (srv_p->frtt > MAX_FRTT))\n-\t return INVALID_FRTT;\n- if (srv_p->nrm > MAX_NRM)\n-\t return INVALID_NRM;\n- if (srv_p->trm > MAX_TRM)\n-\t return INVALID_TRM;\n- if (srv_p->adtf > MAX_ADTF)\n- return INVALID_ADTF;\n- else if (srv_p->adtf == 0)\n-\t srv_p->adtf = 1;\n- if (srv_p->cdf > MAX_CDF)\n-\t return INVALID_CDF;\n- if (srv_p->rif > MAX_RIF)\n-\t return INVALID_RIF;\n- if (srv_p->rdf > MAX_RDF)\n-\t return INVALID_RDF;\n-#endif\n- memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc));\n- f_abr_vc->f_vc_type = ABR;\n- nrm = 2 << srv_p->nrm; /* (2 ** (srv_p->nrm +1)) */\n-\t\t\t /* i.e 2**n = 2 << (n-1) */\n- f_abr_vc->f_nrm = nrm << 8 | nrm;\n- trm = 100000/(2 << (16 - srv_p->trm));\n- if ( trm == 0) trm = 1;\n- f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm;\n- crm = srv_p->tbe / nrm;\n- if (crm == 0) crm = 1;\n- f_abr_vc->f_crm = crm & 0xff;\n- f_abr_vc->f_pcr = cellrate_to_float(srv_p->pcr);\n- icr = min( srv_p->icr, (srv_p->tbe > srv_p->frtt) ?\n-\t\t\t\t((srv_p->tbe/srv_p->frtt)*1000000) :\n-\t\t\t\t(1000000/(srv_p->frtt/srv_p->tbe)));\n- f_abr_vc->f_icr = cellrate_to_float(icr);\n- adtf = (10000 * srv_p->adtf)/8192;\n- if (adtf == 0) adtf = 1; \n- f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff;\n- f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr);\n- f_abr_vc->f_acr = f_abr_vc->f_icr;\n- f_abr_vc->f_status = 0x0042;\n- break;\n- case 0: /* RFRED initialization */\t\n- ptr16 = (u_short *)(dev->reass_ram + REASS_TABLE*dev->memSize); \n- *(ptr16 + vcc->vci) = NO_AAL5_PKT | REASS_ABR;\n- r_abr_vc = (r_vc_abr_entry*)(dev->reass_ram+ABR_VC_TABLE*dev->memSize);\n- r_abr_vc += vcc->vci;\n- r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f;\n- air = srv_p->pcr << (15 - srv_p->rif);\n- if (air == 0) air = 1;\n- r_abr_vc->r_air = cellrate_to_float(air);\n- dev->testTable[vcc->vci]->vc_status = VC_ACTIVE | VC_ABR;\n- dev->sum_mcr\t += srv_p->mcr;\n- dev->n_abr++;\n- break;\n- default:\n- break;\n- }\n- return\t0;\n-}\n-static int ia_cbr_setup (IADEV *dev, struct atm_vcc *vcc) {\n- u32 rateLow=0, rateHigh, rate;\n- int entries;\n- struct ia_vcc *ia_vcc;\n-\n- int idealSlot =0, testSlot, toBeAssigned, inc;\n- u32 spacing;\n- u16 *SchedTbl, *TstSchedTbl;\n- u16 cbrVC, vcIndex;\n- u32 fracSlot = 0;\n- u32 sp_mod = 0;\n- u32 sp_mod2 = 0;\n-\n- /* IpAdjustTrafficParams */\n- if (vcc->qos.txtp.max_pcr <= 0) {\n- IF_ERR(printk(\"PCR for CBR not defined\\n\");)\n- return -1;\n- }\n- rate = vcc->qos.txtp.max_pcr;\n- entries = rate / dev->Granularity;\n- IF_CBR(printk(\"CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\\n\",\n- entries, rate, dev->Granularity);)\n- if (entries < 1)\n- IF_CBR(printk(\"CBR: Bandwidth smaller than granularity of CBR table\\n\");) \n- rateLow = entries * dev->Granularity;\n- rateHigh = (entries + 1) * dev->Granularity;\n- if (3*(rate - rateLow) > (rateHigh - rate))\n- entries++;\n- if (entries > dev->CbrRemEntries) {\n- IF_CBR(printk(\"CBR: Not enough bandwidth to support this PCR.\\n\");)\n- IF_CBR(printk(\"Entries = 0x%x, CbrRemEntries = 0x%x.\\n\",\n- entries, dev->CbrRemEntries);)\n- return -EBUSY;\n- } \n-\n- ia_vcc = INPH_IA_VCC(vcc);\n- ia_vcc->NumCbrEntry = entries; \n- dev->sum_mcr += entries * dev->Granularity; \n- /* IaFFrednInsertCbrSched */\n- // Starting at an arbitrary location, place the entries into the table\n- // as smoothly as possible\n- cbrVC = 0;\n- spacing = dev->CbrTotEntries / entries;\n- sp_mod = dev->CbrTotEntries % entries; // get modulo\n- toBeAssigned = entries;\n- fracSlot = 0;\n- vcIndex = vcc->vci;\n- IF_CBR(printk(\"Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\\n\",vcIndex,spacing,sp_mod);)\n- while (toBeAssigned)\n- {\n- // If this is the first time, start the table loading for this connection\n- // as close to entryPoint as possible.\n- if (toBeAssigned == entries)\n- {\n- idealSlot = dev->CbrEntryPt;\n- dev->CbrEntryPt += 2; // Adding 2 helps to prevent clumping\n- if (dev->CbrEntryPt >= dev->CbrTotEntries) \n- dev->CbrEntryPt -= dev->CbrTotEntries;// Wrap if necessary\n- } else {\n- idealSlot += (u32)(spacing + fracSlot); // Point to the next location\n- // in the table that would be smoothest\n- fracSlot = ((sp_mod + sp_mod2) / entries); // get new integer part\n- sp_mod2 = ((sp_mod + sp_mod2) % entries); // calc new fractional part\n- }\n- if (idealSlot >= (int)dev->CbrTotEntries) \n- idealSlot -= dev->CbrTotEntries; \n- // Continuously check around this ideal value until a null\n- // location is encountered.\n- SchedTbl = (u16*)(dev->seg_ram+CBR_SCHED_TABLE*dev->memSize); \n- inc = 0;\n- testSlot = idealSlot;\n- TstSchedTbl = (u16*)(SchedTbl+testSlot); //set index and read in value\n- IF_CBR(printk(\"CBR Testslot 0x%x AT Location 0x%p, NumToAssign=%d\\n\",\n- testSlot, TstSchedTbl,toBeAssigned);)\n- memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));\n- while (cbrVC) // If another VC at this location, we have to keep looking\n- {\n- inc++;\n- testSlot = idealSlot - inc;\n- if (testSlot < 0) { // Wrap if necessary\n- testSlot += dev->CbrTotEntries;\n- IF_CBR(printk(\"Testslot Wrap. STable Start=0x%p,Testslot=%d\\n\",\n- SchedTbl,testSlot);)\n- }\n- TstSchedTbl = (u16 *)(SchedTbl + testSlot); // set table index\n- memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC)); \n- if (!cbrVC)\n- break;\n- testSlot = idealSlot + inc;\n- if (testSlot >= (int)dev->CbrTotEntries) { // Wrap if necessary\n- testSlot -= dev->CbrTotEntries;\n- IF_CBR(printk(\"TotCbrEntries=%d\",dev->CbrTotEntries);)\n- IF_CBR(printk(\" Testslot=0x%x ToBeAssgned=%d\\n\", \n- testSlot, toBeAssigned);)\n- } \n- // set table index and read in value\n- TstSchedTbl = (u16*)(SchedTbl + testSlot);\n- IF_CBR(printk(\"Reading CBR Tbl from 0x%p, CbrVal=0x%x Iteration %d\\n\",\n- TstSchedTbl,cbrVC,inc);)\n- memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));\n- } /* while */\n- // Move this VCI number into this location of the CBR Sched table.\n- memcpy((caddr_t)TstSchedTbl, (caddr_t)&vcIndex, sizeof(*TstSchedTbl));\n- dev->CbrRemEntries--;\n- toBeAssigned--;\n- } /* while */ \n-\n- /* IaFFrednCbrEnable */\n- dev->NumEnabledCBR++;\n- if (dev->NumEnabledCBR == 1) {\n- writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS);\n- IF_CBR(printk(\"CBR is enabled\\n\");)\n- }\n- return 0;\n-}\n-static void ia_cbrVc_close (struct atm_vcc *vcc) {\n- IADEV *iadev;\n- u16 *SchedTbl, NullVci = 0;\n- u32 i, NumFound;\n-\n- iadev = INPH_IA_DEV(vcc->dev);\n- iadev->NumEnabledCBR--;\n- SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);\n- if (iadev->NumEnabledCBR == 0) {\n- writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);\n- IF_CBR (printk(\"CBR support disabled\\n\");)\n- }\n- NumFound = 0;\n- for (i=0; i < iadev->CbrTotEntries; i++)\n- {\n- if (*SchedTbl == vcc->vci) {\n- iadev->CbrRemEntries++;\n- *SchedTbl = NullVci;\n- IF_CBR(NumFound++;)\n- }\n- SchedTbl++; \n- } \n- IF_CBR(printk(\"Exit ia_cbrVc_close, NumRemoved=%d\\n\",NumFound);)\n-}\n-\n-static int ia_avail_descs(IADEV *iadev) {\n- int tmp = 0;\n- ia_hack_tcq(iadev);\n- if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)\n- tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;\n- else\n- tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -\n- iadev->ffL.tcq_st) / 2;\n- return tmp;\n-} \n-\n-static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb);\n-\n-static int ia_que_tx (IADEV *iadev) { \n- struct sk_buff *skb;\n- int num_desc;\n- struct atm_vcc *vcc;\n- num_desc = ia_avail_descs(iadev);\n-\n- while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {\n- if (!(vcc = ATM_SKB(skb)->vcc)) {\n- dev_kfree_skb_any(skb);\n- printk(\"ia_que_tx: Null vcc\\n\");\n- break;\n- }\n- if (!test_bit(ATM_VF_READY,&vcc->flags)) {\n- dev_kfree_skb_any(skb);\n- printk(\"Free the SKB on closed vci %d \\n\", vcc->vci);\n- break;\n- }\n- if (ia_pkt_tx (vcc, skb)) {\n- skb_queue_head(&iadev->tx_backlog, skb);\n- }\n- num_desc--;\n- }\n- return 0;\n-}\n-\n-static void ia_tx_poll (IADEV *iadev) {\n- struct atm_vcc *vcc = NULL;\n- struct sk_buff *skb = NULL, *skb1 = NULL;\n- struct ia_vcc *iavcc;\n- IARTN_Q * rtne;\n-\n- ia_hack_tcq(iadev);\n- while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {\n- skb = rtne->data.txskb;\n- if (!skb) {\n- printk(\"ia_tx_poll: skb is null\\n\");\n- goto out;\n- }\n- vcc = ATM_SKB(skb)->vcc;\n- if (!vcc) {\n- printk(\"ia_tx_poll: vcc is null\\n\");\n- dev_kfree_skb_any(skb);\n-\t goto out;\n- }\n-\n- iavcc = INPH_IA_VCC(vcc);\n- if (!iavcc) {\n- printk(\"ia_tx_poll: iavcc is null\\n\");\n- dev_kfree_skb_any(skb);\n-\t goto out;\n- }\n-\n- skb1 = skb_dequeue(&iavcc->txing_skb);\n- while (skb1 && (skb1 != skb)) {\n- if (!(IA_SKB_STATE(skb1) & IA_TX_DONE)) {\n- printk(\"IA_tx_intr: Vci %d lost pkt!!!\\n\", vcc->vci);\n- }\n- IF_ERR(printk(\"Release the SKB not match\\n\");)\n- if ((vcc->pop) && (skb1->len != 0))\n- {\n- vcc->pop(vcc, skb1);\n- IF_EVENT(printk(\"Transmit Done - skb 0x%lx return\\n\",\n- (long)skb1);)\n- }\n- else \n- dev_kfree_skb_any(skb1);\n- skb1 = skb_dequeue(&iavcc->txing_skb);\n- } \n- if (!skb1) {\n- IF_EVENT(printk(\"IA: Vci %d - skb not found requeued\\n\",vcc->vci);)\n- ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);\n- break;\n- }\n- if ((vcc->pop) && (skb->len != 0))\n- {\n- vcc->pop(vcc, skb);\n- IF_EVENT(printk(\"Tx Done - skb 0x%lx return\\n\",(long)skb);)\n- }\n- else \n- dev_kfree_skb_any(skb);\n- kfree(rtne);\n- }\n- ia_que_tx(iadev);\n-out:\n- return;\n-}\n-#if 0\n-static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)\n-{\n- u32\tt;\n-\tint\ti;\n-\t/*\n-\t * Issue a command to enable writes to the NOVRAM\n-\t */\n-\tNVRAM_CMD (EXTEND + EWEN);\n-\tNVRAM_CLR_CE;\n-\t/*\n-\t * issue the write command\n-\t */\n-\tNVRAM_CMD(IAWRITE + addr);\n-\t/* \n-\t * Send the data, starting with D15, then D14, and so on for 16 bits\n-\t */\n-\tfor (i=15; i>=0; i--) {\n-\t\tNVRAM_CLKOUT (val & 0x8000);\n-\t\tval <<= 1;\n-\t}\n-\tNVRAM_CLR_CE;\n-\tCFG_OR(NVCE);\n-\tt = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \n-\twhile (!(t & NVDO))\n-\t\tt = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \n-\n-\tNVRAM_CLR_CE;\n-\t/*\n-\t * disable writes again\n-\t */\n-\tNVRAM_CMD(EXTEND + EWDS)\n-\tNVRAM_CLR_CE;\n-\tCFG_AND(~NVDI);\n-}\n-#endif\n-\n-static u16 ia_eeprom_get (IADEV *iadev, u32 addr)\n-{\n-\tu_short\tval;\n- u32\tt;\n-\tint\ti;\n-\t/*\n-\t * Read the first bit that was clocked with the falling edge of\n-\t * the last command data clock\n-\t */\n-\tNVRAM_CMD(IAREAD + addr);\n-\t/*\n-\t * Now read the rest of the bits, the next bit read is D14, then D13,\n-\t * and so on.\n-\t */\n-\tval = 0;\n-\tfor (i=15; i>=0; i--) {\n-\t\tNVRAM_CLKIN(t);\n-\t\tval |= (t << i);\n-\t}\n-\tNVRAM_CLR_CE;\n-\tCFG_AND(~NVDI);\n-\treturn val;\n-}\n-\n-static void ia_hw_type(IADEV *iadev) {\n- u_short memType = ia_eeprom_get(iadev, 25); \n- iadev->memType = memType;\n- if ((memType & MEM_SIZE_MASK) == MEM_SIZE_1M) {\n- iadev->num_tx_desc = IA_TX_BUF;\n- iadev->tx_buf_sz = IA_TX_BUF_SZ;\n- iadev->num_rx_desc = IA_RX_BUF;\n- iadev->rx_buf_sz = IA_RX_BUF_SZ; \n- } else if ((memType & MEM_SIZE_MASK) == MEM_SIZE_512K) {\n- if (IA_TX_BUF == DFL_TX_BUFFERS)\n- iadev->num_tx_desc = IA_TX_BUF / 2;\n- else \n- iadev->num_tx_desc = IA_TX_BUF;\n- iadev->tx_buf_sz = IA_TX_BUF_SZ;\n- if (IA_RX_BUF == DFL_RX_BUFFERS)\n- iadev->num_rx_desc = IA_RX_BUF / 2;\n- else\n- iadev->num_rx_desc = IA_RX_BUF;\n- iadev->rx_buf_sz = IA_RX_BUF_SZ;\n- }\n- else {\n- if (IA_TX_BUF == DFL_TX_BUFFERS) \n- iadev->num_tx_desc = IA_TX_BUF / 8;\n- else\n- iadev->num_tx_desc = IA_TX_BUF;\n- iadev->tx_buf_sz = IA_TX_BUF_SZ;\n- if (IA_RX_BUF == DFL_RX_BUFFERS)\n- iadev->num_rx_desc = IA_RX_BUF / 8;\n- else\n- iadev->num_rx_desc = IA_RX_BUF;\n- iadev->rx_buf_sz = IA_RX_BUF_SZ; \n- } \n- iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz); \n- IF_INIT(printk(\"BUF: tx=%d,sz=%d rx=%d sz= %d rx_pkt_ram=%d\\n\",\n- iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,\n- iadev->rx_buf_sz, iadev->rx_pkt_ram);)\n-\n-#if 0\n- if ((memType & FE_MASK) == FE_SINGLE_MODE) {\n- iadev->phy_type = PHY_OC3C_S;\n- else if ((memType & FE_MASK) == FE_UTP_OPTION)\n- iadev->phy_type = PHY_UTP155;\n- else\n- iadev->phy_type = PHY_OC3C_M;\n-#endif\n- \n- iadev->phy_type = memType & FE_MASK;\n- IF_INIT(printk(\"memType = 0x%x iadev->phy_type = 0x%x\\n\", \n- memType,iadev->phy_type);)\n- if (iadev->phy_type == FE_25MBIT_PHY) \n- iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));\n- else if (iadev->phy_type == FE_DS3_PHY)\n- iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));\n- else if (iadev->phy_type == FE_E3_PHY) \n- iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));\n- else\n- iadev->LineRate = (u32)(ATM_OC3_PCR);\n- IF_INIT(printk(\"iadev->LineRate = %d \\n\", iadev->LineRate);)\n-\n-}\n-\n-static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg)\n-{\n-\treturn readl(ia->phy + (reg >> 2));\n-}\n-\n-static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val)\n-{\n-\twritel(val, ia->phy + (reg >> 2));\n-}\n-\n-static void ia_frontend_intr(struct iadev_priv *iadev)\n-{\n-\tu32 status;\n-\n-\tif (iadev->phy_type & FE_25MBIT_PHY) {\n-\t\tstatus = ia_phy_read32(iadev, MB25_INTR_STATUS);\n-\t\tiadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;\n-\t} else if (iadev->phy_type & FE_DS3_PHY) {\n-\t\tia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);\n-\t\tstatus = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);\n-\t\tiadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;\n-\t} else if (iadev->phy_type & FE_E3_PHY) {\n-\t\tia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);\n-\t\tstatus = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);\n-\t\tiadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;\n-\t} else {\n-\t\tstatus = ia_phy_read32(iadev, SUNI_RSOP_STATUS);\n-\t\tiadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;\n-\t}\n-\n-\tprintk(KERN_INFO \"IA: SUNI carrier %s\\n\",\n-\t\tiadev->carrier_detect ? \"detected\" : \"lost signal\");\n-}\n-\n-static void ia_mb25_init(struct iadev_priv *iadev)\n-{\n-#if 0\n- mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED;\n-#endif\n-\tia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);\n-\tia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);\n-\n-\tiadev->carrier_detect =\n-\t\t(ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;\n-}\n-\n-struct ia_reg {\n-\tu16 reg;\n-\tu16 val;\n-};\n-\n-static void ia_phy_write(struct iadev_priv *iadev,\n-\t\t\t const struct ia_reg *regs, int len)\n-{\n-\twhile (len--) {\n-\t\tia_phy_write32(iadev, regs->reg, regs->val);\n-\t\tregs++;\n-\t}\n-}\n-\n-static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev)\n-{\n-\tstatic const struct ia_reg suni_ds3_init[] = {\n-\t\t{ SUNI_DS3_FRM_INTR_ENBL,\t0x17 },\n-\t\t{ SUNI_DS3_FRM_CFG,\t\t0x01 },\n-\t\t{ SUNI_DS3_TRAN_CFG,\t\t0x01 },\n-\t\t{ SUNI_CONFIG,\t\t\t0 },\n-\t\t{ SUNI_SPLR_CFG,\t\t0 },\n-\t\t{ SUNI_SPLT_CFG,\t\t0 }\n-\t};\n-\tu32 status;\n-\n-\tstatus = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);\n-\tiadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;\n-\n-\tia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));\n-}\n-\n-static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev)\n-{\n-\tstatic const struct ia_reg suni_e3_init[] = {\n-\t\t{ SUNI_E3_FRM_FRAM_OPTIONS,\t\t0x04 },\n-\t\t{ SUNI_E3_FRM_MAINT_OPTIONS,\t\t0x20 },\n-\t\t{ SUNI_E3_FRM_FRAM_INTR_ENBL,\t\t0x1d },\n-\t\t{ SUNI_E3_FRM_MAINT_INTR_ENBL,\t\t0x30 },\n-\t\t{ SUNI_E3_TRAN_STAT_DIAG_OPTIONS,\t0 },\n-\t\t{ SUNI_E3_TRAN_FRAM_OPTIONS,\t\t0x01 },\n-\t\t{ SUNI_CONFIG,\t\t\t\tSUNI_PM7345_E3ENBL },\n-\t\t{ SUNI_SPLR_CFG,\t\t\t0x41 },\n-\t\t{ SUNI_SPLT_CFG,\t\t\t0x41 }\n-\t};\n-\tu32 status;\n-\n-\tstatus = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);\n-\tiadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;\n-\tia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));\n-}\n-\n-static void ia_suni_pm7345_init(struct iadev_priv *iadev)\n-{\n-\tstatic const struct ia_reg suni_init[] = {\n-\t\t/* Enable RSOP loss of signal interrupt. */\n-\t\t{ SUNI_INTR_ENBL,\t\t0x28 },\n-\t\t/* Clear error counters. */\n-\t\t{ SUNI_ID_RESET,\t\t0 },\n-\t\t/* Clear \"PMCTST\" in master test register. */\n-\t\t{ SUNI_MASTER_TEST,\t\t0 },\n-\n-\t\t{ SUNI_RXCP_CTRL,\t\t0x2c },\n-\t\t{ SUNI_RXCP_FCTRL,\t\t0x81 },\n-\n-\t\t{ SUNI_RXCP_IDLE_PAT_H1,\t0 },\n-\t\t{ SUNI_RXCP_IDLE_PAT_H2,\t0 },\n-\t\t{ SUNI_RXCP_IDLE_PAT_H3,\t0 },\n-\t\t{ SUNI_RXCP_IDLE_PAT_H4,\t0x01 },\n-\n-\t\t{ SUNI_RXCP_IDLE_MASK_H1,\t0xff },\n-\t\t{ SUNI_RXCP_IDLE_MASK_H2,\t0xff },\n-\t\t{ SUNI_RXCP_IDLE_MASK_H3,\t0xff },\n-\t\t{ SUNI_RXCP_IDLE_MASK_H4,\t0xfe },\n-\n-\t\t{ SUNI_RXCP_CELL_PAT_H1,\t0 },\n-\t\t{ SUNI_RXCP_CELL_PAT_H2,\t0 },\n-\t\t{ SUNI_RXCP_CELL_PAT_H3,\t0 },\n-\t\t{ SUNI_RXCP_CELL_PAT_H4,\t0x01 },\n-\n-\t\t{ SUNI_RXCP_CELL_MASK_H1,\t0xff },\n-\t\t{ SUNI_RXCP_CELL_MASK_H2,\t0xff },\n-\t\t{ SUNI_RXCP_CELL_MASK_H3,\t0xff },\n-\t\t{ SUNI_RXCP_CELL_MASK_H4,\t0xff },\n-\n-\t\t{ SUNI_TXCP_CTRL,\t\t0xa4 },\n-\t\t{ SUNI_TXCP_INTR_EN_STS,\t0x10 },\n-\t\t{ SUNI_TXCP_IDLE_PAT_H5,\t0x55 }\n-\t};\n-\n-\tif (iadev->phy_type & FE_DS3_PHY)\n-\t\tia_suni_pm7345_init_ds3(iadev);\n-\telse\n-\t\tia_suni_pm7345_init_e3(iadev);\n-\n-\tia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));\n-\n-\tia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &\n-\t\t~(SUNI_PM7345_LLB | SUNI_PM7345_CLB |\n-\t\t SUNI_PM7345_DLB | SUNI_PM7345_PLB));\n-#ifdef __SNMP__\n- suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE;\n-#endif /* __SNMP__ */\n- return;\n-}\n-\n-\n-/***************************** IA_LIB END *****************************/\n- \n-#ifdef CONFIG_ATM_IA_DEBUG\n-static int tcnter = 0;\n-static void xdump( u_char* cp, int length, char* prefix )\n-{\n- int col, count;\n- u_char prntBuf[120];\n- u_char* pBuf = prntBuf;\n- count = 0;\n- while(count < length){\n- pBuf += sprintf( pBuf, \"%s\", prefix );\n- for(col = 0;count + col < length && col < 16; col++){\n- if (col != 0 && (col % 4) == 0)\n- pBuf += sprintf( pBuf, \" \" );\n- pBuf += sprintf( pBuf, \"%02X \", cp[count + col] );\n- }\n- while(col++ < 16){ /* pad end of buffer with blanks */\n- if ((col % 4) == 0)\n- sprintf( pBuf, \" \" );\n- pBuf += sprintf( pBuf, \" \" );\n- }\n- pBuf += sprintf( pBuf, \" \" );\n- for(col = 0;count + col < length && col < 16; col++){\n-\t\tu_char c = cp[count + col];\n-\n-\t\tif (isascii(c) && isprint(c))\n-\t\t\tpBuf += sprintf(pBuf, \"%c\", c);\n-\t\telse\n-\t\t\tpBuf += sprintf(pBuf, \".\");\n- }\n- printk(\"%s\\n\", prntBuf);\n- count += col;\n- pBuf = prntBuf;\n- }\n-\n-} /* close xdump(... */\n-#endif /* CONFIG_ATM_IA_DEBUG */\n-\n- \n-static struct atm_dev *ia_boards = NULL; \n- \n-#define ACTUAL_RAM_BASE \\\n-\tRAM_BASE*((iadev->mem)/(128 * 1024)) \n-#define ACTUAL_SEG_RAM_BASE \\\n-\tIPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024)) \n-#define ACTUAL_REASS_RAM_BASE \\\n-\tIPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024)) \n- \n- \n-/*-- some utilities and memory allocation stuff will come here -------------*/ \n- \n-static void desc_dbg(IADEV *iadev) {\n-\n- u_short tcq_wr_ptr, tcq_st_ptr, tcq_ed_ptr;\n- u32 i;\n- void __iomem *tmp;\n- // regval = readl((u32)ia_cmds->maddr);\n- tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);\n- printk(\"B_tcq_wr = 0x%x desc = %d last desc = %d\\n\",\n- tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),\n- readw(iadev->seg_ram+tcq_wr_ptr-2));\n- printk(\" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \\n\", iadev->host_tcq_wr, \n- iadev->ffL.tcq_rd);\n- tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);\n- tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);\n- printk(\"tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \\n\", tcq_st_ptr, tcq_ed_ptr);\n- i = 0;\n- while (tcq_st_ptr != tcq_ed_ptr) {\n- tmp = iadev->seg_ram+tcq_st_ptr;\n- printk(\"TCQ slot %d desc = %d Addr = %p\\n\", i++, readw(tmp), tmp);\n- tcq_st_ptr += 2;\n- }\n- for(i=0; i num_tx_desc; i++)\n- printk(\"Desc_tbl[%d] = %d \\n\", i, iadev->desc_tbl[i].timestamp);\n-} \n- \n- \n-/*----------------------------- Receiving side stuff --------------------------*/ \n- \n-static void rx_excp_rcvd(struct atm_dev *dev) \n-{ \n-#if 0 /* closing the receiving size will cause too many excp int */ \n- IADEV *iadev; \n- u_short state; \n- u_short excpq_rd_ptr; \n- //u_short *ptr; \n- int vci, error = 1; \n- iadev = INPH_IA_DEV(dev); \n- state = readl(iadev->reass_reg + STATE_REG) & 0xffff; \n- while((state & EXCPQ_EMPTY) != EXCPQ_EMPTY) \n- { printk(\"state = %x \\n\", state); \n- excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff; \n- printk(\"state = %x excpq_rd_ptr = %x \\n\", state, excpq_rd_ptr); \n- if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))\n- IF_ERR(printk(\"excpq_rd_ptr is wrong!!!\\n\");)\n- // TODO: update exception stat\n-\tvci = readw(iadev->reass_ram+excpq_rd_ptr); \n-\terror = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007; \n- // pwang_test\n-\texcpq_rd_ptr += 4; \n-\tif (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff)) \n- \t excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;\n-\twritew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR); \n- state = readl(iadev->reass_reg + STATE_REG) & 0xffff; \n- } \n-#endif\n-} \n- \n-static void free_desc(struct atm_dev *dev, int desc) \n-{ \n-\tIADEV *iadev; \n-\tiadev = INPH_IA_DEV(dev); \n- writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr); \n-\tiadev->rfL.fdq_wr +=2;\n-\tif (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)\n-\t\tiadev->rfL.fdq_wr = iadev->rfL.fdq_st; \n-\twritew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR); \n-} \n- \n- \n-static int rx_pkt(struct atm_dev *dev) \n-{ \n-\tIADEV *iadev; \n-\tstruct atm_vcc *vcc; \n-\tunsigned short status; \n-\tstruct rx_buf_desc __iomem *buf_desc_ptr; \n-\tint desc; \n-\tstruct dle* wr_ptr; \n-\tint len; \n-\tstruct sk_buff *skb; \n-\tu_int buf_addr, dma_addr; \n-\n-\tiadev = INPH_IA_DEV(dev); \n-\tif (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff)) \n-\t{ \n- \t printk(KERN_ERR DEV_LABEL \"(itf %d) Receive queue empty\\n\", dev->number); \n-\t return -EINVAL; \n-\t} \n-\t/* mask 1st 3 bits to get the actual descno. */ \n-\tdesc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff; \n- IF_RX(printk(\"reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\\n\", \n- iadev->reass_ram, iadev->rfL.pcq_rd, desc);\n- printk(\" pcq_wr_ptr = 0x%x\\n\",\n- readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)\n-\t/* update the read pointer - maybe we shud do this in the end*/ \n-\tif ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed) \n-\t\tiadev->rfL.pcq_rd = iadev->rfL.pcq_st; \n-\telse \n-\t\tiadev->rfL.pcq_rd += 2;\n-\twritew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR); \n- \n-\t/* get the buffer desc entry. \n-\t\tupdate stuff. - doesn't seem to be any update necessary \n-\t*/ \n-\tbuf_desc_ptr = iadev->RX_DESC_BASE_ADDR;\n-\t/* make the ptr point to the corresponding buffer desc entry */ \n-\tbuf_desc_ptr += desc;\t \n- if (!desc || (desc > iadev->num_rx_desc) || \n- ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {\n- free_desc(dev, desc);\n- IF_ERR(printk(\"IA: bad descriptor desc = %d \\n\", desc);)\n- return -1;\n- }\n-\tvcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff]; \n-\tif (!vcc) \n-\t{ \n- free_desc(dev, desc); \n-\t\tprintk(\"IA: null vcc, drop PDU\\n\"); \n-\t\treturn -1; \n-\t} \n-\t \n- \n-\t/* might want to check the status bits for errors */ \n-\tstatus = (u_short) (buf_desc_ptr->desc_mode); \n-\tif (status & (RX_CER | RX_PTE | RX_OFL)) \n-\t{ \n- atomic_inc(&vcc->stats->rx_err);\n-\t\tIF_ERR(printk(\"IA: bad packet, dropping it\");) \n- if (status & RX_CER) { \n- IF_ERR(printk(\" cause: packet CRC error\\n\");)\n- }\n- else if (status & RX_PTE) {\n- IF_ERR(printk(\" cause: packet time out\\n\");)\n- }\n- else {\n- IF_ERR(printk(\" cause: buffer overflow\\n\");)\n- }\n-\t\tgoto out_free_desc;\n-\t} \n- \n-\t/* \n-\t\tbuild DLE.\t \n-\t*/ \n- \n-\tbuf_addr = (buf_desc_ptr->buf_start_hi << 16) | buf_desc_ptr->buf_start_lo; \n-\tdma_addr = (buf_desc_ptr->dma_start_hi << 16) | buf_desc_ptr->dma_start_lo; \n-\tlen = dma_addr - buf_addr; \n- if (len > iadev->rx_buf_sz) {\n- printk(\"Over %d bytes sdu received, dropped!!!\\n\", iadev->rx_buf_sz);\n- atomic_inc(&vcc->stats->rx_err);\n-\t goto out_free_desc;\n- }\n-\t\t \n- if (!(skb = atm_alloc_charge(vcc, len, GFP_ATOMIC))) {\n- if (vcc->vci < 32)\n- printk(\"Drop control packets\\n\");\n-\t goto out_free_desc;\n- }\n-\tskb_put(skb,len); \n- // pwang_test\n- ATM_SKB(skb)->vcc = vcc;\n- ATM_DESC(skb) = desc; \n-\tskb_queue_tail(&iadev->rx_dma_q, skb); \n-\n-\t/* Build the DLE structure */ \n-\twr_ptr = iadev->rx_dle_q.write; \n-\twr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,\n-\t\t\t\t\t len, DMA_FROM_DEVICE);\n-\twr_ptr->local_pkt_addr = buf_addr; \n-\twr_ptr->bytes = len;\t/* We don't know this do we ?? */ \n-\twr_ptr->mode = DMA_INT_ENABLE; \n- \n-\t/* shud take care of wrap around here too. */ \n- if(++wr_ptr == iadev->rx_dle_q.end)\n- wr_ptr = iadev->rx_dle_q.start;\n-\tiadev->rx_dle_q.write = wr_ptr; \n-\tudelay(1); \n-\t/* Increment transaction counter */ \n-\twritel(1, iadev->dma+IPHASE5575_RX_COUNTER); \n-out:\treturn 0; \n-out_free_desc:\n- free_desc(dev, desc);\n- goto out;\n-} \n- \n-static void rx_intr(struct atm_dev *dev) \n-{ \n- IADEV *iadev; \n- u_short status; \n- u_short state, i; \n- \n- iadev = INPH_IA_DEV(dev); \n- status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff; \n- IF_EVENT(printk(\"rx_intr: status = 0x%x\\n\", status);)\n- if (status & RX_PKT_RCVD) \n- { \n-\t/* do something */ \n-\t/* Basically recvd an interrupt for receiving a packet. \n-\tA descriptor would have been written to the packet complete \n-\tqueue. Get all the descriptors and set up dma to move the \n-\tpackets till the packet complete queue is empty.. \n-\t*/ \n-\tstate = readl(iadev->reass_reg + STATE_REG) & 0xffff; \n- IF_EVENT(printk(\"Rx intr status: RX_PKT_RCVD %08x\\n\", status);) \n-\twhile(!(state & PCQ_EMPTY)) \n-\t{ \n- rx_pkt(dev); \n-\t state = readl(iadev->reass_reg + STATE_REG) & 0xffff; \n-\t} \n- iadev->rxing = 1;\n- } \n- if (status & RX_FREEQ_EMPT) \n- { \n- if (iadev->rxing) {\n- iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;\n- iadev->rx_tmp_jif = jiffies; \n- iadev->rxing = 0;\n- } \n- else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&\n- ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {\n- for (i = 1; i <= iadev->num_rx_desc; i++)\n- free_desc(dev, i);\n-printk(\"Test logic RUN!!!!\\n\");\n- writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);\n- iadev->rxing = 1;\n- }\n- IF_EVENT(printk(\"Rx intr status: RX_FREEQ_EMPT %08x\\n\", status);) \n- } \n-\n- if (status & RX_EXCP_RCVD) \n- { \n-\t/* probably need to handle the exception queue also. */ \n-\tIF_EVENT(printk(\"Rx intr status: RX_EXCP_RCVD %08x\\n\", status);) \n-\trx_excp_rcvd(dev); \n- } \n-\n-\n- if (status & RX_RAW_RCVD) \n- { \n-\t/* need to handle the raw incoming cells. This deepnds on \n-\twhether we have programmed to receive the raw cells or not. \n-\tElse ignore. */ \n-\tIF_EVENT(printk(\"Rx intr status: RX_RAW_RCVD %08x\\n\", status);) \n- } \n-} \n- \n- \n-static void rx_dle_intr(struct atm_dev *dev) \n-{ \n- IADEV *iadev; \n- struct atm_vcc *vcc; \n- struct sk_buff *skb; \n- int desc; \n- u_short state; \n- struct dle *dle, *cur_dle; \n- u_int dle_lp; \n- int len;\n- iadev = INPH_IA_DEV(dev); \n- \n- /* free all the dles done, that is just update our own dle read pointer \n-\t- do we really need to do this. Think not. */ \n- /* DMA is done, just get all the recevie buffers from the rx dma queue \n-\tand push them up to the higher layer protocol. Also free the desc \n-\tassociated with the buffer. */ \n- dle = iadev->rx_dle_q.read; \n- dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1); \n- cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4)); \n- while(dle != cur_dle) \n- { \n- /* free the DMAed skb */ \n- skb = skb_dequeue(&iadev->rx_dma_q); \n- if (!skb) \n- goto INCR_DLE;\n- desc = ATM_DESC(skb);\n- free_desc(dev, desc); \n- \n- if (!(len = skb->len))\n- { \n- printk(\"rx_dle_intr: skb len 0\\n\"); \n-\t dev_kfree_skb_any(skb); \n- } \n- else \n- { \n- struct cpcs_trailer *trailer;\n- u_short length;\n- struct ia_vcc *ia_vcc;\n-\n-\t dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,\n-\t\t\t len, DMA_FROM_DEVICE);\n- /* no VCC related housekeeping done as yet. lets see */ \n- vcc = ATM_SKB(skb)->vcc;\n-\t if (!vcc) {\n-\t printk(\"IA: null vcc\\n\"); \n- dev_kfree_skb_any(skb);\n- goto INCR_DLE;\n- }\n- ia_vcc = INPH_IA_VCC(vcc);\n- if (ia_vcc == NULL)\n- {\n- atomic_inc(&vcc->stats->rx_err);\n- atm_return(vcc, skb->truesize);\n- dev_kfree_skb_any(skb);\n- goto INCR_DLE;\n- }\n- // get real pkt length pwang_test\n- trailer = (struct cpcs_trailer*)((u_char *)skb->data +\n- skb->len - sizeof(*trailer));\n-\t length = swap_byte_order(trailer->length);\n- if ((length > iadev->rx_buf_sz) || (length > \n- (skb->len - sizeof(struct cpcs_trailer))))\n- {\n- atomic_inc(&vcc->stats->rx_err);\n- IF_ERR(printk(\"rx_dle_intr: Bad AAL5 trailer %d (skb len %d)\", \n- length, skb->len);)\n- atm_return(vcc, skb->truesize);\n- dev_kfree_skb_any(skb);\n- goto INCR_DLE;\n- }\n- skb_trim(skb, length);\n- \n-\t /* Display the packet */ \n-\t IF_RXPKT(printk(\"\\nDmad Recvd data: len = %d \\n\", skb->len); \n- xdump(skb->data, skb->len, \"RX: \");\n- printk(\"\\n\");)\n-\n-\t IF_RX(printk(\"rx_dle_intr: skb push\");) \n-\t vcc->push(vcc,skb); \n-\t atomic_inc(&vcc->stats->rx);\n- iadev->rx_pkt_cnt++;\n- } \n-INCR_DLE:\n- if (++dle == iadev->rx_dle_q.end) \n- \t dle = iadev->rx_dle_q.start; \n- } \n- iadev->rx_dle_q.read = dle; \n- \n- /* if the interrupts are masked because there were no free desc available, \n-\t\tunmask them now. */ \n- if (!iadev->rxing) {\n- state = readl(iadev->reass_reg + STATE_REG) & 0xffff;\n- if (!(state & FREEQ_EMPTY)) {\n- state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;\n- writel(state & ~(RX_FREEQ_EMPT |/* RX_EXCP_RCVD |*/ RX_PKT_RCVD),\n- iadev->reass_reg+REASS_MASK_REG);\n- iadev->rxing++; \n- }\n- }\n-} \n- \n- \n-static int open_rx(struct atm_vcc *vcc) \n-{ \n-\tIADEV *iadev; \n-\tu_short __iomem *vc_table; \n-\tu_short __iomem *reass_ptr; \n-\tIF_EVENT(printk(\"iadev: open_rx %d.%d\\n\", vcc->vpi, vcc->vci);)\n-\n-\tif (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0; \n-\tiadev = INPH_IA_DEV(vcc->dev); \n- if (vcc->qos.rxtp.traffic_class == ATM_ABR) { \n- if (iadev->phy_type & FE_25MBIT_PHY) {\n- printk(\"IA: ABR not support\\n\");\n- return -EINVAL; \n- }\n- }\n-\t/* Make only this VCI in the vc table valid and let all \n-\t\tothers be invalid entries */ \n-\tvc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;\n-\tvc_table += vcc->vci;\n-\t/* mask the last 6 bits and OR it with 3 for 1K VCs */ \n-\n- *vc_table = vcc->vci << 6;\n-\t/* Also keep a list of open rx vcs so that we can attach them with \n-\t\tincoming PDUs later. */ \n-\tif ((vcc->qos.rxtp.traffic_class == ATM_ABR) || \n- (vcc->qos.txtp.traffic_class == ATM_ABR)) \n-\t{ \n- srv_cls_param_t srv_p;\n- init_abr_vc(iadev, &srv_p);\n- ia_open_abr_vc(iadev, &srv_p, vcc, 0);\n-\t} \n- \telse { /* for UBR later may need to add CBR logic */\n- \treass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;\n- \treass_ptr += vcc->vci;\n- \t*reass_ptr = NO_AAL5_PKT;\n- \t}\n-\t\n-\tif (iadev->rx_open[vcc->vci]) \n-\t\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): VCI %d already open\\n\", \n-\t\t\tvcc->dev->number, vcc->vci); \n-\tiadev->rx_open[vcc->vci] = vcc; \n-\treturn 0; \n-} \n- \n-static int rx_init(struct atm_dev *dev) \n-{ \n-\tIADEV *iadev; \n-\tstruct rx_buf_desc __iomem *buf_desc_ptr; \n-\tunsigned long rx_pkt_start = 0; \n-\tvoid *dle_addr; \n-\tstruct abr_vc_table *abr_vc_table; \n-\tu16 *vc_table; \n-\tu16 *reass_table; \n-\tint i,j, vcsize_sel; \n-\tu_short freeq_st_adr; \n-\tu_short *freeq_start; \n- \n-\tiadev = INPH_IA_DEV(dev); \n- // spin_lock_init(&iadev->rx_lock); \n- \n-\t/* Allocate 4k bytes - more aligned than needed (4k boundary) */\n-\tdle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,\n-\t\t\t\t &iadev->rx_dle_dma, GFP_KERNEL);\n-\tif (!dle_addr) { \n-\t\tprintk(KERN_ERR DEV_LABEL \"can't allocate DLEs\\n\");\n-\t\tgoto err_out;\n-\t}\n-\tiadev->rx_dle_q.start = (struct dle *)dle_addr;\n-\tiadev->rx_dle_q.read = iadev->rx_dle_q.start; \n-\tiadev->rx_dle_q.write = iadev->rx_dle_q.start; \n-\tiadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);\n-\t/* the end of the dle q points to the entry after the last \n-\tDLE that can be used. */ \n- \n-\t/* write the upper 20 bits of the start address to rx list address register */ \n-\t/* We know this is 32bit bus addressed so the following is safe */\n-\twritel(iadev->rx_dle_dma & 0xfffff000,\n-\t iadev->dma + IPHASE5575_RX_LIST_ADDR); \n-\tIF_INIT(printk(\"Tx Dle list addr: 0x%p value: 0x%0x\\n\",\n- iadev->dma+IPHASE5575_TX_LIST_ADDR,\n- readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));\n-\tprintk(\"Rx Dle list addr: 0x%p value: 0x%0x\\n\",\n- iadev->dma+IPHASE5575_RX_LIST_ADDR,\n- readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)\n- \n-\twritew(0xffff, iadev->reass_reg+REASS_MASK_REG); \n-\twritew(0, iadev->reass_reg+MODE_REG); \n-\twritew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG); \n- \n-\t/* Receive side control memory map \n-\t ------------------------------- \n- \n-\t\tBuffer descr\t0x0000 (736 - 23K) \n-\t\tVP Table\t0x5c00 (256 - 512) \n-\t\tExcept q\t0x5e00 (128 - 512) \n-\t\tFree buffer q\t0x6000 (1K - 2K) \n-\t\tPacket comp q\t0x6800 (1K - 2K) \n-\t\tReass Table\t0x7000 (1K - 2K) \n-\t\tVC Table\t0x7800 (1K - 2K) \n-\t\tABR VC Table\t0x8000 (1K - 32K) \n-\t*/ \n-\t \n-\t/* Base address for Buffer Descriptor Table */ \n-\twritew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE); \n-\t/* Set the buffer size register */ \n-\twritew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE); \n- \n-\t/* Initialize each entry in the Buffer Descriptor Table */ \n- iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;\n-\tbuf_desc_ptr = iadev->RX_DESC_BASE_ADDR;\n-\tmemset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));\n-\tbuf_desc_ptr++; \n-\trx_pkt_start = iadev->rx_pkt_ram; \n-\tfor(i=1; i<=iadev->num_rx_desc; i++) \n-\t{ \n-\t\tmemset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr)); \n-\t\tbuf_desc_ptr->buf_start_hi = rx_pkt_start >> 16; \n-\t\tbuf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff; \n-\t\tbuf_desc_ptr++;\t\t \n-\t\trx_pkt_start += iadev->rx_buf_sz; \n-\t} \n-\tIF_INIT(printk(\"Rx Buffer desc ptr: 0x%p\\n\", buf_desc_ptr);)\n- i = FREE_BUF_DESC_Q*iadev->memSize; \n-\twritew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE); \n- writew(i, iadev->reass_reg+FREEQ_ST_ADR);\n- writew(i+iadev->num_rx_desc*sizeof(u_short), \n- iadev->reass_reg+FREEQ_ED_ADR);\n- writew(i, iadev->reass_reg+FREEQ_RD_PTR);\n- writew(i+iadev->num_rx_desc*sizeof(u_short), \n- iadev->reass_reg+FREEQ_WR_PTR); \n-\t/* Fill the FREEQ with all the free descriptors. */ \n-\tfreeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR); \n-\tfreeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr); \n-\tfor(i=1; i<=iadev->num_rx_desc; i++) \n-\t{ \n-\t\t*freeq_start = (u_short)i; \n-\t\tfreeq_start++; \n-\t} \n-\tIF_INIT(printk(\"freeq_start: 0x%p\\n\", freeq_start);)\n- /* Packet Complete Queue */\n- i = (PKT_COMP_Q * iadev->memSize) & 0xffff;\n- writew(i, iadev->reass_reg+PCQ_ST_ADR);\n- writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);\n- writew(i, iadev->reass_reg+PCQ_RD_PTR);\n- writew(i, iadev->reass_reg+PCQ_WR_PTR);\n-\n- /* Exception Queue */\n- i = (EXCEPTION_Q * iadev->memSize) & 0xffff;\n- writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);\n- writew(i + NUM_RX_EXCP * sizeof(RX_ERROR_Q), \n- iadev->reass_reg+EXCP_Q_ED_ADR);\n- writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);\n- writew(i, iadev->reass_reg+EXCP_Q_WR_PTR); \n- \n- \t/* Load local copy of FREEQ and PCQ ptrs */\n- iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;\n- \tiadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;\n-\tiadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;\n-\tiadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;\n- iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;\n-\tiadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;\n-\tiadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;\n-\tiadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;\n-\t\n- IF_INIT(printk(\"INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x\", \n- iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd, \n- iadev->rfL.pcq_wr);)\t\t \n-\t/* just for check - no VP TBL */ \n-\t/* VP Table */ \n-\t/* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */ \n-\t/* initialize VP Table for invalid VPIs \n-\t\t- I guess we can write all 1s or 0x000f in the entire memory \n-\t\t space or something similar. \n-\t*/ \n- \n-\t/* This seems to work and looks right to me too !!! */ \n- i = REASS_TABLE * iadev->memSize;\n-\twritew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE); \n- \t/* initialize Reassembly table to I don't know what ???? */ \n-\treass_table = (u16 *)(iadev->reass_ram+i); \n- j = REASS_TABLE_SZ * iadev->memSize;\n-\tfor(i=0; i < j; i++) \n-\t\t*reass_table++ = NO_AAL5_PKT; \n- i = 8*1024;\n- vcsize_sel = 0;\n- while (i != iadev->num_vc) {\n- i /= 2;\n- vcsize_sel++;\n- }\n- i = RX_VC_TABLE * iadev->memSize;\n- writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);\n- vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize); \n- j = RX_VC_TABLE_SZ * iadev->memSize;\n-\tfor(i = 0; i < j; i++) \n-\t{ \n-\t\t/* shift the reassembly pointer by 3 + lower 3 bits of \n-\t\tvc_lkup_base register (=3 for 1K VCs) and the last byte \n-\t\tis those low 3 bits. \n-\t\tShall program this later. \n-\t\t*/ \n-\t\t*vc_table = (i << 6) | 15;\t/* for invalid VCI */ \n-\t\tvc_table++; \n-\t} \n- /* ABR VC table */\n- i = ABR_VC_TABLE * iadev->memSize;\n- writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);\n- \n- i = ABR_VC_TABLE * iadev->memSize;\n-\tabr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i); \n- j = REASS_TABLE_SZ * iadev->memSize;\n- memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));\n- \tfor(i = 0; i < j; i++) { \t\t\n-\t\tabr_vc_table->rdf = 0x0003;\n- \tabr_vc_table->air = 0x5eb1;\n-\t \tabr_vc_table++; \t\n- } \n-\n-\t/* Initialize other registers */ \n- \n-\t/* VP Filter Register set for VC Reassembly only */ \n-\twritew(0xff00, iadev->reass_reg+VP_FILTER); \n- writew(0, iadev->reass_reg+XTRA_RM_OFFSET);\n-\twritew(0x1, iadev->reass_reg+PROTOCOL_ID);\n-\n-\t/* Packet Timeout Count related Registers : \n-\t Set packet timeout to occur in about 3 seconds\n-\t Set Packet Aging Interval count register to overflow in about 4 us\n- \t*/ \n- writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );\n-\n- i = (j >> 6) & 0xFF;\n- j += 2 * (j - 1);\n- i |= ((j << 2) & 0xFF00);\n- writew(i, iadev->reass_reg+TMOUT_RANGE);\n-\n- /* initiate the desc_tble */\n- for(i=0; inum_tx_desc;i++)\n- iadev->desc_tbl[i].timestamp = 0;\n-\n-\t/* to clear the interrupt status register - read it */ \n-\treadw(iadev->reass_reg+REASS_INTR_STATUS_REG); \n- \n-\t/* Mask Register - clear it */ \n-\twritew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG); \n- \n-\tskb_queue_head_init(&iadev->rx_dma_q); \n-\tiadev->rx_free_desc_qhead = NULL; \n-\n-\tiadev->rx_open = kcalloc(iadev->num_vc, sizeof(void *), GFP_KERNEL);\n-\tif (!iadev->rx_open) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"itf %d couldn't get free page\\n\",\n-\t\tdev->number); \n-\t\tgoto err_free_dle;\n-\t} \n-\n- iadev->rxing = 1;\n- iadev->rx_pkt_cnt = 0;\n-\t/* Mode Register */ \n-\twritew(R_ONLINE, iadev->reass_reg+MODE_REG); \n-\treturn 0; \n-\n-err_free_dle:\n-\tdma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,\n-\t\t\t iadev->rx_dle_dma);\n-err_out:\n-\treturn -ENOMEM;\n-} \n- \n-\n-/* \n-\tThe memory map suggested in appendix A and the coding for it. \n-\tKeeping it around just in case we change our mind later. \n- \n-\t\tBuffer descr\t0x0000 (128 - 4K) \n-\t\tUBR sched\t0x1000 (1K - 4K) \n-\t\tUBR Wait q\t0x2000 (1K - 4K) \n-\t\tCommn queues\t0x3000 Packet Ready, Trasmit comp(0x3100) \n-\t\t\t\t\t(128 - 256) each \n-\t\textended VC\t0x4000 (1K - 8K) \n-\t\tABR sched\t0x6000\tand ABR wait queue (1K - 2K) each \n-\t\tCBR sched\t0x7000 (as needed) \n-\t\tVC table\t0x8000 (1K - 32K) \n-*/ \n- \n-static void tx_intr(struct atm_dev *dev) \n-{ \n-\tIADEV *iadev; \n-\tunsigned short status; \n- unsigned long flags;\n-\n-\tiadev = INPH_IA_DEV(dev); \n- \n-\tstatus = readl(iadev->seg_reg+SEG_INTR_STATUS_REG); \n- if (status & TRANSMIT_DONE){\n-\n- IF_EVENT(printk(\"Transmit Done Intr logic run\\n\");)\n- spin_lock_irqsave(&iadev->tx_lock, flags);\n- ia_tx_poll(iadev);\n- spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);\n- if (iadev->close_pending) \n- wake_up(&iadev->close_wait);\n- } \t \n-\tif (status & TCQ_NOT_EMPTY) \n-\t{ \n-\t IF_EVENT(printk(\"TCQ_NOT_EMPTY int received\\n\");) \n-\t} \n-} \n- \n-static void tx_dle_intr(struct atm_dev *dev)\n-{\n- IADEV *iadev;\n- struct dle *dle, *cur_dle; \n- struct sk_buff *skb;\n- struct atm_vcc *vcc;\n- struct ia_vcc *iavcc;\n- u_int dle_lp;\n- unsigned long flags;\n-\n- iadev = INPH_IA_DEV(dev);\n- spin_lock_irqsave(&iadev->tx_lock, flags); \n- dle = iadev->tx_dle_q.read;\n- dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) & \n- (sizeof(struct dle)*DLE_ENTRIES - 1);\n- cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));\n- while (dle != cur_dle)\n- {\n- /* free the DMAed skb */ \n- skb = skb_dequeue(&iadev->tx_dma_q); \n- if (!skb) break;\n-\n-\t /* Revenge of the 2 dle (skb + trailer) used in ia_pkt_tx() */\n-\t if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {\n-\t\tdma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,\n-\t\t\t\t DMA_TO_DEVICE);\n-\t }\n- vcc = ATM_SKB(skb)->vcc;\n- if (!vcc) {\n- printk(\"tx_dle_intr: vcc is null\\n\");\n-\t\t spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- dev_kfree_skb_any(skb);\n-\n- return;\n- }\n- iavcc = INPH_IA_VCC(vcc);\n- if (!iavcc) {\n- printk(\"tx_dle_intr: iavcc is null\\n\");\n-\t\t spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- dev_kfree_skb_any(skb);\n- return;\n- }\n- if (vcc->qos.txtp.pcr >= iadev->rate_limit) {\n- if ((vcc->pop) && (skb->len != 0))\n- { \n- vcc->pop(vcc, skb);\n- } \n- else {\n- dev_kfree_skb_any(skb);\n- }\n- }\n- else { /* Hold the rate-limited skb for flow control */\n- IA_SKB_STATE(skb) |= IA_DLED;\n- skb_queue_tail(&iavcc->txing_skb, skb);\n- }\n- IF_EVENT(printk(\"tx_dle_intr: enque skb = 0x%p \\n\", skb);)\n- if (++dle == iadev->tx_dle_q.end)\n- dle = iadev->tx_dle_q.start;\n- }\n- iadev->tx_dle_q.read = dle;\n- spin_unlock_irqrestore(&iadev->tx_lock, flags);\n-}\n- \n-static int open_tx(struct atm_vcc *vcc) \n-{ \n-\tstruct ia_vcc *ia_vcc; \n-\tIADEV *iadev; \n-\tstruct main_vc *vc; \n-\tstruct ext_vc *evc; \n- int ret;\n-\tIF_EVENT(printk(\"iadev: open_tx entered vcc->vci = %d\\n\", vcc->vci);) \n-\tif (vcc->qos.txtp.traffic_class == ATM_NONE) return 0; \n-\tiadev = INPH_IA_DEV(vcc->dev); \n- \n- if (iadev->phy_type & FE_25MBIT_PHY) {\n- if (vcc->qos.txtp.traffic_class == ATM_ABR) {\n- printk(\"IA: ABR not support\\n\");\n- return -EINVAL; \n- }\n-\t if (vcc->qos.txtp.traffic_class == ATM_CBR) {\n- printk(\"IA: CBR not support\\n\");\n- return -EINVAL; \n- }\n- }\n- ia_vcc = INPH_IA_VCC(vcc);\n- memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));\n- if (vcc->qos.txtp.max_sdu > \n- (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){\n- printk(\"IA: SDU size over (%d) the configured SDU size %d\\n\",\n-\t\t vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);\n-\t vcc->dev_data = NULL;\n- kfree(ia_vcc);\n- return -EINVAL; \n- }\n-\tia_vcc->vc_desc_cnt = 0;\n- ia_vcc->txing = 1;\n-\n- /* find pcr */\n- if (vcc->qos.txtp.max_pcr == ATM_MAX_PCR) \n- vcc->qos.txtp.pcr = iadev->LineRate;\n- else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))\n- vcc->qos.txtp.pcr = iadev->LineRate;\n- else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0)) \n- vcc->qos.txtp.pcr = vcc->qos.txtp.max_pcr;\n- if (vcc->qos.txtp.pcr > iadev->LineRate)\n- vcc->qos.txtp.pcr = iadev->LineRate;\n- ia_vcc->pcr = vcc->qos.txtp.pcr;\n-\n- if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;\n- else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;\n- else if (ia_vcc->pcr <= 170) ia_vcc->ltimeout = 16 * HZ;\n- else ia_vcc->ltimeout = 2700 * HZ / ia_vcc->pcr;\n- if (ia_vcc->pcr < iadev->rate_limit)\n- skb_queue_head_init (&ia_vcc->txing_skb);\n- if (ia_vcc->pcr < iadev->rate_limit) {\n-\t struct sock *sk = sk_atm(vcc);\n-\n-\t if (vcc->qos.txtp.max_sdu != 0) {\n- if (ia_vcc->pcr > 60000)\n- sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 5;\n- else if (ia_vcc->pcr > 2000)\n- sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 4;\n- else\n- sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 3;\n- }\n- else\n- sk->sk_sndbuf = 24576;\n- }\n- \n-\tvc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR; \n-\tevc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR; \n-\tvc += vcc->vci; \n-\tevc += vcc->vci; \n-\tmemset((caddr_t)vc, 0, sizeof(*vc)); \n-\tmemset((caddr_t)evc, 0, sizeof(*evc)); \n-\t \n-\t/* store the most significant 4 bits of vci as the last 4 bits \n-\t\tof first part of atm header. \n-\t store the last 12 bits of vci as first 12 bits of the second \n-\t\tpart of the atm header. \n-\t*/ \n-\tevc->atm_hdr1 = (vcc->vci >> 12) & 0x000f; \n-\tevc->atm_hdr2 = (vcc->vci & 0x0fff) << 4; \n- \n-\t/* check the following for different traffic classes */ \n-\tif (vcc->qos.txtp.traffic_class == ATM_UBR) \n-\t{ \n-\t\tvc->type = UBR; \n- vc->status = CRC_APPEND;\n-\t\tvc->acr = cellrate_to_float(iadev->LineRate); \n- if (vcc->qos.txtp.pcr > 0) \n- vc->acr = cellrate_to_float(vcc->qos.txtp.pcr); \n- IF_UBR(printk(\"UBR: txtp.pcr = 0x%x f_rate = 0x%x\\n\", \n- vcc->qos.txtp.max_pcr,vc->acr);)\n-\t} \n-\telse if (vcc->qos.txtp.traffic_class == ATM_ABR) \n-\t{ srv_cls_param_t srv_p;\n-\t\tIF_ABR(printk(\"Tx ABR VCC\\n\");) \n- init_abr_vc(iadev, &srv_p);\n- if (vcc->qos.txtp.pcr > 0) \n- srv_p.pcr = vcc->qos.txtp.pcr;\n- if (vcc->qos.txtp.min_pcr > 0) {\n- int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;\n- if (tmpsum > iadev->LineRate)\n- return -EBUSY;\n- srv_p.mcr = vcc->qos.txtp.min_pcr;\n- iadev->sum_mcr += vcc->qos.txtp.min_pcr;\n- } \n- else srv_p.mcr = 0;\n- if (vcc->qos.txtp.icr)\n- srv_p.icr = vcc->qos.txtp.icr;\n- if (vcc->qos.txtp.tbe)\n- srv_p.tbe = vcc->qos.txtp.tbe;\n- if (vcc->qos.txtp.frtt)\n- srv_p.frtt = vcc->qos.txtp.frtt;\n- if (vcc->qos.txtp.rif)\n- srv_p.rif = vcc->qos.txtp.rif;\n- if (vcc->qos.txtp.rdf)\n- srv_p.rdf = vcc->qos.txtp.rdf;\n- if (vcc->qos.txtp.nrm_pres)\n- srv_p.nrm = vcc->qos.txtp.nrm;\n- if (vcc->qos.txtp.trm_pres)\n- srv_p.trm = vcc->qos.txtp.trm;\n- if (vcc->qos.txtp.adtf_pres)\n- srv_p.adtf = vcc->qos.txtp.adtf;\n- if (vcc->qos.txtp.cdf_pres)\n- srv_p.cdf = vcc->qos.txtp.cdf; \n- if (srv_p.icr > srv_p.pcr)\n- srv_p.icr = srv_p.pcr; \n- IF_ABR(printk(\"ABR:vcc->qos.txtp.max_pcr = %d mcr = %d\\n\", \n- srv_p.pcr, srv_p.mcr);)\n-\t\tia_open_abr_vc(iadev, &srv_p, vcc, 1);\n-\t} else if (vcc->qos.txtp.traffic_class == ATM_CBR) {\n- if (iadev->phy_type & FE_25MBIT_PHY) {\n- printk(\"IA: CBR not support\\n\");\n- return -EINVAL; \n- }\n- if (vcc->qos.txtp.max_pcr > iadev->LineRate) {\n- IF_CBR(printk(\"PCR is not available\\n\");)\n- return -1;\n- }\n- vc->type = CBR;\n- vc->status = CRC_APPEND;\n- if ((ret = ia_cbr_setup (iadev, vcc)) < 0) { \n- return ret;\n- }\n-\t} else {\n-\t\tprintk(\"iadev: Non UBR, ABR and CBR traffic not supported\\n\");\n-\t}\n- \n- iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;\n-\tIF_EVENT(printk(\"ia open_tx returning \\n\");) \n-\treturn 0; \n-} \n- \n- \n-static int tx_init(struct atm_dev *dev) \n-{ \n-\tIADEV *iadev; \n-\tstruct tx_buf_desc *buf_desc_ptr;\n-\tunsigned int tx_pkt_start; \n-\tvoid *dle_addr; \n-\tint i; \n-\tu_short tcq_st_adr; \n-\tu_short *tcq_start; \n-\tu_short prq_st_adr; \n-\tu_short *prq_start; \n-\tstruct main_vc *vc; \n-\tstruct ext_vc *evc; \n- u_short tmp16;\n- u32 vcsize_sel;\n- \n-\tiadev = INPH_IA_DEV(dev); \n- spin_lock_init(&iadev->tx_lock);\n- \n-\tIF_INIT(printk(\"Tx MASK REG: 0x%0x\\n\", \n- readw(iadev->seg_reg+SEG_MASK_REG));) \n-\n-\t/* Allocate 4k (boundary aligned) bytes */\n-\tdle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,\n-\t\t\t\t &iadev->tx_dle_dma, GFP_KERNEL);\n-\tif (!dle_addr) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"can't allocate DLEs\\n\");\n-\t\tgoto err_out;\n-\t}\n-\tiadev->tx_dle_q.start = (struct dle*)dle_addr; \n-\tiadev->tx_dle_q.read = iadev->tx_dle_q.start; \n-\tiadev->tx_dle_q.write = iadev->tx_dle_q.start; \n-\tiadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);\n-\n-\t/* write the upper 20 bits of the start address to tx list address register */ \n-\twritel(iadev->tx_dle_dma & 0xfffff000,\n-\t iadev->dma + IPHASE5575_TX_LIST_ADDR); \n-\twritew(0xffff, iadev->seg_reg+SEG_MASK_REG); \n-\twritew(0, iadev->seg_reg+MODE_REG_0); \n-\twritew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG); \n- iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;\n- iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;\n- iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;\n- \n-\t/* \n-\t Transmit side control memory map \n-\t -------------------------------- \n-\t Buffer descr \t0x0000 (128 - 4K) \n-\t Commn queues\t0x1000\tTransmit comp, Packet ready(0x1400) \n-\t\t\t\t\t(512 - 1K) each \n-\t\t\t\t\tTCQ - 4K, PRQ - 5K \n-\t CBR Table \t0x1800 (as needed) - 6K \n-\t UBR Table\t0x3000 (1K - 4K) - 12K \n-\t UBR Wait queue\t0x4000 (1K - 4K) - 16K \n-\t ABR sched\t0x5000\tand ABR wait queue (1K - 2K) each \n-\t\t\t\tABR Tbl - 20K, ABR Wq - 22K \n-\t extended VC\t0x6000 (1K - 8K) - 24K \n-\t VC Table\t0x8000 (1K - 32K) - 32K \n-\t \n-\tBetween 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl \n-\tand Wait q, which can be allotted later. \n-\t*/ \n- \n-\t/* Buffer Descriptor Table Base address */ \n-\twritew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE); \n- \n-\t/* initialize each entry in the buffer descriptor table */ \n-\tbuf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE); \n-\tmemset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr)); \n-\tbuf_desc_ptr++; \n-\ttx_pkt_start = TX_PACKET_RAM; \n-\tfor(i=1; i<=iadev->num_tx_desc; i++) \n-\t{ \n-\t\tmemset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr)); \n-\t\tbuf_desc_ptr->desc_mode = AAL5; \n-\t\tbuf_desc_ptr->buf_start_hi = tx_pkt_start >> 16; \n-\t\tbuf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff; \n-\t\tbuf_desc_ptr++;\t\t \n-\t\ttx_pkt_start += iadev->tx_buf_sz; \n-\t} \n-\tiadev->tx_buf = kmalloc_objs(*iadev->tx_buf, iadev->num_tx_desc);\n- if (!iadev->tx_buf) {\n- printk(KERN_ERR DEV_LABEL \" couldn't get mem\\n\");\n-\t goto err_free_dle;\n- }\n- \tfor (i= 0; i< iadev->num_tx_desc; i++)\n- \t{\n-\t struct cpcs_trailer *cpcs;\n- \n- \t cpcs = kmalloc_obj(*cpcs, GFP_KERNEL | GFP_DMA);\n- if(!cpcs) { \n-\t\tprintk(KERN_ERR DEV_LABEL \" couldn't get freepage\\n\"); \n-\t\tgoto err_free_tx_bufs;\n- }\n-\t iadev->tx_buf[i].cpcs = cpcs;\n-\t iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,\n-\t\t\t\t\t\t cpcs,\n-\t\t\t\t\t\t sizeof(*cpcs),\n-\t\t\t\t\t\t DMA_TO_DEVICE);\n- }\n-\tiadev->desc_tbl = kmalloc_objs(*iadev->desc_tbl, iadev->num_tx_desc);\n-\tif (!iadev->desc_tbl) {\n-\t\tprintk(KERN_ERR DEV_LABEL \" couldn't get mem\\n\");\n-\t\tgoto err_free_all_tx_bufs;\n-\t}\n- \n-\t/* Communication Queues base address */ \n- i = TX_COMP_Q * iadev->memSize;\n-\twritew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE); \n- \n-\t/* Transmit Complete Queue */ \n-\twritew(i, iadev->seg_reg+TCQ_ST_ADR); \n-\twritew(i, iadev->seg_reg+TCQ_RD_PTR); \n-\twritew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR); \n-\tiadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);\n- writew(i+2 * iadev->num_tx_desc * sizeof(u_short), \n- iadev->seg_reg+TCQ_ED_ADR); \n-\t/* Fill the TCQ with all the free descriptors. */ \n-\ttcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR); \n-\ttcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr); \n-\tfor(i=1; i<=iadev->num_tx_desc; i++) \n-\t{ \n-\t\t*tcq_start = (u_short)i; \n-\t\ttcq_start++; \n-\t} \n- \n-\t/* Packet Ready Queue */ \n- i = PKT_RDY_Q * iadev->memSize; \n-\twritew(i, iadev->seg_reg+PRQ_ST_ADR); \n-\twritew(i+2 * iadev->num_tx_desc * sizeof(u_short), \n- iadev->seg_reg+PRQ_ED_ADR);\n-\twritew(i, iadev->seg_reg+PRQ_RD_PTR); \n-\twritew(i, iadev->seg_reg+PRQ_WR_PTR); \n-\t \n- /* Load local copy of PRQ and TCQ ptrs */\n- iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;\n-\tiadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;\n- \tiadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;\n-\n-\tiadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;\n-\tiadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;\n-\tiadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;\n-\n-\t/* Just for safety initializing the queue to have desc 1 always */ \n-\t/* Fill the PRQ with all the free descriptors. */ \n-\tprq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR); \n-\tprq_start = (u_short *)(iadev->seg_ram+prq_st_adr); \n-\tfor(i=1; i<=iadev->num_tx_desc; i++) \n-\t{ \n-\t\t*prq_start = (u_short)0;\t/* desc 1 in all entries */ \n-\t\tprq_start++; \n-\t} \n-\t/* CBR Table */ \n- IF_INIT(printk(\"Start CBR Init\\n\");)\n-#if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */\n- writew(0,iadev->seg_reg+CBR_PTR_BASE);\n-#else /* Charlie's logic is wrong ? */\n- tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;\n- IF_INIT(printk(\"cbr_ptr_base = 0x%x \", tmp16);)\n- writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);\n-#endif\n-\n- IF_INIT(printk(\"value in register = 0x%x\\n\",\n- readw(iadev->seg_reg+CBR_PTR_BASE));)\n- tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;\n- writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);\n- IF_INIT(printk(\"cbr_tab_beg = 0x%x in reg = 0x%x \\n\", tmp16,\n- readw(iadev->seg_reg+CBR_TAB_BEG));)\n- writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;\n- tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;\n- writew(tmp16, iadev->seg_reg+CBR_TAB_END);\n- IF_INIT(printk(\"iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\\n\",\n- iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)\n- IF_INIT(printk(\"CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\\n\",\n- readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),\n- readw(iadev->seg_reg+CBR_TAB_END+1));)\n-\n- /* Initialize the CBR Schedualing Table */\n- memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize, \n- 0, iadev->num_vc*6); \n- iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;\n- iadev->CbrEntryPt = 0;\n- iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;\n- iadev->NumEnabledCBR = 0;\n-\n-\t/* UBR scheduling Table and wait queue */ \n-\t/* initialize all bytes of UBR scheduler table and wait queue to 0 \n-\t\t- SCHEDSZ is 1K (# of entries). \n-\t\t- UBR Table size is 4K \n-\t\t- UBR wait queue is 4K \n-\t since the table and wait queues are contiguous, all the bytes \n-\t can be initialized by one memeset.\n-\t*/ \n- \n- vcsize_sel = 0;\n- i = 8*1024;\n- while (i != iadev->num_vc) {\n- i /= 2;\n- vcsize_sel++;\n- }\n- \n- i = MAIN_VC_TABLE * iadev->memSize;\n- writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);\n- i = EXT_VC_TABLE * iadev->memSize;\n- writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);\n- i = UBR_SCHED_TABLE * iadev->memSize;\n- writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);\n- i = UBR_WAIT_Q * iadev->memSize; \n- writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);\n- \tmemset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),\n- 0, iadev->num_vc*8);\n-\t/* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/ \n-\t/* initialize all bytes of ABR scheduler table and wait queue to 0 \n-\t\t- SCHEDSZ is 1K (# of entries). \n-\t\t- ABR Table size is 2K \n-\t\t- ABR wait queue is 2K \n-\t since the table and wait queues are contiguous, all the bytes \n-\t can be initialized by one memeset.\n-\t*/ \n- i = ABR_SCHED_TABLE * iadev->memSize;\n- writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);\n- i = ABR_WAIT_Q * iadev->memSize;\n- writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);\n- \n- i = ABR_SCHED_TABLE*iadev->memSize;\n-\tmemset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);\n-\tvc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR; \n-\tevc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR; \n-\tiadev->testTable = kmalloc_objs(*iadev->testTable, iadev->num_vc);\n- if (!iadev->testTable) {\n- printk(\"Get freepage failed\\n\");\n-\t goto err_free_desc_tbl;\n- }\n-\tfor(i=0; inum_vc; i++) \n-\t{ \n-\t\tmemset((caddr_t)vc, 0, sizeof(*vc)); \n-\t\tmemset((caddr_t)evc, 0, sizeof(*evc)); \n- iadev->testTable[i] = kmalloc_obj(struct testTable_t);\n-\t\tif (!iadev->testTable[i])\n-\t\t\tgoto err_free_test_tables;\n- \tiadev->testTable[i]->lastTime = 0;\n- \t\tiadev->testTable[i]->fract = 0;\n- iadev->testTable[i]->vc_status = VC_UBR;\n-\t\tvc++; \n-\t\tevc++; \n-\t} \n- \n-\t/* Other Initialization */ \n-\t \n-\t/* Max Rate Register */ \n- if (iadev->phy_type & FE_25MBIT_PHY) {\n-\t writew(RATE25, iadev->seg_reg+MAXRATE); \n-\t writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); \n- }\n- else {\n-\t writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);\n-\t writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); \n- }\n-\t/* Set Idle Header Reigisters to be sure */ \n-\twritew(0, iadev->seg_reg+IDLEHEADHI); \n-\twritew(0, iadev->seg_reg+IDLEHEADLO); \n- \n-\t/* Program ABR UBR Priority Register as PRI_ABR_UBR_EQUAL */\n- writew(0xaa00, iadev->seg_reg+ABRUBR_ARB); \n-\n- iadev->close_pending = 0;\n- init_waitqueue_head(&iadev->close_wait);\n- init_waitqueue_head(&iadev->timeout_wait);\n-\tskb_queue_head_init(&iadev->tx_dma_q); \n-\tia_init_rtn_q(&iadev->tx_return_q); \n-\n-\t/* RM Cell Protocol ID and Message Type */ \n-\twritew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE); \n- skb_queue_head_init (&iadev->tx_backlog);\n- \n-\t/* Mode Register 1 */ \n-\twritew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1); \n- \n-\t/* Mode Register 0 */ \n-\twritew(T_ONLINE, iadev->seg_reg+MODE_REG_0); \n- \n-\t/* Interrupt Status Register - read to clear */ \n-\treadw(iadev->seg_reg+SEG_INTR_STATUS_REG); \n- \n-\t/* Interrupt Mask Reg- don't mask TCQ_NOT_EMPTY interrupt generation */ \n- writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);\n- writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG); \n- iadev->tx_pkt_cnt = 0;\n- iadev->rate_limit = iadev->LineRate / 3;\n- \n-\treturn 0;\n-\n-err_free_test_tables:\n-\twhile (--i >= 0)\n-\t\tkfree(iadev->testTable[i]);\n-\tkfree(iadev->testTable);\n-err_free_desc_tbl:\n-\tkfree(iadev->desc_tbl);\n-err_free_all_tx_bufs:\n-\ti = iadev->num_tx_desc;\n-err_free_tx_bufs:\n-\twhile (--i >= 0) {\n-\t\tstruct cpcs_trailer_desc *desc = iadev->tx_buf + i;\n-\n-\t\tdma_unmap_single(&iadev->pci->dev, desc->dma_addr,\n-\t\t\t\t sizeof(*desc->cpcs), DMA_TO_DEVICE);\n-\t\tkfree(desc->cpcs);\n-\t}\n-\tkfree(iadev->tx_buf);\n-err_free_dle:\n-\tdma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,\n-\t\t\t iadev->tx_dle_dma);\n-err_out:\n-\treturn -ENOMEM;\n-} \n- \n-static irqreturn_t ia_int(int irq, void *dev_id) \n-{ \n- struct atm_dev *dev; \n- IADEV *iadev; \n- unsigned int status; \n- int handled = 0;\n-\n- dev = dev_id; \n- iadev = INPH_IA_DEV(dev); \n- while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f)) \n- { \n-\thandled = 1;\n- IF_EVENT(printk(\"ia_int: status = 0x%x\\n\", status);) \n-\tif (status & STAT_REASSINT) \n-\t{ \n-\t /* do something */ \n-\t IF_EVENT(printk(\"REASSINT Bus status reg: %08x\\n\", status);) \n-\t rx_intr(dev); \n-\t} \n-\tif (status & STAT_DLERINT) \n-\t{ \n-\t /* Clear this bit by writing a 1 to it. */ \n-\t writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);\n-\t rx_dle_intr(dev); \n-\t} \n-\tif (status & STAT_SEGINT) \n-\t{ \n-\t /* do something */ \n- IF_EVENT(printk(\"IA: tx_intr \\n\");) \n-\t tx_intr(dev); \n-\t} \n-\tif (status & STAT_DLETINT) \n-\t{ \n-\t writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);\n-\t tx_dle_intr(dev); \n-\t} \n-\tif (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT)) \n-\t{ \n- if (status & STAT_FEINT) \n- ia_frontend_intr(iadev);\n-\t} \n- }\n- return IRQ_RETVAL(handled);\n-} \n-\t \n-\t \n-\t \n-/*----------------------------- entries --------------------------------*/ \n-static int get_esi(struct atm_dev *dev) \n-{ \n-\tIADEV *iadev; \n-\tint i; \n-\tu32 mac1; \n-\tu16 mac2; \n-\t \n-\tiadev = INPH_IA_DEV(dev); \n-\tmac1 = cpu_to_be32(le32_to_cpu(readl( \n-\t\t\t\tiadev->reg+IPHASE5575_MAC1))); \n-\tmac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2))); \n-\tIF_INIT(printk(\"ESI: 0x%08x%04x\\n\", mac1, mac2);) \n-\tfor (i=0; iesi[i] = mac1 >>(8*(MAC1_LEN-1-i)); \n-\t \n-\tfor (i=0; iesi[i+MAC1_LEN] = mac2 >>(8*(MAC2_LEN - 1 -i)); \n-\treturn 0; \n-} \n-\t \n-static int reset_sar(struct atm_dev *dev) \n-{ \n-\tIADEV *iadev; \n-\tint i, error;\n-\tunsigned int pci[64]; \n-\t \n-\tiadev = INPH_IA_DEV(dev); \n-\tfor (i = 0; i < 64; i++) {\n-\t\terror = pci_read_config_dword(iadev->pci, i * 4, &pci[i]);\n-\t\tif (error != PCIBIOS_SUCCESSFUL)\n-\t\t\treturn error;\n-\t}\n-\twritel(0, iadev->reg+IPHASE5575_EXT_RESET); \n-\tfor (i = 0; i < 64; i++) {\n-\t\terror = pci_write_config_dword(iadev->pci, i * 4, pci[i]);\n-\t\tif (error != PCIBIOS_SUCCESSFUL)\n-\t\t\treturn error;\n-\t}\n-\tudelay(5); \n-\treturn 0; \n-} \n-\t \n-\t \n-static int ia_init(struct atm_dev *dev)\n-{ \n-\tIADEV *iadev; \n-\tunsigned long real_base;\n-\tvoid __iomem *base;\n-\tunsigned short command; \n-\tint error, i; \n-\t \n-\t/* The device has been identified and registered. Now we read \n-\t necessary configuration info like memory base address, \n-\t interrupt number etc */ \n-\t \n-\tIF_INIT(printk(\">ia_init\\n\");) \n-\tdev->ci_range.vpi_bits = 0; \n-\tdev->ci_range.vci_bits = NR_VCI_LD; \n-\n-\tiadev = INPH_IA_DEV(dev); \n-\treal_base = pci_resource_start (iadev->pci, 0);\n-\tiadev->irq = iadev->pci->irq;\n-\t\t \n-\terror = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);\n-\tif (error) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): init error 0x%x\\n\", \n-\t\t\t\tdev->number,error); \n-\t\treturn -EINVAL; \n-\t} \n-\tIF_INIT(printk(DEV_LABEL \"(itf %d): rev.%d,realbase=0x%lx,irq=%d\\n\", \n-\t\t\tdev->number, iadev->pci->revision, real_base, iadev->irq);)\n-\t \n-\t/* find mapping size of board */ \n-\t \n-\tiadev->pci_map_size = pci_resource_len(iadev->pci, 0);\n-\n- if (iadev->pci_map_size == 0x100000){\n- iadev->num_vc = 4096;\n-\t dev->ci_range.vci_bits = NR_VCI_4K_LD; \n- iadev->memSize = 4;\n- }\n- else if (iadev->pci_map_size == 0x40000) {\n- iadev->num_vc = 1024;\n- iadev->memSize = 1;\n- }\n- else {\n- printk(\"Unknown pci_map_size = 0x%x\\n\", iadev->pci_map_size);\n- return -EINVAL;\n- }\n-\tIF_INIT(printk (DEV_LABEL \"map size: %i\\n\", iadev->pci_map_size);) \n-\t \n-\t/* enable bus mastering */\n-\tpci_set_master(iadev->pci);\n-\n-\t/* \n-\t * Delay at least 1us before doing any mem accesses (how 'bout 10?) \n-\t */ \n-\tudelay(10); \n-\t \n-\t/* mapping the physical address to a virtual address in address space */ \n-\tbase = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */ \n-\t \n-\tif (!base) \n-\t{ \n-\t\tprintk(DEV_LABEL \" (itf %d): can't set up page mapping\\n\", \n-\t\t\t dev->number); \n-\t\treturn -ENOMEM;\n-\t} \n-\tIF_INIT(printk(DEV_LABEL \" (itf %d): rev.%d,base=%p,irq=%d\\n\", \n-\t\t\tdev->number, iadev->pci->revision, base, iadev->irq);)\n-\t \n-\t/* filling the iphase dev structure */ \n-\tiadev->mem = iadev->pci_map_size /2; \n-\tiadev->real_base = real_base; \n-\tiadev->base = base; \n-\t\t \n-\t/* Bus Interface Control Registers */ \n-\tiadev->reg = base + REG_BASE;\n-\t/* Segmentation Control Registers */ \n-\tiadev->seg_reg = base + SEG_BASE;\n-\t/* Reassembly Control Registers */ \n-\tiadev->reass_reg = base + REASS_BASE; \n-\t/* Front end/ DMA control registers */ \n-\tiadev->phy = base + PHY_BASE; \n-\tiadev->dma = base + PHY_BASE; \n-\t/* RAM - Segmentation RAm and Reassembly RAM */ \n-\tiadev->ram = base + ACTUAL_RAM_BASE; \n-\tiadev->seg_ram = base + ACTUAL_SEG_RAM_BASE; \n-\tiadev->reass_ram = base + ACTUAL_REASS_RAM_BASE; \n- \n-\t/* lets print out the above */ \n-\tIF_INIT(printk(\"Base addrs: %p %p %p \\n %p %p %p %p\\n\", \n- iadev->reg,iadev->seg_reg,iadev->reass_reg, \n- iadev->phy, iadev->ram, iadev->seg_ram, \n- iadev->reass_ram);) \n-\t \n-\t/* lets try reading the MAC address */ \n-\terror = get_esi(dev); \n-\tif (error) {\n-\t iounmap(iadev->base);\n-\t return error; \n-\t}\n- printk(\"IA: \");\n-\tfor (i=0; i < ESI_LEN; i++) \n- printk(\"%s%02X\",i ? \"-\" : \"\",dev->esi[i]); \n- printk(\"\\n\"); \n- \n- /* reset SAR */ \n- if (reset_sar(dev)) {\n-\t iounmap(iadev->base);\n- printk(\"IA: reset SAR fail, please try again\\n\");\n- return 1;\n- }\n-\treturn 0; \n-} \n-\n-static void ia_update_stats(IADEV *iadev) {\n- if (!iadev->carrier_detect)\n- return;\n- iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;\n- iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;\n- iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;\n- iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;\n- iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;\n- iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;\n- return;\n-}\n- \n-static void ia_led_timer(struct timer_list *unused) {\n- \tunsigned long flags;\n- \tstatic u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};\n- u_char i;\n- static u32 ctrl_reg; \n- for (i = 0; i < iadev_count; i++) {\n- if (ia_dev[i]) {\n-\t ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);\n-\t if (blinking[i] == 0) {\n-\t\t blinking[i]++;\n- ctrl_reg &= (~CTRL_LED);\n- writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);\n- ia_update_stats(ia_dev[i]);\n- }\n- else {\n-\t\t blinking[i] = 0;\n-\t\t ctrl_reg |= CTRL_LED;\n- writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);\n- spin_lock_irqsave(&ia_dev[i]->tx_lock, flags);\n- if (ia_dev[i]->close_pending) \n- wake_up(&ia_dev[i]->close_wait);\n- ia_tx_poll(ia_dev[i]);\n- spin_unlock_irqrestore(&ia_dev[i]->tx_lock, flags);\n- }\n- }\n- }\n-\tmod_timer(&ia_timer, jiffies + HZ / 4);\n- \treturn;\n-}\n-\n-static void ia_phy_put(struct atm_dev *dev, unsigned char value, \n-\tunsigned long addr) \n-{ \n-\twritel(value, INPH_IA_DEV(dev)->phy+addr); \n-} \n- \n-static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr) \n-{ \n-\treturn readl(INPH_IA_DEV(dev)->phy+addr); \n-} \n-\n-static void ia_free_tx(IADEV *iadev)\n-{\n-\tint i;\n-\n-\tkfree(iadev->desc_tbl);\n-\tfor (i = 0; i < iadev->num_vc; i++)\n-\t\tkfree(iadev->testTable[i]);\n-\tkfree(iadev->testTable);\n-\tfor (i = 0; i < iadev->num_tx_desc; i++) {\n-\t\tstruct cpcs_trailer_desc *desc = iadev->tx_buf + i;\n-\n-\t\tdma_unmap_single(&iadev->pci->dev, desc->dma_addr,\n-\t\t\t\t sizeof(*desc->cpcs), DMA_TO_DEVICE);\n-\t\tkfree(desc->cpcs);\n-\t}\n-\tkfree(iadev->tx_buf);\n-\tdma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,\n-\t\t\t iadev->tx_dle_dma);\n-}\n-\n-static void ia_free_rx(IADEV *iadev)\n-{\n-\tkfree(iadev->rx_open);\n-\tdma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,\n-\t\t\t iadev->rx_dle_dma);\n-}\n-\n-static int ia_start(struct atm_dev *dev)\n-{ \n-\tIADEV *iadev; \n-\tint error; \n-\tunsigned char phy; \n-\tu32 ctrl_reg; \n-\tIF_EVENT(printk(\">ia_start\\n\");) \n-\tiadev = INPH_IA_DEV(dev); \n- if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {\n- printk(KERN_ERR DEV_LABEL \"(itf %d): IRQ%d is already in use\\n\", \n- dev->number, iadev->irq); \n-\t\terror = -EAGAIN;\n-\t\tgoto err_out;\n- } \n- /* @@@ should release IRQ on error */ \n-\t/* enabling memory + master */ \n- if ((error = pci_write_config_word(iadev->pci, \n-\t\t\t\tPCI_COMMAND, \n-\t\t\t\tPCI_COMMAND_MEMORY | PCI_COMMAND_MASTER ))) \n-\t{ \n- printk(KERN_ERR DEV_LABEL \"(itf %d): can't enable memory+\" \n- \"master (0x%x)\\n\",dev->number, error); \n-\t\terror = -EIO; \n-\t\tgoto err_free_irq;\n- } \n-\tudelay(10); \n- \n-\t/* Maybe we should reset the front end, initialize Bus Interface Control \n-\t\tRegisters and see. */ \n- \n-\tIF_INIT(printk(\"Bus ctrl reg: %08x\\n\", \n- readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));) \n-\tctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG); \n-\tctrl_reg = (ctrl_reg & (CTRL_LED | CTRL_FE_RST)) \n-\t\t\t| CTRL_B8 \n-\t\t\t| CTRL_B16 \n-\t\t\t| CTRL_B32 \n-\t\t\t| CTRL_B48 \n-\t\t\t| CTRL_B64 \n-\t\t\t| CTRL_B128 \n-\t\t\t| CTRL_ERRMASK \n-\t\t\t| CTRL_DLETMASK\t\t/* shud be removed l8r */ \n-\t\t\t| CTRL_DLERMASK \n-\t\t\t| CTRL_SEGMASK \n-\t\t\t| CTRL_REASSMASK \t \n-\t\t\t| CTRL_FEMASK \n-\t\t\t| CTRL_CSPREEMPT; \n- \n- writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG); \n- \n-\tIF_INIT(printk(\"Bus ctrl reg after initializing: %08x\\n\", \n- readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG)); \n-\t printk(\"Bus status reg after init: %08x\\n\", \n- readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));) \n- \n- ia_hw_type(iadev); \n-\terror = tx_init(dev); \n-\tif (error)\n-\t\tgoto err_free_irq;\n-\terror = rx_init(dev); \n-\tif (error)\n-\t\tgoto err_free_tx;\n- \n-\tctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG); \n- \twritel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG); \n-\tIF_INIT(printk(\"Bus ctrl reg after initializing: %08x\\n\", \n- readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));) \n- phy = 0; /* resolve compiler complaint */\n- IF_INIT ( \n-\tif ((phy=ia_phy_get(dev,0)) == 0x30) \n-\t\tprintk(\"IA: pm5346,rev.%d\\n\",phy&0x0f); \n-\telse \n-\t\tprintk(\"IA: utopia,rev.%0x\\n\",phy);) \n-\n-\tif (iadev->phy_type & FE_25MBIT_PHY)\n- ia_mb25_init(iadev);\n-\telse if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))\n- ia_suni_pm7345_init(iadev);\n-\telse {\n-\t\terror = suni_init(dev);\n-\t\tif (error)\n-\t\t\tgoto err_free_rx;\n-\t\tif (dev->phy->start) {\n-\t\t\terror = dev->phy->start(dev);\n-\t\t\tif (error)\n-\t\t\t\tgoto err_free_rx;\n-\t\t}\n-\t\t/* Get iadev->carrier_detect status */\n-\t\tia_frontend_intr(iadev);\n-\t}\n-\treturn 0;\n-\n-err_free_rx:\n-\tia_free_rx(iadev);\n-err_free_tx:\n-\tia_free_tx(iadev);\n-err_free_irq:\n-\tfree_irq(iadev->irq, dev); \n-err_out:\n-\treturn error;\n-} \n- \n-static void ia_close(struct atm_vcc *vcc) \n-{\n-\tDEFINE_WAIT(wait);\n- u16 *vc_table;\n- IADEV *iadev;\n- struct ia_vcc *ia_vcc;\n- struct sk_buff *skb = NULL;\n- struct sk_buff_head tmp_tx_backlog, tmp_vcc_backlog;\n- unsigned long closetime, flags;\n-\n- iadev = INPH_IA_DEV(vcc->dev);\n- ia_vcc = INPH_IA_VCC(vcc);\n-\tif (!ia_vcc) return; \n-\n- IF_EVENT(printk(\"ia_close: ia_vcc->vc_desc_cnt = %d vci = %d\\n\", \n- ia_vcc->vc_desc_cnt,vcc->vci);)\n-\tclear_bit(ATM_VF_READY,&vcc->flags);\n- skb_queue_head_init (&tmp_tx_backlog);\n- skb_queue_head_init (&tmp_vcc_backlog); \n- if (vcc->qos.txtp.traffic_class != ATM_NONE) {\n- iadev->close_pending++;\n-\t prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);\n-\t schedule_timeout(msecs_to_jiffies(500));\n-\t finish_wait(&iadev->timeout_wait, &wait);\n- spin_lock_irqsave(&iadev->tx_lock, flags); \n- while((skb = skb_dequeue(&iadev->tx_backlog))) {\n- if (ATM_SKB(skb)->vcc == vcc){ \n- if (vcc->pop) vcc->pop(vcc, skb);\n- else dev_kfree_skb_any(skb);\n- }\n- else \n- skb_queue_tail(&tmp_tx_backlog, skb);\n- } \n- while((skb = skb_dequeue(&tmp_tx_backlog))) \n- skb_queue_tail(&iadev->tx_backlog, skb);\n- IF_EVENT(printk(\"IA TX Done decs_cnt = %d\\n\", ia_vcc->vc_desc_cnt);) \n- closetime = 300000 / ia_vcc->pcr;\n- if (closetime == 0)\n- closetime = 1;\n- spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);\n- spin_lock_irqsave(&iadev->tx_lock, flags);\n- iadev->close_pending--;\n- iadev->testTable[vcc->vci]->lastTime = 0;\n- iadev->testTable[vcc->vci]->fract = 0; \n- iadev->testTable[vcc->vci]->vc_status = VC_UBR; \n- if (vcc->qos.txtp.traffic_class == ATM_ABR) {\n- if (vcc->qos.txtp.min_pcr > 0)\n- iadev->sum_mcr -= vcc->qos.txtp.min_pcr;\n- }\n- if (vcc->qos.txtp.traffic_class == ATM_CBR) {\n- ia_vcc = INPH_IA_VCC(vcc); \n- iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;\n- ia_cbrVc_close (vcc);\n- }\n- spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- }\n- \n- if (vcc->qos.rxtp.traffic_class != ATM_NONE) { \n- // reset reass table\n- vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);\n- vc_table += vcc->vci; \n- *vc_table = NO_AAL5_PKT;\n- // reset vc table\n- vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);\n- vc_table += vcc->vci;\n- *vc_table = (vcc->vci << 6) | 15;\n- if (vcc->qos.rxtp.traffic_class == ATM_ABR) {\n- struct abr_vc_table __iomem *abr_vc_table = \n- (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);\n- abr_vc_table += vcc->vci;\n- abr_vc_table->rdf = 0x0003;\n- abr_vc_table->air = 0x5eb1;\n- } \n- // Drain the packets\n- rx_dle_intr(vcc->dev); \n- iadev->rx_open[vcc->vci] = NULL;\n- }\n-\tkfree(INPH_IA_VCC(vcc)); \n- ia_vcc = NULL;\n- vcc->dev_data = NULL;\n- clear_bit(ATM_VF_ADDR,&vcc->flags);\n- return; \n-} \n- \n-static int ia_open(struct atm_vcc *vcc)\n-{ \n-\tstruct ia_vcc *ia_vcc; \n-\tint error; \n-\tif (!test_bit(ATM_VF_PARTIAL,&vcc->flags)) \n-\t{ \n-\t\tIF_EVENT(printk(\"ia: not partially allocated resources\\n\");) \n-\t\tvcc->dev_data = NULL;\n-\t} \n-\tif (vcc->vci != ATM_VPI_UNSPEC && vcc->vpi != ATM_VCI_UNSPEC) \n-\t{ \n-\t\tIF_EVENT(printk(\"iphase open: unspec part\\n\");) \n-\t\tset_bit(ATM_VF_ADDR,&vcc->flags);\n-\t} \n-\tif (vcc->qos.aal != ATM_AAL5) \n-\t\treturn -EINVAL; \n-\tIF_EVENT(printk(DEV_LABEL \"(itf %d): open %d.%d\\n\", \n- vcc->dev->number, vcc->vpi, vcc->vci);) \n- \n-\t/* Device dependent initialization */ \n-\tia_vcc = kmalloc_obj(*ia_vcc); \n-\tif (!ia_vcc) return -ENOMEM; \n-\tvcc->dev_data = ia_vcc;\n- \n-\tif ((error = open_rx(vcc))) \n-\t{ \n-\t\tIF_EVENT(printk(\"iadev: error in open_rx, closing\\n\");) \n-\t\tia_close(vcc); \n-\t\treturn error; \n-\t} \n- \n-\tif ((error = open_tx(vcc))) \n-\t{ \n-\t\tIF_EVENT(printk(\"iadev: error in open_tx, closing\\n\");) \n-\t\tia_close(vcc); \n-\t\treturn error; \n-\t} \n- \n-\tset_bit(ATM_VF_READY,&vcc->flags);\n-\n-#if 0\n- {\n- static u8 first = 1; \n- if (first) {\n- ia_timer.expires = jiffies + 3*HZ;\n- add_timer(&ia_timer);\n- first = 0;\n- } \n- }\n-#endif\n-\tIF_EVENT(printk(\"ia open returning\\n\");) \n-\treturn 0; \n-} \n- \n-static int ia_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) \n-{ \n-\tIF_EVENT(printk(\">ia_change_qos\\n\");) \n-\treturn 0; \n-} \n- \n-static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg) \n-{ \n- IA_CMDBUF ia_cmds;\n- IADEV *iadev;\n- int i, board;\n- u16 __user *tmps;\n- IF_EVENT(printk(\">ia_ioctl\\n\");) \n- if (cmd != IA_CMD) {\n- if (!dev->phy->ioctl) return -EINVAL;\n- return dev->phy->ioctl(dev,cmd,arg);\n- }\n- if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT; \n- board = ia_cmds.status;\n-\n-\tif ((board < 0) || (board > iadev_count))\n-\t\tboard = 0;\n-\tboard = array_index_nospec(board, iadev_count + 1);\n-\n- iadev = ia_dev[board];\n- switch (ia_cmds.cmd) {\n- case MEMDUMP:\n- {\n-\tswitch (ia_cmds.sub_cmd) {\n- case MEMDUMP_SEGREG:\n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n- tmps = (u16 __user *)ia_cmds.buf;\n- for(i=0; i<0x80; i+=2, tmps++)\n- if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;\n- ia_cmds.status = 0;\n- ia_cmds.len = 0x80;\n- break;\n- case MEMDUMP_REASSREG:\n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n- tmps = (u16 __user *)ia_cmds.buf;\n- for(i=0; i<0x80; i+=2, tmps++)\n- if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;\n- ia_cmds.status = 0;\n- ia_cmds.len = 0x80;\n- break;\n- case MEMDUMP_FFL:\n- { \n- ia_regs_t *regs_local;\n- ffredn_t *ffL;\n- rfredn_t *rfL;\n- \n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n-\t regs_local = kmalloc_obj(*regs_local);\n-\t if (!regs_local) return -ENOMEM;\n-\t ffL = ®s_local->ffredn;\n-\t rfL = ®s_local->rfredn;\n- /* Copy real rfred registers into the local copy */\n- \t for (i=0; i<(sizeof (rfredn_t))/4; i++)\n- ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;\n- \t/* Copy real ffred registers into the local copy */\n-\t for (i=0; i<(sizeof (ffredn_t))/4; i++)\n- ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;\n-\n- if (copy_to_user(ia_cmds.buf, regs_local,sizeof(ia_regs_t))) {\n- kfree(regs_local);\n- return -EFAULT;\n- }\n- kfree(regs_local);\n- printk(\"Board %d registers dumped\\n\", board);\n- ia_cmds.status = 0; \n-\t }\t\n- \t break; \n- case READ_REG:\n- { \n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n- desc_dbg(iadev); \n- ia_cmds.status = 0; \n- }\n- break;\n- case 0x6:\n- { \n- ia_cmds.status = 0; \n- printk(\"skb = 0x%p\\n\", skb_peek(&iadev->tx_backlog));\n- printk(\"rtn_q: 0x%p\\n\",ia_deque_rtn_q(&iadev->tx_return_q));\n- }\n- break;\n- case 0x8:\n- {\n- struct k_sonet_stats *stats;\n- stats = &PRIV(_ia_dev[board])->sonet_stats;\n- printk(\"section_bip: %d\\n\", atomic_read(&stats->section_bip));\n- printk(\"line_bip : %d\\n\", atomic_read(&stats->line_bip));\n- printk(\"path_bip : %d\\n\", atomic_read(&stats->path_bip));\n- printk(\"line_febe : %d\\n\", atomic_read(&stats->line_febe));\n- printk(\"path_febe : %d\\n\", atomic_read(&stats->path_febe));\n- printk(\"corr_hcs : %d\\n\", atomic_read(&stats->corr_hcs));\n- printk(\"uncorr_hcs : %d\\n\", atomic_read(&stats->uncorr_hcs));\n- printk(\"tx_cells : %d\\n\", atomic_read(&stats->tx_cells));\n- printk(\"rx_cells : %d\\n\", atomic_read(&stats->rx_cells));\n- }\n- ia_cmds.status = 0;\n- break;\n- case 0x9:\n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n- for (i = 1; i <= iadev->num_rx_desc; i++)\n- free_desc(_ia_dev[board], i);\n- writew( ~(RX_FREEQ_EMPT | RX_EXCP_RCVD), \n- iadev->reass_reg+REASS_MASK_REG);\n- iadev->rxing = 1;\n- \n- ia_cmds.status = 0;\n- break;\n-\n- case 0xb:\n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n- ia_frontend_intr(iadev);\n- break;\n- case 0xa:\n-\t if (!capable(CAP_NET_ADMIN)) return -EPERM;\n- { \n- ia_cmds.status = 0; \n- IADebugFlag = ia_cmds.maddr;\n- printk(\"New debug option loaded\\n\");\n- }\n- break;\n- default:\n- ia_cmds.status = 0;\n- break;\n- }\t\n- }\n- break;\n- default:\n- break;\n-\n- }\t\n- return 0; \n-} \n- \n-static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {\n- IADEV *iadev;\n- struct dle *wr_ptr;\n- struct tx_buf_desc __iomem *buf_desc_ptr;\n- int desc;\n- int comp_code;\n- int total_len;\n- struct cpcs_trailer *trailer;\n- struct ia_vcc *iavcc;\n-\n- iadev = INPH_IA_DEV(vcc->dev); \n- iavcc = INPH_IA_VCC(vcc);\n- if (!iavcc->txing) {\n- printk(\"discard packet on closed VC\\n\");\n- if (vcc->pop)\n-\t\tvcc->pop(vcc, skb);\n- else\n-\t\tdev_kfree_skb_any(skb);\n-\t return 0;\n- }\n-\n- if (skb->len > iadev->tx_buf_sz - 8) {\n- printk(\"Transmit size over tx buffer size\\n\");\n- if (vcc->pop)\n- vcc->pop(vcc, skb);\n- else\n- dev_kfree_skb_any(skb);\n- return 0;\n- }\n- if ((unsigned long)skb->data & 3) {\n- printk(\"Misaligned SKB\\n\");\n- if (vcc->pop)\n- vcc->pop(vcc, skb);\n- else\n- dev_kfree_skb_any(skb);\n- return 0;\n- } \n-\t/* Get a descriptor number from our free descriptor queue \n-\t We get the descr number from the TCQ now, since I am using \n-\t the TCQ as a free buffer queue. Initially TCQ will be \n-\t initialized with all the descriptors and is hence, full. \n-\t*/\n-\tdesc = get_desc (iadev, iavcc);\n-\tif (desc == 0xffff) \n-\t return 1;\n-\tcomp_code = desc >> 13; \n-\tdesc &= 0x1fff; \n- \n-\tif ((desc == 0) || (desc > iadev->num_tx_desc)) \n-\t{ \n-\t\tIF_ERR(printk(DEV_LABEL \"invalid desc for send: %d\\n\", desc);) \n- atomic_inc(&vcc->stats->tx);\n-\t\tif (vcc->pop) \n-\t\t vcc->pop(vcc, skb); \n-\t\telse \n-\t\t dev_kfree_skb_any(skb);\n-\t\treturn 0; /* return SUCCESS */\n-\t} \n- \n-\tif (comp_code) \n-\t{ \n-\t IF_ERR(printk(DEV_LABEL \"send desc:%d completion code %d error\\n\", \n- desc, comp_code);) \n-\t} \n- \n- /* remember the desc and vcc mapping */\n- iavcc->vc_desc_cnt++;\n- iadev->desc_tbl[desc-1].iavcc = iavcc;\n- iadev->desc_tbl[desc-1].txskb = skb;\n- IA_SKB_STATE(skb) = 0;\n-\n- iadev->ffL.tcq_rd += 2;\n- if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)\n-\t \tiadev->ffL.tcq_rd = iadev->ffL.tcq_st;\n-\twritew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);\n- \n-\t/* Put the descriptor number in the packet ready queue \n-\t\tand put the updated write pointer in the DLE field \n-\t*/ \n-\t*(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc; \n-\n- \tiadev->ffL.prq_wr += 2;\n- if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)\n- iadev->ffL.prq_wr = iadev->ffL.prq_st;\n-\t \n-\t/* Figure out the exact length of the packet and padding required to \n- make it aligned on a 48 byte boundary. */\n-\ttotal_len = skb->len + sizeof(struct cpcs_trailer); \n-\ttotal_len = ((total_len + 47) / 48) * 48;\n-\tIF_TX(printk(\"ia packet len:%d padding:%d\\n\", total_len, total_len - skb->len);) \n- \n-\t/* Put the packet in a tx buffer */ \n-\ttrailer = iadev->tx_buf[desc-1].cpcs;\n- IF_TX(printk(\"Sent: skb = 0x%p skb->data: 0x%p len: %d, desc: %d\\n\",\n- skb, skb->data, skb->len, desc);)\n-\ttrailer->control = 0; \n- /*big endian*/ \n-\ttrailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);\n-\ttrailer->crc32 = 0;\t/* not needed - dummy bytes */ \n-\n-\t/* Display the packet */ \n-\tIF_TXPKT(printk(\"Sent data: len = %d MsgNum = %d\\n\", \n- skb->len, tcnter++); \n- xdump(skb->data, skb->len, \"TX: \");\n- printk(\"\\n\");)\n-\n-\t/* Build the buffer descriptor */ \n-\tbuf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;\n-\tbuf_desc_ptr += desc;\t/* points to the corresponding entry */ \n-\tbuf_desc_ptr->desc_mode = AAL5 | EOM_EN | APP_CRC32 | CMPL_INT; \n-\t/* Huh ? p.115 of users guide describes this as a read-only register */\n- writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);\n-\tbuf_desc_ptr->vc_index = vcc->vci;\n-\tbuf_desc_ptr->bytes = total_len; \n-\n- if (vcc->qos.txtp.traffic_class == ATM_ABR) \n-\t clear_lockup (vcc, iadev);\n-\n-\t/* Build the DLE structure */ \n-\twr_ptr = iadev->tx_dle_q.write; \n-\tmemset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr)); \n-\twr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,\n-\t\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\twr_ptr->local_pkt_addr = (buf_desc_ptr->buf_start_hi << 16) | \n- buf_desc_ptr->buf_start_lo; \n-\t/* wr_ptr->bytes = swap_byte_order(total_len); didn't seem to affect?? */\n-\twr_ptr->bytes = skb->len; \n-\n- /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */\n- if ((wr_ptr->bytes >> 2) == 0xb)\n- wr_ptr->bytes = 0x30;\n-\n-\twr_ptr->mode = TX_DLE_PSI; \n-\twr_ptr->prq_wr_ptr_data = 0;\n- \n-\t/* end is not to be used for the DLE q */ \n-\tif (++wr_ptr == iadev->tx_dle_q.end) \n-\t\twr_ptr = iadev->tx_dle_q.start; \n- \n- /* Build trailer dle */\n- wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;\n- wr_ptr->local_pkt_addr = ((buf_desc_ptr->buf_start_hi << 16) | \n- buf_desc_ptr->buf_start_lo) + total_len - sizeof(struct cpcs_trailer);\n-\n- wr_ptr->bytes = sizeof(struct cpcs_trailer);\n- wr_ptr->mode = DMA_INT_ENABLE; \n- wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;\n- \n- /* end is not to be used for the DLE q */\n- if (++wr_ptr == iadev->tx_dle_q.end) \n- wr_ptr = iadev->tx_dle_q.start;\n-\n-\tiadev->tx_dle_q.write = wr_ptr; \n- ATM_DESC(skb) = vcc->vci;\n- skb_queue_tail(&iadev->tx_dma_q, skb);\n-\n- atomic_inc(&vcc->stats->tx);\n- iadev->tx_pkt_cnt++;\n-\t/* Increment transaction counter */ \n-\twritel(2, iadev->dma+IPHASE5575_TX_COUNTER); \n- \n-#if 0 \n- /* add flow control logic */ \n- if (atomic_read(&vcc->stats->tx) % 20 == 0) {\n- if (iavcc->vc_desc_cnt > 10) {\n- vcc->tx_quota = vcc->tx_quota * 3 / 4;\n- printk(\"Tx1: vcc->tx_quota = %d \\n\", (u32)vcc->tx_quota );\n- iavcc->flow_inc = -1;\n- iavcc->saved_tx_quota = vcc->tx_quota;\n- } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {\n- // vcc->tx_quota = 3 * iavcc->saved_tx_quota / 4;\n- printk(\"Tx2: vcc->tx_quota = %d \\n\", (u32)vcc->tx_quota ); \n- iavcc->flow_inc = 0;\n- }\n- }\n-#endif\n-\tIF_TX(printk(\"ia send done\\n\");) \n-\treturn 0; \n-} \n-\n-static int ia_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n- IADEV *iadev; \n- unsigned long flags;\n-\n- iadev = INPH_IA_DEV(vcc->dev);\n- if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))\n- {\n- if (!skb)\n- printk(KERN_CRIT \"null skb in ia_send\\n\");\n- else dev_kfree_skb_any(skb);\n- return -EINVAL;\n- } \n- spin_lock_irqsave(&iadev->tx_lock, flags); \n- if (!test_bit(ATM_VF_READY,&vcc->flags)){ \n- dev_kfree_skb_any(skb);\n- spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- return -EINVAL; \n- }\n- ATM_SKB(skb)->vcc = vcc;\n- \n- if (skb_peek(&iadev->tx_backlog)) {\n- skb_queue_tail(&iadev->tx_backlog, skb);\n- }\n- else {\n- if (ia_pkt_tx (vcc, skb)) {\n- skb_queue_tail(&iadev->tx_backlog, skb);\n- }\n- }\n- spin_unlock_irqrestore(&iadev->tx_lock, flags);\n- return 0;\n-\n-}\n-\n-static int ia_proc_read(struct atm_dev *dev,loff_t *pos,char *page)\n-{ \n- int left = *pos, n; \n- char *tmpPtr;\n- IADEV *iadev = INPH_IA_DEV(dev);\n- if(!left--) {\n- if (iadev->phy_type == FE_25MBIT_PHY) {\n- n = sprintf(page, \" Board Type : Iphase5525-1KVC-128K\\n\");\n- return n;\n- }\n- if (iadev->phy_type == FE_DS3_PHY)\n- n = sprintf(page, \" Board Type : Iphase-ATM-DS3\");\n- else if (iadev->phy_type == FE_E3_PHY)\n- n = sprintf(page, \" Board Type : Iphase-ATM-E3\");\n- else if (iadev->phy_type == FE_UTP_OPTION)\n- n = sprintf(page, \" Board Type : Iphase-ATM-UTP155\"); \n- else\n- n = sprintf(page, \" Board Type : Iphase-ATM-OC3\");\n- tmpPtr = page + n;\n- if (iadev->pci_map_size == 0x40000)\n- n += sprintf(tmpPtr, \"-1KVC-\");\n- else\n- n += sprintf(tmpPtr, \"-4KVC-\"); \n- tmpPtr = page + n; \n- if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)\n- n += sprintf(tmpPtr, \"1M \\n\");\n- else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)\n- n += sprintf(tmpPtr, \"512K\\n\");\n- else\n- n += sprintf(tmpPtr, \"128K\\n\");\n- return n;\n- }\n- if (!left) {\n- return sprintf(page, \" Number of Tx Buffer: %u\\n\"\n- \" Size of Tx Buffer : %u\\n\"\n- \" Number of Rx Buffer: %u\\n\"\n- \" Size of Rx Buffer : %u\\n\"\n- \" Packets Received : %u\\n\"\n- \" Packets Transmitted: %u\\n\"\n- \" Cells Received : %u\\n\"\n- \" Cells Transmitted : %u\\n\"\n- \" Board Dropped Cells: %u\\n\"\n- \" Board Dropped Pkts : %u\\n\",\n- iadev->num_tx_desc, iadev->tx_buf_sz,\n- iadev->num_rx_desc, iadev->rx_buf_sz,\n- iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,\n- iadev->rx_cell_cnt, iadev->tx_cell_cnt,\n- iadev->drop_rxcell, iadev->drop_rxpkt); \n- }\n- return 0;\n-}\n- \n-static const struct atmdev_ops ops = { \n-\t.open\t\t= ia_open, \n-\t.close\t\t= ia_close, \n-\t.ioctl\t\t= ia_ioctl, \n-\t.send\t\t= ia_send, \n-\t.phy_put\t= ia_phy_put, \n-\t.phy_get\t= ia_phy_get, \n-\t.change_qos\t= ia_change_qos, \n-\t.proc_read\t= ia_proc_read,\n-\t.owner\t\t= THIS_MODULE,\n-}; \n-\t \n-static int ia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)\n-{ \n-\tstruct atm_dev *dev; \n-\tIADEV *iadev; \n-\tint ret;\n-\n-\tiadev = kzalloc_obj(*iadev);\n-\tif (!iadev) {\n-\t\tret = -ENOMEM;\n-\t\tgoto err_out;\n-\t}\n-\n-\tiadev->pci = pdev;\n-\n-\tIF_INIT(printk(\"ia detected at bus:%d dev: %d function:%d\\n\",\n-\t\tpdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));)\n-\tif (pci_enable_device(pdev)) {\n-\t\tret = -ENODEV;\n-\t\tgoto err_out_free_iadev;\n-\t}\n-\tdev = atm_dev_register(DEV_LABEL, &pdev->dev, &ops, -1, NULL);\n-\tif (!dev) {\n-\t\tret = -ENOMEM;\n-\t\tgoto err_out_disable_dev;\n-\t}\n-\tdev->dev_data = iadev;\n-\tIF_INIT(printk(DEV_LABEL \"registered at (itf :%d)\\n\", dev->number);)\n-\tIF_INIT(printk(\"dev_id = 0x%p iadev->LineRate = %d \\n\", dev,\n-\t\tiadev->LineRate);)\n-\n-\tpci_set_drvdata(pdev, dev);\n-\n-\tia_dev[iadev_count] = iadev;\n-\t_ia_dev[iadev_count] = dev;\n-\tiadev_count++;\n-\tif (ia_init(dev) || ia_start(dev)) { \n-\t\tIF_INIT(printk(\"IA register failed!\\n\");)\n-\t\tiadev_count--;\n-\t\tia_dev[iadev_count] = NULL;\n-\t\t_ia_dev[iadev_count] = NULL;\n-\t\tret = -EINVAL;\n-\t\tgoto err_out_deregister_dev;\n-\t}\n-\tIF_EVENT(printk(\"iadev_count = %d\\n\", iadev_count);)\n-\n-\tiadev->next_board = ia_boards; \n-\tia_boards = dev; \n-\n-\treturn 0;\n-\n-err_out_deregister_dev:\n-\tatm_dev_deregister(dev); \n-err_out_disable_dev:\n-\tpci_disable_device(pdev);\n-err_out_free_iadev:\n-\tkfree(iadev);\n-err_out:\n-\treturn ret;\n-}\n-\n-static void ia_remove_one(struct pci_dev *pdev)\n-{\n-\tstruct atm_dev *dev = pci_get_drvdata(pdev);\n-\tIADEV *iadev = INPH_IA_DEV(dev);\n-\n-\t/* Disable phy interrupts */\n-\tia_phy_put(dev, ia_phy_get(dev, SUNI_RSOP_CIE) & ~(SUNI_RSOP_CIE_LOSE),\n-\t\t\t\t SUNI_RSOP_CIE);\n-\tudelay(1);\n-\n-\tif (dev->phy && dev->phy->stop)\n-\t\tdev->phy->stop(dev);\n-\n-\t/* De-register device */ \n- \tfree_irq(iadev->irq, dev);\n-\tiadev_count--;\n-\tia_dev[iadev_count] = NULL;\n-\t_ia_dev[iadev_count] = NULL;\n-\tIF_EVENT(printk(\"deregistering iav at (itf:%d)\\n\", dev->number);)\n-\tatm_dev_deregister(dev);\n-\n- \tiounmap(iadev->base); \n-\tpci_disable_device(pdev);\n-\n-\tia_free_rx(iadev);\n-\tia_free_tx(iadev);\n-\n- \tkfree(iadev);\n-}\n-\n-static const struct pci_device_id ia_pci_tbl[] = {\n-\t{ PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },\n-\t{ PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },\n-\t{ 0,}\n-};\n-MODULE_DEVICE_TABLE(pci, ia_pci_tbl);\n-\n-static struct pci_driver ia_driver = {\n-\t.name = DEV_LABEL,\n-\t.id_table = ia_pci_tbl,\n-\t.probe = ia_init_one,\n-\t.remove = ia_remove_one,\n-};\n-\n-static int __init ia_module_init(void)\n-{\n-\tint ret;\n-\n-\tret = pci_register_driver(&ia_driver);\n-\tif (ret >= 0) {\n-\t\tia_timer.expires = jiffies + 3*HZ;\n-\t\tadd_timer(&ia_timer); \n-\t} else\n-\t\tprintk(KERN_ERR DEV_LABEL \": no adapter found\\n\"); \n-\treturn ret;\n-}\n-\n-static void __exit ia_module_exit(void)\n-{\n-\tpci_unregister_driver(&ia_driver);\n-\n-\ttimer_delete_sync(&ia_timer);\n-}\n-\n-module_init(ia_module_init);\n-module_exit(ia_module_exit);\ndiff --git a/drivers/atm/lanai.c b/drivers/atm/lanai.c\ndeleted file mode 100644\nindex d6af999a9ebb..000000000000\n--- a/drivers/atm/lanai.c\n+++ /dev/null\n@@ -1,2603 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later\n-/* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr \n- *\n- * This driver supports ATM cards based on the Efficient \"Lanai\"\n- * chipset such as the Speedstream 3010 and the ENI-25p. The\n- * Speedstream 3060 is currently not supported since we don't\n- * have the code to drive the on-board Alcatel DSL chipset (yet).\n- *\n- * Thanks to Efficient for supporting this project with hardware,\n- * documentation, and by answering my questions.\n- *\n- * Things not working yet:\n- *\n- * o We don't support the Speedstream 3060 yet - this card has\n- * an on-board DSL modem chip by Alcatel and the driver will\n- * need some extra code added to handle it\n- *\n- * o Note that due to limitations of the Lanai only one VCC can be\n- * in CBR at once\n- *\n- * o We don't currently parse the EEPROM at all. The code is all\n- * there as per the spec, but it doesn't actually work. I think\n- * there may be some issues with the docs. Anyway, do NOT\n- * enable it yet - bugs in that code may actually damage your\n- * hardware! Because of this you should hardware an ESI before\n- * trying to use this in a LANE or MPOA environment.\n- *\n- * o AAL0 is stubbed in but the actual rx/tx path isn't written yet:\n- *\tvcc_tx_aal0() needs to send or queue a SKB\n- *\tvcc_tx_unqueue_aal0() needs to attempt to send queued SKBs\n- *\tvcc_rx_aal0() needs to handle AAL0 interrupts\n- * This isn't too much work - I just wanted to get other things\n- * done first.\n- *\n- * o lanai_change_qos() isn't written yet\n- *\n- * o There aren't any ioctl's yet -- I'd like to eventually support\n- * setting loopback and LED modes that way.\n- *\n- * o If the segmentation engine or DMA gets shut down we should restart\n- * card as per section 17.0i. (see lanai_reset)\n- *\n- * o setsockopt(SO_CIRANGE) isn't done (although despite what the\n- * API says it isn't exactly commonly implemented)\n- */\n-\n-/* Version history:\n- * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates\n- * v.0.02 -- 11-JAN-2000 -- Endian fixes\n- * v.0.01 -- 30-NOV-1999 -- Initial release\n- */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-/* -------------------- TUNABLE PARAMATERS: */\n-\n-/*\n- * Maximum number of VCIs per card. Setting it lower could theoretically\n- * save some memory, but since we allocate our vcc list with get_free_pages,\n- * it's not really likely for most architectures\n- */\n-#define NUM_VCI\t\t\t(1024)\n-\n-/*\n- * Enable extra debugging\n- */\n-#define DEBUG\n-/*\n- * Debug _all_ register operations with card, except the memory test.\n- * Also disables the timed poll to prevent extra chattiness. This\n- * isn't for normal use\n- */\n-#undef DEBUG_RW\n-\n-/*\n- * The programming guide specifies a full test of the on-board SRAM\n- * at initialization time. Undefine to remove this\n- */\n-#define FULL_MEMORY_TEST\n-\n-/*\n- * This is the number of (4 byte) service entries that we will\n- * try to allocate at startup. Note that we will end up with\n- * one PAGE_SIZE's worth regardless of what this is set to\n- */\n-#define SERVICE_ENTRIES\t\t(1024)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * We normally read the onboard EEPROM in order to discover our MAC\n- * address. Undefine to _not_ do this\n- */\n-/* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */\n-/* TODO: make above a module load-time option (also) */\n-\n-/*\n- * Depth of TX fifo (in 128 byte units; range 2-31)\n- * Smaller numbers are better for network latency\n- * Larger numbers are better for PCI latency\n- * I'm really sure where the best tradeoff is, but the BSD driver uses\n- * 7 and it seems to work ok.\n- */\n-#define TX_FIFO_DEPTH\t\t(7)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * How often (in jiffies) we will try to unstick stuck connections -\n- * shouldn't need to happen much\n- */\n-#define LANAI_POLL_PERIOD\t(10*HZ)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * When allocating an AAL5 receiving buffer, try to make it at least\n- * large enough to hold this many max_sdu sized PDUs\n- */\n-#define AAL5_RX_MULTIPLIER\t(3)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * Same for transmitting buffer\n- */\n-#define AAL5_TX_MULTIPLIER\t(3)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * When allocating an AAL0 transmiting buffer, how many cells should fit.\n- * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't\n- * really critical\n- */\n-#define AAL0_TX_MULTIPLIER\t(40)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * How large should we make the AAL0 receiving buffer. Remember that this\n- * is shared between all AAL0 VC's\n- */\n-#define AAL0_RX_BUFFER_SIZE\t(PAGE_SIZE)\n-/* TODO: make above a module load-time option */\n-\n-/*\n- * Should we use Lanai's \"powerdown\" feature when no vcc's are bound?\n- */\n-/* #define USE_POWERDOWN */\n-/* TODO: make above a module load-time option (also) */\n-\n-/* -------------------- DEBUGGING AIDS: */\n-\n-#define DEV_LABEL \"lanai\"\n-\n-#ifdef DEBUG\n-\n-#define DPRINTK(format, args...) \\\n-\tprintk(KERN_DEBUG DEV_LABEL \": \" format, ##args)\n-#define APRINTK(truth, format, args...) \\\n-\tdo { \\\n-\t\tif (unlikely(!(truth))) \\\n-\t\t\tprintk(KERN_ERR DEV_LABEL \": \" format, ##args); \\\n-\t} while (0)\n-\n-#else /* !DEBUG */\n-\n-#define DPRINTK(format, args...)\n-#define APRINTK(truth, format, args...)\n-\n-#endif /* DEBUG */\n-\n-#ifdef DEBUG_RW\n-#define RWDEBUG(format, args...) \\\n-\tprintk(KERN_DEBUG DEV_LABEL \": \" format, ##args)\n-#else /* !DEBUG_RW */\n-#define RWDEBUG(format, args...)\n-#endif\n-\n-/* -------------------- DATA DEFINITIONS: */\n-\n-#define LANAI_MAPPING_SIZE\t(0x40000)\n-#define LANAI_EEPROM_SIZE\t(128)\n-\n-typedef int vci_t;\n-typedef void __iomem *bus_addr_t;\n-\n-/* DMA buffer in host memory for TX, RX, or service list. */\n-struct lanai_buffer {\n-\tu32 *start;\t/* From get_free_pages */\n-\tu32 *end;\t/* One past last byte */\n-\tu32 *ptr;\t/* Pointer to current host location */\n-\tdma_addr_t dmaaddr;\n-};\n-\n-struct lanai_vcc_stats {\n-\tunsigned rx_nomem;\n-\tunion {\n-\t\tstruct {\n-\t\t\tunsigned rx_badlen;\n-\t\t\tunsigned service_trash;\n-\t\t\tunsigned service_stream;\n-\t\t\tunsigned service_rxcrc;\n-\t\t} aal5;\n-\t\tstruct {\n-\t\t} aal0;\n-\t} x;\n-};\n-\n-struct lanai_dev;\t\t\t/* Forward declaration */\n-\n-/*\n- * This is the card-specific per-vcc data. Note that unlike some other\n- * drivers there is NOT a 1-to-1 correspondance between these and\n- * atm_vcc's - each one of these represents an actual 2-way vcc, but\n- * an atm_vcc can be 1-way and share with a 1-way vcc in the other\n- * direction. To make it weirder, there can even be 0-way vccs\n- * bound to us, waiting to do a change_qos\n- */\n-struct lanai_vcc {\n-\tbus_addr_t vbase;\t\t/* Base of VCC's registers */\n-\tstruct lanai_vcc_stats stats;\n-\tint nref;\t\t\t/* # of atm_vcc's who reference us */\n-\tvci_t vci;\n-\tstruct {\n-\t\tstruct lanai_buffer buf;\n-\t\tstruct atm_vcc *atmvcc;\t/* atm_vcc who is receiver */\n-\t} rx;\n-\tstruct {\n-\t\tstruct lanai_buffer buf;\n-\t\tstruct atm_vcc *atmvcc;\t/* atm_vcc who is transmitter */\n-\t\tint endptr;\t\t/* last endptr from service entry */\n-\t\tstruct sk_buff_head backlog;\n-\t\tvoid (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);\n-\t} tx;\n-};\n-\n-enum lanai_type {\n-\tlanai2\t= PCI_DEVICE_ID_EF_ATM_LANAI2,\n-\tlanaihb\t= PCI_DEVICE_ID_EF_ATM_LANAIHB\n-};\n-\n-struct lanai_dev_stats {\n-\tunsigned ovfl_trash;\t/* # of cells dropped - buffer overflow */\n-\tunsigned vci_trash;\t/* # of cells dropped - closed vci */\n-\tunsigned hec_err;\t/* # of cells dropped - bad HEC */\n-\tunsigned atm_ovfl;\t/* # of cells dropped - rx fifo overflow */\n-\tunsigned pcierr_parity_detect;\n-\tunsigned pcierr_serr_set;\n-\tunsigned pcierr_master_abort;\n-\tunsigned pcierr_m_target_abort;\n-\tunsigned pcierr_s_target_abort;\n-\tunsigned pcierr_master_parity;\n-\tunsigned service_notx;\n-\tunsigned service_norx;\n-\tunsigned service_rxnotaal5;\n-\tunsigned dma_reenable;\n-\tunsigned card_reset;\n-};\n-\n-struct lanai_dev {\n-\tbus_addr_t base;\n-\tstruct lanai_dev_stats stats;\n-\tstruct lanai_buffer service;\n-\tstruct lanai_vcc **vccs;\n-#ifdef USE_POWERDOWN\n-\tint nbound;\t\t\t/* number of bound vccs */\n-#endif\n-\tenum lanai_type type;\n-\tvci_t num_vci;\t\t\t/* Currently just NUM_VCI */\n-\tu8 eeprom[LANAI_EEPROM_SIZE];\n-\tu32 serialno, magicno;\n-\tstruct pci_dev *pci;\n-\tDECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */\n-\tDECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */\n-\tstruct timer_list timer;\n-\tint naal0;\n-\tstruct lanai_buffer aal0buf;\t/* AAL0 RX buffers */\n-\tu32 conf1, conf2;\t\t/* CONFIG[12] registers */\n-\tu32 status;\t\t\t/* STATUS register */\n-\tspinlock_t endtxlock;\n-\tspinlock_t servicelock;\n-\tstruct atm_vcc *cbrvcc;\n-\tint number;\n-\tint board_rev;\n-/* TODO - look at race conditions with maintence of conf1/conf2 */\n-/* TODO - transmit locking: should we use _irq not _irqsave? */\n-/* TODO - organize above in some rational fashion (see ) */\n-};\n-\n-/*\n- * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)\n- * This function iterates one of these, calling a given function for each\n- * vci with their bit set\n- */\n-static void vci_bitfield_iterate(struct lanai_dev *lanai,\n-\tconst unsigned long *lp,\n-\tvoid (*func)(struct lanai_dev *,vci_t vci))\n-{\n-\tvci_t vci;\n-\n-\tfor_each_set_bit(vci, lp, NUM_VCI)\n-\t\tfunc(lanai, vci);\n-}\n-\n-/* -------------------- BUFFER UTILITIES: */\n-\n-/*\n- * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -\n- * usually any page allocation will do. Just to be safe in case\n- * PAGE_SIZE is insanely tiny, though...\n- */\n-#define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)\n-\n-/*\n- * Allocate a buffer in host RAM for service list, RX, or TX\n- * Returns buf->start==NULL if no memory\n- * Note that the size will be rounded up 2^n bytes, and\n- * if we can't allocate that we'll settle for something smaller\n- * until minbytes\n- */\n-static void lanai_buf_allocate(struct lanai_buffer *buf,\n-\tsize_t bytes, size_t minbytes, struct pci_dev *pci)\n-{\n-\tint size;\n-\n-\tif (bytes > (128 * 1024))\t/* max lanai buffer size */\n-\t\tbytes = 128 * 1024;\n-\tfor (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)\n-\t\t;\n-\tif (minbytes < LANAI_PAGE_SIZE)\n-\t\tminbytes = LANAI_PAGE_SIZE;\n-\tdo {\n-\t\t/*\n-\t\t * Technically we could use non-consistent mappings for\n-\t\t * everything, but the way the lanai uses DMA memory would\n-\t\t * make that a terrific pain. This is much simpler.\n-\t\t */\n-\t\tbuf->start = dma_alloc_coherent(&pci->dev,\n-\t\t\t\t\t\tsize, &buf->dmaaddr, GFP_KERNEL);\n-\t\tif (buf->start != NULL) {\t/* Success */\n-\t\t\t/* Lanai requires 256-byte alignment of DMA bufs */\n-\t\t\tAPRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,\n-\t\t\t \"bad dmaaddr: 0x%lx\\n\",\n-\t\t\t (unsigned long) buf->dmaaddr);\n-\t\t\tbuf->ptr = buf->start;\n-\t\t\tbuf->end = (u32 *)\n-\t\t\t (&((unsigned char *) buf->start)[size]);\n-\t\t\tmemset(buf->start, 0, size);\n-\t\t\tbreak;\n-\t\t}\n-\t\tsize /= 2;\n-\t} while (size >= minbytes);\n-}\n-\n-/* size of buffer in bytes */\n-static inline size_t lanai_buf_size(const struct lanai_buffer *buf)\n-{\n-\treturn ((unsigned long) buf->end) - ((unsigned long) buf->start);\n-}\n-\n-static void lanai_buf_deallocate(struct lanai_buffer *buf,\n-\tstruct pci_dev *pci)\n-{\n-\tif (buf->start != NULL) {\n-\t\tdma_free_coherent(&pci->dev, lanai_buf_size(buf),\n-\t\t\t\t buf->start, buf->dmaaddr);\n-\t\tbuf->start = buf->end = buf->ptr = NULL;\n-\t}\n-}\n-\n-/* size of buffer as \"card order\" (0=1k .. 7=128k) */\n-static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)\n-{\n-\tint order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);\n-\n-\t/* This can only happen if PAGE_SIZE is gigantic, but just in case */\n-\tif (order > 7)\n-\t\torder = 7;\n-\treturn order;\n-}\n-\n-/* -------------------- PORT I/O UTILITIES: */\n-\n-/* Registers (and their bit-fields) */\n-enum lanai_register {\n-\tReset_Reg\t\t= 0x00,\t/* Reset; read for chip type; bits: */\n-#define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03)\t/* Board revision */\n-#define RESET_GET_BOARD_ID(x)\t (((x)>> 2)&0x03)\t/* Board ID */\n-#define BOARD_ID_LANAI256\t\t(0)\t/* 25.6M adapter card */\n-\tEndian_Reg\t\t= 0x04,\t/* Endian setting */\n-\tIntStatus_Reg\t\t= 0x08,\t/* Interrupt status */\n-\tIntStatusMasked_Reg\t= 0x0C,\t/* Interrupt status (masked) */\n-\tIntAck_Reg\t\t= 0x10,\t/* Interrupt acknowledge */\n-\tIntAckMasked_Reg\t= 0x14,\t/* Interrupt acknowledge (masked) */\n-\tIntStatusSet_Reg\t= 0x18,\t/* Get status + enable/disable */\n-\tIntStatusSetMasked_Reg\t= 0x1C,\t/* Get status + en/di (masked) */\n-\tIntControlEna_Reg\t= 0x20,\t/* Interrupt control enable */\n-\tIntControlDis_Reg\t= 0x24,\t/* Interrupt control disable */\n-\tStatus_Reg\t\t= 0x28,\t/* Status */\n-#define STATUS_PROMDATA\t (0x00000001)\t/* PROM_DATA pin */\n-#define STATUS_WAITING\t (0x00000002)\t/* Interrupt being delayed */\n-#define\t STATUS_SOOL\t\t (0x00000004)\t/* SOOL alarm */\n-#define STATUS_LOCD\t\t (0x00000008)\t/* LOCD alarm */\n-#define\t STATUS_LED\t\t (0x00000010)\t/* LED (HAPPI) output */\n-#define STATUS_GPIN\t\t (0x00000020)\t/* GPIN pin */\n-#define STATUS_BUTTBUSY\t (0x00000040)\t/* Butt register is pending */\n-\tConfig1_Reg\t\t= 0x2C,\t/* Config word 1; bits: */\n-#define CONFIG1_PROMDATA\t (0x00000001)\t/* PROM_DATA pin */\n-#define CONFIG1_PROMCLK\t (0x00000002)\t/* PROM_CLK pin */\n-#define CONFIG1_SET_READMODE(x) ((x)*0x004)\t/* PCI BM reads; values: */\n-#define READMODE_PLAIN\t (0)\t\t/* Plain memory read */\n-#define READMODE_LINE\t (2)\t\t/* Memory read line */\n-#define READMODE_MULTIPLE\t (3)\t\t/* Memory read multiple */\n-#define CONFIG1_DMA_ENABLE\t (0x00000010)\t/* Turn on DMA */\n-#define CONFIG1_POWERDOWN\t (0x00000020)\t/* Turn off clocks */\n-#define CONFIG1_SET_LOOPMODE(x) ((x)*0x080)\t/* Clock&loop mode; values: */\n-#define LOOPMODE_NORMAL\t (0)\t\t/* Normal - no loop */\n-#define LOOPMODE_TIME\t (1)\n-#define LOOPMODE_DIAG\t (2)\n-#define LOOPMODE_LINE\t (3)\n-#define CONFIG1_MASK_LOOPMODE (0x00000180)\n-#define CONFIG1_SET_LEDMODE(x) ((x)*0x0200)\t/* Mode of LED; values: */\n-#define LEDMODE_NOT_SOOL\t (0)\t\t/* !SOOL */\n-#define\t LEDMODE_OFF\t\t (1)\t\t/* 0 */\n-#define\t LEDMODE_ON\t\t (2)\t\t/* 1 */\n-#define\t LEDMODE_NOT_LOCD\t (3)\t\t/* !LOCD */\n-#define\t LEDMORE_GPIN\t (4)\t\t/* GPIN */\n-#define LEDMODE_NOT_GPIN\t (7)\t\t/* !GPIN */\n-#define CONFIG1_MASK_LEDMODE\t (0x00000E00)\n-#define CONFIG1_GPOUT1\t (0x00001000)\t/* Toggle for reset */\n-#define CONFIG1_GPOUT2\t (0x00002000)\t/* Loopback PHY */\n-#define CONFIG1_GPOUT3\t (0x00004000)\t/* Loopback lanai */\n-\tConfig2_Reg\t\t= 0x30,\t/* Config word 2; bits: */\n-#define CONFIG2_HOWMANY\t (0x00000001)\t/* >512 VCIs? */\n-#define CONFIG2_PTI7_MODE\t (0x00000002)\t/* Make PTI=7 RM, not OAM */\n-#define CONFIG2_VPI_CHK_DIS\t (0x00000004)\t/* Ignore RX VPI value */\n-#define CONFIG2_HEC_DROP\t (0x00000008)\t/* Drop cells w/ HEC errors */\n-#define CONFIG2_VCI0_NORMAL\t (0x00000010)\t/* Treat VCI=0 normally */\n-#define CONFIG2_CBR_ENABLE\t (0x00000020)\t/* Deal with CBR traffic */\n-#define CONFIG2_TRASH_ALL\t (0x00000040)\t/* Trashing incoming cells */\n-#define CONFIG2_TX_DISABLE\t (0x00000080)\t/* Trashing outgoing cells */\n-#define CONFIG2_SET_TRASH\t (0x00000100)\t/* Turn trashing on */\n-\tStatistics_Reg\t\t= 0x34,\t/* Statistics; bits: */\n-#define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF)\t/* FIFO overflowed */\n-#define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF)\t/* HEC was bad */\n-#define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF)\t/* VCI not open */\n-#define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF)\t/* VCC buffer full */\n-\tServiceStuff_Reg\t= 0x38,\t/* Service stuff; bits: */\n-#define SSTUFF_SET_SIZE(x) ((x)*0x20000000)\t/* size of service buffer */\n-#define SSTUFF_SET_ADDR(x)\t ((x)>>8)\t/* set address of buffer */\n-\tServWrite_Reg\t\t= 0x3C,\t/* ServWrite Pointer */\n-\tServRead_Reg\t\t= 0x40,\t/* ServRead Pointer */\n-\tTxDepth_Reg\t\t= 0x44,\t/* FIFO Transmit Depth */\n-\tButt_Reg\t\t= 0x48,\t/* Butt register */\n-\tCBR_ICG_Reg\t\t= 0x50,\n-\tCBR_PTR_Reg\t\t= 0x54,\n-\tPingCount_Reg\t\t= 0x58,\t/* Ping count */\n-\tDMA_Addr_Reg\t\t= 0x5C\t/* DMA address */\n-};\n-\n-static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,\n-\tenum lanai_register reg)\n-{\n-\treturn lanai->base + reg;\n-}\n-\n-static inline u32 reg_read(const struct lanai_dev *lanai,\n-\tenum lanai_register reg)\n-{\n-\tu32 t;\n-\tt = readl(reg_addr(lanai, reg));\n-\tRWDEBUG(\"R [0x%08X] 0x%02X = 0x%08X\\n\", (unsigned int) lanai->base,\n-\t (int) reg, t);\n-\treturn t;\n-}\n-\n-static inline void reg_write(const struct lanai_dev *lanai, u32 val,\n-\tenum lanai_register reg)\n-{\n-\tRWDEBUG(\"W [0x%08X] 0x%02X < 0x%08X\\n\", (unsigned int) lanai->base,\n-\t (int) reg, val);\n-\twritel(val, reg_addr(lanai, reg));\n-}\n-\n-static inline void conf1_write(const struct lanai_dev *lanai)\n-{\n-\treg_write(lanai, lanai->conf1, Config1_Reg);\n-}\n-\n-static inline void conf2_write(const struct lanai_dev *lanai)\n-{\n-\treg_write(lanai, lanai->conf2, Config2_Reg);\n-}\n-\n-/* Same as conf2_write(), but defers I/O if we're powered down */\n-static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)\n-{\n-#ifdef USE_POWERDOWN\n-\tif (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))\n-\t\treturn;\n-#endif /* USE_POWERDOWN */\n-\tconf2_write(lanai);\n-}\n-\n-static inline void reset_board(const struct lanai_dev *lanai)\n-{\n-\tDPRINTK(\"about to reset board\\n\");\n-\treg_write(lanai, 0, Reset_Reg);\n-\t/*\n-\t * If we don't delay a little while here then we can end up\n-\t * leaving the card in a VERY weird state and lock up the\n-\t * PCI bus. This isn't documented anywhere but I've convinced\n-\t * myself after a lot of painful experimentation\n-\t */\n-\tudelay(5);\n-}\n-\n-/* -------------------- CARD SRAM UTILITIES: */\n-\n-/* The SRAM is mapped into normal PCI memory space - the only catch is\n- * that it is only 16-bits wide but must be accessed as 32-bit. The\n- * 16 high bits will be zero. We don't hide this, since they get\n- * programmed mostly like discrete registers anyway\n- */\n-#define SRAM_START (0x20000)\n-#define SRAM_BYTES (0x20000)\t/* Again, half don't really exist */\n-\n-static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)\n-{\n-\treturn lanai->base + SRAM_START + offset;\n-}\n-\n-static inline u32 sram_read(const struct lanai_dev *lanai, int offset)\n-{\n-\treturn readl(sram_addr(lanai, offset));\n-}\n-\n-static inline void sram_write(const struct lanai_dev *lanai,\n-\tu32 val, int offset)\n-{\n-\twritel(val, sram_addr(lanai, offset));\n-}\n-\n-static int sram_test_word(const struct lanai_dev *lanai, int offset,\n-\t\t\t u32 pattern)\n-{\n-\tu32 readback;\n-\tsram_write(lanai, pattern, offset);\n-\treadback = sram_read(lanai, offset);\n-\tif (likely(readback == pattern))\n-\t\treturn 0;\n-\tprintk(KERN_ERR DEV_LABEL\n-\t \"(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\\n\",\n-\t lanai->number, offset,\n-\t (unsigned int) pattern, (unsigned int) readback);\n-\treturn -EIO;\n-}\n-\n-static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern)\n-{\n-\tint offset, result = 0;\n-\tfor (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)\n-\t\tresult = sram_test_word(lanai, offset, pattern);\n-\treturn result;\n-}\n-\n-static int sram_test_and_clear(const struct lanai_dev *lanai)\n-{\n-#ifdef FULL_MEMORY_TEST\n-\tint result;\n-\tDPRINTK(\"testing SRAM\\n\");\n-\tif ((result = sram_test_pass(lanai, 0x5555)) != 0)\n-\t\treturn result;\n-\tif ((result = sram_test_pass(lanai, 0xAAAA)) != 0)\n-\t\treturn result;\n-#endif\n-\tDPRINTK(\"clearing SRAM\\n\");\n-\treturn sram_test_pass(lanai, 0x0000);\n-}\n-\n-/* -------------------- CARD-BASED VCC TABLE UTILITIES: */\n-\n-/* vcc table */\n-enum lanai_vcc_offset {\n-\tvcc_rxaddr1\t\t= 0x00,\t/* Location1, plus bits: */\n-#define RXADDR1_SET_SIZE(x) ((x)*0x0000100)\t/* size of RX buffer */\n-#define RXADDR1_SET_RMMODE(x) ((x)*0x00800)\t/* RM cell action; values: */\n-#define RMMODE_TRASH\t (0)\t\t/* discard */\n-#define RMMODE_PRESERVE\t (1)\t\t/* input as AAL0 */\n-#define RMMODE_PIPE\t\t (2)\t\t/* pipe to coscheduler */\n-#define RMMODE_PIPEALL\t (3)\t\t/* pipe non-RM too */\n-#define RXADDR1_OAM_PRESERVE\t (0x00002000)\t/* Input OAM cells as AAL0 */\n-#define RXADDR1_SET_MODE(x) ((x)*0x0004000)\t/* Reassembly mode */\n-#define RXMODE_TRASH\t (0)\t\t/* discard */\n-#define RXMODE_AAL0\t\t (1)\t\t/* non-AAL5 mode */\n-#define RXMODE_AAL5\t\t (2)\t\t/* AAL5, intr. each PDU */\n-#define RXMODE_AAL5_STREAM\t (3)\t\t/* AAL5 w/o per-PDU intr */\n-\tvcc_rxaddr2\t\t= 0x04,\t/* Location2 */\n-\tvcc_rxcrc1\t\t= 0x08,\t/* RX CRC claculation space */\n-\tvcc_rxcrc2\t\t= 0x0C,\n-\tvcc_rxwriteptr\t\t= 0x10, /* RX writeptr, plus bits: */\n-#define RXWRITEPTR_LASTEFCI\t (0x00002000)\t/* Last PDU had EFCI bit */\n-#define RXWRITEPTR_DROPPING\t (0x00004000)\t/* Had error, dropping */\n-#define RXWRITEPTR_TRASHING\t (0x00008000)\t/* Trashing */\n-\tvcc_rxbufstart\t\t= 0x14,\t/* RX bufstart, plus bits: */\n-#define RXBUFSTART_CLP\t (0x00004000)\n-#define RXBUFSTART_CI\t\t (0x00008000)\n-\tvcc_rxreadptr\t\t= 0x18,\t/* RX readptr */\n-\tvcc_txicg\t\t= 0x1C, /* TX ICG */\n-\tvcc_txaddr1\t\t= 0x20,\t/* Location1, plus bits: */\n-#define TXADDR1_SET_SIZE(x) ((x)*0x0000100)\t/* size of TX buffer */\n-#define TXADDR1_ABR\t\t (0x00008000)\t/* use ABR (doesn't work) */\n-\tvcc_txaddr2\t\t= 0x24,\t/* Location2 */\n-\tvcc_txcrc1\t\t= 0x28,\t/* TX CRC claculation space */\n-\tvcc_txcrc2\t\t= 0x2C,\n-\tvcc_txreadptr\t\t= 0x30, /* TX Readptr, plus bits: */\n-#define TXREADPTR_GET_PTR(x) ((x)&0x01FFF)\n-#define TXREADPTR_MASK_DELTA\t(0x0000E000)\t/* ? */\n-\tvcc_txendptr\t\t= 0x34, /* TX Endptr, plus bits: */\n-#define TXENDPTR_CLP\t\t(0x00002000)\n-#define TXENDPTR_MASK_PDUMODE\t(0x0000C000)\t/* PDU mode; values: */\n-#define PDUMODE_AAL0\t (0*0x04000)\n-#define PDUMODE_AAL5\t (2*0x04000)\n-#define PDUMODE_AAL5STREAM\t (3*0x04000)\n-\tvcc_txwriteptr\t\t= 0x38,\t/* TX Writeptr */\n-#define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)\n-\tvcc_txcbr_next\t\t= 0x3C\t/* # of next CBR VCI in ring */\n-#define TXCBR_NEXT_BOZO\t(0x00008000)\t/* \"bozo bit\" */\n-};\n-\n-#define CARDVCC_SIZE\t(0x40)\n-\n-static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,\n-\tvci_t vci)\n-{\n-\treturn sram_addr(lanai, vci * CARDVCC_SIZE);\n-}\n-\n-static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,\n-\tenum lanai_vcc_offset offset)\n-{\n-\tu32 val;\n-\tAPRINTK(lvcc->vbase != NULL, \"cardvcc_read: unbound vcc!\\n\");\n-\tval= readl(lvcc->vbase + offset);\n-\tRWDEBUG(\"VR vci=%04d 0x%02X = 0x%08X\\n\",\n-\t lvcc->vci, (int) offset, val);\n-\treturn val;\n-}\n-\n-static inline void cardvcc_write(const struct lanai_vcc *lvcc,\n-\tu32 val, enum lanai_vcc_offset offset)\n-{\n-\tAPRINTK(lvcc->vbase != NULL, \"cardvcc_write: unbound vcc!\\n\");\n-\tAPRINTK((val & ~0xFFFF) == 0,\n-\t \"cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\\n\",\n-\t (unsigned int) val, lvcc->vci, (unsigned int) offset);\n-\tRWDEBUG(\"VW vci=%04d 0x%02X > 0x%08X\\n\",\n-\t lvcc->vci, (unsigned int) offset, (unsigned int) val);\n-\twritel(val, lvcc->vbase + offset);\n-}\n-\n-/* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */\n-\n-/* How many bytes will an AAL5 PDU take to transmit - remember that:\n- * o we need to add 8 bytes for length, CPI, UU, and CRC\n- * o we need to round up to 48 bytes for cells\n- */\n-static inline int aal5_size(int size)\n-{\n-\tint cells = (size + 8 + 47) / 48;\n-\treturn cells * 48;\n-}\n-\n-/* -------------------- FREE AN ATM SKB: */\n-\n-static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)\n-{\n-\tif (atmvcc->pop != NULL)\n-\t\tatmvcc->pop(atmvcc, skb);\n-\telse\n-\t\tdev_kfree_skb_any(skb);\n-}\n-\n-/* -------------------- TURN VCCS ON AND OFF: */\n-\n-static void host_vcc_start_rx(const struct lanai_vcc *lvcc)\n-{\n-\tu32 addr1;\n-\tif (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {\n-\t\tdma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;\n-\t\tcardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);\n-\t\tcardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);\n-\t\tcardvcc_write(lvcc, 0, vcc_rxwriteptr);\n-\t\tcardvcc_write(lvcc, 0, vcc_rxbufstart);\n-\t\tcardvcc_write(lvcc, 0, vcc_rxreadptr);\n-\t\tcardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);\n-\t\taddr1 = ((dmaaddr >> 8) & 0xFF) |\n-\t\t RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|\n-\t\t RXADDR1_SET_RMMODE(RMMODE_TRASH) |\t/* ??? */\n-\t\t /* RXADDR1_OAM_PRESERVE |\t--- no OAM support yet */\n-\t\t RXADDR1_SET_MODE(RXMODE_AAL5);\n-\t} else\n-\t\taddr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */\n-\t\t RXADDR1_OAM_PRESERVE |\t\t /* ??? */\n-\t\t RXADDR1_SET_MODE(RXMODE_AAL0);\n-\t/* This one must be last! */\n-\tcardvcc_write(lvcc, addr1, vcc_rxaddr1);\n-}\n-\n-static void host_vcc_start_tx(const struct lanai_vcc *lvcc)\n-{\n-\tdma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;\n-\tcardvcc_write(lvcc, 0, vcc_txicg);\n-\tcardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);\n-\tcardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);\n-\tcardvcc_write(lvcc, 0, vcc_txreadptr);\n-\tcardvcc_write(lvcc, 0, vcc_txendptr);\n-\tcardvcc_write(lvcc, 0, vcc_txwriteptr);\n-\tcardvcc_write(lvcc,\n-\t\t(lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?\n-\t\tTXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);\n-\tcardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);\n-\tcardvcc_write(lvcc,\n-\t ((dmaaddr >> 8) & 0xFF) |\n-\t TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),\n-\t vcc_txaddr1);\n-}\n-\n-/* Shutdown receiving on card */\n-static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)\n-{\n-\tif (lvcc->vbase == NULL)\t/* We were never bound to a VCI */\n-\t\treturn;\n-\t/* 15.1.1 - set to trashing, wait one cell time (15us) */\n-\tcardvcc_write(lvcc,\n-\t RXADDR1_SET_RMMODE(RMMODE_TRASH) |\n-\t RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);\n-\tudelay(15);\n-\t/* 15.1.2 - clear rest of entries */\n-\tcardvcc_write(lvcc, 0, vcc_rxaddr2);\n-\tcardvcc_write(lvcc, 0, vcc_rxcrc1);\n-\tcardvcc_write(lvcc, 0, vcc_rxcrc2);\n-\tcardvcc_write(lvcc, 0, vcc_rxwriteptr);\n-\tcardvcc_write(lvcc, 0, vcc_rxbufstart);\n-\tcardvcc_write(lvcc, 0, vcc_rxreadptr);\n-}\n-\n-/* Shutdown transmitting on card.\n- * Unfortunately the lanai needs us to wait until all the data\n- * drains out of the buffer before we can dealloc it, so this\n- * can take a while -- up to 370ms for a full 128KB buffer\n- * assuming everone else is quiet. In theory the time is\n- * boundless if there's a CBR VCC holding things up.\n- */\n-static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc)\n-{\n-\tstruct sk_buff *skb;\n-\tunsigned long flags, timeout;\n-\tint read, write, lastread = -1;\n-\n-\tif (lvcc->vbase == NULL)\t/* We were never bound to a VCI */\n-\t\treturn;\n-\t/* 15.2.1 - wait for queue to drain */\n-\twhile ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)\n-\t\tlanai_free_skb(lvcc->tx.atmvcc, skb);\n-\tread_lock_irqsave(&vcc_sklist_lock, flags);\n-\t__clear_bit(lvcc->vci, lanai->backlog_vccs);\n-\tread_unlock_irqrestore(&vcc_sklist_lock, flags);\n-\t/*\n-\t * We need to wait for the VCC to drain but don't wait forever. We\n-\t * give each 1K of buffer size 1/128th of a second to clear out.\n-\t * TODO: maybe disable CBR if we're about to timeout?\n-\t */\n-\ttimeout = jiffies +\n-\t (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);\n-\twrite = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));\n-\tfor (;;) {\n-\t\tread = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));\n-\t\tif (read == write &&\t /* Is TX buffer empty? */\n-\t\t (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||\n-\t\t (cardvcc_read(lvcc, vcc_txcbr_next) &\n-\t\t TXCBR_NEXT_BOZO) == 0))\n-\t\t\tbreak;\n-\t\tif (read != lastread) {\t /* Has there been any progress? */\n-\t\t\tlastread = read;\n-\t\t\ttimeout += HZ / 10;\n-\t\t}\n-\t\tif (unlikely(time_after(jiffies, timeout))) {\n-\t\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): Timed out on \"\n-\t\t\t \"backlog closing vci %d\\n\",\n-\t\t\t lvcc->tx.atmvcc->dev->number, lvcc->vci);\n-\t\t\tDPRINTK(\"read, write = %d, %d\\n\", read, write);\n-\t\t\tbreak;\n-\t\t}\n-\t\tmsleep(40);\n-\t}\n-\t/* 15.2.2 - clear out all tx registers */\n-\tcardvcc_write(lvcc, 0, vcc_txreadptr);\n-\tcardvcc_write(lvcc, 0, vcc_txwriteptr);\n-\tcardvcc_write(lvcc, 0, vcc_txendptr);\n-\tcardvcc_write(lvcc, 0, vcc_txcrc1);\n-\tcardvcc_write(lvcc, 0, vcc_txcrc2);\n-\tcardvcc_write(lvcc, 0, vcc_txaddr2);\n-\tcardvcc_write(lvcc, 0, vcc_txaddr1);\n-}\n-\n-/* -------------------- MANAGING AAL0 RX BUFFER: */\n-\n-static inline int aal0_buffer_allocate(struct lanai_dev *lanai)\n-{\n-\tDPRINTK(\"aal0_buffer_allocate: allocating AAL0 RX buffer\\n\");\n-\tlanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,\n-\t\t\t lanai->pci);\n-\treturn (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;\n-}\n-\n-static inline void aal0_buffer_free(struct lanai_dev *lanai)\n-{\n-\tDPRINTK(\"aal0_buffer_allocate: freeing AAL0 RX buffer\\n\");\n-\tlanai_buf_deallocate(&lanai->aal0buf, lanai->pci);\n-}\n-\n-/* -------------------- EEPROM UTILITIES: */\n-\n-/* Offsets of data in the EEPROM */\n-#define EEPROM_COPYRIGHT\t(0)\n-#define EEPROM_COPYRIGHT_LEN\t(44)\n-#define EEPROM_CHECKSUM\t\t(62)\n-#define EEPROM_CHECKSUM_REV\t(63)\n-#define EEPROM_MAC\t\t(64)\n-#define EEPROM_MAC_REV\t\t(70)\n-#define EEPROM_SERIAL\t\t(112)\n-#define EEPROM_SERIAL_REV\t(116)\n-#define EEPROM_MAGIC\t\t(120)\n-#define EEPROM_MAGIC_REV\t(124)\n-\n-#define EEPROM_MAGIC_VALUE\t(0x5AB478D2)\n-\n-#ifndef READ_EEPROM\n-\n-/* Stub functions to use if EEPROM reading is disabled */\n-static int eeprom_read(struct lanai_dev *lanai)\n-{\n-\tprintk(KERN_INFO DEV_LABEL \"(itf %d): *NOT* reading EEPROM\\n\",\n-\t lanai->number);\n-\tmemset(&lanai->eeprom[EEPROM_MAC], 0, 6);\n-\treturn 0;\n-}\n-\n-static int eeprom_validate(struct lanai_dev *lanai)\n-{\n-\tlanai->serialno = 0;\n-\tlanai->magicno = EEPROM_MAGIC_VALUE;\n-\treturn 0;\n-}\n-\n-#else /* READ_EEPROM */\n-\n-static int eeprom_read(struct lanai_dev *lanai)\n-{\n-\tint i, address;\n-\tu8 data;\n-\tu32 tmp;\n-#define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \\\n-\t\t\t } while (0)\n-#define clock_h()\t set_config1(lanai->conf1 | CONFIG1_PROMCLK)\n-#define clock_l()\t set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)\n-#define data_h()\t set_config1(lanai->conf1 | CONFIG1_PROMDATA)\n-#define data_l()\t set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)\n-#define pre_read()\t do { data_h(); clock_h(); udelay(5); } while (0)\n-#define read_pin()\t (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)\n-#define send_stop()\t do { data_l(); udelay(5); clock_h(); udelay(5); \\\n-\t\t\t data_h(); udelay(5); } while (0)\n-\t/* start with both clock and data high */\n-\tdata_h(); clock_h(); udelay(5);\n-\tfor (address = 0; address < LANAI_EEPROM_SIZE; address++) {\n-\t\tdata = (address << 1) | 1;\t/* Command=read + address */\n-\t\t/* send start bit */\n-\t\tdata_l(); udelay(5);\n-\t\tclock_l(); udelay(5);\n-\t\tfor (i = 128; i != 0; i >>= 1) { /* write command out */\n-\t\t\ttmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |\n-\t\t\t ((data & i) ? CONFIG1_PROMDATA : 0);\n-\t\t\tif (lanai->conf1 != tmp) {\n-\t\t\t\tset_config1(tmp);\n-\t\t\t\tudelay(5);\t/* Let new data settle */\n-\t\t\t}\n-\t\t\tclock_h(); udelay(5); clock_l(); udelay(5);\n-\t\t}\n-\t\t/* look for ack */\n-\t\tdata_h(); clock_h(); udelay(5);\n-\t\tif (read_pin() != 0)\n-\t\t\tgoto error;\t/* No ack seen */\n-\t\tclock_l(); udelay(5);\n-\t\t/* read back result */\n-\t\tfor (data = 0, i = 7; i >= 0; i--) {\n-\t\t\tdata_h(); clock_h(); udelay(5);\n-\t\t\tdata = (data << 1) | !!read_pin();\n-\t\t\tclock_l(); udelay(5);\n-\t\t}\n-\t\t/* look again for ack */\n-\t\tdata_h(); clock_h(); udelay(5);\n-\t\tif (read_pin() == 0)\n-\t\t\tgoto error;\t/* Spurious ack */\n-\t\tclock_l(); udelay(5);\n-\t\tsend_stop();\n-\t\tlanai->eeprom[address] = data;\n-\t\tDPRINTK(\"EEPROM 0x%04X %02X\\n\",\n-\t\t (unsigned int) address, (unsigned int) data);\n-\t}\n-\treturn 0;\n- error:\n-\tclock_l(); udelay(5);\t\t/* finish read */\n-\tsend_stop();\n-\tprintk(KERN_ERR DEV_LABEL \"(itf %d): error reading EEPROM byte %d\\n\",\n-\t lanai->number, address);\n-\treturn -EIO;\n-#undef set_config1\n-#undef clock_h\n-#undef clock_l\n-#undef data_h\n-#undef data_l\n-#undef pre_read\n-#undef read_pin\n-#undef send_stop\n-}\n-\n-/* read a big-endian 4-byte value out of eeprom */\n-static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)\n-{\n-\treturn be32_to_cpup((const u32 *) &lanai->eeprom[address]);\n-}\n-\n-/* Checksum/validate EEPROM contents */\n-static int eeprom_validate(struct lanai_dev *lanai)\n-{\n-\tint i, s;\n-\tu32 v;\n-\tconst u8 *e = lanai->eeprom;\n-#ifdef DEBUG\n-\t/* First, see if we can get an ASCIIZ string out of the copyright */\n-\tfor (i = EEPROM_COPYRIGHT;\n-\t i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)\n-\t\tif (e[i] < 0x20 || e[i] > 0x7E)\n-\t\t\tbreak;\n-\tif ( i != EEPROM_COPYRIGHT &&\n-\t i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\\0')\n-\t\tDPRINTK(\"eeprom: copyright = \\\"%s\\\"\\n\",\n-\t\t (char *) &e[EEPROM_COPYRIGHT]);\n-\telse\n-\t\tDPRINTK(\"eeprom: copyright not found\\n\");\n-#endif\n-\t/* Validate checksum */\n-\tfor (i = s = 0; i < EEPROM_CHECKSUM; i++)\n-\t\ts += e[i];\n-\ts &= 0xFF;\n-\tif (s != e[EEPROM_CHECKSUM]) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): EEPROM checksum bad \"\n-\t\t \"(wanted 0x%02X, got 0x%02X)\\n\", lanai->number,\n-\t\t (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);\n-\t\treturn -EIO;\n-\t}\n-\ts ^= 0xFF;\n-\tif (s != e[EEPROM_CHECKSUM_REV]) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): EEPROM inverse checksum \"\n-\t\t \"bad (wanted 0x%02X, got 0x%02X)\\n\", lanai->number,\n-\t\t (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);\n-\t\treturn -EIO;\n-\t}\n-\t/* Verify MAC address */\n-\tfor (i = 0; i < 6; i++)\n-\t\tif ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {\n-\t\t\tprintk(KERN_ERR DEV_LABEL\n-\t\t\t \"(itf %d) : EEPROM MAC addresses don't match \"\n-\t\t\t \"(0x%02X, inverse 0x%02X)\\n\", lanai->number,\n-\t\t\t (unsigned int) e[EEPROM_MAC + i],\n-\t\t\t (unsigned int) e[EEPROM_MAC_REV + i]);\n-\t\t\treturn -EIO;\n-\t\t}\n-\tDPRINTK(\"eeprom: MAC address = %pM\\n\", &e[EEPROM_MAC]);\n-\t/* Verify serial number */\n-\tlanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);\n-\tv = eeprom_be4(lanai, EEPROM_SERIAL_REV);\n-\tif ((lanai->serialno ^ v) != 0xFFFFFFFF) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): EEPROM serial numbers \"\n-\t\t \"don't match (0x%08X, inverse 0x%08X)\\n\", lanai->number,\n-\t\t (unsigned int) lanai->serialno, (unsigned int) v);\n-\t\treturn -EIO;\n-\t}\n-\tDPRINTK(\"eeprom: Serial number = %d\\n\", (unsigned int) lanai->serialno);\n-\t/* Verify magic number */\n-\tlanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);\n-\tv = eeprom_be4(lanai, EEPROM_MAGIC_REV);\n-\tif ((lanai->magicno ^ v) != 0xFFFFFFFF) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): EEPROM magic numbers \"\n-\t\t \"don't match (0x%08X, inverse 0x%08X)\\n\", lanai->number,\n-\t\t lanai->magicno, v);\n-\t\treturn -EIO;\n-\t}\n-\tDPRINTK(\"eeprom: Magic number = 0x%08X\\n\", lanai->magicno);\n-\tif (lanai->magicno != EEPROM_MAGIC_VALUE)\n-\t\tprintk(KERN_WARNING DEV_LABEL \"(itf %d): warning - EEPROM \"\n-\t\t \"magic not what expected (got 0x%08X, not 0x%08X)\\n\",\n-\t\t lanai->number, (unsigned int) lanai->magicno,\n-\t\t (unsigned int) EEPROM_MAGIC_VALUE);\n-\treturn 0;\n-}\n-\n-#endif /* READ_EEPROM */\n-\n-static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)\n-{\n-\treturn &lanai->eeprom[EEPROM_MAC];\n-}\n-\n-/* -------------------- INTERRUPT HANDLING UTILITIES: */\n-\n-/* Interrupt types */\n-#define INT_STATS\t(0x00000002)\t/* Statistics counter overflow */\n-#define INT_SOOL\t(0x00000004)\t/* SOOL changed state */\n-#define INT_LOCD\t(0x00000008)\t/* LOCD changed state */\n-#define INT_LED\t\t(0x00000010)\t/* LED (HAPPI) changed state */\n-#define INT_GPIN\t(0x00000020)\t/* GPIN changed state */\n-#define INT_PING\t(0x00000040)\t/* PING_COUNT fulfilled */\n-#define INT_WAKE\t(0x00000080)\t/* Lanai wants bus */\n-#define INT_CBR0\t(0x00000100)\t/* CBR sched hit VCI 0 */\n-#define INT_LOCK\t(0x00000200)\t/* Service list overflow */\n-#define INT_MISMATCH\t(0x00000400)\t/* TX magic list mismatch */\n-#define INT_AAL0_STR\t(0x00000800)\t/* Non-AAL5 buffer half filled */\n-#define INT_AAL0\t(0x00001000)\t/* Non-AAL5 data available */\n-#define INT_SERVICE\t(0x00002000)\t/* Service list entries available */\n-#define INT_TABORTSENT\t(0x00004000)\t/* Target abort sent by lanai */\n-#define INT_TABORTBM\t(0x00008000)\t/* Abort rcv'd as bus master */\n-#define INT_TIMEOUTBM\t(0x00010000)\t/* No response to bus master */\n-#define INT_PCIPARITY\t(0x00020000)\t/* Parity error on PCI */\n-\n-/* Sets of the above */\n-#define INT_ALL\t\t(0x0003FFFE)\t/* All interrupts */\n-#define INT_STATUS\t(0x0000003C)\t/* Some status pin changed */\n-#define INT_DMASHUT\t(0x00038000)\t/* DMA engine got shut down */\n-#define INT_SEGSHUT\t(0x00000700)\t/* Segmentation got shut down */\n-\n-static inline u32 intr_pending(const struct lanai_dev *lanai)\n-{\n-\treturn reg_read(lanai, IntStatusMasked_Reg);\n-}\n-\n-static inline void intr_enable(const struct lanai_dev *lanai, u32 i)\n-{\n-\treg_write(lanai, i, IntControlEna_Reg);\n-}\n-\n-static inline void intr_disable(const struct lanai_dev *lanai, u32 i)\n-{\n-\treg_write(lanai, i, IntControlDis_Reg);\n-}\n-\n-/* -------------------- CARD/PCI STATUS: */\n-\n-static void status_message(int itf, const char *name, int status)\n-{\n-\tstatic const char *onoff[2] = { \"off to on\", \"on to off\" };\n-\tprintk(KERN_INFO DEV_LABEL \"(itf %d): %s changed from %s\\n\",\n-\t itf, name, onoff[!status]);\n-}\n-\n-static void lanai_check_status(struct lanai_dev *lanai)\n-{\n-\tu32 new = reg_read(lanai, Status_Reg);\n-\tu32 changes = new ^ lanai->status;\n-\tlanai->status = new;\n-#define e(flag, name) \\\n-\t\tif (changes & flag) \\\n-\t\t\tstatus_message(lanai->number, name, new & flag)\n-\te(STATUS_SOOL, \"SOOL\");\n-\te(STATUS_LOCD, \"LOCD\");\n-\te(STATUS_LED, \"LED\");\n-\te(STATUS_GPIN, \"GPIN\");\n-#undef e\n-}\n-\n-static void pcistatus_got(int itf, const char *name)\n-{\n-\tprintk(KERN_INFO DEV_LABEL \"(itf %d): PCI got %s error\\n\", itf, name);\n-}\n-\n-static void pcistatus_check(struct lanai_dev *lanai, int clearonly)\n-{\n-\tu16 s;\n-\tint result;\n-\tresult = pci_read_config_word(lanai->pci, PCI_STATUS, &s);\n-\tif (result != PCIBIOS_SUCCESSFUL) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't read PCI_STATUS: \"\n-\t\t \"%d\\n\", lanai->number, result);\n-\t\treturn;\n-\t}\n-\ts &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |\n-\t PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |\n-\t PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;\n-\tif (s == 0)\n-\t\treturn;\n-\tresult = pci_write_config_word(lanai->pci, PCI_STATUS, s);\n-\tif (result != PCIBIOS_SUCCESSFUL)\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't write PCI_STATUS: \"\n-\t\t \"%d\\n\", lanai->number, result);\n-\tif (clearonly)\n-\t\treturn;\n-#define e(flag, name, stat) \\\n-\t\tif (s & flag) { \\\n-\t\t\tpcistatus_got(lanai->number, name); \\\n-\t\t\t++lanai->stats.pcierr_##stat; \\\n-\t\t}\n-\te(PCI_STATUS_DETECTED_PARITY, \"parity\", parity_detect);\n-\te(PCI_STATUS_SIG_SYSTEM_ERROR, \"signalled system\", serr_set);\n-\te(PCI_STATUS_REC_MASTER_ABORT, \"master\", master_abort);\n-\te(PCI_STATUS_REC_TARGET_ABORT, \"master target\", m_target_abort);\n-\te(PCI_STATUS_SIG_TARGET_ABORT, \"slave\", s_target_abort);\n-\te(PCI_STATUS_PARITY, \"master parity\", master_parity);\n-#undef e\n-}\n-\n-/* -------------------- VCC TX BUFFER UTILITIES: */\n-\n-/* space left in tx buffer in bytes */\n-static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)\n-{\n-\tint r;\n-\tr = endptr * 16;\n-\tr -= ((unsigned long) lvcc->tx.buf.ptr) -\n-\t ((unsigned long) lvcc->tx.buf.start);\n-\tr -= 16;\t/* Leave \"bubble\" - if start==end it looks empty */\n-\tif (r < 0)\n-\t\tr += lanai_buf_size(&lvcc->tx.buf);\n-\treturn r;\n-}\n-\n-/* test if VCC is currently backlogged */\n-static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)\n-{\n-\treturn !skb_queue_empty(&lvcc->tx.backlog);\n-}\n-\n-/* Bit fields in the segmentation buffer descriptor */\n-#define DESCRIPTOR_MAGIC\t(0xD0000000)\n-#define DESCRIPTOR_AAL5\t\t(0x00008000)\n-#define DESCRIPTOR_AAL5_STREAM\t(0x00004000)\n-#define DESCRIPTOR_CLP\t\t(0x00002000)\n-\n-/* Add 32-bit descriptor with its padding */\n-static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,\n-\tu32 flags, int len)\n-{\n-\tint pos;\n-\tAPRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,\n-\t \"vcc_tx_add_aal5_descriptor: bad ptr=%p\\n\", lvcc->tx.buf.ptr);\n-\tlvcc->tx.buf.ptr += 4;\t/* Hope the values REALLY don't matter */\n-\tpos = ((unsigned char *) lvcc->tx.buf.ptr) -\n-\t (unsigned char *) lvcc->tx.buf.start;\n-\tAPRINTK((pos & ~0x0001FFF0) == 0,\n-\t \"vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, \"\n-\t \"start,ptr,end=%p,%p,%p\\n\", pos, lvcc->vci,\n-\t lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);\n-\tpos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);\n-\tAPRINTK((pos & ~0x0001FFF0) == 0,\n-\t \"vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, \"\n-\t \"start,ptr,end=%p,%p,%p\\n\", pos, lvcc->vci,\n-\t lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);\n-\tlvcc->tx.buf.ptr[-1] =\n-\t cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |\n-\t ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?\n-\t DESCRIPTOR_CLP : 0) | flags | pos >> 4);\n-\tif (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)\n-\t\tlvcc->tx.buf.ptr = lvcc->tx.buf.start;\n-}\n-\n-/* Add 32-bit AAL5 trailer and leave room for its CRC */\n-static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,\n-\tint len, int cpi, int uu)\n-{\n-\tAPRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,\n-\t \"vcc_tx_add_aal5_trailer: bad ptr=%p\\n\", lvcc->tx.buf.ptr);\n-\tlvcc->tx.buf.ptr += 2;\n-\tlvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);\n-\tif (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)\n-\t\tlvcc->tx.buf.ptr = lvcc->tx.buf.start;\n-}\n-\n-static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,\n-\tconst unsigned char *src, int n)\n-{\n-\tunsigned char *e;\n-\tint m;\n-\te = ((unsigned char *) lvcc->tx.buf.ptr) + n;\n-\tm = e - (unsigned char *) lvcc->tx.buf.end;\n-\tif (m < 0)\n-\t\tm = 0;\n-\tmemcpy(lvcc->tx.buf.ptr, src, n - m);\n-\tif (m != 0) {\n-\t\tmemcpy(lvcc->tx.buf.start, src + n - m, m);\n-\t\te = ((unsigned char *) lvcc->tx.buf.start) + m;\n-\t}\n-\tlvcc->tx.buf.ptr = (u32 *) e;\n-}\n-\n-static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)\n-{\n-\tunsigned char *e;\n-\tint m;\n-\tif (n == 0)\n-\t\treturn;\n-\te = ((unsigned char *) lvcc->tx.buf.ptr) + n;\n-\tm = e - (unsigned char *) lvcc->tx.buf.end;\n-\tif (m < 0)\n-\t\tm = 0;\n-\tmemset(lvcc->tx.buf.ptr, 0, n - m);\n-\tif (m != 0) {\n-\t\tmemset(lvcc->tx.buf.start, 0, m);\n-\t\te = ((unsigned char *) lvcc->tx.buf.start) + m;\n-\t}\n-\tlvcc->tx.buf.ptr = (u32 *) e;\n-}\n-\n-/* Update \"butt\" register to specify new WritePtr */\n-static inline void lanai_endtx(struct lanai_dev *lanai,\n-\tconst struct lanai_vcc *lvcc)\n-{\n-\tint i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -\n-\t (unsigned char *) lvcc->tx.buf.start;\n-\tAPRINTK((ptr & ~0x0001FFF0) == 0,\n-\t \"lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\\n\",\n-\t ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,\n-\t lvcc->tx.buf.end);\n-\n-\t/*\n-\t * Since the \"butt register\" is a shared resounce on the card we\n-\t * serialize all accesses to it through this spinlock. This is\n-\t * mostly just paranoia since the register is rarely \"busy\" anyway\n-\t * but is needed for correctness.\n-\t */\n-\tspin_lock(&lanai->endtxlock);\n-\t/*\n-\t * We need to check if the \"butt busy\" bit is set before\n-\t * updating the butt register. In theory this should\n-\t * never happen because the ATM card is plenty fast at\n-\t * updating the register. Still, we should make sure\n-\t */\n-\tfor (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {\n-\t\tif (unlikely(i > 50)) {\n-\t\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): butt register \"\n-\t\t\t \"always busy!\\n\", lanai->number);\n-\t\t\tbreak;\n-\t\t}\n-\t\tudelay(5);\n-\t}\n-\t/*\n-\t * Before we tall the card to start work we need to be sure 100% of\n-\t * the info in the service buffer has been written before we tell\n-\t * the card about it\n-\t */\n-\twmb();\n-\treg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);\n-\tspin_unlock(&lanai->endtxlock);\n-}\n-\n-/*\n- * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's\n- * space available. \"pdusize\" is the number of bytes the PDU will take\n- */\n-static void lanai_send_one_aal5(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)\n-{\n-\tint pad;\n-\tAPRINTK(pdusize == aal5_size(skb->len),\n-\t \"lanai_send_one_aal5: wrong size packet (%d != %d)\\n\",\n-\t pdusize, aal5_size(skb->len));\n-\tvcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);\n-\tpad = pdusize - skb->len - 8;\n-\tAPRINTK(pad >= 0, \"pad is negative (%d)\\n\", pad);\n-\tAPRINTK(pad < 48, \"pad is too big (%d)\\n\", pad);\n-\tvcc_tx_memcpy(lvcc, skb->data, skb->len);\n-\tvcc_tx_memzero(lvcc, pad);\n-\tvcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);\n-\tlanai_endtx(lanai, lvcc);\n-\tlanai_free_skb(lvcc->tx.atmvcc, skb);\n-\tatomic_inc(&lvcc->tx.atmvcc->stats->tx);\n-}\n-\n-/* Try to fill the buffer - don't call unless there is backlog */\n-static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc, int endptr)\n-{\n-\tint n;\n-\tstruct sk_buff *skb;\n-\tint space = vcc_tx_space(lvcc, endptr);\n-\tAPRINTK(vcc_is_backlogged(lvcc),\n-\t \"vcc_tx_unqueue() called with empty backlog (vci=%d)\\n\",\n-\t lvcc->vci);\n-\twhile (space >= 64) {\n-\t\tskb = skb_dequeue(&lvcc->tx.backlog);\n-\t\tif (skb == NULL)\n-\t\t\tgoto no_backlog;\n-\t\tn = aal5_size(skb->len);\n-\t\tif (n + 16 > space) {\n-\t\t\t/* No room for this packet - put it back on queue */\n-\t\t\tskb_queue_head(&lvcc->tx.backlog, skb);\n-\t\t\treturn;\n-\t\t}\n-\t\tlanai_send_one_aal5(lanai, lvcc, skb, n);\n-\t\tspace -= n + 16;\n-\t}\n-\tif (!vcc_is_backlogged(lvcc)) {\n-\t no_backlog:\n-\t\t__clear_bit(lvcc->vci, lanai->backlog_vccs);\n-\t}\n-}\n-\n-/* Given an skb that we want to transmit either send it now or queue */\n-static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,\n-\tstruct sk_buff *skb)\n-{\n-\tint space, n;\n-\tif (vcc_is_backlogged(lvcc))\t\t/* Already backlogged */\n-\t\tgoto queue_it;\n-\tspace = vcc_tx_space(lvcc,\n-\t\t TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));\n-\tn = aal5_size(skb->len);\n-\tAPRINTK(n + 16 >= 64, \"vcc_tx_aal5: n too small (%d)\\n\", n);\n-\tif (space < n + 16) {\t\t\t/* No space for this PDU */\n-\t\t__set_bit(lvcc->vci, lanai->backlog_vccs);\n-\t queue_it:\n-\t\tskb_queue_tail(&lvcc->tx.backlog, skb);\n-\t\treturn;\n-\t}\n-\tlanai_send_one_aal5(lanai, lvcc, skb, n);\n-}\n-\n-static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc, int endptr)\n-{\n-\tprintk(KERN_INFO DEV_LABEL\n-\t \": vcc_tx_unqueue_aal0: not implemented\\n\");\n-}\n-\n-static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,\n-\tstruct sk_buff *skb)\n-{\n-\tprintk(KERN_INFO DEV_LABEL \": vcc_tx_aal0: not implemented\\n\");\n-\t/* Remember to increment lvcc->tx.atmvcc->stats->tx */\n-\tlanai_free_skb(lvcc->tx.atmvcc, skb);\n-}\n-\n-/* -------------------- VCC RX BUFFER UTILITIES: */\n-\n-/* unlike the _tx_ cousins, this doesn't update ptr */\n-static inline void vcc_rx_memcpy(unsigned char *dest,\n-\tconst struct lanai_vcc *lvcc, int n)\n-{\n-\tint m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -\n-\t ((const unsigned char *) (lvcc->rx.buf.end));\n-\tif (m < 0)\n-\t\tm = 0;\n-\tmemcpy(dest, lvcc->rx.buf.ptr, n - m);\n-\tmemcpy(dest + n - m, lvcc->rx.buf.start, m);\n-\t/* Make sure that these copies don't get reordered */\n-\tbarrier();\n-}\n-\n-/* Receive AAL5 data on a VCC with a particular endptr */\n-static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)\n-{\n-\tint size;\n-\tstruct sk_buff *skb;\n-\tconst u32 *x;\n-\tu32 *end = &lvcc->rx.buf.start[endptr * 4];\n-\tint n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);\n-\tif (n < 0)\n-\t\tn += lanai_buf_size(&lvcc->rx.buf);\n-\tAPRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),\n-\t \"vcc_rx_aal5: n out of range (%d/%zu)\\n\",\n-\t n, lanai_buf_size(&lvcc->rx.buf));\n-\t/* Recover the second-to-last word to get true pdu length */\n-\tif ((x = &end[-2]) < lvcc->rx.buf.start)\n-\t\tx = &lvcc->rx.buf.end[-2];\n-\t/*\n-\t * Before we actually read from the buffer, make sure the memory\n-\t * changes have arrived\n-\t */\n-\trmb();\n-\tsize = be32_to_cpup(x) & 0xffff;\n-\tif (unlikely(n != aal5_size(size))) {\n-\t\t/* Make sure size matches padding */\n-\t\tprintk(KERN_INFO DEV_LABEL \"(itf %d): Got bad AAL5 length \"\n-\t\t \"on vci=%d - size=%d n=%d\\n\",\n-\t\t lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);\n-\t\tlvcc->stats.x.aal5.rx_badlen++;\n-\t\tgoto out;\n-\t}\n-\tskb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);\n-\tif (unlikely(skb == NULL)) {\n-\t\tlvcc->stats.rx_nomem++;\n-\t\tgoto out;\n-\t}\n-\tskb_put(skb, size);\n-\tvcc_rx_memcpy(skb->data, lvcc, size);\n-\tATM_SKB(skb)->vcc = lvcc->rx.atmvcc;\n-\t__net_timestamp(skb);\n-\tlvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);\n-\tatomic_inc(&lvcc->rx.atmvcc->stats->rx);\n- out:\n-\tlvcc->rx.buf.ptr = end;\n-\tcardvcc_write(lvcc, endptr, vcc_rxreadptr);\n-}\n-\n-static void vcc_rx_aal0(struct lanai_dev *lanai)\n-{\n-\tprintk(KERN_INFO DEV_LABEL \": vcc_rx_aal0: not implemented\\n\");\n-\t/* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */\n-\t/* Remember to increment lvcc->rx.atmvcc->stats->rx */\n-}\n-\n-/* -------------------- MANAGING HOST-BASED VCC TABLE: */\n-\n-/* Decide whether to use vmalloc or get_zeroed_page for VCC table */\n-#if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE\n-#define VCCTABLE_GETFREEPAGE\n-#else\n-#include \n-#endif\n-\n-static int vcc_table_allocate(struct lanai_dev *lanai)\n-{\n-#ifdef VCCTABLE_GETFREEPAGE\n-\tAPRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,\n-\t \"vcc table > PAGE_SIZE!\");\n-\tlanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);\n-\treturn (lanai->vccs == NULL) ? -ENOMEM : 0;\n-#else\n-\tint bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);\n-\tlanai->vccs = vzalloc(bytes);\n-\tif (unlikely(lanai->vccs == NULL))\n-\t\treturn -ENOMEM;\n-\treturn 0;\n-#endif\n-}\n-\n-static inline void vcc_table_deallocate(const struct lanai_dev *lanai)\n-{\n-#ifdef VCCTABLE_GETFREEPAGE\n-\tfree_page((unsigned long) lanai->vccs);\n-#else\n-\tvfree(lanai->vccs);\n-#endif\n-}\n-\n-/* Allocate a fresh lanai_vcc, with the appropriate things cleared */\n-static inline struct lanai_vcc *new_lanai_vcc(void)\n-{\n-\tstruct lanai_vcc *lvcc;\n-\tlvcc = kzalloc_obj(*lvcc);\n-\tif (likely(lvcc != NULL)) {\n-\t\tskb_queue_head_init(&lvcc->tx.backlog);\n-#ifdef DEBUG\n-\t\tlvcc->vci = -1;\n-#endif\n-\t}\n-\treturn lvcc;\n-}\n-\n-static int lanai_get_sized_buffer(struct lanai_dev *lanai,\n-\tstruct lanai_buffer *buf, int max_sdu, int multiplier,\n-\tconst char *name)\n-{\n-\tint size;\n-\tif (unlikely(max_sdu < 1))\n-\t\tmax_sdu = 1;\n-\tmax_sdu = aal5_size(max_sdu);\n-\tsize = (max_sdu + 16) * multiplier + 16;\n-\tlanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);\n-\tif (unlikely(buf->start == NULL))\n-\t\treturn -ENOMEM;\n-\tif (unlikely(lanai_buf_size(buf) < size))\n-\t\tprintk(KERN_WARNING DEV_LABEL \"(itf %d): wanted %d bytes \"\n-\t\t \"for %s buffer, got only %zu\\n\", lanai->number, size,\n-\t\t name, lanai_buf_size(buf));\n-\tDPRINTK(\"Allocated %zu byte %s buffer\\n\", lanai_buf_size(buf), name);\n-\treturn 0;\n-}\n-\n-/* Setup a RX buffer for a currently unbound AAL5 vci */\n-static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc, const struct atm_qos *qos)\n-{\n-\treturn lanai_get_sized_buffer(lanai, &lvcc->rx.buf,\n-\t qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, \"RX\");\n-}\n-\n-/* Setup a TX buffer for a currently unbound AAL5 vci */\n-static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,\n-\tconst struct atm_qos *qos)\n-{\n-\tint max_sdu, multiplier;\n-\tif (qos->aal == ATM_AAL0) {\n-\t\tlvcc->tx.unqueue = vcc_tx_unqueue_aal0;\n-\t\tmax_sdu = ATM_CELL_SIZE - 1;\n-\t\tmultiplier = AAL0_TX_MULTIPLIER;\n-\t} else {\n-\t\tlvcc->tx.unqueue = vcc_tx_unqueue_aal5;\n-\t\tmax_sdu = qos->txtp.max_sdu;\n-\t\tmultiplier = AAL5_TX_MULTIPLIER;\n-\t}\n-\treturn lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,\n-\t multiplier, \"TX\");\n-}\n-\n-static inline void host_vcc_bind(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc, vci_t vci)\n-{\n-\tif (lvcc->vbase != NULL)\n-\t\treturn; /* We already were bound in the other direction */\n-\tDPRINTK(\"Binding vci %d\\n\", vci);\n-#ifdef USE_POWERDOWN\n-\tif (lanai->nbound++ == 0) {\n-\t\tDPRINTK(\"Coming out of powerdown\\n\");\n-\t\tlanai->conf1 &= ~CONFIG1_POWERDOWN;\n-\t\tconf1_write(lanai);\n-\t\tconf2_write(lanai);\n-\t}\n-#endif\n-\tlvcc->vbase = cardvcc_addr(lanai, vci);\n-\tlanai->vccs[lvcc->vci = vci] = lvcc;\n-}\n-\n-static inline void host_vcc_unbind(struct lanai_dev *lanai,\n-\tstruct lanai_vcc *lvcc)\n-{\n-\tif (lvcc->vbase == NULL)\n-\t\treturn;\t/* This vcc was never bound */\n-\tDPRINTK(\"Unbinding vci %d\\n\", lvcc->vci);\n-\tlvcc->vbase = NULL;\n-\tlanai->vccs[lvcc->vci] = NULL;\n-#ifdef USE_POWERDOWN\n-\tif (--lanai->nbound == 0) {\n-\t\tDPRINTK(\"Going into powerdown\\n\");\n-\t\tlanai->conf1 |= CONFIG1_POWERDOWN;\n-\t\tconf1_write(lanai);\n-\t}\n-#endif\n-}\n-\n-/* -------------------- RESET CARD: */\n-\n-static void lanai_reset(struct lanai_dev *lanai)\n-{\n-\tprintk(KERN_CRIT DEV_LABEL \"(itf %d): *NOT* resetting - not \"\n-\t \"implemented\\n\", lanai->number);\n-\t/* TODO */\n-\t/* The following is just a hack until we write the real\n-\t * resetter - at least ack whatever interrupt sent us\n-\t * here\n-\t */\n-\treg_write(lanai, INT_ALL, IntAck_Reg);\n-\tlanai->stats.card_reset++;\n-}\n-\n-/* -------------------- SERVICE LIST UTILITIES: */\n-\n-/*\n- * Allocate service buffer and tell card about it\n- */\n-static int service_buffer_allocate(struct lanai_dev *lanai)\n-{\n-\tlanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,\n-\t lanai->pci);\n-\tif (unlikely(lanai->service.start == NULL))\n-\t\treturn -ENOMEM;\n-\tDPRINTK(\"allocated service buffer at %p, size %zu(%d)\\n\",\n-\t lanai->service.start,\n-\t lanai_buf_size(&lanai->service),\n-\t lanai_buf_size_cardorder(&lanai->service));\n-\t/* Clear ServWrite register to be safe */\n-\treg_write(lanai, 0, ServWrite_Reg);\n-\t/* ServiceStuff register contains size and address of buffer */\n-\treg_write(lanai,\n-\t SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |\n-\t SSTUFF_SET_ADDR(lanai->service.dmaaddr),\n-\t ServiceStuff_Reg);\n-\treturn 0;\n-}\n-\n-static inline void service_buffer_deallocate(struct lanai_dev *lanai)\n-{\n-\tlanai_buf_deallocate(&lanai->service, lanai->pci);\n-}\n-\n-/* Bitfields in service list */\n-#define SERVICE_TX\t(0x80000000)\t/* Was from transmission */\n-#define SERVICE_TRASH\t(0x40000000)\t/* RXed PDU was trashed */\n-#define SERVICE_CRCERR\t(0x20000000)\t/* RXed PDU had CRC error */\n-#define SERVICE_CI\t(0x10000000)\t/* RXed PDU had CI set */\n-#define SERVICE_CLP\t(0x08000000)\t/* RXed PDU had CLP set */\n-#define SERVICE_STREAM\t(0x04000000)\t/* RX Stream mode */\n-#define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)\n-#define SERVICE_GET_END(x) ((x)&0x1FFF)\n-\n-/* Handle one thing from the service list - returns true if it marked a\n- * VCC ready for xmit\n- */\n-static int handle_service(struct lanai_dev *lanai, u32 s)\n-{\n-\tvci_t vci = SERVICE_GET_VCI(s);\n-\tstruct lanai_vcc *lvcc;\n-\tread_lock(&vcc_sklist_lock);\n-\tlvcc = lanai->vccs[vci];\n-\tif (unlikely(lvcc == NULL)) {\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\tDPRINTK(\"(itf %d) got service entry 0x%X for nonexistent \"\n-\t\t \"vcc %d\\n\", lanai->number, (unsigned int) s, vci);\n-\t\tif (s & SERVICE_TX)\n-\t\t\tlanai->stats.service_notx++;\n-\t\telse\n-\t\t\tlanai->stats.service_norx++;\n-\t\treturn 0;\n-\t}\n-\tif (s & SERVICE_TX) {\t\t\t/* segmentation interrupt */\n-\t\tif (unlikely(lvcc->tx.atmvcc == NULL)) {\n-\t\t\tread_unlock(&vcc_sklist_lock);\n-\t\t\tDPRINTK(\"(itf %d) got service entry 0x%X for non-TX \"\n-\t\t\t \"vcc %d\\n\", lanai->number, (unsigned int) s, vci);\n-\t\t\tlanai->stats.service_notx++;\n-\t\t\treturn 0;\n-\t\t}\n-\t\t__set_bit(vci, lanai->transmit_ready);\n-\t\tlvcc->tx.endptr = SERVICE_GET_END(s);\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\treturn 1;\n-\t}\n-\tif (unlikely(lvcc->rx.atmvcc == NULL)) {\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\tDPRINTK(\"(itf %d) got service entry 0x%X for non-RX \"\n-\t\t \"vcc %d\\n\", lanai->number, (unsigned int) s, vci);\n-\t\tlanai->stats.service_norx++;\n-\t\treturn 0;\n-\t}\n-\tif (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\tDPRINTK(\"(itf %d) got RX service entry 0x%X for non-AAL5 \"\n-\t\t \"vcc %d\\n\", lanai->number, (unsigned int) s, vci);\n-\t\tlanai->stats.service_rxnotaal5++;\n-\t\tatomic_inc(&lvcc->rx.atmvcc->stats->rx_err);\n-\t\treturn 0;\n-\t}\n-\tif (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {\n-\t\tvcc_rx_aal5(lvcc, SERVICE_GET_END(s));\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\treturn 0;\n-\t}\n-\tif (s & SERVICE_TRASH) {\n-\t\tint bytes;\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\tDPRINTK(\"got trashed rx pdu on vci %d\\n\", vci);\n-\t\tatomic_inc(&lvcc->rx.atmvcc->stats->rx_err);\n-\t\tlvcc->stats.x.aal5.service_trash++;\n-\t\tbytes = (SERVICE_GET_END(s) * 16) -\n-\t\t (((unsigned long) lvcc->rx.buf.ptr) -\n-\t\t ((unsigned long) lvcc->rx.buf.start)) + 47;\n-\t\tif (bytes < 0)\n-\t\t\tbytes += lanai_buf_size(&lvcc->rx.buf);\n-\t\tlanai->stats.ovfl_trash += (bytes / 48);\n-\t\treturn 0;\n-\t}\n-\tif (s & SERVICE_STREAM) {\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t\tatomic_inc(&lvcc->rx.atmvcc->stats->rx_err);\n-\t\tlvcc->stats.x.aal5.service_stream++;\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): Got AAL5 stream \"\n-\t\t \"PDU on VCI %d!\\n\", lanai->number, vci);\n-\t\tlanai_reset(lanai);\n-\t\treturn 0;\n-\t}\n-\tDPRINTK(\"got rx crc error on vci %d\\n\", vci);\n-\tatomic_inc(&lvcc->rx.atmvcc->stats->rx_err);\n-\tlvcc->stats.x.aal5.service_rxcrc++;\n-\tlvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];\n-\tcardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);\n-\tread_unlock(&vcc_sklist_lock);\n-\treturn 0;\n-}\n-\n-/* Try transmitting on all VCIs that we marked ready to serve */\n-static void iter_transmit(struct lanai_dev *lanai, vci_t vci)\n-{\n-\tstruct lanai_vcc *lvcc = lanai->vccs[vci];\n-\tif (vcc_is_backlogged(lvcc))\n-\t\tlvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);\n-}\n-\n-/* Run service queue -- called from interrupt context or with\n- * interrupts otherwise disabled and with the lanai->servicelock\n- * lock held\n- */\n-static void run_service(struct lanai_dev *lanai)\n-{\n-\tint ntx = 0;\n-\tu32 wreg = reg_read(lanai, ServWrite_Reg);\n-\tconst u32 *end = lanai->service.start + wreg;\n-\twhile (lanai->service.ptr != end) {\n-\t\tntx += handle_service(lanai,\n-\t\t le32_to_cpup(lanai->service.ptr++));\n-\t\tif (lanai->service.ptr >= lanai->service.end)\n-\t\t\tlanai->service.ptr = lanai->service.start;\n-\t}\n-\treg_write(lanai, wreg, ServRead_Reg);\n-\tif (ntx != 0) {\n-\t\tread_lock(&vcc_sklist_lock);\n-\t\tvci_bitfield_iterate(lanai, lanai->transmit_ready,\n-\t\t iter_transmit);\n-\t\tbitmap_zero(lanai->transmit_ready, NUM_VCI);\n-\t\tread_unlock(&vcc_sklist_lock);\n-\t}\n-}\n-\n-/* -------------------- GATHER STATISTICS: */\n-\n-static void get_statistics(struct lanai_dev *lanai)\n-{\n-\tu32 statreg = reg_read(lanai, Statistics_Reg);\n-\tlanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);\n-\tlanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);\n-\tlanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);\n-\tlanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);\n-}\n-\n-/* -------------------- POLLING TIMER: */\n-\n-#ifndef DEBUG_RW\n-/* Try to undequeue 1 backlogged vcc */\n-static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)\n-{\n-\tstruct lanai_vcc *lvcc = lanai->vccs[vci];\n-\tint endptr;\n-\tif (lvcc == NULL || lvcc->tx.atmvcc == NULL ||\n-\t !vcc_is_backlogged(lvcc)) {\n-\t\t__clear_bit(vci, lanai->backlog_vccs);\n-\t\treturn;\n-\t}\n-\tendptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));\n-\tlvcc->tx.unqueue(lanai, lvcc, endptr);\n-}\n-#endif /* !DEBUG_RW */\n-\n-static void lanai_timed_poll(struct timer_list *t)\n-{\n-\tstruct lanai_dev *lanai = timer_container_of(lanai, t, timer);\n-#ifndef DEBUG_RW\n-\tunsigned long flags;\n-#ifdef USE_POWERDOWN\n-\tif (lanai->conf1 & CONFIG1_POWERDOWN)\n-\t\treturn;\n-#endif /* USE_POWERDOWN */\n-\tlocal_irq_save(flags);\n-\t/* If we can grab the spinlock, check if any services need to be run */\n-\tif (spin_trylock(&lanai->servicelock)) {\n-\t\trun_service(lanai);\n-\t\tspin_unlock(&lanai->servicelock);\n-\t}\n-\t/* ...and see if any backlogged VCs can make progress */\n-\t/* unfortunately linux has no read_trylock() currently */\n-\tread_lock(&vcc_sklist_lock);\n-\tvci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);\n-\tread_unlock(&vcc_sklist_lock);\n-\tlocal_irq_restore(flags);\n-\n-\tget_statistics(lanai);\n-#endif /* !DEBUG_RW */\n-\tmod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);\n-}\n-\n-static inline void lanai_timed_poll_start(struct lanai_dev *lanai)\n-{\n-\ttimer_setup(&lanai->timer, lanai_timed_poll, 0);\n-\tlanai->timer.expires = jiffies + LANAI_POLL_PERIOD;\n-\tadd_timer(&lanai->timer);\n-}\n-\n-static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)\n-{\n-\ttimer_delete_sync(&lanai->timer);\n-}\n-\n-/* -------------------- INTERRUPT SERVICE: */\n-\n-static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)\n-{\n-\tu32 ack = 0;\n-\tif (reason & INT_SERVICE) {\n-\t\tack = INT_SERVICE;\n-\t\tspin_lock(&lanai->servicelock);\n-\t\trun_service(lanai);\n-\t\tspin_unlock(&lanai->servicelock);\n-\t}\n-\tif (reason & (INT_AAL0_STR | INT_AAL0)) {\n-\t\tack |= reason & (INT_AAL0_STR | INT_AAL0);\n-\t\tvcc_rx_aal0(lanai);\n-\t}\n-\t/* The rest of the interrupts are pretty rare */\n-\tif (ack == reason)\n-\t\tgoto done;\n-\tif (reason & INT_STATS) {\n-\t\treason &= ~INT_STATS;\t/* No need to ack */\n-\t\tget_statistics(lanai);\n-\t}\n-\tif (reason & INT_STATUS) {\n-\t\tack |= reason & INT_STATUS;\n-\t\tlanai_check_status(lanai);\n-\t}\n-\tif (unlikely(reason & INT_DMASHUT)) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): driver error - DMA \"\n-\t\t \"shutdown, reason=0x%08X, address=0x%08X\\n\",\n-\t\t lanai->number, (unsigned int) (reason & INT_DMASHUT),\n-\t\t (unsigned int) reg_read(lanai, DMA_Addr_Reg));\n-\t\tif (reason & INT_TABORTBM) {\n-\t\t\tlanai_reset(lanai);\n-\t\t\treturn;\n-\t\t}\n-\t\tack |= (reason & INT_DMASHUT);\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): re-enabling DMA\\n\",\n-\t\t lanai->number);\n-\t\tconf1_write(lanai);\n-\t\tlanai->stats.dma_reenable++;\n-\t\tpcistatus_check(lanai, 0);\n-\t}\n-\tif (unlikely(reason & INT_TABORTSENT)) {\n-\t\tack |= (reason & INT_TABORTSENT);\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): sent PCI target abort\\n\",\n-\t\t lanai->number);\n-\t\tpcistatus_check(lanai, 0);\n-\t}\n-\tif (unlikely(reason & INT_SEGSHUT)) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): driver error - \"\n-\t\t \"segmentation shutdown, reason=0x%08X\\n\", lanai->number,\n-\t\t (unsigned int) (reason & INT_SEGSHUT));\n-\t\tlanai_reset(lanai);\n-\t\treturn;\n-\t}\n-\tif (unlikely(reason & (INT_PING | INT_WAKE))) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): driver error - \"\n-\t\t \"unexpected interrupt 0x%08X, resetting\\n\",\n-\t\t lanai->number,\n-\t\t (unsigned int) (reason & (INT_PING | INT_WAKE)));\n-\t\tlanai_reset(lanai);\n-\t\treturn;\n-\t}\n-#ifdef DEBUG\n-\tif (unlikely(ack != reason)) {\n-\t\tDPRINTK(\"unacked ints: 0x%08X\\n\",\n-\t\t (unsigned int) (reason & ~ack));\n-\t\tack = reason;\n-\t}\n-#endif\n- done:\n-\tif (ack != 0)\n-\t\treg_write(lanai, ack, IntAck_Reg);\n-}\n-\n-static irqreturn_t lanai_int(int irq, void *devid)\n-{\n-\tstruct lanai_dev *lanai = devid;\n-\tu32 reason;\n-\n-#ifdef USE_POWERDOWN\n-\t/*\n-\t * If we're powered down we shouldn't be generating any interrupts -\n-\t * so assume that this is a shared interrupt line and it's for someone\n-\t * else\n-\t */\n-\tif (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))\n-\t\treturn IRQ_NONE;\n-#endif\n-\n-\treason = intr_pending(lanai);\n-\tif (reason == 0)\n-\t\treturn IRQ_NONE;\t/* Must be for someone else */\n-\n-\tdo {\n-\t\tif (unlikely(reason == 0xFFFFFFFF))\n-\t\t\tbreak;\t\t/* Maybe we've been unplugged? */\n-\t\tlanai_int_1(lanai, reason);\n-\t\treason = intr_pending(lanai);\n-\t} while (reason != 0);\n-\n-\treturn IRQ_HANDLED;\n-}\n-\n-/* TODO - it would be nice if we could use the \"delayed interrupt\" system\n- * to some advantage\n- */\n-\n-/* -------------------- CHECK BOARD ID/REV: */\n-\n-/*\n- * The board id and revision are stored both in the reset register and\n- * in the PCI configuration space - the documentation says to check\n- * each of them. If revp!=NULL we store the revision there\n- */\n-static int check_board_id_and_rev(const char *name, u32 val, int *revp)\n-{\n-\tDPRINTK(\"%s says board_id=%d, board_rev=%d\\n\", name,\n-\t\t(int) RESET_GET_BOARD_ID(val),\n-\t\t(int) RESET_GET_BOARD_REV(val));\n-\tif (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {\n-\t\tprintk(KERN_ERR DEV_LABEL \": Found %s board-id %d -- not a \"\n-\t\t \"Lanai 25.6\\n\", name, (int) RESET_GET_BOARD_ID(val));\n-\t\treturn -ENODEV;\n-\t}\n-\tif (revp != NULL)\n-\t\t*revp = RESET_GET_BOARD_REV(val);\n-\treturn 0;\n-}\n-\n-/* -------------------- PCI INITIALIZATION/SHUTDOWN: */\n-\n-static int lanai_pci_start(struct lanai_dev *lanai)\n-{\n-\tstruct pci_dev *pci = lanai->pci;\n-\tint result;\n-\n-\tif (pci_enable_device(pci) != 0) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't enable \"\n-\t\t \"PCI device\", lanai->number);\n-\t\treturn -ENXIO;\n-\t}\n-\tpci_set_master(pci);\n-\tif (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)) != 0) {\n-\t\tprintk(KERN_WARNING DEV_LABEL\n-\t\t \"(itf %d): No suitable DMA available.\\n\", lanai->number);\n-\t\treturn -EBUSY;\n-\t}\n-\tresult = check_board_id_and_rev(\"PCI\", pci->subsystem_device, NULL);\n-\tif (result != 0)\n-\t\treturn result;\n-\t/* Set latency timer to zero as per lanai docs */\n-\tresult = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);\n-\tif (result != PCIBIOS_SUCCESSFUL) {\n-\t\tprintk(KERN_ERR DEV_LABEL \"(itf %d): can't write \"\n-\t\t \"PCI_LATENCY_TIMER: %d\\n\", lanai->number, result);\n-\t\treturn -EINVAL;\n-\t}\n-\tpcistatus_check(lanai, 1);\n-\tpcistatus_check(lanai, 0);\n-\treturn 0;\n-}\n-\n-/* -------------------- VPI/VCI ALLOCATION: */\n-\n-/*\n- * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll\n- * get a CBRZERO interrupt), and we can use it only if no one is receiving\n- * AAL0 traffic (since they will use the same queue) - according to the\n- * docs we shouldn't even use it for AAL0 traffic\n- */\n-static inline int vci0_is_ok(struct lanai_dev *lanai,\n-\tconst struct atm_qos *qos)\n-{\n-\tif (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)\n-\t\treturn 0;\n-\tif (qos->rxtp.traffic_class != ATM_NONE) {\n-\t\tif (lanai->naal0 != 0)\n-\t\t\treturn 0;\n-\t\tlanai->conf2 |= CONFIG2_VCI0_NORMAL;\n-\t\tconf2_write_if_powerup(lanai);\n-\t}\n-\treturn 1;\n-}\n-\n-/* return true if vci is currently unused, or if requested qos is\n- * compatible\n- */\n-static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,\n-\tconst struct atm_vcc *atmvcc)\n-{\n-\tconst struct atm_qos *qos = &atmvcc->qos;\n-\tconst struct lanai_vcc *lvcc = lanai->vccs[vci];\n-\tif (vci == 0 && !vci0_is_ok(lanai, qos))\n-\t\treturn 0;\n-\tif (unlikely(lvcc != NULL)) {\n-\t\tif (qos->rxtp.traffic_class != ATM_NONE &&\n-\t\t lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)\n-\t\t\treturn 0;\n-\t\tif (qos->txtp.traffic_class != ATM_NONE &&\n-\t\t lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)\n-\t\t\treturn 0;\n-\t\tif (qos->txtp.traffic_class == ATM_CBR &&\n-\t\t lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)\n-\t\t\treturn 0;\n-\t}\n-\tif (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&\n-\t qos->rxtp.traffic_class != ATM_NONE) {\n-\t\tconst struct lanai_vcc *vci0 = lanai->vccs[0];\n-\t\tif (vci0 != NULL && vci0->rx.atmvcc != NULL)\n-\t\t\treturn 0;\n-\t\tlanai->conf2 &= ~CONFIG2_VCI0_NORMAL;\n-\t\tconf2_write_if_powerup(lanai);\n-\t}\n-\treturn 1;\n-}\n-\n-static int lanai_normalize_ci(struct lanai_dev *lanai,\n-\tconst struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)\n-{\n-\tswitch (*vpip) {\n-\t\tcase ATM_VPI_ANY:\n-\t\t\t*vpip = 0;\n-\t\t\tfallthrough;\n-\t\tcase 0:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EADDRINUSE;\n-\t}\n-\tswitch (*vcip) {\n-\t\tcase ATM_VCI_ANY:\n-\t\t\tfor (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;\n-\t\t\t (*vcip)++)\n-\t\t\t\tif (vci_is_ok(lanai, *vcip, atmvcc))\n-\t\t\t\t\treturn 0;\n-\t\t\treturn -EADDRINUSE;\n-\t\tdefault:\n-\t\t\tif (*vcip >= lanai->num_vci || *vcip < 0 ||\n-\t\t\t !vci_is_ok(lanai, *vcip, atmvcc))\n-\t\t\t\treturn -EADDRINUSE;\n-\t}\n-\treturn 0;\n-}\n-\n-/* -------------------- MANAGE CBR: */\n-\n-/*\n- * CBR ICG is stored as a fixed-point number with 4 fractional bits.\n- * Note that storing a number greater than 2046.0 will result in\n- * incorrect shaping\n- */\n-#define CBRICG_FRAC_BITS\t(4)\n-#define CBRICG_MAX\t\t(2046 << CBRICG_FRAC_BITS)\n-\n-/*\n- * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)\n- * where MAXPCR is (according to the docs) 25600000/(54*8),\n- * which is equal to (3125<<9)/27.\n- *\n- * Solving for ICG, we get:\n- * ICG = MAXPCR/PCR - 1\n- * ICG = (3125<<9)/(27*PCR) - 1\n- * ICG = ((3125<<9) - (27*PCR)) / (27*PCR)\n- *\n- * The end result is supposed to be a fixed-point number with FRAC_BITS\n- * bits of a fractional part, so we keep everything in the numerator\n- * shifted by that much as we compute\n- *\n- */\n-static int pcr_to_cbricg(const struct atm_qos *qos)\n-{\n-\tint rounddown = 0;\t/* 1 = Round PCR down, i.e. round ICG _up_ */\n-\tint x, icg, pcr = atm_pcr_goal(&qos->txtp);\n-\tif (pcr == 0)\t\t/* Use maximum bandwidth */\n-\t\treturn 0;\n-\tif (pcr < 0) {\n-\t\trounddown = 1;\n-\t\tpcr = -pcr;\n-\t}\n-\tx = pcr * 27;\n-\ticg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);\n-\tif (rounddown)\n-\t\ticg += x - 1;\n-\ticg /= x;\n-\tif (icg > CBRICG_MAX)\n-\t\ticg = CBRICG_MAX;\n-\tDPRINTK(\"pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\\n\",\n-\t pcr, rounddown ? 'Y' : 'N', icg);\n-\treturn icg;\n-}\n-\n-static inline void lanai_cbr_setup(struct lanai_dev *lanai)\n-{\n-\treg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);\n-\treg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);\n-\tlanai->conf2 |= CONFIG2_CBR_ENABLE;\n-\tconf2_write(lanai);\n-}\n-\n-static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)\n-{\n-\tlanai->conf2 &= ~CONFIG2_CBR_ENABLE;\n-\tconf2_write(lanai);\n-}\n-\n-/* -------------------- OPERATIONS: */\n-\n-/* setup a newly detected device */\n-static int lanai_dev_open(struct atm_dev *atmdev)\n-{\n-\tstruct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;\n-\tunsigned long raw_base;\n-\tint result;\n-\n-\tDPRINTK(\"In lanai_dev_open()\\n\");\n-\t/* Basic device fields */\n-\tlanai->number = atmdev->number;\n-\tlanai->num_vci = NUM_VCI;\n-\tbitmap_zero(lanai->backlog_vccs, NUM_VCI);\n-\tbitmap_zero(lanai->transmit_ready, NUM_VCI);\n-\tlanai->naal0 = 0;\n-#ifdef USE_POWERDOWN\n-\tlanai->nbound = 0;\n-#endif\n-\tlanai->cbrvcc = NULL;\n-\tmemset(&lanai->stats, 0, sizeof lanai->stats);\n-\tspin_lock_init(&lanai->endtxlock);\n-\tspin_lock_init(&lanai->servicelock);\n-\tatmdev->ci_range.vpi_bits = 0;\n-\tatmdev->ci_range.vci_bits = 0;\n-\twhile (1 << atmdev->ci_range.vci_bits < lanai->num_vci)\n-\t\tatmdev->ci_range.vci_bits++;\n-\tatmdev->link_rate = ATM_25_PCR;\n-\n-\t/* 3.2: PCI initialization */\n-\tif ((result = lanai_pci_start(lanai)) != 0)\n-\t\tgoto error;\n-\traw_base = lanai->pci->resource[0].start;\n-\tlanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);\n-\tif (lanai->base == NULL) {\n-\t\tprintk(KERN_ERR DEV_LABEL \": couldn't remap I/O space\\n\");\n-\t\tresult = -ENOMEM;\n-\t\tgoto error_pci;\n-\t}\n-\t/* 3.3: Reset lanai and PHY */\n-\treset_board(lanai);\n-\tlanai->conf1 = reg_read(lanai, Config1_Reg);\n-\tlanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |\n-\t CONFIG1_MASK_LEDMODE);\n-\tlanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);\n-\treg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);\n-\tudelay(1000);\n-\tconf1_write(lanai);\n-\n-\t/*\n-\t * 3.4: Turn on endian mode for big-endian hardware\n-\t * We don't actually want to do this - the actual bit fields\n-\t * in the endian register are not documented anywhere.\n-\t * Instead we do the bit-flipping ourselves on big-endian\n-\t * hardware.\n-\t *\n-\t * 3.5: get the board ID/rev by reading the reset register\n-\t */\n-\tresult = check_board_id_and_rev(\"register\",\n-\t reg_read(lanai, Reset_Reg), &lanai->board_rev);\n-\tif (result != 0)\n-\t\tgoto error_unmap;\n-\n-\t/* 3.6: read EEPROM */\n-\tif ((result = eeprom_read(lanai)) != 0)\n-\t\tgoto error_unmap;\n-\tif ((result = eeprom_validate(lanai)) != 0)\n-\t\tgoto error_unmap;\n-\n-\t/* 3.7: re-reset PHY, do loopback tests, setup PHY */\n-\treg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);\n-\tudelay(1000);\n-\tconf1_write(lanai);\n-\t/* TODO - loopback tests */\n-\tlanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);\n-\tconf1_write(lanai);\n-\n-\t/* 3.8/3.9: test and initialize card SRAM */\n-\tif ((result = sram_test_and_clear(lanai)) != 0)\n-\t\tgoto error_unmap;\n-\n-\t/* 3.10: initialize lanai registers */\n-\tlanai->conf1 |= CONFIG1_DMA_ENABLE;\n-\tconf1_write(lanai);\n-\tif ((result = service_buffer_allocate(lanai)) != 0)\n-\t\tgoto error_unmap;\n-\tif ((result = vcc_table_allocate(lanai)) != 0)\n-\t\tgoto error_service;\n-\tlanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |\n-\t CONFIG2_HEC_DROP |\t/* ??? */ CONFIG2_PTI7_MODE;\n-\tconf2_write(lanai);\n-\treg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);\n-\treg_write(lanai, 0, CBR_ICG_Reg);\t/* CBR defaults to no limit */\n-\tif ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,\n-\t DEV_LABEL, lanai)) != 0) {\n-\t\tprintk(KERN_ERR DEV_LABEL \": can't allocate interrupt\\n\");\n-\t\tgoto error_vcctable;\n-\t}\n-\tmb();\t\t\t\t/* Make sure that all that made it */\n-\tintr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));\n-\t/* 3.11: initialize loop mode (i.e. turn looping off) */\n-\tlanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |\n-\t CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |\n-\t CONFIG1_GPOUT2 | CONFIG1_GPOUT3;\n-\tconf1_write(lanai);\n-\tlanai->status = reg_read(lanai, Status_Reg);\n-\t/* We're now done initializing this card */\n-#ifdef USE_POWERDOWN\n-\tlanai->conf1 |= CONFIG1_POWERDOWN;\n-\tconf1_write(lanai);\n-#endif\n-\tmemcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);\n-\tlanai_timed_poll_start(lanai);\n-\tprintk(KERN_NOTICE DEV_LABEL \"(itf %d): rev.%d, base=%p, irq=%u \"\n-\t\t\"(%pMF)\\n\", lanai->number, (int) lanai->pci->revision,\n-\t\tlanai->base, lanai->pci->irq, atmdev->esi);\n-\tprintk(KERN_NOTICE DEV_LABEL \"(itf %d): LANAI%s, serialno=%u(0x%X), \"\n-\t \"board_rev=%d\\n\", lanai->number,\n-\t lanai->type==lanai2 ? \"2\" : \"HB\", (unsigned int) lanai->serialno,\n-\t (unsigned int) lanai->serialno, lanai->board_rev);\n-\treturn 0;\n-\n- error_vcctable:\n-\tvcc_table_deallocate(lanai);\n- error_service:\n-\tservice_buffer_deallocate(lanai);\n- error_unmap:\n-\treset_board(lanai);\n-#ifdef USE_POWERDOWN\n-\tlanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;\n-\tconf1_write(lanai);\n-#endif\n-\tiounmap(lanai->base);\n-\tlanai->base = NULL;\n- error_pci:\n-\tpci_disable_device(lanai->pci);\n- error:\n-\treturn result;\n-}\n-\n-/* called when device is being shutdown, and all vcc's are gone - higher\n- * levels will deallocate the atm device for us\n- */\n-static void lanai_dev_close(struct atm_dev *atmdev)\n-{\n-\tstruct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;\n-\tif (lanai->base==NULL)\n-\t\treturn;\n-\tprintk(KERN_INFO DEV_LABEL \"(itf %d): shutting down interface\\n\",\n-\t lanai->number);\n-\tlanai_timed_poll_stop(lanai);\n-#ifdef USE_POWERDOWN\n-\tlanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;\n-\tconf1_write(lanai);\n-#endif\n-\tintr_disable(lanai, INT_ALL);\n-\tfree_irq(lanai->pci->irq, lanai);\n-\treset_board(lanai);\n-#ifdef USE_POWERDOWN\n-\tlanai->conf1 |= CONFIG1_POWERDOWN;\n-\tconf1_write(lanai);\n-#endif\n-\tpci_disable_device(lanai->pci);\n-\tvcc_table_deallocate(lanai);\n-\tservice_buffer_deallocate(lanai);\n-\tiounmap(lanai->base);\n-\tkfree(lanai);\n-}\n-\n-/* close a vcc */\n-static void lanai_close(struct atm_vcc *atmvcc)\n-{\n-\tstruct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;\n-\tstruct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;\n-\tif (lvcc == NULL)\n-\t\treturn;\n-\tclear_bit(ATM_VF_READY, &atmvcc->flags);\n-\tclear_bit(ATM_VF_PARTIAL, &atmvcc->flags);\n-\tif (lvcc->rx.atmvcc == atmvcc) {\n-\t\tlanai_shutdown_rx_vci(lvcc);\n-\t\tif (atmvcc->qos.aal == ATM_AAL0) {\n-\t\t\tif (--lanai->naal0 <= 0)\n-\t\t\t\taal0_buffer_free(lanai);\n-\t\t} else\n-\t\t\tlanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);\n-\t\tlvcc->rx.atmvcc = NULL;\n-\t}\n-\tif (lvcc->tx.atmvcc == atmvcc) {\n-\t\tif (atmvcc == lanai->cbrvcc) {\n-\t\t\tif (lvcc->vbase != NULL)\n-\t\t\t\tlanai_cbr_shutdown(lanai);\n-\t\t\tlanai->cbrvcc = NULL;\n-\t\t}\n-\t\tlanai_shutdown_tx_vci(lanai, lvcc);\n-\t\tlanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);\n-\t\tlvcc->tx.atmvcc = NULL;\n-\t}\n-\tif (--lvcc->nref == 0) {\n-\t\thost_vcc_unbind(lanai, lvcc);\n-\t\tkfree(lvcc);\n-\t}\n-\tatmvcc->dev_data = NULL;\n-\tclear_bit(ATM_VF_ADDR, &atmvcc->flags);\n-}\n-\n-/* open a vcc on the card to vpi/vci */\n-static int lanai_open(struct atm_vcc *atmvcc)\n-{\n-\tstruct lanai_dev *lanai;\n-\tstruct lanai_vcc *lvcc;\n-\tint result = 0;\n-\tint vci = atmvcc->vci;\n-\tshort vpi = atmvcc->vpi;\n-\t/* we don't support partial open - it's not really useful anyway */\n-\tif ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||\n-\t (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))\n-\t\treturn -EINVAL;\n-\tlanai = (struct lanai_dev *) atmvcc->dev->dev_data;\n-\tresult = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);\n-\tif (unlikely(result != 0))\n-\t\tgoto out;\n-\tset_bit(ATM_VF_ADDR, &atmvcc->flags);\n-\tif (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)\n-\t\treturn -EINVAL;\n-\tDPRINTK(DEV_LABEL \"(itf %d): open %d.%d\\n\", lanai->number,\n-\t (int) vpi, vci);\n-\tlvcc = lanai->vccs[vci];\n-\tif (lvcc == NULL) {\n-\t\tlvcc = new_lanai_vcc();\n-\t\tif (unlikely(lvcc == NULL))\n-\t\t\treturn -ENOMEM;\n-\t\tatmvcc->dev_data = lvcc;\n-\t}\n-\tlvcc->nref++;\n-\tif (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\tAPRINTK(lvcc->rx.atmvcc == NULL, \"rx.atmvcc!=NULL, vci=%d\\n\",\n-\t\t vci);\n-\t\tif (atmvcc->qos.aal == ATM_AAL0) {\n-\t\t\tif (lanai->naal0 == 0)\n-\t\t\t\tresult = aal0_buffer_allocate(lanai);\n-\t\t} else\n-\t\t\tresult = lanai_setup_rx_vci_aal5(\n-\t\t\t lanai, lvcc, &atmvcc->qos);\n-\t\tif (unlikely(result != 0))\n-\t\t\tgoto out_free;\n-\t\tlvcc->rx.atmvcc = atmvcc;\n-\t\tlvcc->stats.rx_nomem = 0;\n-\t\tlvcc->stats.x.aal5.rx_badlen = 0;\n-\t\tlvcc->stats.x.aal5.service_trash = 0;\n-\t\tlvcc->stats.x.aal5.service_stream = 0;\n-\t\tlvcc->stats.x.aal5.service_rxcrc = 0;\n-\t\tif (atmvcc->qos.aal == ATM_AAL0)\n-\t\t\tlanai->naal0++;\n-\t}\n-\tif (atmvcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\tAPRINTK(lvcc->tx.atmvcc == NULL, \"tx.atmvcc!=NULL, vci=%d\\n\",\n-\t\t vci);\n-\t\tresult = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);\n-\t\tif (unlikely(result != 0))\n-\t\t\tgoto out_free;\n-\t\tlvcc->tx.atmvcc = atmvcc;\n-\t\tif (atmvcc->qos.txtp.traffic_class == ATM_CBR) {\n-\t\t\tAPRINTK(lanai->cbrvcc == NULL,\n-\t\t\t \"cbrvcc!=NULL, vci=%d\\n\", vci);\n-\t\t\tlanai->cbrvcc = atmvcc;\n-\t\t}\n-\t}\n-\thost_vcc_bind(lanai, lvcc, vci);\n-\t/*\n-\t * Make sure everything made it to RAM before we tell the card about\n-\t * the VCC\n-\t */\n-\twmb();\n-\tif (atmvcc == lvcc->rx.atmvcc)\n-\t\thost_vcc_start_rx(lvcc);\n-\tif (atmvcc == lvcc->tx.atmvcc) {\n-\t\thost_vcc_start_tx(lvcc);\n-\t\tif (lanai->cbrvcc == atmvcc)\n-\t\t\tlanai_cbr_setup(lanai);\n-\t}\n-\tset_bit(ATM_VF_READY, &atmvcc->flags);\n-\treturn 0;\n- out_free:\n-\tlanai_close(atmvcc);\n- out:\n-\treturn result;\n-}\n-\n-static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)\n-{\n-\tstruct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;\n-\tstruct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;\n-\tunsigned long flags;\n-\tif (unlikely(lvcc == NULL || lvcc->vbase == NULL ||\n-\t lvcc->tx.atmvcc != atmvcc))\n-\t\tgoto einval;\n-#ifdef DEBUG\n-\tif (unlikely(skb == NULL)) {\n-\t\tDPRINTK(\"lanai_send: skb==NULL for vci=%d\\n\", atmvcc->vci);\n-\t\tgoto einval;\n-\t}\n-\tif (unlikely(lanai == NULL)) {\n-\t\tDPRINTK(\"lanai_send: lanai==NULL for vci=%d\\n\", atmvcc->vci);\n-\t\tgoto einval;\n-\t}\n-#endif\n-\tATM_SKB(skb)->vcc = atmvcc;\n-\tswitch (atmvcc->qos.aal) {\n-\t\tcase ATM_AAL5:\n-\t\t\tread_lock_irqsave(&vcc_sklist_lock, flags);\n-\t\t\tvcc_tx_aal5(lanai, lvcc, skb);\n-\t\t\tread_unlock_irqrestore(&vcc_sklist_lock, flags);\n-\t\t\treturn 0;\n-\t\tcase ATM_AAL0:\n-\t\t\tif (unlikely(skb->len != ATM_CELL_SIZE-1))\n-\t\t\t\tgoto einval;\n- /* NOTE - this next line is technically invalid - we haven't unshared skb */\n-\t\t\tcpu_to_be32s((u32 *) skb->data);\n-\t\t\tread_lock_irqsave(&vcc_sklist_lock, flags);\n-\t\t\tvcc_tx_aal0(lanai, lvcc, skb);\n-\t\t\tread_unlock_irqrestore(&vcc_sklist_lock, flags);\n-\t\t\treturn 0;\n-\t}\n-\tDPRINTK(\"lanai_send: bad aal=%d on vci=%d\\n\", (int) atmvcc->qos.aal,\n-\t atmvcc->vci);\n- einval:\n-\tlanai_free_skb(atmvcc, skb);\n-\treturn -EINVAL;\n-}\n-\n-static int lanai_change_qos(struct atm_vcc *atmvcc,\n-\t/*const*/ struct atm_qos *qos, int flags)\n-{\n-\treturn -EBUSY;\t\t/* TODO: need to write this */\n-}\n-\n-#ifndef CONFIG_PROC_FS\n-#define lanai_proc_read NULL\n-#else\n-static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)\n-{\n-\tstruct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;\n-\tloff_t left = *pos;\n-\tstruct lanai_vcc *lvcc;\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, DEV_LABEL \"(itf %d): chip=LANAI%s, \"\n-\t\t \"serial=%u, magic=0x%08X, num_vci=%d\\n\",\n-\t\t atmdev->number, lanai->type==lanai2 ? \"2\" : \"HB\",\n-\t\t (unsigned int) lanai->serialno,\n-\t\t (unsigned int) lanai->magicno, lanai->num_vci);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \"revision: board=%d, pci_if=%d\\n\",\n-\t\t lanai->board_rev, (int) lanai->pci->revision);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \"EEPROM ESI: %pM\\n\",\n-\t\t &lanai->eeprom[EEPROM_MAC]);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \"status: SOOL=%d, LOCD=%d, LED=%d, \"\n-\t\t \"GPIN=%d\\n\", (lanai->status & STATUS_SOOL) ? 1 : 0,\n-\t\t (lanai->status & STATUS_LOCD) ? 1 : 0,\n-\t\t (lanai->status & STATUS_LED) ? 1 : 0,\n-\t\t (lanai->status & STATUS_GPIN) ? 1 : 0);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \"global buffer sizes: service=%zu, \"\n-\t\t \"aal0_rx=%zu\\n\", lanai_buf_size(&lanai->service),\n-\t\t lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);\n-\tif (left-- == 0) {\n-\t\tget_statistics(lanai);\n-\t\treturn sprintf(page, \"cells in error: overflow=%u, \"\n-\t\t \"closed_vci=%u, bad_HEC=%u, rx_fifo=%u\\n\",\n-\t\t lanai->stats.ovfl_trash, lanai->stats.vci_trash,\n-\t\t lanai->stats.hec_err, lanai->stats.atm_ovfl);\n-\t}\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \"PCI errors: parity_detect=%u, \"\n-\t\t \"master_abort=%u, master_target_abort=%u,\\n\",\n-\t\t lanai->stats.pcierr_parity_detect,\n-\t\t lanai->stats.pcierr_serr_set,\n-\t\t lanai->stats.pcierr_m_target_abort);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \" slave_target_abort=%u, \"\n-\t\t \"master_parity=%u\\n\", lanai->stats.pcierr_s_target_abort,\n-\t\t lanai->stats.pcierr_master_parity);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \" no_tx=%u, \"\n-\t\t \"no_rx=%u, bad_rx_aal=%u\\n\", lanai->stats.service_norx,\n-\t\t lanai->stats.service_notx,\n-\t\t lanai->stats.service_rxnotaal5);\n-\tif (left-- == 0)\n-\t\treturn sprintf(page, \"resets: dma=%u, card=%u\\n\",\n-\t\t lanai->stats.dma_reenable, lanai->stats.card_reset);\n-\t/* At this point, \"left\" should be the VCI we're looking for */\n-\tread_lock(&vcc_sklist_lock);\n-\tfor (; ; left++) {\n-\t\tif (left >= NUM_VCI) {\n-\t\t\tleft = 0;\n-\t\t\tgoto out;\n-\t\t}\n-\t\tif ((lvcc = lanai->vccs[left]) != NULL)\n-\t\t\tbreak;\n-\t\t(*pos)++;\n-\t}\n-\t/* Note that we re-use \"left\" here since we're done with it */\n-\tleft = sprintf(page, \"VCI %4d: nref=%d, rx_nomem=%u\", (vci_t) left,\n-\t lvcc->nref, lvcc->stats.rx_nomem);\n-\tif (lvcc->rx.atmvcc != NULL) {\n-\t\tleft += sprintf(&page[left], \",\\n rx_AAL=%d\",\n-\t\t lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);\n-\t\tif (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)\n-\t\t\tleft += sprintf(&page[left], \", rx_buf_size=%zu, \"\n-\t\t\t \"rx_bad_len=%u,\\n rx_service_trash=%u, \"\n-\t\t\t \"rx_service_stream=%u, rx_bad_crc=%u\",\n-\t\t\t lanai_buf_size(&lvcc->rx.buf),\n-\t\t\t lvcc->stats.x.aal5.rx_badlen,\n-\t\t\t lvcc->stats.x.aal5.service_trash,\n-\t\t\t lvcc->stats.x.aal5.service_stream,\n-\t\t\t lvcc->stats.x.aal5.service_rxcrc);\n-\t}\n-\tif (lvcc->tx.atmvcc != NULL)\n-\t\tleft += sprintf(&page[left], \",\\n tx_AAL=%d, \"\n-\t\t \"tx_buf_size=%zu, tx_qos=%cBR, tx_backlogged=%c\",\n-\t\t lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,\n-\t\t lanai_buf_size(&lvcc->tx.buf),\n-\t\t lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',\n-\t\t vcc_is_backlogged(lvcc) ? 'Y' : 'N');\n-\tpage[left++] = '\\n';\n-\tpage[left] = '\\0';\n- out:\n-\tread_unlock(&vcc_sklist_lock);\n-\treturn left;\n-}\n-#endif /* CONFIG_PROC_FS */\n-\n-/* -------------------- HOOKS: */\n-\n-static const struct atmdev_ops ops = {\n-\t.dev_close\t= lanai_dev_close,\n-\t.open\t\t= lanai_open,\n-\t.close\t\t= lanai_close,\n-\t.send\t\t= lanai_send,\n-\t.phy_put\t= NULL,\n-\t.phy_get\t= NULL,\n-\t.change_qos\t= lanai_change_qos,\n-\t.proc_read\t= lanai_proc_read,\n-\t.owner\t\t= THIS_MODULE\n-};\n-\n-/* initialize one probed card */\n-static int lanai_init_one(struct pci_dev *pci,\n-\t\t\t const struct pci_device_id *ident)\n-{\n-\tstruct lanai_dev *lanai;\n-\tstruct atm_dev *atmdev;\n-\tint result;\n-\n-\tlanai = kzalloc_obj(*lanai);\n-\tif (lanai == NULL) {\n-\t\tprintk(KERN_ERR DEV_LABEL\n-\t\t \": couldn't allocate dev_data structure!\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tatmdev = atm_dev_register(DEV_LABEL, &pci->dev, &ops, -1, NULL);\n-\tif (atmdev == NULL) {\n-\t\tprintk(KERN_ERR DEV_LABEL\n-\t\t \": couldn't register atm device!\\n\");\n-\t\tkfree(lanai);\n-\t\treturn -EBUSY;\n-\t}\n-\n-\tatmdev->dev_data = lanai;\n-\tlanai->pci = pci;\n-\tlanai->type = (enum lanai_type) ident->device;\n-\n-\tresult = lanai_dev_open(atmdev);\n-\tif (result != 0) {\n-\t\tDPRINTK(\"lanai_start() failed, err=%d\\n\", -result);\n-\t\tatm_dev_deregister(atmdev);\n-\t\tkfree(lanai);\n-\t}\n-\treturn result;\n-}\n-\n-static const struct pci_device_id lanai_pci_tbl[] = {\n-\t{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },\n-\t{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },\n-\t{ 0, }\t/* terminal entry */\n-};\n-MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);\n-\n-static struct pci_driver lanai_driver = {\n-\t.name = DEV_LABEL,\n-\t.id_table = lanai_pci_tbl,\n-\t.probe = lanai_init_one,\n-};\n-\n-module_pci_driver(lanai_driver);\n-\n-MODULE_AUTHOR(\"Mitchell Blank Jr \");\n-MODULE_DESCRIPTION(\"Efficient Networks Speedstream 3010 driver\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/atm/nicstar.c b/drivers/atm/nicstar.c\ndeleted file mode 100644\nindex 24e51343df15..000000000000\n--- a/drivers/atm/nicstar.c\n+++ /dev/null\n@@ -1,2759 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * nicstar.c\n- *\n- * Device driver supporting CBR for IDT 77201/77211 \"NICStAR\" based cards.\n- *\n- * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.\n- * It was taken from the frle-0.22 device driver.\n- * As the file doesn't have a copyright notice, in the file\n- * nicstarmac.copyright I put the copyright notice from the\n- * frle-0.22 device driver.\n- * Some code is based on the nicstar driver by M. Welsh.\n- *\n- * Author: Rui Prior (rprior@inescn.pt)\n- * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999\n- *\n- *\n- * (C) INESC 1999\n- */\n-\n-/*\n- * IMPORTANT INFORMATION\n- *\n- * There are currently three types of spinlocks:\n- *\n- * 1 - Per card interrupt spinlock (to protect structures and such)\n- * 2 - Per SCQ scq spinlock\n- * 3 - Per card resource spinlock (to access registers, etc.)\n- *\n- * These must NEVER be grabbed in reverse order.\n- *\n- */\n-\n-/* Header files */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \"nicstar.h\"\n-#ifdef CONFIG_ATM_NICSTAR_USE_SUNI\n-#include \"suni.h\"\n-#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */\n-#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105\n-#include \"idt77105.h\"\n-#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */\n-\n-/* Additional code */\n-\n-#include \"nicstarmac.c\"\n-\n-/* Configurable parameters */\n-\n-#undef PHY_LOOPBACK\n-#undef TX_DEBUG\n-#undef RX_DEBUG\n-#undef GENERAL_DEBUG\n-#undef EXTRA_DEBUG\n-\n-/* Do not touch these */\n-\n-#ifdef TX_DEBUG\n-#define TXPRINTK(args...) printk(args)\n-#else\n-#define TXPRINTK(args...)\n-#endif /* TX_DEBUG */\n-\n-#ifdef RX_DEBUG\n-#define RXPRINTK(args...) printk(args)\n-#else\n-#define RXPRINTK(args...)\n-#endif /* RX_DEBUG */\n-\n-#ifdef GENERAL_DEBUG\n-#define PRINTK(args...) printk(args)\n-#else\n-#define PRINTK(args...) do {} while (0)\n-#endif /* GENERAL_DEBUG */\n-\n-#ifdef EXTRA_DEBUG\n-#define XPRINTK(args...) printk(args)\n-#else\n-#define XPRINTK(args...)\n-#endif /* EXTRA_DEBUG */\n-\n-/* Macros */\n-\n-#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)\n-\n-#define NS_DELAY mdelay(1)\n-\n-#define PTR_DIFF(a, b)\t((u32)((unsigned long)(a) - (unsigned long)(b)))\n-\n-#ifndef ATM_SKB\n-#define ATM_SKB(s) (&(s)->atm)\n-#endif\n-\n-#define scq_virt_to_bus(scq, p) \\\n-\t\t(scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))\n-\n-/* Function declarations */\n-\n-static u32 ns_read_sram(ns_dev * card, u32 sram_address);\n-static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,\n-\t\t\t int count);\n-static int ns_init_card(int i, struct pci_dev *pcidev);\n-static void ns_init_card_error(ns_dev * card, int error);\n-static scq_info *get_scq(ns_dev *card, int size, u32 scd);\n-static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);\n-static void push_rxbufs(ns_dev *, struct sk_buff *);\n-static irqreturn_t ns_irq_handler(int irq, void *dev_id);\n-static int ns_open(struct atm_vcc *vcc);\n-static void ns_close(struct atm_vcc *vcc);\n-static void fill_tst(ns_dev * card, int n, vc_map * vc);\n-static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);\n-static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);\n-static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,\n-\t\t struct sk_buff *skb, bool may_sleep);\n-static void process_tsq(ns_dev * card);\n-static void drain_scq(ns_dev * card, scq_info * scq, int pos);\n-static void process_rsq(ns_dev * card);\n-static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);\n-static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);\n-static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);\n-static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);\n-static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);\n-static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);\n-static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);\n-static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);\n-#ifdef EXTRA_DEBUG\n-static void which_list(ns_dev * card, struct sk_buff *skb);\n-#endif\n-static void ns_poll(struct timer_list *unused);\n-static void ns_phy_put(struct atm_dev *dev, unsigned char value,\n-\t\t unsigned long addr);\n-static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);\n-\n-/* Global variables */\n-\n-static struct ns_dev *cards[NS_MAX_CARDS];\n-static unsigned num_cards;\n-static const struct atmdev_ops atm_ops = {\n-\t.open = ns_open,\n-\t.close = ns_close,\n-\t.ioctl = ns_ioctl,\n-\t.send = ns_send,\n-\t.send_bh = ns_send_bh,\n-\t.phy_put = ns_phy_put,\n-\t.phy_get = ns_phy_get,\n-\t.proc_read = ns_proc_read,\n-\t.owner = THIS_MODULE,\n-};\n-\n-static struct timer_list ns_timer;\n-static char *mac[NS_MAX_CARDS];\n-module_param_array(mac, charp, NULL, 0);\n-MODULE_DESCRIPTION(\"ATM NIC driver for IDT 77201/77211 \\\"NICStAR\\\" and Fore ForeRunnerLE.\");\n-MODULE_LICENSE(\"GPL\");\n-\n-/* Functions */\n-\n-static int nicstar_init_one(struct pci_dev *pcidev,\n-\t\t\t const struct pci_device_id *ent)\n-{\n-\tstatic int index = -1;\n-\tunsigned int error;\n-\n-\tindex++;\n-\tcards[index] = NULL;\n-\n-\terror = ns_init_card(index, pcidev);\n-\tif (error) {\n-\t\tcards[index--] = NULL;\t/* don't increment index */\n-\t\tgoto err_out;\n-\t}\n-\n-\treturn 0;\n-err_out:\n-\treturn -ENODEV;\n-}\n-\n-static void nicstar_remove_one(struct pci_dev *pcidev)\n-{\n-\tint i, j;\n-\tns_dev *card = pci_get_drvdata(pcidev);\n-\tstruct sk_buff *hb;\n-\tstruct sk_buff *iovb;\n-\tstruct sk_buff *lb;\n-\tstruct sk_buff *sb;\n-\n-\ti = card->index;\n-\n-\tif (cards[i] == NULL)\n-\t\treturn;\n-\n-\tif (card->atmdev->phy && card->atmdev->phy->stop)\n-\t\tcard->atmdev->phy->stop(card->atmdev);\n-\n-\t/* Stop everything */\n-\twritel(0x00000000, card->membase + CFG);\n-\n-\t/* De-register device */\n-\tatm_dev_deregister(card->atmdev);\n-\n-\t/* Disable PCI device */\n-\tpci_disable_device(pcidev);\n-\n-\t/* Free up resources */\n-\tj = 0;\n-\tPRINTK(\"nicstar%d: freeing %d huge buffers.\\n\", i, card->hbpool.count);\n-\twhile ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {\n-\t\tdev_kfree_skb_any(hb);\n-\t\tj++;\n-\t}\n-\tPRINTK(\"nicstar%d: %d huge buffers freed.\\n\", i, j);\n-\tj = 0;\n-\tPRINTK(\"nicstar%d: freeing %d iovec buffers.\\n\", i,\n-\t card->iovpool.count);\n-\twhile ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {\n-\t\tdev_kfree_skb_any(iovb);\n-\t\tj++;\n-\t}\n-\tPRINTK(\"nicstar%d: %d iovec buffers freed.\\n\", i, j);\n-\twhile ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)\n-\t\tdev_kfree_skb_any(lb);\n-\twhile ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)\n-\t\tdev_kfree_skb_any(sb);\n-\tfree_scq(card, card->scq0, NULL);\n-\tfor (j = 0; j < NS_FRSCD_NUM; j++) {\n-\t\tif (card->scd2vc[j] != NULL)\n-\t\t\tfree_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);\n-\t}\n-\tidr_destroy(&card->idr);\n-\tdma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,\n-\t\t\t card->rsq.org, card->rsq.dma);\n-\tdma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,\n-\t\t\t card->tsq.org, card->tsq.dma);\n-\tfree_irq(card->pcidev->irq, card);\n-\tiounmap(card->membase);\n-\tkfree(card);\n-}\n-\n-static const struct pci_device_id nicstar_pci_tbl[] = {\n-\t{ PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },\n-\t{0,}\t\t\t/* terminate list */\n-};\n-\n-MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);\n-\n-static struct pci_driver nicstar_driver = {\n-\t.name = \"nicstar\",\n-\t.id_table = nicstar_pci_tbl,\n-\t.probe = nicstar_init_one,\n-\t.remove = nicstar_remove_one,\n-};\n-\n-static int __init nicstar_init(void)\n-{\n-\tunsigned error = 0;\t/* Initialized to remove compile warning */\n-\n-\tXPRINTK(\"nicstar: nicstar_init() called.\\n\");\n-\n-\terror = pci_register_driver(&nicstar_driver);\n-\n-\tTXPRINTK(\"nicstar: TX debug enabled.\\n\");\n-\tRXPRINTK(\"nicstar: RX debug enabled.\\n\");\n-\tPRINTK(\"nicstar: General debug enabled.\\n\");\n-#ifdef PHY_LOOPBACK\n-\tprintk(\"nicstar: using PHY loopback.\\n\");\n-#endif /* PHY_LOOPBACK */\n-\tXPRINTK(\"nicstar: nicstar_init() returned.\\n\");\n-\n-\tif (!error) {\n-\t\ttimer_setup(&ns_timer, ns_poll, 0);\n-\t\tns_timer.expires = jiffies + NS_POLL_PERIOD;\n-\t\tadd_timer(&ns_timer);\n-\t}\n-\n-\treturn error;\n-}\n-\n-static void __exit nicstar_cleanup(void)\n-{\n-\tXPRINTK(\"nicstar: nicstar_cleanup() called.\\n\");\n-\n-\ttimer_delete_sync(&ns_timer);\n-\n-\tpci_unregister_driver(&nicstar_driver);\n-\n-\tXPRINTK(\"nicstar: nicstar_cleanup() returned.\\n\");\n-}\n-\n-static u32 ns_read_sram(ns_dev * card, u32 sram_address)\n-{\n-\tunsigned long flags;\n-\tu32 data;\n-\tsram_address <<= 2;\n-\tsram_address &= 0x0007FFFC;\t/* address must be dword aligned */\n-\tsram_address |= 0x50000000;\t/* SRAM read command */\n-\tspin_lock_irqsave(&card->res_lock, flags);\n-\twhile (CMD_BUSY(card)) ;\n-\twritel(sram_address, card->membase + CMD);\n-\twhile (CMD_BUSY(card)) ;\n-\tdata = readl(card->membase + DR0);\n-\tspin_unlock_irqrestore(&card->res_lock, flags);\n-\treturn data;\n-}\n-\n-static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,\n-\t\t\t int count)\n-{\n-\tunsigned long flags;\n-\tint i, c;\n-\tcount--;\t\t/* count range now is 0..3 instead of 1..4 */\n-\tc = count;\n-\tc <<= 2;\t\t/* to use increments of 4 */\n-\tspin_lock_irqsave(&card->res_lock, flags);\n-\twhile (CMD_BUSY(card)) ;\n-\tfor (i = 0; i <= c; i += 4)\n-\t\twritel(*(value++), card->membase + i);\n-\t/* Note: DR# registers are the first 4 dwords in nicstar's memspace,\n-\t so card->membase + DR0 == card->membase */\n-\tsram_address <<= 2;\n-\tsram_address &= 0x0007FFFC;\n-\tsram_address |= (0x40000000 | count);\n-\twritel(sram_address, card->membase + CMD);\n-\tspin_unlock_irqrestore(&card->res_lock, flags);\n-}\n-\n-static int ns_init_card(int i, struct pci_dev *pcidev)\n-{\n-\tint j;\n-\tstruct ns_dev *card = NULL;\n-\tunsigned char pci_latency;\n-\tunsigned error;\n-\tu32 data;\n-\tu32 u32d[4];\n-\tu32 ns_cfg_rctsize;\n-\tint bcount;\n-\tunsigned long membase;\n-\n-\terror = 0;\n-\n-\tif (pci_enable_device(pcidev)) {\n-\t\tprintk(\"nicstar%d: can't enable PCI device\\n\", i);\n-\t\terror = 2;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n- if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {\n- printk(KERN_WARNING\n-\t\t \"nicstar%d: No suitable DMA available.\\n\", i);\n-\t\terror = 2;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n- }\n-\n-\tcard = kmalloc_obj(*card);\n-\tif (!card) {\n-\t\tprintk\n-\t\t (\"nicstar%d: can't allocate memory for device structure.\\n\",\n-\t\t i);\n-\t\terror = 2;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\tcards[i] = card;\n-\tspin_lock_init(&card->int_lock);\n-\tspin_lock_init(&card->res_lock);\n-\n-\tpci_set_drvdata(pcidev, card);\n-\n-\tcard->index = i;\n-\tcard->atmdev = NULL;\n-\tcard->pcidev = pcidev;\n-\tmembase = pci_resource_start(pcidev, 1);\n-\tcard->membase = ioremap(membase, NS_IOREMAP_SIZE);\n-\tif (!card->membase) {\n-\t\tprintk(\"nicstar%d: can't ioremap() membase.\\n\", i);\n-\t\terror = 3;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\tPRINTK(\"nicstar%d: membase at 0x%p.\\n\", i, card->membase);\n-\n-\tpci_set_master(pcidev);\n-\n-\tif (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {\n-\t\tprintk(\"nicstar%d: can't read PCI latency timer.\\n\", i);\n-\t\terror = 6;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-#ifdef NS_PCI_LATENCY\n-\tif (pci_latency < NS_PCI_LATENCY) {\n-\t\tPRINTK(\"nicstar%d: setting PCI latency timer to %d.\\n\", i,\n-\t\t NS_PCI_LATENCY);\n-\t\tfor (j = 1; j < 4; j++) {\n-\t\t\tif (pci_write_config_byte\n-\t\t\t (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)\n-\t\t\t\tbreak;\n-\t\t}\n-\t\tif (j == 4) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: can't set PCI latency timer to %d.\\n\",\n-\t\t\t i, NS_PCI_LATENCY);\n-\t\t\terror = 7;\n-\t\t\tns_init_card_error(card, error);\n-\t\t\treturn error;\n-\t\t}\n-\t}\n-#endif /* NS_PCI_LATENCY */\n-\n-\t/* Clear timer overflow */\n-\tdata = readl(card->membase + STAT);\n-\tif (data & NS_STAT_TMROF)\n-\t\twritel(NS_STAT_TMROF, card->membase + STAT);\n-\n-\t/* Software reset */\n-\twritel(NS_CFG_SWRST, card->membase + CFG);\n-\tNS_DELAY;\n-\twritel(0x00000000, card->membase + CFG);\n-\n-\t/* PHY reset */\n-\twritel(0x00000008, card->membase + GP);\n-\tNS_DELAY;\n-\twritel(0x00000001, card->membase + GP);\n-\tNS_DELAY;\n-\twhile (CMD_BUSY(card)) ;\n-\twritel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD);\t/* Sync UTOPIA with SAR clock */\n-\tNS_DELAY;\n-\n-\t/* Detect PHY type */\n-\twhile (CMD_BUSY(card)) ;\n-\twritel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);\n-\twhile (CMD_BUSY(card)) ;\n-\tdata = readl(card->membase + DR0);\n-\tswitch (data) {\n-\tcase 0x00000009:\n-\t\tprintk(\"nicstar%d: PHY seems to be 25 Mbps.\\n\", i);\n-\t\tcard->max_pcr = ATM_25_PCR;\n-\t\twhile (CMD_BUSY(card)) ;\n-\t\twritel(0x00000008, card->membase + DR0);\n-\t\twritel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);\n-\t\t/* Clear an eventual pending interrupt */\n-\t\twritel(NS_STAT_SFBQF, card->membase + STAT);\n-#ifdef PHY_LOOPBACK\n-\t\twhile (CMD_BUSY(card)) ;\n-\t\twritel(0x00000022, card->membase + DR0);\n-\t\twritel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);\n-#endif /* PHY_LOOPBACK */\n-\t\tbreak;\n-\tcase 0x00000030:\n-\tcase 0x00000031:\n-\t\tprintk(\"nicstar%d: PHY seems to be 155 Mbps.\\n\", i);\n-\t\tcard->max_pcr = ATM_OC3_PCR;\n-#ifdef PHY_LOOPBACK\n-\t\twhile (CMD_BUSY(card)) ;\n-\t\twritel(0x00000002, card->membase + DR0);\n-\t\twritel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);\n-#endif /* PHY_LOOPBACK */\n-\t\tbreak;\n-\tdefault:\n-\t\tprintk(\"nicstar%d: unknown PHY type (0x%08X).\\n\", i, data);\n-\t\terror = 8;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\twritel(0x00000000, card->membase + GP);\n-\n-\t/* Determine SRAM size */\n-\tdata = 0x76543210;\n-\tns_write_sram(card, 0x1C003, &data, 1);\n-\tdata = 0x89ABCDEF;\n-\tns_write_sram(card, 0x14003, &data, 1);\n-\tif (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&\n-\t ns_read_sram(card, 0x1C003) == 0x76543210)\n-\t\tcard->sram_size = 128;\n-\telse\n-\t\tcard->sram_size = 32;\n-\tPRINTK(\"nicstar%d: %dK x 32bit SRAM size.\\n\", i, card->sram_size);\n-\n-\tcard->rct_size = NS_MAX_RCTSIZE;\n-\n-#if (NS_MAX_RCTSIZE == 4096)\n-\tif (card->sram_size == 128)\n-\t\tprintk\n-\t\t (\"nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\\n\",\n-\t\t i);\n-#elif (NS_MAX_RCTSIZE == 16384)\n-\tif (card->sram_size == 32) {\n-\t\tprintk\n-\t\t (\"nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\\n\",\n-\t\t i);\n-\t\tcard->rct_size = 4096;\n-\t}\n-#else\n-#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c\n-#endif\n-\n-\tcard->vpibits = NS_VPIBITS;\n-\tif (card->rct_size == 4096)\n-\t\tcard->vcibits = 12 - NS_VPIBITS;\n-\telse\t\t\t/* card->rct_size == 16384 */\n-\t\tcard->vcibits = 14 - NS_VPIBITS;\n-\n-\t/* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */\n-\tif (mac[i] == NULL)\n-\t\tnicstar_init_eprom(card->membase);\n-\n-\t/* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */\n-\twritel(0x00000000, card->membase + VPM);\n-\n-\tcard->intcnt = 0;\n-\tif (request_irq\n-\t (pcidev->irq, &ns_irq_handler, IRQF_SHARED, \"nicstar\", card) != 0) {\n-\t\tpr_err(\"nicstar%d: can't allocate IRQ %d.\\n\", i, pcidev->irq);\n-\t\terror = 9;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\n-\t/* Initialize TSQ */\n-\tcard->tsq.org = dma_alloc_coherent(&card->pcidev->dev,\n-\t\t\t\t\t NS_TSQSIZE + NS_TSQ_ALIGNMENT,\n-\t\t\t\t\t &card->tsq.dma, GFP_KERNEL);\n-\tif (card->tsq.org == NULL) {\n-\t\tprintk(\"nicstar%d: can't allocate TSQ.\\n\", i);\n-\t\terror = 10;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\tcard->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);\n-\tcard->tsq.next = card->tsq.base;\n-\tcard->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);\n-\tfor (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)\n-\t\tns_tsi_init(card->tsq.base + j);\n-\twritel(0x00000000, card->membase + TSQH);\n-\twritel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);\n-\tPRINTK(\"nicstar%d: TSQ base at 0x%p.\\n\", i, card->tsq.base);\n-\n-\t/* Initialize RSQ */\n-\tcard->rsq.org = dma_alloc_coherent(&card->pcidev->dev,\n-\t\t\t\t\t NS_RSQSIZE + NS_RSQ_ALIGNMENT,\n-\t\t\t\t\t &card->rsq.dma, GFP_KERNEL);\n-\tif (card->rsq.org == NULL) {\n-\t\tprintk(\"nicstar%d: can't allocate RSQ.\\n\", i);\n-\t\terror = 11;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\tcard->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);\n-\tcard->rsq.next = card->rsq.base;\n-\tcard->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);\n-\tfor (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)\n-\t\tns_rsqe_init(card->rsq.base + j);\n-\twritel(0x00000000, card->membase + RSQH);\n-\twritel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);\n-\tPRINTK(\"nicstar%d: RSQ base at 0x%p.\\n\", i, card->rsq.base);\n-\n-\t/* Initialize SCQ0, the only VBR SCQ used */\n-\tcard->scq1 = NULL;\n-\tcard->scq2 = NULL;\n-\tcard->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);\n-\tif (card->scq0 == NULL) {\n-\t\tprintk(\"nicstar%d: can't get SCQ0.\\n\", i);\n-\t\terror = 12;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\tu32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);\n-\tu32d[1] = (u32) 0x00000000;\n-\tu32d[2] = (u32) 0xffffffff;\n-\tu32d[3] = (u32) 0x00000000;\n-\tns_write_sram(card, NS_VRSCD0, u32d, 4);\n-\tns_write_sram(card, NS_VRSCD1, u32d, 4);\t/* These last two won't be used */\n-\tns_write_sram(card, NS_VRSCD2, u32d, 4);\t/* but are initialized, just in case... */\n-\tcard->scq0->scd = NS_VRSCD0;\n-\tPRINTK(\"nicstar%d: VBR-SCQ0 base at 0x%p.\\n\", i, card->scq0->base);\n-\n-\t/* Initialize TSTs */\n-\tcard->tst_addr = NS_TST0;\n-\tcard->tst_free_entries = NS_TST_NUM_ENTRIES;\n-\tdata = NS_TST_OPCODE_VARIABLE;\n-\tfor (j = 0; j < NS_TST_NUM_ENTRIES; j++)\n-\t\tns_write_sram(card, NS_TST0 + j, &data, 1);\n-\tdata = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);\n-\tns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);\n-\tfor (j = 0; j < NS_TST_NUM_ENTRIES; j++)\n-\t\tns_write_sram(card, NS_TST1 + j, &data, 1);\n-\tdata = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);\n-\tns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);\n-\tfor (j = 0; j < NS_TST_NUM_ENTRIES; j++)\n-\t\tcard->tste2vc[j] = NULL;\n-\twritel(NS_TST0 << 2, card->membase + TSTB);\n-\n-\t/* Initialize RCT. AAL type is set on opening the VC. */\n-#ifdef RCQ_SUPPORT\n-\tu32d[0] = NS_RCTE_RAWCELLINTEN;\n-#else\n-\tu32d[0] = 0x00000000;\n-#endif /* RCQ_SUPPORT */\n-\tu32d[1] = 0x00000000;\n-\tu32d[2] = 0x00000000;\n-\tu32d[3] = 0xFFFFFFFF;\n-\tfor (j = 0; j < card->rct_size; j++)\n-\t\tns_write_sram(card, j * 4, u32d, 4);\n-\n-\tmemset(card->vcmap, 0, sizeof(card->vcmap));\n-\n-\tfor (j = 0; j < NS_FRSCD_NUM; j++)\n-\t\tcard->scd2vc[j] = NULL;\n-\n-\t/* Initialize buffer levels */\n-\tcard->sbnr.min = MIN_SB;\n-\tcard->sbnr.init = NUM_SB;\n-\tcard->sbnr.max = MAX_SB;\n-\tcard->lbnr.min = MIN_LB;\n-\tcard->lbnr.init = NUM_LB;\n-\tcard->lbnr.max = MAX_LB;\n-\tcard->iovnr.min = MIN_IOVB;\n-\tcard->iovnr.init = NUM_IOVB;\n-\tcard->iovnr.max = MAX_IOVB;\n-\tcard->hbnr.min = MIN_HB;\n-\tcard->hbnr.init = NUM_HB;\n-\tcard->hbnr.max = MAX_HB;\n-\n-\tcard->sm_handle = NULL;\n-\tcard->sm_addr = 0x00000000;\n-\tcard->lg_handle = NULL;\n-\tcard->lg_addr = 0x00000000;\n-\n-\tcard->efbie = 1;\t/* To prevent push_rxbufs from enabling the interrupt */\n-\n-\tidr_init(&card->idr);\n-\n-\t/* Pre-allocate some huge buffers */\n-\tskb_queue_head_init(&card->hbpool.queue);\n-\tcard->hbpool.count = 0;\n-\tfor (j = 0; j < NUM_HB; j++) {\n-\t\tstruct sk_buff *hb;\n-\t\thb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);\n-\t\tif (hb == NULL) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: can't allocate %dth of %d huge buffers.\\n\",\n-\t\t\t i, j, NUM_HB);\n-\t\t\terror = 13;\n-\t\t\tns_init_card_error(card, error);\n-\t\t\treturn error;\n-\t\t}\n-\t\tNS_PRV_BUFTYPE(hb) = BUF_NONE;\n-\t\tskb_queue_tail(&card->hbpool.queue, hb);\n-\t\tcard->hbpool.count++;\n-\t}\n-\n-\t/* Allocate large buffers */\n-\tskb_queue_head_init(&card->lbpool.queue);\n-\tcard->lbpool.count = 0;\t/* Not used */\n-\tfor (j = 0; j < NUM_LB; j++) {\n-\t\tstruct sk_buff *lb;\n-\t\tlb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);\n-\t\tif (lb == NULL) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: can't allocate %dth of %d large buffers.\\n\",\n-\t\t\t i, j, NUM_LB);\n-\t\t\terror = 14;\n-\t\t\tns_init_card_error(card, error);\n-\t\t\treturn error;\n-\t\t}\n-\t\tNS_PRV_BUFTYPE(lb) = BUF_LG;\n-\t\tskb_queue_tail(&card->lbpool.queue, lb);\n-\t\tskb_reserve(lb, NS_SMBUFSIZE);\n-\t\tpush_rxbufs(card, lb);\n-\t\t/* Due to the implementation of push_rxbufs() this is 1, not 0 */\n-\t\tif (j == 1) {\n-\t\t\tcard->rcbuf = lb;\n-\t\t\tcard->rawcell = (struct ns_rcqe *) lb->data;\n-\t\t\tcard->rawch = NS_PRV_DMA(lb);\n-\t\t}\n-\t}\n-\t/* Test for strange behaviour which leads to crashes */\n-\tif ((bcount =\n-\t ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {\n-\t\tprintk\n-\t\t (\"nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\\n\",\n-\t\t i, j, bcount);\n-\t\terror = 14;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\n-\t/* Allocate small buffers */\n-\tskb_queue_head_init(&card->sbpool.queue);\n-\tcard->sbpool.count = 0;\t/* Not used */\n-\tfor (j = 0; j < NUM_SB; j++) {\n-\t\tstruct sk_buff *sb;\n-\t\tsb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);\n-\t\tif (sb == NULL) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: can't allocate %dth of %d small buffers.\\n\",\n-\t\t\t i, j, NUM_SB);\n-\t\t\terror = 15;\n-\t\t\tns_init_card_error(card, error);\n-\t\t\treturn error;\n-\t\t}\n-\t\tNS_PRV_BUFTYPE(sb) = BUF_SM;\n-\t\tskb_queue_tail(&card->sbpool.queue, sb);\n-\t\tskb_reserve(sb, NS_AAL0_HEADER);\n-\t\tpush_rxbufs(card, sb);\n-\t}\n-\t/* Test for strange behaviour which leads to crashes */\n-\tif ((bcount =\n-\t ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {\n-\t\tprintk\n-\t\t (\"nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\\n\",\n-\t\t i, j, bcount);\n-\t\terror = 15;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\n-\t/* Allocate iovec buffers */\n-\tskb_queue_head_init(&card->iovpool.queue);\n-\tcard->iovpool.count = 0;\n-\tfor (j = 0; j < NUM_IOVB; j++) {\n-\t\tstruct sk_buff *iovb;\n-\t\tiovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);\n-\t\tif (iovb == NULL) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: can't allocate %dth of %d iovec buffers.\\n\",\n-\t\t\t i, j, NUM_IOVB);\n-\t\t\terror = 16;\n-\t\t\tns_init_card_error(card, error);\n-\t\t\treturn error;\n-\t\t}\n-\t\tNS_PRV_BUFTYPE(iovb) = BUF_NONE;\n-\t\tskb_queue_tail(&card->iovpool.queue, iovb);\n-\t\tcard->iovpool.count++;\n-\t}\n-\n-\t/* Configure NICStAR */\n-\tif (card->rct_size == 4096)\n-\t\tns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;\n-\telse\t\t\t/* (card->rct_size == 16384) */\n-\t\tns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;\n-\n-\tcard->efbie = 1;\n-\n-\t/* Register device */\n-\tcard->atmdev = atm_dev_register(\"nicstar\", &card->pcidev->dev, &atm_ops,\n-\t\t\t\t\t-1, NULL);\n-\tif (card->atmdev == NULL) {\n-\t\tprintk(\"nicstar%d: can't register device.\\n\", i);\n-\t\terror = 17;\n-\t\tns_init_card_error(card, error);\n-\t\treturn error;\n-\t}\n-\n-\tif (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {\n-\t\tnicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,\n-\t\t\t\t card->atmdev->esi, 6);\n-\t\tif (ether_addr_equal(card->atmdev->esi, \"\\x00\\x00\\x00\\x00\\x00\\x00\")) {\n-\t\t\tnicstar_read_eprom(card->membase,\n-\t\t\t\t\t NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,\n-\t\t\t\t\t card->atmdev->esi, 6);\n-\t\t}\n-\t}\n-\n-\tprintk(\"nicstar%d: MAC address %pM\\n\", i, card->atmdev->esi);\n-\n-\tcard->atmdev->dev_data = card;\n-\tcard->atmdev->ci_range.vpi_bits = card->vpibits;\n-\tcard->atmdev->ci_range.vci_bits = card->vcibits;\n-\tcard->atmdev->link_rate = card->max_pcr;\n-\tcard->atmdev->phy = NULL;\n-\n-#ifdef CONFIG_ATM_NICSTAR_USE_SUNI\n-\tif (card->max_pcr == ATM_OC3_PCR)\n-\t\tsuni_init(card->atmdev);\n-#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */\n-\n-#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105\n-\tif (card->max_pcr == ATM_25_PCR)\n-\t\tidt77105_init(card->atmdev);\n-#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */\n-\n-\tif (card->atmdev->phy && card->atmdev->phy->start)\n-\t\tcard->atmdev->phy->start(card->atmdev);\n-\n-\twritel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE |\t/* Only enabled if RCQ_SUPPORT */\n-\t NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT |\t/* Only enabled if ENABLE_TSQFIE */\n-\t NS_CFG_PHYIE, card->membase + CFG);\n-\n-\tnum_cards++;\n-\n-\treturn error;\n-}\n-\n-static void ns_init_card_error(ns_dev *card, int error)\n-{\n-\tif (error >= 17) {\n-\t\twritel(0x00000000, card->membase + CFG);\n-\t}\n-\tif (error >= 16) {\n-\t\tstruct sk_buff *iovb;\n-\t\twhile ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)\n-\t\t\tdev_kfree_skb_any(iovb);\n-\t}\n-\tif (error >= 15) {\n-\t\tstruct sk_buff *sb;\n-\t\twhile ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)\n-\t\t\tdev_kfree_skb_any(sb);\n-\t\tfree_scq(card, card->scq0, NULL);\n-\t}\n-\tif (error >= 14) {\n-\t\tstruct sk_buff *lb;\n-\t\twhile ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)\n-\t\t\tdev_kfree_skb_any(lb);\n-\t}\n-\tif (error >= 13) {\n-\t\tstruct sk_buff *hb;\n-\t\twhile ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)\n-\t\t\tdev_kfree_skb_any(hb);\n-\t}\n-\tif (error >= 12) {\n-\t\tdma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,\n-\t\t\t\tcard->rsq.org, card->rsq.dma);\n-\t}\n-\tif (error >= 11) {\n-\t\tdma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,\n-\t\t\t\tcard->tsq.org, card->tsq.dma);\n-\t}\n-\tif (error >= 10) {\n-\t\tfree_irq(card->pcidev->irq, card);\n-\t}\n-\tif (error >= 4) {\n-\t\tiounmap(card->membase);\n-\t}\n-\tif (error >= 3) {\n-\t\tpci_disable_device(card->pcidev);\n-\t\tkfree(card);\n-\t}\n-}\n-\n-static scq_info *get_scq(ns_dev *card, int size, u32 scd)\n-{\n-\tscq_info *scq;\n-\n-\tif (size != VBR_SCQSIZE && size != CBR_SCQSIZE)\n-\t\treturn NULL;\n-\n-\tscq = kmalloc_obj(*scq);\n-\tif (!scq)\n-\t\treturn NULL;\n- scq->org = dma_alloc_coherent(&card->pcidev->dev,\n-\t\t\t\t 2 * size, &scq->dma, GFP_KERNEL);\n-\tif (!scq->org) {\n-\t\tkfree(scq);\n-\t\treturn NULL;\n-\t}\n-\tscq->skb = kzalloc_objs(*scq->skb, size / NS_SCQE_SIZE);\n-\tif (!scq->skb) {\n-\t\tdma_free_coherent(&card->pcidev->dev,\n-\t\t\t\t 2 * size, scq->org, scq->dma);\n-\t\tkfree(scq);\n-\t\treturn NULL;\n-\t}\n-\tscq->num_entries = size / NS_SCQE_SIZE;\n-\tscq->base = PTR_ALIGN(scq->org, size);\n-\tscq->next = scq->base;\n-\tscq->last = scq->base + (scq->num_entries - 1);\n-\tscq->tail = scq->last;\n-\tscq->scd = scd;\n-\tscq->tbd_count = 0;\n-\tinit_waitqueue_head(&scq->scqfull_waitq);\n-\tscq->full = 0;\n-\tspin_lock_init(&scq->lock);\n-\n-\treturn scq;\n-}\n-\n-/* For variable rate SCQ vcc must be NULL */\n-static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)\n-{\n-\tint i;\n-\n-\tif (scq->num_entries == VBR_SCQ_NUM_ENTRIES)\n-\t\tfor (i = 0; i < scq->num_entries; i++) {\n-\t\t\tif (scq->skb[i] != NULL) {\n-\t\t\t\tvcc = ATM_SKB(scq->skb[i])->vcc;\n-\t\t\t\tif (vcc->pop != NULL)\n-\t\t\t\t\tvcc->pop(vcc, scq->skb[i]);\n-\t\t\t\telse\n-\t\t\t\t\tdev_kfree_skb_any(scq->skb[i]);\n-\t\t\t}\n-\t} else {\t\t/* vcc must be != NULL */\n-\n-\t\tif (vcc == NULL) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar: free_scq() called with vcc == NULL for fixed rate scq.\");\n-\t\t\tfor (i = 0; i < scq->num_entries; i++)\n-\t\t\t\tdev_kfree_skb_any(scq->skb[i]);\n-\t\t} else\n-\t\t\tfor (i = 0; i < scq->num_entries; i++) {\n-\t\t\t\tif (scq->skb[i] != NULL) {\n-\t\t\t\t\tif (vcc->pop != NULL)\n-\t\t\t\t\t\tvcc->pop(vcc, scq->skb[i]);\n-\t\t\t\t\telse\n-\t\t\t\t\t\tdev_kfree_skb_any(scq->skb[i]);\n-\t\t\t\t}\n-\t\t\t}\n-\t}\n-\tkfree(scq->skb);\n-\tdma_free_coherent(&card->pcidev->dev,\n-\t\t\t 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?\n-\t\t\t VBR_SCQSIZE : CBR_SCQSIZE),\n-\t\t\t scq->org, scq->dma);\n-\tkfree(scq);\n-}\n-\n-/* The handles passed must be pointers to the sk_buff containing the small\n- or large buffer(s) cast to u32. */\n-static void push_rxbufs(ns_dev * card, struct sk_buff *skb)\n-{\n-\tstruct sk_buff *handle1, *handle2;\n-\tint id1, id2;\n-\tu32 addr1, addr2;\n-\tu32 stat;\n-\tunsigned long flags;\n-\n-\t/* *BARF* */\n-\thandle2 = NULL;\n-\taddr2 = 0;\n-\thandle1 = skb;\n-\taddr1 = dma_map_single(&card->pcidev->dev,\n-\t\t\t skb->data,\n-\t\t\t (NS_PRV_BUFTYPE(skb) == BUF_SM\n-\t\t\t\t? NS_SMSKBSIZE : NS_LGSKBSIZE),\n-\t\t\t DMA_TO_DEVICE);\n-\tNS_PRV_DMA(skb) = addr1; /* save so we can unmap later */\n-\n-#ifdef GENERAL_DEBUG\n-\tif (!addr1)\n-\t\tprintk(\"nicstar%d: push_rxbufs called with addr1 = 0.\\n\",\n-\t\t card->index);\n-#endif /* GENERAL_DEBUG */\n-\n-\tstat = readl(card->membase + STAT);\n-\tcard->sbfqc = ns_stat_sfbqc_get(stat);\n-\tcard->lbfqc = ns_stat_lfbqc_get(stat);\n-\tif (NS_PRV_BUFTYPE(skb) == BUF_SM) {\n-\t\tif (!addr2) {\n-\t\t\tif (card->sm_addr) {\n-\t\t\t\taddr2 = card->sm_addr;\n-\t\t\t\thandle2 = card->sm_handle;\n-\t\t\t\tcard->sm_addr = 0x00000000;\n-\t\t\t\tcard->sm_handle = NULL;\n-\t\t\t} else {\t/* (!sm_addr) */\n-\n-\t\t\t\tcard->sm_addr = addr1;\n-\t\t\t\tcard->sm_handle = handle1;\n-\t\t\t}\n-\t\t}\n-\t} else {\t\t/* buf_type == BUF_LG */\n-\n-\t\tif (!addr2) {\n-\t\t\tif (card->lg_addr) {\n-\t\t\t\taddr2 = card->lg_addr;\n-\t\t\t\thandle2 = card->lg_handle;\n-\t\t\t\tcard->lg_addr = 0x00000000;\n-\t\t\t\tcard->lg_handle = NULL;\n-\t\t\t} else {\t/* (!lg_addr) */\n-\n-\t\t\t\tcard->lg_addr = addr1;\n-\t\t\t\tcard->lg_handle = handle1;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tif (addr2) {\n-\t\tif (NS_PRV_BUFTYPE(skb) == BUF_SM) {\n-\t\t\tif (card->sbfqc >= card->sbnr.max) {\n-\t\t\t\tskb_unlink(handle1, &card->sbpool.queue);\n-\t\t\t\tdev_kfree_skb_any(handle1);\n-\t\t\t\tskb_unlink(handle2, &card->sbpool.queue);\n-\t\t\t\tdev_kfree_skb_any(handle2);\n-\t\t\t\treturn;\n-\t\t\t} else\n-\t\t\t\tcard->sbfqc += 2;\n-\t\t} else {\t/* (buf_type == BUF_LG) */\n-\n-\t\t\tif (card->lbfqc >= card->lbnr.max) {\n-\t\t\t\tskb_unlink(handle1, &card->lbpool.queue);\n-\t\t\t\tdev_kfree_skb_any(handle1);\n-\t\t\t\tskb_unlink(handle2, &card->lbpool.queue);\n-\t\t\t\tdev_kfree_skb_any(handle2);\n-\t\t\t\treturn;\n-\t\t\t} else\n-\t\t\t\tcard->lbfqc += 2;\n-\t\t}\n-\n-\t\tid1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);\n-\t\tif (id1 < 0)\n-\t\t\tgoto out;\n-\n-\t\tid2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);\n-\t\tif (id2 < 0)\n-\t\t\tgoto out;\n-\n-\t\tspin_lock_irqsave(&card->res_lock, flags);\n-\t\twhile (CMD_BUSY(card)) ;\n-\t\twritel(addr2, card->membase + DR3);\n-\t\twritel(id2, card->membase + DR2);\n-\t\twritel(addr1, card->membase + DR1);\n-\t\twritel(id1, card->membase + DR0);\n-\t\twritel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),\n-\t\t card->membase + CMD);\n-\t\tspin_unlock_irqrestore(&card->res_lock, flags);\n-\n-\t\tXPRINTK(\"nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\\n\",\n-\t\t\tcard->index,\n-\t\t\t(NS_PRV_BUFTYPE(skb) == BUF_SM ? \"small\" : \"large\"),\n-\t\t\taddr1, addr2);\n-\t}\n-\n-\tif (!card->efbie && card->sbfqc >= card->sbnr.min &&\n-\t card->lbfqc >= card->lbnr.min) {\n-\t\tcard->efbie = 1;\n-\t\twritel((readl(card->membase + CFG) | NS_CFG_EFBIE),\n-\t\t card->membase + CFG);\n-\t}\n-\n-out:\n-\treturn;\n-}\n-\n-static irqreturn_t ns_irq_handler(int irq, void *dev_id)\n-{\n-\tu32 stat_r;\n-\tns_dev *card;\n-\tstruct atm_dev *dev;\n-\tunsigned long flags;\n-\n-\tcard = (ns_dev *) dev_id;\n-\tdev = card->atmdev;\n-\tcard->intcnt++;\n-\n-\tPRINTK(\"nicstar%d: NICStAR generated an interrupt\\n\", card->index);\n-\n-\tspin_lock_irqsave(&card->int_lock, flags);\n-\n-\tstat_r = readl(card->membase + STAT);\n-\n-\t/* Transmit Status Indicator has been written to T. S. Queue */\n-\tif (stat_r & NS_STAT_TSIF) {\n-\t\tTXPRINTK(\"nicstar%d: TSI interrupt\\n\", card->index);\n-\t\tprocess_tsq(card);\n-\t\twritel(NS_STAT_TSIF, card->membase + STAT);\n-\t}\n-\n-\t/* Incomplete CS-PDU has been transmitted */\n-\tif (stat_r & NS_STAT_TXICP) {\n-\t\twritel(NS_STAT_TXICP, card->membase + STAT);\n-\t\tTXPRINTK(\"nicstar%d: Incomplete CS-PDU transmitted.\\n\",\n-\t\t\t card->index);\n-\t}\n-\n-\t/* Transmit Status Queue 7/8 full */\n-\tif (stat_r & NS_STAT_TSQF) {\n-\t\twritel(NS_STAT_TSQF, card->membase + STAT);\n-\t\tPRINTK(\"nicstar%d: TSQ full.\\n\", card->index);\n-\t\tprocess_tsq(card);\n-\t}\n-\n-\t/* Timer overflow */\n-\tif (stat_r & NS_STAT_TMROF) {\n-\t\twritel(NS_STAT_TMROF, card->membase + STAT);\n-\t\tPRINTK(\"nicstar%d: Timer overflow.\\n\", card->index);\n-\t}\n-\n-\t/* PHY device interrupt signal active */\n-\tif (stat_r & NS_STAT_PHYI) {\n-\t\twritel(NS_STAT_PHYI, card->membase + STAT);\n-\t\tPRINTK(\"nicstar%d: PHY interrupt.\\n\", card->index);\n-\t\tif (dev->phy && dev->phy->interrupt) {\n-\t\t\tdev->phy->interrupt(dev);\n-\t\t}\n-\t}\n-\n-\t/* Small Buffer Queue is full */\n-\tif (stat_r & NS_STAT_SFBQF) {\n-\t\twritel(NS_STAT_SFBQF, card->membase + STAT);\n-\t\tprintk(\"nicstar%d: Small free buffer queue is full.\\n\",\n-\t\t card->index);\n-\t}\n-\n-\t/* Large Buffer Queue is full */\n-\tif (stat_r & NS_STAT_LFBQF) {\n-\t\twritel(NS_STAT_LFBQF, card->membase + STAT);\n-\t\tprintk(\"nicstar%d: Large free buffer queue is full.\\n\",\n-\t\t card->index);\n-\t}\n-\n-\t/* Receive Status Queue is full */\n-\tif (stat_r & NS_STAT_RSQF) {\n-\t\twritel(NS_STAT_RSQF, card->membase + STAT);\n-\t\tprintk(\"nicstar%d: RSQ full.\\n\", card->index);\n-\t\tprocess_rsq(card);\n-\t}\n-\n-\t/* Complete CS-PDU received */\n-\tif (stat_r & NS_STAT_EOPDU) {\n-\t\tRXPRINTK(\"nicstar%d: End of CS-PDU received.\\n\", card->index);\n-\t\tprocess_rsq(card);\n-\t\twritel(NS_STAT_EOPDU, card->membase + STAT);\n-\t}\n-\n-\t/* Raw cell received */\n-\tif (stat_r & NS_STAT_RAWCF) {\n-\t\twritel(NS_STAT_RAWCF, card->membase + STAT);\n-#ifndef RCQ_SUPPORT\n-\t\tprintk(\"nicstar%d: Raw cell received and no support yet...\\n\",\n-\t\t card->index);\n-#endif /* RCQ_SUPPORT */\n-\t\t/* NOTE: the following procedure may keep a raw cell pending until the\n-\t\t next interrupt. As this preliminary support is only meant to\n-\t\t avoid buffer leakage, this is not an issue. */\n-\t\twhile (readl(card->membase + RAWCT) != card->rawch) {\n-\n-\t\t\tif (ns_rcqe_islast(card->rawcell)) {\n-\t\t\t\tstruct sk_buff *oldbuf;\n-\n-\t\t\t\toldbuf = card->rcbuf;\n-\t\t\t\tcard->rcbuf = idr_find(&card->idr,\n-\t\t\t\t\t\t ns_rcqe_nextbufhandle(card->rawcell));\n-\t\t\t\tcard->rawch = NS_PRV_DMA(card->rcbuf);\n-\t\t\t\tcard->rawcell = (struct ns_rcqe *)\n-\t\t\t\t\t\tcard->rcbuf->data;\n-\t\t\t\trecycle_rx_buf(card, oldbuf);\n-\t\t\t} else {\n-\t\t\t\tcard->rawch += NS_RCQE_SIZE;\n-\t\t\t\tcard->rawcell++;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\t/* Small buffer queue is empty */\n-\tif (stat_r & NS_STAT_SFBQE) {\n-\t\tint i;\n-\t\tstruct sk_buff *sb;\n-\n-\t\twritel(NS_STAT_SFBQE, card->membase + STAT);\n-\t\tprintk(\"nicstar%d: Small free buffer queue empty.\\n\",\n-\t\t card->index);\n-\t\tfor (i = 0; i < card->sbnr.min; i++) {\n-\t\t\tsb = dev_alloc_skb(NS_SMSKBSIZE);\n-\t\t\tif (sb == NULL) {\n-\t\t\t\twritel(readl(card->membase + CFG) &\n-\t\t\t\t ~NS_CFG_EFBIE, card->membase + CFG);\n-\t\t\t\tcard->efbie = 0;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tNS_PRV_BUFTYPE(sb) = BUF_SM;\n-\t\t\tskb_queue_tail(&card->sbpool.queue, sb);\n-\t\t\tskb_reserve(sb, NS_AAL0_HEADER);\n-\t\t\tpush_rxbufs(card, sb);\n-\t\t}\n-\t\tcard->sbfqc = i;\n-\t\tprocess_rsq(card);\n-\t}\n-\n-\t/* Large buffer queue empty */\n-\tif (stat_r & NS_STAT_LFBQE) {\n-\t\tint i;\n-\t\tstruct sk_buff *lb;\n-\n-\t\twritel(NS_STAT_LFBQE, card->membase + STAT);\n-\t\tprintk(\"nicstar%d: Large free buffer queue empty.\\n\",\n-\t\t card->index);\n-\t\tfor (i = 0; i < card->lbnr.min; i++) {\n-\t\t\tlb = dev_alloc_skb(NS_LGSKBSIZE);\n-\t\t\tif (lb == NULL) {\n-\t\t\t\twritel(readl(card->membase + CFG) &\n-\t\t\t\t ~NS_CFG_EFBIE, card->membase + CFG);\n-\t\t\t\tcard->efbie = 0;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tNS_PRV_BUFTYPE(lb) = BUF_LG;\n-\t\t\tskb_queue_tail(&card->lbpool.queue, lb);\n-\t\t\tskb_reserve(lb, NS_SMBUFSIZE);\n-\t\t\tpush_rxbufs(card, lb);\n-\t\t}\n-\t\tcard->lbfqc = i;\n-\t\tprocess_rsq(card);\n-\t}\n-\n-\t/* Receive Status Queue is 7/8 full */\n-\tif (stat_r & NS_STAT_RSQAF) {\n-\t\twritel(NS_STAT_RSQAF, card->membase + STAT);\n-\t\tRXPRINTK(\"nicstar%d: RSQ almost full.\\n\", card->index);\n-\t\tprocess_rsq(card);\n-\t}\n-\n-\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\tPRINTK(\"nicstar%d: end of interrupt service\\n\", card->index);\n-\treturn IRQ_HANDLED;\n-}\n-\n-static int ns_open(struct atm_vcc *vcc)\n-{\n-\tns_dev *card;\n-\tvc_map *vc;\n-\tunsigned long tmpl, modl;\n-\tint tcr, tcra;\t\t/* target cell rate, and absolute value */\n-\tint n = 0;\t\t/* Number of entries in the TST. Initialized to remove\n-\t\t\t\t the compiler warning. */\n-\tu32 u32d[4];\n-\tint frscdi = 0;\t\t/* Index of the SCD. Initialized to remove the compiler\n-\t\t\t\t warning. How I wish compilers were clever enough to\n-\t\t\t\t tell which variables can truly be used\n-\t\t\t\t uninitialized... */\n-\tint inuse;\t\t/* tx or rx vc already in use by another vcc */\n-\tshort vpi = vcc->vpi;\n-\tint vci = vcc->vci;\n-\n-\tcard = (ns_dev *) vcc->dev->dev_data;\n-\tPRINTK(\"nicstar%d: opening vpi.vci %d.%d \\n\", card->index, (int)vpi,\n-\t vci);\n-\tif (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {\n-\t\tPRINTK(\"nicstar%d: unsupported AAL.\\n\", card->index);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tvc = &(card->vcmap[vpi << card->vcibits | vci]);\n-\tvcc->dev_data = vc;\n-\n-\tinuse = 0;\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)\n-\t\tinuse = 1;\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)\n-\t\tinuse += 2;\n-\tif (inuse) {\n-\t\tprintk(\"nicstar%d: %s vci already in use.\\n\", card->index,\n-\t\t inuse == 1 ? \"tx\" : inuse == 2 ? \"rx\" : \"tx and rx\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tset_bit(ATM_VF_ADDR, &vcc->flags);\n-\n-\t/* NOTE: You are not allowed to modify an open connection's QOS. To change\n-\t that, remove the ATM_VF_PARTIAL flag checking. There may be other changes\n-\t needed to do that. */\n-\tif (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {\n-\t\tscq_info *scq;\n-\n-\t\tset_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\tif (vcc->qos.txtp.traffic_class == ATM_CBR) {\n-\t\t\t/* Check requested cell rate and availability of SCD */\n-\t\t\tif (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0\n-\t\t\t && vcc->qos.txtp.min_pcr == 0) {\n-\t\t\t\tPRINTK\n-\t\t\t\t (\"nicstar%d: trying to open a CBR vc with cell rate = 0 \\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\t\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\n-\t\t\ttcr = atm_pcr_goal(&(vcc->qos.txtp));\n-\t\t\ttcra = tcr >= 0 ? tcr : -tcr;\n-\n-\t\t\tPRINTK(\"nicstar%d: target cell rate = %d.\\n\",\n-\t\t\t card->index, vcc->qos.txtp.max_pcr);\n-\n-\t\t\ttmpl =\n-\t\t\t (unsigned long)tcra *(unsigned long)\n-\t\t\t NS_TST_NUM_ENTRIES;\n-\t\t\tmodl = tmpl % card->max_pcr;\n-\n-\t\t\tn = (int)(tmpl / card->max_pcr);\n-\t\t\tif (tcr > 0) {\n-\t\t\t\tif (modl > 0)\n-\t\t\t\t\tn++;\n-\t\t\t} else if (tcr == 0) {\n-\t\t\t\tif ((n =\n-\t\t\t\t (card->tst_free_entries -\n-\t\t\t\t NS_TST_RESERVED)) <= 0) {\n-\t\t\t\t\tPRINTK\n-\t\t\t\t\t (\"nicstar%d: no CBR bandwidth free.\\n\",\n-\t\t\t\t\t card->index);\n-\t\t\t\t\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\t\t\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t\t\t\t\treturn -EINVAL;\n-\t\t\t\t}\n-\t\t\t}\n-\n-\t\t\tif (n == 0) {\n-\t\t\t\tprintk\n-\t\t\t\t (\"nicstar%d: selected bandwidth < granularity.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\t\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\n-\t\t\tif (n > (card->tst_free_entries - NS_TST_RESERVED)) {\n-\t\t\t\tPRINTK\n-\t\t\t\t (\"nicstar%d: not enough free CBR bandwidth.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\t\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t} else\n-\t\t\t\tcard->tst_free_entries -= n;\n-\n-\t\t\tXPRINTK(\"nicstar%d: writing %d tst entries.\\n\",\n-\t\t\t\tcard->index, n);\n-\t\t\tfor (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {\n-\t\t\t\tif (card->scd2vc[frscdi] == NULL) {\n-\t\t\t\t\tcard->scd2vc[frscdi] = vc;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tif (frscdi == NS_FRSCD_NUM) {\n-\t\t\t\tPRINTK\n-\t\t\t\t (\"nicstar%d: no SCD available for CBR channel.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tcard->tst_free_entries += n;\n-\t\t\t\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\t\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t\t\t\treturn -EBUSY;\n-\t\t\t}\n-\n-\t\t\tvc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;\n-\n-\t\t\tscq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);\n-\t\t\tif (scq == NULL) {\n-\t\t\t\tPRINTK(\"nicstar%d: can't get fixed rate SCQ.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tcard->scd2vc[frscdi] = NULL;\n-\t\t\t\tcard->tst_free_entries += n;\n-\t\t\t\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\t\t\t\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\t\t\t\treturn -ENOMEM;\n-\t\t\t}\n-\t\t\tvc->scq = scq;\n-\t\t\tu32d[0] = scq_virt_to_bus(scq, scq->base);\n-\t\t\tu32d[1] = (u32) 0x00000000;\n-\t\t\tu32d[2] = (u32) 0xffffffff;\n-\t\t\tu32d[3] = (u32) 0x00000000;\n-\t\t\tns_write_sram(card, vc->cbr_scd, u32d, 4);\n-\n-\t\t\tfill_tst(card, n, vc);\n-\t\t} else if (vcc->qos.txtp.traffic_class == ATM_UBR) {\n-\t\t\tvc->cbr_scd = 0x00000000;\n-\t\t\tvc->scq = card->scq0;\n-\t\t}\n-\n-\t\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\t\tvc->tx = 1;\n-\t\t\tvc->tx_vcc = vcc;\n-\t\t\tvc->tbd_count = 0;\n-\t\t}\n-\t\tif (vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\t\tu32 status;\n-\n-\t\t\tvc->rx = 1;\n-\t\t\tvc->rx_vcc = vcc;\n-\t\t\tvc->rx_iov = NULL;\n-\n-\t\t\t/* Open the connection in hardware */\n-\t\t\tif (vcc->qos.aal == ATM_AAL5)\n-\t\t\t\tstatus = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;\n-\t\t\telse\t/* vcc->qos.aal == ATM_AAL0 */\n-\t\t\t\tstatus = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;\n-#ifdef RCQ_SUPPORT\n-\t\t\tstatus |= NS_RCTE_RAWCELLINTEN;\n-#endif /* RCQ_SUPPORT */\n-\t\t\tns_write_sram(card,\n-\t\t\t\t NS_RCT +\n-\t\t\t\t (vpi << card->vcibits | vci) *\n-\t\t\t\t NS_RCT_ENTRY_SIZE, &status, 1);\n-\t\t}\n-\n-\t}\n-\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\treturn 0;\n-}\n-\n-static void ns_close(struct atm_vcc *vcc)\n-{\n-\tvc_map *vc;\n-\tns_dev *card;\n-\tu32 data;\n-\tint i;\n-\n-\tvc = vcc->dev_data;\n-\tcard = vcc->dev->dev_data;\n-\tPRINTK(\"nicstar%d: closing vpi.vci %d.%d \\n\", card->index,\n-\t (int)vcc->vpi, vcc->vci);\n-\n-\tclear_bit(ATM_VF_READY, &vcc->flags);\n-\n-\tif (vcc->qos.rxtp.traffic_class != ATM_NONE) {\n-\t\tu32 addr;\n-\t\tunsigned long flags;\n-\n-\t\taddr =\n-\t\t NS_RCT +\n-\t\t (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;\n-\t\tspin_lock_irqsave(&card->res_lock, flags);\n-\t\twhile (CMD_BUSY(card)) ;\n-\t\twritel(NS_CMD_CLOSE_CONNECTION | addr << 2,\n-\t\t card->membase + CMD);\n-\t\tspin_unlock_irqrestore(&card->res_lock, flags);\n-\n-\t\tvc->rx = 0;\n-\t\tif (vc->rx_iov != NULL) {\n-\t\t\tstruct sk_buff *iovb;\n-\t\t\tu32 stat;\n-\n-\t\t\tstat = readl(card->membase + STAT);\n-\t\t\tcard->sbfqc = ns_stat_sfbqc_get(stat);\n-\t\t\tcard->lbfqc = ns_stat_lfbqc_get(stat);\n-\n-\t\t\tPRINTK\n-\t\t\t (\"nicstar%d: closing a VC with pending rx buffers.\\n\",\n-\t\t\t card->index);\n-\t\t\tiovb = vc->rx_iov;\n-\t\t\trecycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,\n-\t\t\t\t\t NS_PRV_IOVCNT(iovb));\n-\t\t\tNS_PRV_IOVCNT(iovb) = 0;\n-\t\t\tspin_lock_irqsave(&card->int_lock, flags);\n-\t\t\trecycle_iov_buf(card, iovb);\n-\t\t\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\t\t\tvc->rx_iov = NULL;\n-\t\t}\n-\t}\n-\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\tvc->tx = 0;\n-\t}\n-\n-\tif (vcc->qos.txtp.traffic_class == ATM_CBR) {\n-\t\tunsigned long flags;\n-\t\tns_scqe *scqep;\n-\t\tscq_info *scq;\n-\n-\t\tscq = vc->scq;\n-\n-\t\tfor (;;) {\n-\t\t\tspin_lock_irqsave(&scq->lock, flags);\n-\t\t\tscqep = scq->next;\n-\t\t\tif (scqep == scq->base)\n-\t\t\t\tscqep = scq->last;\n-\t\t\telse\n-\t\t\t\tscqep--;\n-\t\t\tif (scqep == scq->tail) {\n-\t\t\t\tspin_unlock_irqrestore(&scq->lock, flags);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\t/* If the last entry is not a TSR, place one in the SCQ in order to\n-\t\t\t be able to completely drain it and then close. */\n-\t\t\tif (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {\n-\t\t\t\tns_scqe tsr;\n-\t\t\t\tu32 scdi, scqi;\n-\t\t\t\tu32 data;\n-\t\t\t\tint index;\n-\n-\t\t\t\ttsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);\n-\t\t\t\tscdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;\n-\t\t\t\tscqi = scq->next - scq->base;\n-\t\t\t\ttsr.word_2 = ns_tsr_mkword_2(scdi, scqi);\n-\t\t\t\ttsr.word_3 = 0x00000000;\n-\t\t\t\ttsr.word_4 = 0x00000000;\n-\t\t\t\t*scq->next = tsr;\n-\t\t\t\tindex = (int)scqi;\n-\t\t\t\tscq->skb[index] = NULL;\n-\t\t\t\tif (scq->next == scq->last)\n-\t\t\t\t\tscq->next = scq->base;\n-\t\t\t\telse\n-\t\t\t\t\tscq->next++;\n-\t\t\t\tdata = scq_virt_to_bus(scq, scq->next);\n-\t\t\t\tns_write_sram(card, scq->scd, &data, 1);\n-\t\t\t}\n-\t\t\tspin_unlock_irqrestore(&scq->lock, flags);\n-\t\t\tschedule();\n-\t\t}\n-\n-\t\t/* Free all TST entries */\n-\t\tdata = NS_TST_OPCODE_VARIABLE;\n-\t\tfor (i = 0; i < NS_TST_NUM_ENTRIES; i++) {\n-\t\t\tif (card->tste2vc[i] == vc) {\n-\t\t\t\tns_write_sram(card, card->tst_addr + i, &data,\n-\t\t\t\t\t 1);\n-\t\t\t\tcard->tste2vc[i] = NULL;\n-\t\t\t\tcard->tst_free_entries++;\n-\t\t\t}\n-\t\t}\n-\n-\t\tcard->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;\n-\t\tfree_scq(card, vc->scq, vcc);\n-\t}\n-\n-\t/* remove all references to vcc before deleting it */\n-\tif (vcc->qos.txtp.traffic_class != ATM_NONE) {\n-\t\tunsigned long flags;\n-\t\tscq_info *scq = card->scq0;\n-\n-\t\tspin_lock_irqsave(&scq->lock, flags);\n-\n-\t\tfor (i = 0; i < scq->num_entries; i++) {\n-\t\t\tif (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {\n-\t\t\t\tATM_SKB(scq->skb[i])->vcc = NULL;\n-\t\t\t\tatm_return(vcc, scq->skb[i]->truesize);\n-\t\t\t\tPRINTK\n-\t\t\t\t (\"nicstar: deleted pending vcc mapping\\n\");\n-\t\t\t}\n-\t\t}\n-\n-\t\tspin_unlock_irqrestore(&scq->lock, flags);\n-\t}\n-\n-\tvcc->dev_data = NULL;\n-\tclear_bit(ATM_VF_PARTIAL, &vcc->flags);\n-\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\n-#ifdef RX_DEBUG\n-\t{\n-\t\tu32 stat, cfg;\n-\t\tstat = readl(card->membase + STAT);\n-\t\tcfg = readl(card->membase + CFG);\n-\t\tprintk(\"STAT = 0x%08X CFG = 0x%08X \\n\", stat, cfg);\n-\t\tprintk\n-\t\t (\"TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \\n\",\n-\t\t card->tsq.base, card->tsq.next,\n-\t\t card->tsq.last, readl(card->membase + TSQT));\n-\t\tprintk\n-\t\t (\"RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \\n\",\n-\t\t card->rsq.base, card->rsq.next,\n-\t\t card->rsq.last, readl(card->membase + RSQT));\n-\t\tprintk(\"Empty free buffer queue interrupt %s \\n\",\n-\t\t card->efbie ? \"enabled\" : \"disabled\");\n-\t\tprintk(\"SBCNT = %d count = %d LBCNT = %d count = %d \\n\",\n-\t\t ns_stat_sfbqc_get(stat), card->sbpool.count,\n-\t\t ns_stat_lfbqc_get(stat), card->lbpool.count);\n-\t\tprintk(\"hbpool.count = %d iovpool.count = %d \\n\",\n-\t\t card->hbpool.count, card->iovpool.count);\n-\t}\n-#endif /* RX_DEBUG */\n-}\n-\n-static void fill_tst(ns_dev * card, int n, vc_map * vc)\n-{\n-\tu32 new_tst;\n-\tunsigned long cl;\n-\tint e, r;\n-\tu32 data;\n-\n-\t/* It would be very complicated to keep the two TSTs synchronized while\n-\t assuring that writes are only made to the inactive TST. So, for now I\n-\t will use only one TST. If problems occur, I will change this again */\n-\n-\tnew_tst = card->tst_addr;\n-\n-\t/* Fill procedure */\n-\n-\tfor (e = 0; e < NS_TST_NUM_ENTRIES; e++) {\n-\t\tif (card->tste2vc[e] == NULL)\n-\t\t\tbreak;\n-\t}\n-\tif (e == NS_TST_NUM_ENTRIES) {\n-\t\tprintk(\"nicstar%d: No free TST entries found. \\n\", card->index);\n-\t\treturn;\n-\t}\n-\n-\tr = n;\n-\tcl = NS_TST_NUM_ENTRIES;\n-\tdata = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);\n-\n-\twhile (r > 0) {\n-\t\tif (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {\n-\t\t\tcard->tste2vc[e] = vc;\n-\t\t\tns_write_sram(card, new_tst + e, &data, 1);\n-\t\t\tcl -= NS_TST_NUM_ENTRIES;\n-\t\t\tr--;\n-\t\t}\n-\n-\t\tif (++e == NS_TST_NUM_ENTRIES) {\n-\t\t\te = 0;\n-\t\t}\n-\t\tcl += n;\n-\t}\n-\n-\t/* End of fill procedure */\n-\n-\tdata = ns_tste_make(NS_TST_OPCODE_END, new_tst);\n-\tns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);\n-\tns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);\n-\tcard->tst_addr = new_tst;\n-}\n-\n-static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)\n-{\n-\tns_dev *card;\n-\tvc_map *vc;\n-\tscq_info *scq;\n-\tunsigned long buflen;\n-\tns_scqe scqe;\n-\tu32 flags;\t\t/* TBD flags, not CPU flags */\n-\n-\tcard = vcc->dev->dev_data;\n-\tTXPRINTK(\"nicstar%d: ns_send() called.\\n\", card->index);\n-\tif ((vc = (vc_map *) vcc->dev_data) == NULL) {\n-\t\tprintk(\"nicstar%d: vcc->dev_data == NULL on ns_send().\\n\",\n-\t\t card->index);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!vc->tx) {\n-\t\tprintk(\"nicstar%d: Trying to transmit on a non-tx VC.\\n\",\n-\t\t card->index);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {\n-\t\tprintk(\"nicstar%d: Only AAL0 and AAL5 are supported.\\n\",\n-\t\t card->index);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (skb_shinfo(skb)->nr_frags != 0) {\n-\t\tprintk(\"nicstar%d: No scatter-gather yet.\\n\", card->index);\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tATM_SKB(skb)->vcc = vcc;\n-\n-\tNS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,\n-\t\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\n-\tif (vcc->qos.aal == ATM_AAL5) {\n-\t\tbuflen = (skb->len + 47 + 8) / 48 * 48;\t/* Multiple of 48 */\n-\t\tflags = NS_TBD_AAL5;\n-\t\tscqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));\n-\t\tscqe.word_3 = cpu_to_le32(skb->len);\n-\t\tscqe.word_4 =\n-\t\t ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,\n-\t\t\t\t ATM_SKB(skb)->\n-\t\t\t\t atm_options & ATM_ATMOPT_CLP ? 1 : 0);\n-\t\tflags |= NS_TBD_EOPDU;\n-\t} else {\t\t/* (vcc->qos.aal == ATM_AAL0) */\n-\n-\t\tbuflen = ATM_CELL_PAYLOAD;\t/* i.e., 48 bytes */\n-\t\tflags = NS_TBD_AAL0;\n-\t\tscqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);\n-\t\tscqe.word_3 = cpu_to_le32(0x00000000);\n-\t\tif (*skb->data & 0x02)\t/* Payload type 1 - end of pdu */\n-\t\t\tflags |= NS_TBD_EOPDU;\n-\t\tscqe.word_4 =\n-\t\t cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);\n-\t\t/* Force the VPI/VCI to be the same as in VCC struct */\n-\t\tscqe.word_4 |=\n-\t\t cpu_to_le32((((u32) vcc->\n-\t\t\t\t vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->\n-\t\t\t\t\t\t\t vci) <<\n-\t\t\t\t NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);\n-\t}\n-\n-\tif (vcc->qos.txtp.traffic_class == ATM_CBR) {\n-\t\tscqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);\n-\t\tscq = ((vc_map *) vcc->dev_data)->scq;\n-\t} else {\n-\t\tscqe.word_1 =\n-\t\t ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);\n-\t\tscq = card->scq0;\n-\t}\n-\n-\tif (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {\n-\t\tatomic_inc(&vcc->stats->tx_err);\n-\t\tdma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,\n-\t\t\t\t DMA_TO_DEVICE);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn -EIO;\n-\t}\n-\tatomic_inc(&vcc->stats->tx);\n-\n-\treturn 0;\n-}\n-\n-static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\treturn _ns_send(vcc, skb, true);\n-}\n-\n-static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\treturn _ns_send(vcc, skb, false);\n-}\n-\n-static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,\n-\t\t struct sk_buff *skb, bool may_sleep)\n-{\n-\tunsigned long flags;\n-\tns_scqe tsr;\n-\tu32 scdi, scqi;\n-\tint scq_is_vbr;\n-\tu32 data;\n-\tint index;\n-\n-\tspin_lock_irqsave(&scq->lock, flags);\n-\twhile (scq->tail == scq->next) {\n-\t\tif (!may_sleep) {\n-\t\t\tspin_unlock_irqrestore(&scq->lock, flags);\n-\t\t\tprintk(\"nicstar%d: Error pushing TBD.\\n\", card->index);\n-\t\t\treturn 1;\n-\t\t}\n-\n-\t\tscq->full = 1;\n-\t\twait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,\n-\t\t\t\t\t\t\t scq->tail != scq->next,\n-\t\t\t\t\t\t\t scq->lock,\n-\t\t\t\t\t\t\t SCQFULL_TIMEOUT);\n-\n-\t\tif (scq->full) {\n-\t\t\tspin_unlock_irqrestore(&scq->lock, flags);\n-\t\t\tprintk(\"nicstar%d: Timeout pushing TBD.\\n\",\n-\t\t\t card->index);\n-\t\t\treturn 1;\n-\t\t}\n-\t}\n-\t*scq->next = *tbd;\n-\tindex = (int)(scq->next - scq->base);\n-\tscq->skb[index] = skb;\n-\tXPRINTK(\"nicstar%d: sending skb at 0x%p (pos %d).\\n\",\n-\t\tcard->index, skb, index);\n-\tXPRINTK(\"nicstar%d: TBD written:\\n0x%x\\n0x%x\\n0x%x\\n0x%x\\n at 0x%p.\\n\",\n-\t\tcard->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),\n-\t\tle32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),\n-\t\tscq->next);\n-\tif (scq->next == scq->last)\n-\t\tscq->next = scq->base;\n-\telse\n-\t\tscq->next++;\n-\n-\tvc->tbd_count++;\n-\tif (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {\n-\t\tscq->tbd_count++;\n-\t\tscq_is_vbr = 1;\n-\t} else\n-\t\tscq_is_vbr = 0;\n-\n-\tif (vc->tbd_count >= MAX_TBD_PER_VC\n-\t || scq->tbd_count >= MAX_TBD_PER_SCQ) {\n-\t\tint has_run = 0;\n-\n-\t\twhile (scq->tail == scq->next) {\n-\t\t\tif (!may_sleep) {\n-\t\t\t\tdata = scq_virt_to_bus(scq, scq->next);\n-\t\t\t\tns_write_sram(card, scq->scd, &data, 1);\n-\t\t\t\tspin_unlock_irqrestore(&scq->lock, flags);\n-\t\t\t\tprintk(\"nicstar%d: Error pushing TSR.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tscq->full = 1;\n-\t\t\tif (has_run++)\n-\t\t\t\tbreak;\n-\t\t\twait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,\n-\t\t\t\t\t\t\t\t scq->tail != scq->next,\n-\t\t\t\t\t\t\t\t scq->lock,\n-\t\t\t\t\t\t\t\t SCQFULL_TIMEOUT);\n-\t\t}\n-\n-\t\tif (!scq->full) {\n-\t\t\ttsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);\n-\t\t\tif (scq_is_vbr)\n-\t\t\t\tscdi = NS_TSR_SCDISVBR;\n-\t\t\telse\n-\t\t\t\tscdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;\n-\t\t\tscqi = scq->next - scq->base;\n-\t\t\ttsr.word_2 = ns_tsr_mkword_2(scdi, scqi);\n-\t\t\ttsr.word_3 = 0x00000000;\n-\t\t\ttsr.word_4 = 0x00000000;\n-\n-\t\t\t*scq->next = tsr;\n-\t\t\tindex = (int)scqi;\n-\t\t\tscq->skb[index] = NULL;\n-\t\t\tXPRINTK\n-\t\t\t (\"nicstar%d: TSR written:\\n0x%x\\n0x%x\\n0x%x\\n0x%x\\n at 0x%p.\\n\",\n-\t\t\t card->index, le32_to_cpu(tsr.word_1),\n-\t\t\t le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),\n-\t\t\t le32_to_cpu(tsr.word_4), scq->next);\n-\t\t\tif (scq->next == scq->last)\n-\t\t\t\tscq->next = scq->base;\n-\t\t\telse\n-\t\t\t\tscq->next++;\n-\t\t\tvc->tbd_count = 0;\n-\t\t\tscq->tbd_count = 0;\n-\t\t} else\n-\t\t\tPRINTK(\"nicstar%d: Timeout pushing TSR.\\n\",\n-\t\t\t card->index);\n-\t}\n-\tdata = scq_virt_to_bus(scq, scq->next);\n-\tns_write_sram(card, scq->scd, &data, 1);\n-\n-\tspin_unlock_irqrestore(&scq->lock, flags);\n-\n-\treturn 0;\n-}\n-\n-static void process_tsq(ns_dev * card)\n-{\n-\tu32 scdi;\n-\tscq_info *scq;\n-\tns_tsi *previous = NULL, *one_ahead, *two_ahead;\n-\tint serviced_entries;\t/* flag indicating at least on entry was serviced */\n-\n-\tserviced_entries = 0;\n-\n-\tif (card->tsq.next == card->tsq.last)\n-\t\tone_ahead = card->tsq.base;\n-\telse\n-\t\tone_ahead = card->tsq.next + 1;\n-\n-\tif (one_ahead == card->tsq.last)\n-\t\ttwo_ahead = card->tsq.base;\n-\telse\n-\t\ttwo_ahead = one_ahead + 1;\n-\n-\twhile (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||\n-\t !ns_tsi_isempty(two_ahead))\n-\t\t/* At most two empty, as stated in the 77201 errata */\n-\t{\n-\t\tserviced_entries = 1;\n-\n-\t\t/* Skip the one or two possible empty entries */\n-\t\twhile (ns_tsi_isempty(card->tsq.next)) {\n-\t\t\tif (card->tsq.next == card->tsq.last)\n-\t\t\t\tcard->tsq.next = card->tsq.base;\n-\t\t\telse\n-\t\t\t\tcard->tsq.next++;\n-\t\t}\n-\n-\t\tif (!ns_tsi_tmrof(card->tsq.next)) {\n-\t\t\tscdi = ns_tsi_getscdindex(card->tsq.next);\n-\t\t\tif (scdi == NS_TSI_SCDISVBR)\n-\t\t\t\tscq = card->scq0;\n-\t\t\telse {\n-\t\t\t\tif (card->scd2vc[scdi] == NULL) {\n-\t\t\t\t\tprintk\n-\t\t\t\t\t (\"nicstar%d: could not find VC from SCD index.\\n\",\n-\t\t\t\t\t card->index);\n-\t\t\t\t\tns_tsi_init(card->tsq.next);\n-\t\t\t\t\treturn;\n-\t\t\t\t}\n-\t\t\t\tscq = card->scd2vc[scdi]->scq;\n-\t\t\t}\n-\t\t\tdrain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));\n-\t\t\tscq->full = 0;\n-\t\t\twake_up_interruptible(&(scq->scqfull_waitq));\n-\t\t}\n-\n-\t\tns_tsi_init(card->tsq.next);\n-\t\tprevious = card->tsq.next;\n-\t\tif (card->tsq.next == card->tsq.last)\n-\t\t\tcard->tsq.next = card->tsq.base;\n-\t\telse\n-\t\t\tcard->tsq.next++;\n-\n-\t\tif (card->tsq.next == card->tsq.last)\n-\t\t\tone_ahead = card->tsq.base;\n-\t\telse\n-\t\t\tone_ahead = card->tsq.next + 1;\n-\n-\t\tif (one_ahead == card->tsq.last)\n-\t\t\ttwo_ahead = card->tsq.base;\n-\t\telse\n-\t\t\ttwo_ahead = one_ahead + 1;\n-\t}\n-\n-\tif (serviced_entries)\n-\t\twritel(PTR_DIFF(previous, card->tsq.base),\n-\t\t card->membase + TSQH);\n-}\n-\n-static void drain_scq(ns_dev * card, scq_info * scq, int pos)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct sk_buff *skb;\n-\tint i;\n-\tunsigned long flags;\n-\n-\tXPRINTK(\"nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\\n\",\n-\t\tcard->index, scq, pos);\n-\tif (pos >= scq->num_entries) {\n-\t\tprintk(\"nicstar%d: Bad index on drain_scq().\\n\", card->index);\n-\t\treturn;\n-\t}\n-\n-\tspin_lock_irqsave(&scq->lock, flags);\n-\ti = (int)(scq->tail - scq->base);\n-\tif (++i == scq->num_entries)\n-\t\ti = 0;\n-\twhile (i != pos) {\n-\t\tskb = scq->skb[i];\n-\t\tXPRINTK(\"nicstar%d: freeing skb at 0x%p (index %d).\\n\",\n-\t\t\tcard->index, skb, i);\n-\t\tif (skb != NULL) {\n-\t\t\tdma_unmap_single(&card->pcidev->dev,\n-\t\t\t\t\t NS_PRV_DMA(skb),\n-\t\t\t\t\t skb->len,\n-\t\t\t\t\t DMA_TO_DEVICE);\n-\t\t\tvcc = ATM_SKB(skb)->vcc;\n-\t\t\tif (vcc && vcc->pop != NULL) {\n-\t\t\t\tvcc->pop(vcc, skb);\n-\t\t\t} else {\n-\t\t\t\tdev_kfree_skb_irq(skb);\n-\t\t\t}\n-\t\t\tscq->skb[i] = NULL;\n-\t\t}\n-\t\tif (++i == scq->num_entries)\n-\t\t\ti = 0;\n-\t}\n-\tscq->tail = scq->base + pos;\n-\tspin_unlock_irqrestore(&scq->lock, flags);\n-}\n-\n-static void process_rsq(ns_dev * card)\n-{\n-\tns_rsqe *previous;\n-\n-\tif (!ns_rsqe_valid(card->rsq.next))\n-\t\treturn;\n-\tdo {\n-\t\tdequeue_rx(card, card->rsq.next);\n-\t\tns_rsqe_init(card->rsq.next);\n-\t\tprevious = card->rsq.next;\n-\t\tif (card->rsq.next == card->rsq.last)\n-\t\t\tcard->rsq.next = card->rsq.base;\n-\t\telse\n-\t\t\tcard->rsq.next++;\n-\t} while (ns_rsqe_valid(card->rsq.next));\n-\twritel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);\n-}\n-\n-static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)\n-{\n-\tu32 vpi, vci;\n-\tvc_map *vc;\n-\tstruct sk_buff *iovb;\n-\tstruct iovec *iov;\n-\tstruct atm_vcc *vcc;\n-\tstruct sk_buff *skb;\n-\tunsigned short aal5_len;\n-\tint len;\n-\tu32 stat;\n-\tu32 id;\n-\n-\tstat = readl(card->membase + STAT);\n-\tcard->sbfqc = ns_stat_sfbqc_get(stat);\n-\tcard->lbfqc = ns_stat_lfbqc_get(stat);\n-\n-\tid = le32_to_cpu(rsqe->buffer_handle);\n-\tskb = idr_remove(&card->idr, id);\n-\tif (!skb) {\n-\t\tRXPRINTK(KERN_ERR\n-\t\t\t \"nicstar%d: skb not found!\\n\", card->index);\n-\t\treturn;\n-\t}\n-\tdma_sync_single_for_cpu(&card->pcidev->dev,\n-\t\t\t\tNS_PRV_DMA(skb),\n-\t\t\t\t(NS_PRV_BUFTYPE(skb) == BUF_SM\n-\t\t\t\t ? NS_SMSKBSIZE : NS_LGSKBSIZE),\n-\t\t\t\tDMA_FROM_DEVICE);\n-\tdma_unmap_single(&card->pcidev->dev,\n-\t\t\t NS_PRV_DMA(skb),\n-\t\t\t (NS_PRV_BUFTYPE(skb) == BUF_SM\n-\t\t\t ? NS_SMSKBSIZE : NS_LGSKBSIZE),\n-\t\t\t DMA_FROM_DEVICE);\n-\tvpi = ns_rsqe_vpi(rsqe);\n-\tvci = ns_rsqe_vci(rsqe);\n-\tif (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {\n-\t\tprintk(\"nicstar%d: SDU received for out-of-range vc %d.%d.\\n\",\n-\t\t card->index, vpi, vci);\n-\t\trecycle_rx_buf(card, skb);\n-\t\treturn;\n-\t}\n-\n-\tvc = &(card->vcmap[vpi << card->vcibits | vci]);\n-\tif (!vc->rx) {\n-\t\tRXPRINTK(\"nicstar%d: SDU received on non-rx vc %d.%d.\\n\",\n-\t\t\t card->index, vpi, vci);\n-\t\trecycle_rx_buf(card, skb);\n-\t\treturn;\n-\t}\n-\n-\tvcc = vc->rx_vcc;\n-\n-\tif (vcc->qos.aal == ATM_AAL0) {\n-\t\tstruct sk_buff *sb;\n-\t\tunsigned char *cell;\n-\t\tint i;\n-\n-\t\tcell = skb->data;\n-\t\tfor (i = ns_rsqe_cellcount(rsqe); i; i--) {\n-\t\t\tsb = dev_alloc_skb(NS_SMSKBSIZE);\n-\t\t\tif (!sb) {\n-\t\t\t\tprintk\n-\t\t\t\t (\"nicstar%d: Can't allocate buffers for aal0.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tatomic_add(i, &vcc->stats->rx_drop);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (!atm_charge(vcc, sb->truesize)) {\n-\t\t\t\tRXPRINTK\n-\t\t\t\t (\"nicstar%d: atm_charge() dropped aal0 packets.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tatomic_add(i - 1, &vcc->stats->rx_drop);\t/* already increased by 1 */\n-\t\t\t\tdev_kfree_skb_any(sb);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\t/* Rebuild the header */\n-\t\t\t*((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |\n-\t\t\t (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);\n-\t\t\tif (i == 1 && ns_rsqe_eopdu(rsqe))\n-\t\t\t\t*((u32 *) sb->data) |= 0x00000002;\n-\t\t\tskb_put(sb, NS_AAL0_HEADER);\n-\t\t\tmemcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);\n-\t\t\tskb_put(sb, ATM_CELL_PAYLOAD);\n-\t\t\tATM_SKB(sb)->vcc = vcc;\n-\t\t\t__net_timestamp(sb);\n-\t\t\tvcc->push(vcc, sb);\n-\t\t\tatomic_inc(&vcc->stats->rx);\n-\t\t\tcell += ATM_CELL_PAYLOAD;\n-\t\t}\n-\n-\t\trecycle_rx_buf(card, skb);\n-\t\treturn;\n-\t}\n-\n-\t/* To reach this point, the AAL layer can only be AAL5 */\n-\n-\tif ((iovb = vc->rx_iov) == NULL) {\n-\t\tiovb = skb_dequeue(&(card->iovpool.queue));\n-\t\tif (iovb == NULL) {\t/* No buffers in the queue */\n-\t\t\tiovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);\n-\t\t\tif (iovb == NULL) {\n-\t\t\t\tprintk(\"nicstar%d: Out of iovec buffers.\\n\",\n-\t\t\t\t card->index);\n-\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\t\trecycle_rx_buf(card, skb);\n-\t\t\t\treturn;\n-\t\t\t}\n-\t\t\tNS_PRV_BUFTYPE(iovb) = BUF_NONE;\n-\t\t} else if (--card->iovpool.count < card->iovnr.min) {\n-\t\t\tstruct sk_buff *new_iovb;\n-\t\t\tif ((new_iovb =\n-\t\t\t alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {\n-\t\t\t\tNS_PRV_BUFTYPE(iovb) = BUF_NONE;\n-\t\t\t\tskb_queue_tail(&card->iovpool.queue, new_iovb);\n-\t\t\t\tcard->iovpool.count++;\n-\t\t\t}\n-\t\t}\n-\t\tvc->rx_iov = iovb;\n-\t\tNS_PRV_IOVCNT(iovb) = 0;\n-\t\tiovb->len = 0;\n-\t\tiovb->data = iovb->head;\n-\t\tskb_reset_tail_pointer(iovb);\n-\t\t/* IMPORTANT: a pointer to the sk_buff containing the small or large\n-\t\t buffer is stored as iovec base, NOT a pointer to the\n-\t\t small or large buffer itself. */\n-\t} else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {\n-\t\tprintk(\"nicstar%d: received too big AAL5 SDU.\\n\", card->index);\n-\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\trecycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,\n-\t\t\t\t NS_MAX_IOVECS);\n-\t\tNS_PRV_IOVCNT(iovb) = 0;\n-\t\tiovb->len = 0;\n-\t\tiovb->data = iovb->head;\n-\t\tskb_reset_tail_pointer(iovb);\n-\t}\n-\tiov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];\n-\tiov->iov_base = (void *)skb;\n-\tiov->iov_len = ns_rsqe_cellcount(rsqe) * 48;\n-\tiovb->len += iov->iov_len;\n-\n-#ifdef EXTRA_DEBUG\n-\tif (NS_PRV_IOVCNT(iovb) == 1) {\n-\t\tif (NS_PRV_BUFTYPE(skb) != BUF_SM) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: Expected a small buffer, and this is not one.\\n\",\n-\t\t\t card->index);\n-\t\t\twhich_list(card, skb);\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\trecycle_rx_buf(card, skb);\n-\t\t\tvc->rx_iov = NULL;\n-\t\t\trecycle_iov_buf(card, iovb);\n-\t\t\treturn;\n-\t\t}\n-\t} else {\t\t/* NS_PRV_IOVCNT(iovb) >= 2 */\n-\n-\t\tif (NS_PRV_BUFTYPE(skb) != BUF_LG) {\n-\t\t\tprintk\n-\t\t\t (\"nicstar%d: Expected a large buffer, and this is not one.\\n\",\n-\t\t\t card->index);\n-\t\t\twhich_list(card, skb);\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\trecycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,\n-\t\t\t\t\t NS_PRV_IOVCNT(iovb));\n-\t\t\tvc->rx_iov = NULL;\n-\t\t\trecycle_iov_buf(card, iovb);\n-\t\t\treturn;\n-\t\t}\n-\t}\n-#endif /* EXTRA_DEBUG */\n-\n-\tif (ns_rsqe_eopdu(rsqe)) {\n-\t\t/* This works correctly regardless of the endianness of the host */\n-\t\tunsigned char *L1L2 = (unsigned char *)\n-\t\t\t\t\t\t(skb->data + iov->iov_len - 6);\n-\t\taal5_len = L1L2[0] << 8 | L1L2[1];\n-\t\tlen = (aal5_len == 0x0000) ? 0x10000 : aal5_len;\n-\t\tif (ns_rsqe_crcerr(rsqe) ||\n-\t\t len + 8 > iovb->len || len + (47 + 8) < iovb->len) {\n-\t\t\tprintk(\"nicstar%d: AAL5 CRC error\", card->index);\n-\t\t\tif (len + 8 > iovb->len || len + (47 + 8) < iovb->len)\n-\t\t\t\tprintk(\" - PDU size mismatch.\\n\");\n-\t\t\telse\n-\t\t\t\tprintk(\".\\n\");\n-\t\t\tatomic_inc(&vcc->stats->rx_err);\n-\t\t\trecycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,\n-\t\t\t\t\t NS_PRV_IOVCNT(iovb));\n-\t\t\tvc->rx_iov = NULL;\n-\t\t\trecycle_iov_buf(card, iovb);\n-\t\t\treturn;\n-\t\t}\n-\n-\t\t/* By this point we (hopefully) have a complete SDU without errors. */\n-\n-\t\tif (NS_PRV_IOVCNT(iovb) == 1) {\t/* Just a small buffer */\n-\t\t\t/* skb points to a small buffer */\n-\t\t\tif (!atm_charge(vcc, skb->truesize)) {\n-\t\t\t\tpush_rxbufs(card, skb);\n-\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\t} else {\n-\t\t\t\tskb_put(skb, len);\n-\t\t\t\tdequeue_sm_buf(card, skb);\n-\t\t\t\tATM_SKB(skb)->vcc = vcc;\n-\t\t\t\t__net_timestamp(skb);\n-\t\t\t\tvcc->push(vcc, skb);\n-\t\t\t\tatomic_inc(&vcc->stats->rx);\n-\t\t\t}\n-\t\t} else if (NS_PRV_IOVCNT(iovb) == 2) {\t/* One small plus one large buffer */\n-\t\t\tstruct sk_buff *sb;\n-\n-\t\t\tsb = (struct sk_buff *)(iov - 1)->iov_base;\n-\t\t\t/* skb points to a large buffer */\n-\n-\t\t\tif (len <= NS_SMBUFSIZE) {\n-\t\t\t\tif (!atm_charge(vcc, sb->truesize)) {\n-\t\t\t\t\tpush_rxbufs(card, sb);\n-\t\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\t\t} else {\n-\t\t\t\t\tskb_put(sb, len);\n-\t\t\t\t\tdequeue_sm_buf(card, sb);\n-\t\t\t\t\tATM_SKB(sb)->vcc = vcc;\n-\t\t\t\t\t__net_timestamp(sb);\n-\t\t\t\t\tvcc->push(vcc, sb);\n-\t\t\t\t\tatomic_inc(&vcc->stats->rx);\n-\t\t\t\t}\n-\n-\t\t\t\tpush_rxbufs(card, skb);\n-\n-\t\t\t} else {\t/* len > NS_SMBUFSIZE, the usual case */\n-\n-\t\t\t\tif (!atm_charge(vcc, skb->truesize)) {\n-\t\t\t\t\tpush_rxbufs(card, skb);\n-\t\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\t\t} else {\n-\t\t\t\t\tdequeue_lg_buf(card, skb);\n-\t\t\t\t\tskb_push(skb, NS_SMBUFSIZE);\n-\t\t\t\t\tskb_copy_from_linear_data(sb, skb->data,\n-\t\t\t\t\t\t\t\t NS_SMBUFSIZE);\n-\t\t\t\t\tskb_put(skb, len - NS_SMBUFSIZE);\n-\t\t\t\t\tATM_SKB(skb)->vcc = vcc;\n-\t\t\t\t\t__net_timestamp(skb);\n-\t\t\t\t\tvcc->push(vcc, skb);\n-\t\t\t\t\tatomic_inc(&vcc->stats->rx);\n-\t\t\t\t}\n-\n-\t\t\t\tpush_rxbufs(card, sb);\n-\n-\t\t\t}\n-\n-\t\t} else {\t/* Must push a huge buffer */\n-\n-\t\t\tstruct sk_buff *hb, *sb, *lb;\n-\t\t\tint remaining, tocopy;\n-\t\t\tint j;\n-\n-\t\t\thb = skb_dequeue(&(card->hbpool.queue));\n-\t\t\tif (hb == NULL) {\t/* No buffers in the queue */\n-\n-\t\t\t\thb = dev_alloc_skb(NS_HBUFSIZE);\n-\t\t\t\tif (hb == NULL) {\n-\t\t\t\t\tprintk\n-\t\t\t\t\t (\"nicstar%d: Out of huge buffers.\\n\",\n-\t\t\t\t\t card->index);\n-\t\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\t\t\trecycle_iovec_rx_bufs(card,\n-\t\t\t\t\t\t\t (struct iovec *)\n-\t\t\t\t\t\t\t iovb->data,\n-\t\t\t\t\t\t\t NS_PRV_IOVCNT(iovb));\n-\t\t\t\t\tvc->rx_iov = NULL;\n-\t\t\t\t\trecycle_iov_buf(card, iovb);\n-\t\t\t\t\treturn;\n-\t\t\t\t} else if (card->hbpool.count < card->hbnr.min) {\n-\t\t\t\t\tstruct sk_buff *new_hb;\n-\t\t\t\t\tif ((new_hb =\n-\t\t\t\t\t dev_alloc_skb(NS_HBUFSIZE)) !=\n-\t\t\t\t\t NULL) {\n-\t\t\t\t\t\tskb_queue_tail(&card->hbpool.\n-\t\t\t\t\t\t\t queue, new_hb);\n-\t\t\t\t\t\tcard->hbpool.count++;\n-\t\t\t\t\t}\n-\t\t\t\t}\n-\t\t\t\tNS_PRV_BUFTYPE(hb) = BUF_NONE;\n-\t\t\t} else if (--card->hbpool.count < card->hbnr.min) {\n-\t\t\t\tstruct sk_buff *new_hb;\n-\t\t\t\tif ((new_hb =\n-\t\t\t\t dev_alloc_skb(NS_HBUFSIZE)) != NULL) {\n-\t\t\t\t\tNS_PRV_BUFTYPE(new_hb) = BUF_NONE;\n-\t\t\t\t\tskb_queue_tail(&card->hbpool.queue,\n-\t\t\t\t\t\t new_hb);\n-\t\t\t\t\tcard->hbpool.count++;\n-\t\t\t\t}\n-\t\t\t\tif (card->hbpool.count < card->hbnr.min) {\n-\t\t\t\t\tif ((new_hb =\n-\t\t\t\t\t dev_alloc_skb(NS_HBUFSIZE)) !=\n-\t\t\t\t\t NULL) {\n-\t\t\t\t\t\tNS_PRV_BUFTYPE(new_hb) =\n-\t\t\t\t\t\t BUF_NONE;\n-\t\t\t\t\t\tskb_queue_tail(&card->hbpool.\n-\t\t\t\t\t\t\t queue, new_hb);\n-\t\t\t\t\t\tcard->hbpool.count++;\n-\t\t\t\t\t}\n-\t\t\t\t}\n-\t\t\t}\n-\n-\t\t\tiov = (struct iovec *)iovb->data;\n-\n-\t\t\tif (!atm_charge(vcc, hb->truesize)) {\n-\t\t\t\trecycle_iovec_rx_bufs(card, iov,\n-\t\t\t\t\t\t NS_PRV_IOVCNT(iovb));\n-\t\t\t\tif (card->hbpool.count < card->hbnr.max) {\n-\t\t\t\t\tskb_queue_tail(&card->hbpool.queue, hb);\n-\t\t\t\t\tcard->hbpool.count++;\n-\t\t\t\t} else\n-\t\t\t\t\tdev_kfree_skb_any(hb);\n-\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n-\t\t\t} else {\n-\t\t\t\t/* Copy the small buffer to the huge buffer */\n-\t\t\t\tsb = (struct sk_buff *)iov->iov_base;\n-\t\t\t\tskb_copy_from_linear_data(sb, hb->data,\n-\t\t\t\t\t\t\t iov->iov_len);\n-\t\t\t\tskb_put(hb, iov->iov_len);\n-\t\t\t\tremaining = len - iov->iov_len;\n-\t\t\t\tiov++;\n-\t\t\t\t/* Free the small buffer */\n-\t\t\t\tpush_rxbufs(card, sb);\n-\n-\t\t\t\t/* Copy all large buffers to the huge buffer and free them */\n-\t\t\t\tfor (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {\n-\t\t\t\t\tlb = (struct sk_buff *)iov->iov_base;\n-\t\t\t\t\ttocopy =\n-\t\t\t\t\t min_t(int, remaining, iov->iov_len);\n-\t\t\t\t\tskb_copy_from_linear_data(lb,\n-\t\t\t\t\t\t\t\t skb_tail_pointer\n-\t\t\t\t\t\t\t\t (hb), tocopy);\n-\t\t\t\t\tskb_put(hb, tocopy);\n-\t\t\t\t\tiov++;\n-\t\t\t\t\tremaining -= tocopy;\n-\t\t\t\t\tpush_rxbufs(card, lb);\n-\t\t\t\t}\n-#ifdef EXTRA_DEBUG\n-\t\t\t\tif (remaining != 0 || hb->len != len)\n-\t\t\t\t\tprintk\n-\t\t\t\t\t (\"nicstar%d: Huge buffer len mismatch.\\n\",\n-\t\t\t\t\t card->index);\n-#endif /* EXTRA_DEBUG */\n-\t\t\t\tATM_SKB(hb)->vcc = vcc;\n-\t\t\t\t__net_timestamp(hb);\n-\t\t\t\tvcc->push(vcc, hb);\n-\t\t\t\tatomic_inc(&vcc->stats->rx);\n-\t\t\t}\n-\t\t}\n-\n-\t\tvc->rx_iov = NULL;\n-\t\trecycle_iov_buf(card, iovb);\n-\t}\n-\n-}\n-\n-static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)\n-{\n-\tif (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {\n-\t\tprintk(\"nicstar%d: What kind of rx buffer is this?\\n\",\n-\t\t card->index);\n-\t\tdev_kfree_skb_any(skb);\n-\t} else\n-\t\tpush_rxbufs(card, skb);\n-}\n-\n-static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)\n-{\n-\twhile (count-- > 0)\n-\t\trecycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);\n-}\n-\n-static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)\n-{\n-\tif (card->iovpool.count < card->iovnr.max) {\n-\t\tskb_queue_tail(&card->iovpool.queue, iovb);\n-\t\tcard->iovpool.count++;\n-\t} else\n-\t\tdev_kfree_skb_any(iovb);\n-}\n-\n-static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)\n-{\n-\tskb_unlink(sb, &card->sbpool.queue);\n-\tif (card->sbfqc < card->sbnr.init) {\n-\t\tstruct sk_buff *new_sb;\n-\t\tif ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {\n-\t\t\tNS_PRV_BUFTYPE(new_sb) = BUF_SM;\n-\t\t\tskb_queue_tail(&card->sbpool.queue, new_sb);\n-\t\t\tskb_reserve(new_sb, NS_AAL0_HEADER);\n-\t\t\tpush_rxbufs(card, new_sb);\n-\t\t}\n-\t}\n-\tif (card->sbfqc < card->sbnr.init)\n-\t{\n-\t\tstruct sk_buff *new_sb;\n-\t\tif ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {\n-\t\t\tNS_PRV_BUFTYPE(new_sb) = BUF_SM;\n-\t\t\tskb_queue_tail(&card->sbpool.queue, new_sb);\n-\t\t\tskb_reserve(new_sb, NS_AAL0_HEADER);\n-\t\t\tpush_rxbufs(card, new_sb);\n-\t\t}\n-\t}\n-}\n-\n-static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)\n-{\n-\tskb_unlink(lb, &card->lbpool.queue);\n-\tif (card->lbfqc < card->lbnr.init) {\n-\t\tstruct sk_buff *new_lb;\n-\t\tif ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {\n-\t\t\tNS_PRV_BUFTYPE(new_lb) = BUF_LG;\n-\t\t\tskb_queue_tail(&card->lbpool.queue, new_lb);\n-\t\t\tskb_reserve(new_lb, NS_SMBUFSIZE);\n-\t\t\tpush_rxbufs(card, new_lb);\n-\t\t}\n-\t}\n-\tif (card->lbfqc < card->lbnr.init)\n-\t{\n-\t\tstruct sk_buff *new_lb;\n-\t\tif ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {\n-\t\t\tNS_PRV_BUFTYPE(new_lb) = BUF_LG;\n-\t\t\tskb_queue_tail(&card->lbpool.queue, new_lb);\n-\t\t\tskb_reserve(new_lb, NS_SMBUFSIZE);\n-\t\t\tpush_rxbufs(card, new_lb);\n-\t\t}\n-\t}\n-}\n-\n-static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)\n-{\n-\tu32 stat;\n-\tns_dev *card;\n-\tint left;\n-\n-\tleft = (int)*pos;\n-\tcard = (ns_dev *) dev->dev_data;\n-\tstat = readl(card->membase + STAT);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"Pool count min init max \\n\");\n-\tif (!left--)\n-\t\treturn sprintf(page, \"Small %5d %5d %5d %5d \\n\",\n-\t\t\t ns_stat_sfbqc_get(stat), card->sbnr.min,\n-\t\t\t card->sbnr.init, card->sbnr.max);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"Large %5d %5d %5d %5d \\n\",\n-\t\t\t ns_stat_lfbqc_get(stat), card->lbnr.min,\n-\t\t\t card->lbnr.init, card->lbnr.max);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"Huge %5d %5d %5d %5d \\n\",\n-\t\t\t card->hbpool.count, card->hbnr.min,\n-\t\t\t card->hbnr.init, card->hbnr.max);\n-\tif (!left--)\n-\t\treturn sprintf(page, \"Iovec %5d %5d %5d %5d \\n\",\n-\t\t\t card->iovpool.count, card->iovnr.min,\n-\t\t\t card->iovnr.init, card->iovnr.max);\n-\tif (!left--) {\n-\t\tint retval;\n-\t\tretval =\n-\t\t sprintf(page, \"Interrupt counter: %u \\n\", card->intcnt);\n-\t\tcard->intcnt = 0;\n-\t\treturn retval;\n-\t}\n-#if 0\n-\t/* Dump 25.6 Mbps PHY registers */\n-\t/* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it\n-\t here just in case it's needed for debugging. */\n-\tif (card->max_pcr == ATM_25_PCR && !left--) {\n-\t\tu32 phy_regs[4];\n-\t\tu32 i;\n-\n-\t\tfor (i = 0; i < 4; i++) {\n-\t\t\twhile (CMD_BUSY(card)) ;\n-\t\t\twritel(NS_CMD_READ_UTILITY | 0x00000200 | i,\n-\t\t\t card->membase + CMD);\n-\t\t\twhile (CMD_BUSY(card)) ;\n-\t\t\tphy_regs[i] = readl(card->membase + DR0) & 0x000000FF;\n-\t\t}\n-\n-\t\treturn sprintf(page, \"PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \\n\",\n-\t\t\t phy_regs[0], phy_regs[1], phy_regs[2],\n-\t\t\t phy_regs[3]);\n-\t}\n-#endif /* 0 - Dump 25.6 Mbps PHY registers */\n-#if 0\n-\t/* Dump TST */\n-\tif (left-- < NS_TST_NUM_ENTRIES) {\n-\t\tif (card->tste2vc[left + 1] == NULL)\n-\t\t\treturn sprintf(page, \"%5d - VBR/UBR \\n\", left + 1);\n-\t\telse\n-\t\t\treturn sprintf(page, \"%5d - %d %d \\n\", left + 1,\n-\t\t\t\t card->tste2vc[left + 1]->tx_vcc->vpi,\n-\t\t\t\t card->tste2vc[left + 1]->tx_vcc->vci);\n-\t}\n-#endif /* 0 */\n-\treturn 0;\n-}\n-\n-static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)\n-{\n-\tns_dev *card;\n-\tpool_levels pl;\n-\tlong btype;\n-\tunsigned long flags;\n-\n-\tcard = dev->dev_data;\n-\tswitch (cmd) {\n-\tcase NS_GETPSTAT:\n-\t\tif (get_user\n-\t\t (pl.buftype, &((pool_levels __user *) arg)->buftype))\n-\t\t\treturn -EFAULT;\n-\t\tswitch (pl.buftype) {\n-\t\tcase NS_BUFTYPE_SMALL:\n-\t\t\tpl.count =\n-\t\t\t ns_stat_sfbqc_get(readl(card->membase + STAT));\n-\t\t\tpl.level.min = card->sbnr.min;\n-\t\t\tpl.level.init = card->sbnr.init;\n-\t\t\tpl.level.max = card->sbnr.max;\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_LARGE:\n-\t\t\tpl.count =\n-\t\t\t ns_stat_lfbqc_get(readl(card->membase + STAT));\n-\t\t\tpl.level.min = card->lbnr.min;\n-\t\t\tpl.level.init = card->lbnr.init;\n-\t\t\tpl.level.max = card->lbnr.max;\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_HUGE:\n-\t\t\tpl.count = card->hbpool.count;\n-\t\t\tpl.level.min = card->hbnr.min;\n-\t\t\tpl.level.init = card->hbnr.init;\n-\t\t\tpl.level.max = card->hbnr.max;\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_IOVEC:\n-\t\t\tpl.count = card->iovpool.count;\n-\t\t\tpl.level.min = card->iovnr.min;\n-\t\t\tpl.level.init = card->iovnr.init;\n-\t\t\tpl.level.max = card->iovnr.max;\n-\t\t\tbreak;\n-\n-\t\tdefault:\n-\t\t\treturn -ENOIOCTLCMD;\n-\n-\t\t}\n-\t\tif (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))\n-\t\t\treturn (sizeof(pl));\n-\t\telse\n-\t\t\treturn -EFAULT;\n-\n-\tcase NS_SETBUFLEV:\n-\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\treturn -EPERM;\n-\t\tif (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))\n-\t\t\treturn -EFAULT;\n-\t\tif (pl.level.min >= pl.level.init\n-\t\t || pl.level.init >= pl.level.max)\n-\t\t\treturn -EINVAL;\n-\t\tif (pl.level.min == 0)\n-\t\t\treturn -EINVAL;\n-\t\tswitch (pl.buftype) {\n-\t\tcase NS_BUFTYPE_SMALL:\n-\t\t\tif (pl.level.max > TOP_SB)\n-\t\t\t\treturn -EINVAL;\n-\t\t\tcard->sbnr.min = pl.level.min;\n-\t\t\tcard->sbnr.init = pl.level.init;\n-\t\t\tcard->sbnr.max = pl.level.max;\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_LARGE:\n-\t\t\tif (pl.level.max > TOP_LB)\n-\t\t\t\treturn -EINVAL;\n-\t\t\tcard->lbnr.min = pl.level.min;\n-\t\t\tcard->lbnr.init = pl.level.init;\n-\t\t\tcard->lbnr.max = pl.level.max;\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_HUGE:\n-\t\t\tif (pl.level.max > TOP_HB)\n-\t\t\t\treturn -EINVAL;\n-\t\t\tcard->hbnr.min = pl.level.min;\n-\t\t\tcard->hbnr.init = pl.level.init;\n-\t\t\tcard->hbnr.max = pl.level.max;\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_IOVEC:\n-\t\t\tif (pl.level.max > TOP_IOVB)\n-\t\t\t\treturn -EINVAL;\n-\t\t\tcard->iovnr.min = pl.level.min;\n-\t\t\tcard->iovnr.init = pl.level.init;\n-\t\t\tcard->iovnr.max = pl.level.max;\n-\t\t\tbreak;\n-\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\n-\t\t}\n-\t\treturn 0;\n-\n-\tcase NS_ADJBUFLEV:\n-\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\treturn -EPERM;\n-\t\tbtype = (long)arg;\t/* a long is the same size as a pointer or bigger */\n-\t\tswitch (btype) {\n-\t\tcase NS_BUFTYPE_SMALL:\n-\t\t\twhile (card->sbfqc < card->sbnr.init) {\n-\t\t\t\tstruct sk_buff *sb;\n-\n-\t\t\t\tsb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);\n-\t\t\t\tif (sb == NULL)\n-\t\t\t\t\treturn -ENOMEM;\n-\t\t\t\tNS_PRV_BUFTYPE(sb) = BUF_SM;\n-\t\t\t\tskb_queue_tail(&card->sbpool.queue, sb);\n-\t\t\t\tskb_reserve(sb, NS_AAL0_HEADER);\n-\t\t\t\tpush_rxbufs(card, sb);\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_LARGE:\n-\t\t\twhile (card->lbfqc < card->lbnr.init) {\n-\t\t\t\tstruct sk_buff *lb;\n-\n-\t\t\t\tlb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);\n-\t\t\t\tif (lb == NULL)\n-\t\t\t\t\treturn -ENOMEM;\n-\t\t\t\tNS_PRV_BUFTYPE(lb) = BUF_LG;\n-\t\t\t\tskb_queue_tail(&card->lbpool.queue, lb);\n-\t\t\t\tskb_reserve(lb, NS_SMBUFSIZE);\n-\t\t\t\tpush_rxbufs(card, lb);\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_HUGE:\n-\t\t\twhile (card->hbpool.count > card->hbnr.init) {\n-\t\t\t\tstruct sk_buff *hb;\n-\n-\t\t\t\tspin_lock_irqsave(&card->int_lock, flags);\n-\t\t\t\thb = skb_dequeue(&card->hbpool.queue);\n-\t\t\t\tcard->hbpool.count--;\n-\t\t\t\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\t\t\t\tif (hb == NULL)\n-\t\t\t\t\tprintk\n-\t\t\t\t\t (\"nicstar%d: huge buffer count inconsistent.\\n\",\n-\t\t\t\t\t card->index);\n-\t\t\t\telse\n-\t\t\t\t\tdev_kfree_skb_any(hb);\n-\n-\t\t\t}\n-\t\t\twhile (card->hbpool.count < card->hbnr.init) {\n-\t\t\t\tstruct sk_buff *hb;\n-\n-\t\t\t\thb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);\n-\t\t\t\tif (hb == NULL)\n-\t\t\t\t\treturn -ENOMEM;\n-\t\t\t\tNS_PRV_BUFTYPE(hb) = BUF_NONE;\n-\t\t\t\tspin_lock_irqsave(&card->int_lock, flags);\n-\t\t\t\tskb_queue_tail(&card->hbpool.queue, hb);\n-\t\t\t\tcard->hbpool.count++;\n-\t\t\t\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase NS_BUFTYPE_IOVEC:\n-\t\t\twhile (card->iovpool.count > card->iovnr.init) {\n-\t\t\t\tstruct sk_buff *iovb;\n-\n-\t\t\t\tspin_lock_irqsave(&card->int_lock, flags);\n-\t\t\t\tiovb = skb_dequeue(&card->iovpool.queue);\n-\t\t\t\tcard->iovpool.count--;\n-\t\t\t\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\t\t\t\tif (iovb == NULL)\n-\t\t\t\t\tprintk\n-\t\t\t\t\t (\"nicstar%d: iovec buffer count inconsistent.\\n\",\n-\t\t\t\t\t card->index);\n-\t\t\t\telse\n-\t\t\t\t\tdev_kfree_skb_any(iovb);\n-\n-\t\t\t}\n-\t\t\twhile (card->iovpool.count < card->iovnr.init) {\n-\t\t\t\tstruct sk_buff *iovb;\n-\n-\t\t\t\tiovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);\n-\t\t\t\tif (iovb == NULL)\n-\t\t\t\t\treturn -ENOMEM;\n-\t\t\t\tNS_PRV_BUFTYPE(iovb) = BUF_NONE;\n-\t\t\t\tspin_lock_irqsave(&card->int_lock, flags);\n-\t\t\t\tskb_queue_tail(&card->iovpool.queue, iovb);\n-\t\t\t\tcard->iovpool.count++;\n-\t\t\t\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\n-\t\t}\n-\t\treturn 0;\n-\n-\tdefault:\n-\t\tif (dev->phy && dev->phy->ioctl) {\n-\t\t\treturn dev->phy->ioctl(dev, cmd, arg);\n-\t\t} else {\n-\t\t\tprintk(\"nicstar%d: %s == NULL \\n\", card->index,\n-\t\t\t dev->phy ? \"dev->phy->ioctl\" : \"dev->phy\");\n-\t\t\treturn -ENOIOCTLCMD;\n-\t\t}\n-\t}\n-}\n-\n-#ifdef EXTRA_DEBUG\n-static void which_list(ns_dev * card, struct sk_buff *skb)\n-{\n-\tprintk(\"skb buf_type: 0x%08x\\n\", NS_PRV_BUFTYPE(skb));\n-}\n-#endif /* EXTRA_DEBUG */\n-\n-static void ns_poll(struct timer_list *unused)\n-{\n-\tint i;\n-\tns_dev *card;\n-\tunsigned long flags;\n-\tu32 stat_r, stat_w;\n-\n-\tPRINTK(\"nicstar: Entering ns_poll().\\n\");\n-\tfor (i = 0; i < num_cards; i++) {\n-\t\tcard = cards[i];\n-\t\tif (!spin_trylock_irqsave(&card->int_lock, flags)) {\n-\t\t\t/* Probably it isn't worth spinning */\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tstat_w = 0;\n-\t\tstat_r = readl(card->membase + STAT);\n-\t\tif (stat_r & NS_STAT_TSIF)\n-\t\t\tstat_w |= NS_STAT_TSIF;\n-\t\tif (stat_r & NS_STAT_EOPDU)\n-\t\t\tstat_w |= NS_STAT_EOPDU;\n-\n-\t\tprocess_tsq(card);\n-\t\tprocess_rsq(card);\n-\n-\t\twritel(stat_w, card->membase + STAT);\n-\t\tspin_unlock_irqrestore(&card->int_lock, flags);\n-\t}\n-\tmod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);\n-\tPRINTK(\"nicstar: Leaving ns_poll().\\n\");\n-}\n-\n-static void ns_phy_put(struct atm_dev *dev, unsigned char value,\n-\t\t unsigned long addr)\n-{\n-\tns_dev *card;\n-\tunsigned long flags;\n-\n-\tcard = dev->dev_data;\n-\tspin_lock_irqsave(&card->res_lock, flags);\n-\twhile (CMD_BUSY(card)) ;\n-\twritel((u32) value, card->membase + DR0);\n-\twritel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),\n-\t card->membase + CMD);\n-\tspin_unlock_irqrestore(&card->res_lock, flags);\n-}\n-\n-static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)\n-{\n-\tns_dev *card;\n-\tunsigned long flags;\n-\tu32 data;\n-\n-\tcard = dev->dev_data;\n-\tspin_lock_irqsave(&card->res_lock, flags);\n-\twhile (CMD_BUSY(card)) ;\n-\twritel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),\n-\t card->membase + CMD);\n-\twhile (CMD_BUSY(card)) ;\n-\tdata = readl(card->membase + DR0) & 0x000000FF;\n-\tspin_unlock_irqrestore(&card->res_lock, flags);\n-\treturn (unsigned char)data;\n-}\n-\n-module_init(nicstar_init);\n-module_exit(nicstar_cleanup);\ndiff --git a/drivers/atm/nicstarmac.c b/drivers/atm/nicstarmac.c\ndeleted file mode 100644\nindex 791f69a07ddf..000000000000\n--- a/drivers/atm/nicstarmac.c\n+++ /dev/null\n@@ -1,244 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-/*\n- * this file included by nicstar.c\n- */\n-\n-/*\n- * nicstarmac.c\n- * Read this ForeRunner's MAC address from eprom/eeprom\n- */\n-\n-#include \n-\n-typedef void __iomem *virt_addr_t;\n-\n-#define CYCLE_DELAY 5\n-\n-#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \\\n- udelay((useconds));}\n-/*\n- * The following tables represent the timing diagrams found in\n- * the Data Sheet for the Xicor X25020 EEProm. The #defines below\n- * represent the bits in the NICStAR's General Purpose register\n- * that must be toggled for the corresponding actions on the EEProm\n- * to occur.\n- */\n-\n-/* Write Data To EEProm from SI line on rising edge of CLK */\n-/* Read Data From EEProm on falling edge of CLK */\n-\n-#define CS_HIGH\t\t0x0002\t/* Chip select high */\n-#define CS_LOW\t\t0x0000\t/* Chip select low (active low) */\n-#define CLK_HIGH\t0x0004\t/* Clock high */\n-#define CLK_LOW\t\t0x0000\t/* Clock low */\n-#define SI_HIGH\t\t0x0001\t/* Serial input data high */\n-#define SI_LOW\t\t0x0000\t/* Serial input data low */\n-\n-/* Read Status Register = 0000 0101b */\n-#if 0\n-static u_int32_t rdsrtab[] = {\n-\tCS_HIGH | CLK_HIGH,\n-\tCS_LOW | CLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW | SI_HIGH,\n-\tCLK_HIGH | SI_HIGH,\t/* 1 */\n-\tCLK_LOW | SI_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW | SI_HIGH,\n-\tCLK_HIGH | SI_HIGH\t/* 1 */\n-};\n-#endif /* 0 */\n-\n-/* Read from EEPROM = 0000 0011b */\n-static u_int32_t readtab[] = {\n-\t/*\n-\t CS_HIGH | CLK_HIGH,\n-\t */\n-\tCS_LOW | CLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW,\n-\tCLK_HIGH,\t\t/* 0 */\n-\tCLK_LOW | SI_HIGH,\n-\tCLK_HIGH | SI_HIGH,\t/* 1 */\n-\tCLK_LOW | SI_HIGH,\n-\tCLK_HIGH | SI_HIGH\t/* 1 */\n-};\n-\n-/* Clock to read from/write to the eeprom */\n-static u_int32_t clocktab[] = {\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW,\n-\tCLK_HIGH,\n-\tCLK_LOW\n-};\n-\n-#define NICSTAR_REG_WRITE(bs, reg, val) \\\n-\twhile ( readl(bs + STAT) & 0x0200 ) ; \\\n-\twritel((val),(base)+(reg))\n-#define NICSTAR_REG_READ(bs, reg) \\\n-\treadl((base)+(reg))\n-#define NICSTAR_REG_GENERAL_PURPOSE GP\n-\n-/*\n- * This routine will clock the Read_Status_reg function into the X2520\n- * eeprom, then pull the result from bit 16 of the NicSTaR's General Purpose \n- * register. \n- */\n-#if 0\n-u_int32_t nicstar_read_eprom_status(virt_addr_t base)\n-{\n-\tu_int32_t val;\n-\tu_int32_t rbyte;\n-\tint32_t i, j;\n-\n-\t/* Send read instruction */\n-\tval = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;\n-\n-\tfor (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | rdsrtab[i]));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t}\n-\n-\t/* Done sending instruction - now pull data off of bit 16, MSB first */\n-\t/* Data clocked out of eeprom on falling edge of clock */\n-\n-\trbyte = 0;\n-\tfor (i = 7, j = 0; i >= 0; i--) {\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | clocktab[j++]));\n-\t\trbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)\n-\t\t\t & 0x00010000) >> 16) << i);\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | clocktab[j++]));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t}\n-\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);\n-\tosp_MicroDelay(CYCLE_DELAY);\n-\treturn rbyte;\n-}\n-#endif /* 0 */\n-\n-/*\n- * This routine will clock the Read_data function into the X2520\n- * eeprom, followed by the address to read from, through the NicSTaR's General\n- * Purpose register. \n- */\n-\n-static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset)\n-{\n-\tu_int32_t val = 0;\n-\tint i, j = 0;\n-\tu_int8_t tempread = 0;\n-\n-\tval = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;\n-\n-\t/* Send READ instruction */\n-\tfor (i = 0; i < ARRAY_SIZE(readtab); i++) {\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | readtab[i]));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t}\n-\n-\t/* Next, we need to send the byte address to read from */\n-\tfor (i = 7; i >= 0; i--) {\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | clocktab[j++] | ((offset >> i) & 1)));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | clocktab[j++] | ((offset >> i) & 1)));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t}\n-\n-\tj = 0;\n-\n-\t/* Now, we can read data from the eeprom by clocking it in */\n-\tfor (i = 7; i >= 0; i--) {\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | clocktab[j++]));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t\ttempread |=\n-\t\t (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE)\n-\t\t & 0x00010000) >> 16) << i);\n-\t\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t\t (val | clocktab[j++]));\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t}\n-\n-\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2);\n-\tosp_MicroDelay(CYCLE_DELAY);\n-\treturn tempread;\n-}\n-\n-static void nicstar_init_eprom(virt_addr_t base)\n-{\n-\tu_int32_t val;\n-\n-\t/*\n-\t * turn chip select off\n-\t */\n-\tval = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;\n-\n-\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t (val | CS_HIGH | CLK_HIGH));\n-\tosp_MicroDelay(CYCLE_DELAY);\n-\n-\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t (val | CS_HIGH | CLK_LOW));\n-\tosp_MicroDelay(CYCLE_DELAY);\n-\n-\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t (val | CS_HIGH | CLK_HIGH));\n-\tosp_MicroDelay(CYCLE_DELAY);\n-\n-\tNICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,\n-\t\t\t (val | CS_HIGH | CLK_LOW));\n-\tosp_MicroDelay(CYCLE_DELAY);\n-}\n-\n-/*\n- * This routine will be the interface to the ReadPromByte function\n- * above.\n- */\n-\n-static void\n-nicstar_read_eprom(virt_addr_t base,\n-\t\t u_int8_t prom_offset, u_int8_t * buffer, u_int32_t nbytes)\n-{\n-\tu_int i;\n-\n-\tfor (i = 0; i < nbytes; i++) {\n-\t\tbuffer[i] = read_eprom_byte(base, prom_offset);\n-\t\t++prom_offset;\n-\t\tosp_MicroDelay(CYCLE_DELAY);\n-\t}\n-}\ndiff --git a/drivers/atm/solos-attrlist.c b/drivers/atm/solos-attrlist.c\ndeleted file mode 100644\nindex 1830d1b8619f..000000000000\n--- a/drivers/atm/solos-attrlist.c\n+++ /dev/null\n@@ -1,83 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-SOLOS_ATTR_RO(DriverVersion)\n-SOLOS_ATTR_RO(APIVersion)\n-SOLOS_ATTR_RO(FirmwareVersion)\n-SOLOS_ATTR_RO(Version)\n-// SOLOS_ATTR_RO(DspVersion)\n-// SOLOS_ATTR_RO(CommonHandshake)\n-SOLOS_ATTR_RO(Connected)\n-SOLOS_ATTR_RO(OperationalMode)\n-SOLOS_ATTR_RO(State)\n-SOLOS_ATTR_RO(Watchdog)\n-SOLOS_ATTR_RO(OperationProgress)\n-SOLOS_ATTR_RO(LastFailed)\n-SOLOS_ATTR_RO(TxBitRate)\n-SOLOS_ATTR_RO(RxBitRate)\n-// SOLOS_ATTR_RO(DeltACTATPds)\n-// SOLOS_ATTR_RO(DeltACTATPus)\n-SOLOS_ATTR_RO(TxATTNDR)\n-SOLOS_ATTR_RO(RxATTNDR)\n-SOLOS_ATTR_RO(AnnexType)\n-SOLOS_ATTR_RO(GeneralFailure)\n-SOLOS_ATTR_RO(InterleaveDpDn)\n-SOLOS_ATTR_RO(InterleaveDpUp)\n-SOLOS_ATTR_RO(RSCorrectedErrorsDn)\n-SOLOS_ATTR_RO(RSUnCorrectedErrorsDn)\n-SOLOS_ATTR_RO(RSCorrectedErrorsUp)\n-SOLOS_ATTR_RO(RSUnCorrectedErrorsUp)\n-SOLOS_ATTR_RO(InterleaveRDn)\n-SOLOS_ATTR_RO(InterleaveRUp)\n-SOLOS_ATTR_RO(BisRDn)\n-SOLOS_ATTR_RO(BisRUp)\n-SOLOS_ATTR_RO(INPdown)\n-SOLOS_ATTR_RO(INPup)\n-SOLOS_ATTR_RO(ShowtimeStart)\n-SOLOS_ATTR_RO(ATURVendor)\n-SOLOS_ATTR_RO(ATUCCountry)\n-SOLOS_ATTR_RO(ATURANSIRev)\n-SOLOS_ATTR_RO(ATURANSISTD)\n-SOLOS_ATTR_RO(ATUCANSIRev)\n-SOLOS_ATTR_RO(ATUCANSIId)\n-SOLOS_ATTR_RO(ATUCANSISTD)\n-SOLOS_ATTR_RO(DataBoost)\n-SOLOS_ATTR_RO(LocalITUCountryCode)\n-SOLOS_ATTR_RO(LocalSEF)\n-SOLOS_ATTR_RO(LocalEndLOS)\n-SOLOS_ATTR_RO(LocalSNRMargin)\n-SOLOS_ATTR_RO(LocalLineAttn)\n-SOLOS_ATTR_RO(RawAttn)\n-SOLOS_ATTR_RO(LocalTxPower)\n-SOLOS_ATTR_RO(RemoteTxPower)\n-SOLOS_ATTR_RO(RemoteSEF)\n-SOLOS_ATTR_RO(RemoteLOS)\n-SOLOS_ATTR_RO(RemoteLineAttn)\n-SOLOS_ATTR_RO(RemoteSNRMargin)\n-SOLOS_ATTR_RO(LineUpCount)\n-SOLOS_ATTR_RO(SRACnt)\n-SOLOS_ATTR_RO(SRACntUp)\n-SOLOS_ATTR_RO(ProfileStatus)\n-SOLOS_ATTR_RW(Action)\n-SOLOS_ATTR_RW(ActivateLine)\n-SOLOS_ATTR_RO(LineStatus)\n-SOLOS_ATTR_RW(HostControl)\n-SOLOS_ATTR_RW(AutoStart)\n-SOLOS_ATTR_RW(Failsafe)\n-SOLOS_ATTR_RW(ShowtimeLed)\n-SOLOS_ATTR_RW(Retrain)\n-SOLOS_ATTR_RW(Defaults)\n-SOLOS_ATTR_RW(LineMode)\n-SOLOS_ATTR_RW(Profile)\n-SOLOS_ATTR_RW(DetectNoise)\n-SOLOS_ATTR_RW(BisAForceSNRMarginDn)\n-SOLOS_ATTR_RW(BisMForceSNRMarginDn)\n-SOLOS_ATTR_RW(BisAMaxMargin)\n-SOLOS_ATTR_RW(BisMMaxMargin)\n-SOLOS_ATTR_RW(AnnexAForceSNRMarginDn)\n-SOLOS_ATTR_RW(AnnexAMaxMargin)\n-SOLOS_ATTR_RW(AnnexMMaxMargin)\n-SOLOS_ATTR_RO(SupportedAnnexes)\n-SOLOS_ATTR_RO(Status)\n-SOLOS_ATTR_RO(TotalStart)\n-SOLOS_ATTR_RO(RecentShowtimeStart)\n-SOLOS_ATTR_RO(TotalRxBlocks)\n-SOLOS_ATTR_RO(TotalTxBlocks)\ndiff --git a/drivers/atm/solos-pci.c b/drivers/atm/solos-pci.c\ndeleted file mode 100644\nindex 24c764664c24..000000000000\n--- a/drivers/atm/solos-pci.c\n+++ /dev/null\n@@ -1,1496 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Driver for the Solos PCI ADSL2+ card, designed to support Linux by\n- * Traverse Technologies -- https://www.traverse.com.au/\n- * Xrio Limited -- http://www.xrio.com/\n- *\n- * Copyright © 2008 Traverse Technologies\n- * Copyright © 2008 Intel Corporation\n- *\n- * Authors: Nathan Williams \n- * David Woodhouse \n- * Treker Chen \n- */\n-\n-#define DEBUG\n-#define VERBOSE_DEBUG\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#define VERSION \"1.04\"\n-#define DRIVER_VERSION 0x01\n-#define PTAG \"solos-pci\"\n-\n-#define CONFIG_RAM_SIZE\t128\n-#define FLAGS_ADDR\t0x7C\n-#define IRQ_EN_ADDR\t0x78\n-#define FPGA_VER\t0x74\n-#define IRQ_CLEAR\t0x70\n-#define WRITE_FLASH\t0x6C\n-#define PORTS\t\t0x68\n-#define FLASH_BLOCK\t0x64\n-#define FLASH_BUSY\t0x60\n-#define FPGA_MODE\t0x5C\n-#define FLASH_MODE\t0x58\n-#define GPIO_STATUS\t0x54\n-#define DRIVER_VER\t0x50\n-#define TX_DMA_ADDR(port)\t(0x40 + (4 * (port)))\n-#define RX_DMA_ADDR(port)\t(0x30 + (4 * (port)))\n-\n-#define DATA_RAM_SIZE\t32768\n-#define BUF_SIZE\t2048\n-#define OLD_BUF_SIZE\t4096 /* For FPGA versions <= 2*/\n-/* Old boards use ATMEL AD45DB161D flash */\n-#define ATMEL_FPGA_PAGE\t528 /* FPGA flash page size*/\n-#define ATMEL_SOLOS_PAGE\t512 /* Solos flash page size*/\n-#define ATMEL_FPGA_BLOCK\t(ATMEL_FPGA_PAGE * 8) /* FPGA block size*/\n-#define ATMEL_SOLOS_BLOCK\t(ATMEL_SOLOS_PAGE * 8) /* Solos block size*/\n-/* Current boards use M25P/M25PE SPI flash */\n-#define SPI_FLASH_BLOCK\t(256 * 64)\n-\n-#define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)\n-#define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))\n-#define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)\n-\n-#define RX_DMA_SIZE\t2048\n-\n-#define FPGA_VERSION(a,b) (((a) << 8) + (b))\n-#define LEGACY_BUFFERS\t2\n-#define DMA_SUPPORTED\t4\n-\n-static int reset = 0;\n-static int atmdebug = 0;\n-static int firmware_upgrade = 0;\n-static int fpga_upgrade = 0;\n-static int db_firmware_upgrade = 0;\n-static int db_fpga_upgrade = 0;\n-\n-struct pkt_hdr {\n-\t__le16 size;\n-\t__le16 vpi;\n-\t__le16 vci;\n-\t__le16 type;\n-};\n-\n-struct solos_skb_cb {\n-\tstruct atm_vcc *vcc;\n-\tuint32_t dma_addr;\n-};\n-\n-\n-#define SKB_CB(skb)\t\t((struct solos_skb_cb *)skb->cb)\n-\n-#define PKT_DATA\t0\n-#define PKT_COMMAND\t1\n-#define PKT_POPEN\t3\n-#define PKT_PCLOSE\t4\n-#define PKT_STATUS\t5\n-\n-struct solos_card {\n-\tvoid __iomem *config_regs;\n-\tvoid __iomem *buffers;\n-\tint nr_ports;\n-\tint tx_mask;\n-\tstruct pci_dev *dev;\n-\tstruct atm_dev *atmdev[4];\n-\tstruct tasklet_struct tlet;\n-\tspinlock_t tx_lock;\n-\tspinlock_t tx_queue_lock;\n-\tspinlock_t cli_queue_lock;\n-\tspinlock_t param_queue_lock;\n-\tstruct list_head param_queue;\n-\tstruct sk_buff_head tx_queue[4];\n-\tstruct sk_buff_head cli_queue[4];\n-\tstruct sk_buff *tx_skb[4];\n-\tstruct sk_buff *rx_skb[4];\n-\tunsigned char *dma_bounce;\n-\twait_queue_head_t param_wq;\n-\twait_queue_head_t fw_wq;\n-\tint using_dma;\n-\tint dma_alignment;\n-\tint fpga_version;\n-\tint buffer_size;\n-\tint atmel_flash;\n-};\n-\n-\n-struct solos_param {\n-\tstruct list_head list;\n-\tpid_t pid;\n-\tint port;\n-\tstruct sk_buff *response;\n-};\n-\n-#define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)\n-\n-MODULE_AUTHOR(\"Traverse Technologies \");\n-MODULE_DESCRIPTION(\"Solos PCI driver\");\n-MODULE_VERSION(VERSION);\n-MODULE_LICENSE(\"GPL\");\n-MODULE_FIRMWARE(\"solos-FPGA.bin\");\n-MODULE_FIRMWARE(\"solos-Firmware.bin\");\n-MODULE_FIRMWARE(\"solos-db-FPGA.bin\");\n-MODULE_PARM_DESC(reset, \"Reset Solos chips on startup\");\n-MODULE_PARM_DESC(atmdebug, \"Print ATM data\");\n-MODULE_PARM_DESC(firmware_upgrade, \"Initiate Solos firmware upgrade\");\n-MODULE_PARM_DESC(fpga_upgrade, \"Initiate FPGA upgrade\");\n-MODULE_PARM_DESC(db_firmware_upgrade, \"Initiate daughter board Solos firmware upgrade\");\n-MODULE_PARM_DESC(db_fpga_upgrade, \"Initiate daughter board FPGA upgrade\");\n-module_param(reset, int, 0444);\n-module_param(atmdebug, int, 0644);\n-module_param(firmware_upgrade, int, 0444);\n-module_param(fpga_upgrade, int, 0444);\n-module_param(db_firmware_upgrade, int, 0444);\n-module_param(db_fpga_upgrade, int, 0444);\n-\n-static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,\n-\t\t struct atm_vcc *vcc);\n-static uint32_t fpga_tx(struct solos_card *);\n-static irqreturn_t solos_irq(int irq, void *dev_id);\n-static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);\n-static int atm_init(struct solos_card *, struct device *);\n-static void atm_remove(struct solos_card *);\n-static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);\n-static void solos_bh(unsigned long);\n-static int print_buffer(struct sk_buff *buf);\n-\n-static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n- if (vcc->pop)\n- vcc->pop(vcc, skb);\n- else\n- dev_kfree_skb_any(skb);\n-}\n-\n-static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,\n-\t\t\t\tchar *buf)\n-{\n-\tstruct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);\n-\tstruct solos_card *card = atmdev->dev_data;\n-\tstruct solos_param prm;\n-\tstruct sk_buff *skb;\n-\tstruct pkt_hdr *header;\n-\tint buflen;\n-\n-\tbuflen = strlen(attr->attr.name) + 10;\n-\n-\tskb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);\n-\tif (!skb) {\n-\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff in solos_param_show()\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\theader = skb_put(skb, sizeof(*header));\n-\n-\tbuflen = snprintf((void *)&header[1], buflen - 1,\n-\t\t\t \"L%05d\\n%s\\n\", current->pid, attr->attr.name);\n-\tskb_put(skb, buflen);\n-\n-\theader->size = cpu_to_le16(buflen);\n-\theader->vpi = cpu_to_le16(0);\n-\theader->vci = cpu_to_le16(0);\n-\theader->type = cpu_to_le16(PKT_COMMAND);\n-\n-\tprm.pid = current->pid;\n-\tprm.response = NULL;\n-\tprm.port = SOLOS_CHAN(atmdev);\n-\n-\tspin_lock_irq(&card->param_queue_lock);\n-\tlist_add(&prm.list, &card->param_queue);\n-\tspin_unlock_irq(&card->param_queue_lock);\n-\n-\tfpga_queue(card, prm.port, skb, NULL);\n-\n-\twait_event_timeout(card->param_wq, prm.response, 5 * HZ);\n-\n-\tspin_lock_irq(&card->param_queue_lock);\n-\tlist_del(&prm.list);\n-\tspin_unlock_irq(&card->param_queue_lock);\n-\n-\tif (!prm.response)\n-\t\treturn -EIO;\n-\n-\tbuflen = prm.response->len;\n-\tmemcpy(buf, prm.response->data, buflen);\n-\tkfree_skb(prm.response);\n-\n-\treturn buflen;\n-}\n-\n-static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,\n-\t\t\t\t const char *buf, size_t count)\n-{\n-\tstruct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);\n-\tstruct solos_card *card = atmdev->dev_data;\n-\tstruct solos_param prm;\n-\tstruct sk_buff *skb;\n-\tstruct pkt_hdr *header;\n-\tint buflen;\n-\tssize_t ret;\n-\n-\tbuflen = strlen(attr->attr.name) + 11 + count;\n-\n-\tskb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);\n-\tif (!skb) {\n-\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff in solos_param_store()\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\theader = skb_put(skb, sizeof(*header));\n-\n-\tbuflen = snprintf((void *)&header[1], buflen - 1,\n-\t\t\t \"L%05d\\n%s\\n%s\\n\", current->pid, attr->attr.name, buf);\n-\n-\tskb_put(skb, buflen);\n-\theader->size = cpu_to_le16(buflen);\n-\theader->vpi = cpu_to_le16(0);\n-\theader->vci = cpu_to_le16(0);\n-\theader->type = cpu_to_le16(PKT_COMMAND);\n-\n-\tprm.pid = current->pid;\n-\tprm.response = NULL;\n-\tprm.port = SOLOS_CHAN(atmdev);\n-\n-\tspin_lock_irq(&card->param_queue_lock);\n-\tlist_add(&prm.list, &card->param_queue);\n-\tspin_unlock_irq(&card->param_queue_lock);\n-\n-\tfpga_queue(card, prm.port, skb, NULL);\n-\n-\twait_event_timeout(card->param_wq, prm.response, 5 * HZ);\n-\n-\tspin_lock_irq(&card->param_queue_lock);\n-\tlist_del(&prm.list);\n-\tspin_unlock_irq(&card->param_queue_lock);\n-\n-\tskb = prm.response;\n-\n-\tif (!skb)\n-\t\treturn -EIO;\n-\n-\tbuflen = skb->len;\n-\n-\t/* Sometimes it has a newline, sometimes it doesn't. */\n-\tif (skb->data[buflen - 1] == '\\n')\n-\t\tbuflen--;\n-\n-\tif (buflen == 2 && !strncmp(skb->data, \"OK\", 2))\n-\t\tret = count;\n-\telse if (buflen == 5 && !strncmp(skb->data, \"ERROR\", 5))\n-\t\tret = -EIO;\n-\telse {\n-\t\t/* We know we have enough space allocated for this; we allocated \n-\t\t it ourselves */\n-\t\tskb->data[buflen] = 0;\n-\t\n-\t\tdev_warn(&card->dev->dev, \"Unexpected parameter response: '%s'\\n\",\n-\t\t\t skb->data);\n-\t\tret = -EIO;\n-\t}\n-\tkfree_skb(skb);\n-\n-\treturn ret;\n-}\n-\n-static char *next_string(struct sk_buff *skb)\n-{\n-\tint i = 0;\n-\tchar *this = skb->data;\n-\t\n-\tfor (i = 0; i < skb->len; i++) {\n-\t\tif (this[i] == '\\n') {\n-\t\t\tthis[i] = 0;\n-\t\t\tskb_pull(skb, i + 1);\n-\t\t\treturn this;\n-\t\t}\n-\t\tif (!isprint(this[i]))\n-\t\t\treturn NULL;\n-\t}\n-\treturn NULL;\n-}\n-\n-/*\n- * Status packet has fields separated by \\n, starting with a version number\n- * for the information therein. Fields are....\n- *\n- * packet version\n- * RxBitRate\t(version >= 1)\n- * TxBitRate\t(version >= 1)\n- * State\t\t(version >= 1)\n- * LocalSNRMargin\t(version >= 1)\n- * LocalLineAttn\t(version >= 1)\n- */ \n-static int process_status(struct solos_card *card, int port, struct sk_buff *skb)\n-{\n-\tchar *str, *state_str, *snr, *attn;\n-\tint ver, rate_up, rate_down, err;\n-\n-\tif (!card->atmdev[port])\n-\t\treturn -ENODEV;\n-\n-\tstr = next_string(skb);\n-\tif (!str)\n-\t\treturn -EIO;\n-\n-\terr = kstrtoint(str, 10, &ver);\n-\tif (err) {\n-\t\tdev_warn(&card->dev->dev, \"Unexpected status interrupt version\\n\");\n-\t\treturn err;\n-\t}\n-\tif (ver < 1) {\n-\t\tdev_warn(&card->dev->dev, \"Unexpected status interrupt version %d\\n\",\n-\t\t\t ver);\n-\t\treturn -EIO;\n-\t}\n-\n-\tstr = next_string(skb);\n-\tif (!str)\n-\t\treturn -EIO;\n-\tif (!strcmp(str, \"ERROR\")) {\n-\t\tdev_dbg(&card->dev->dev, \"Status packet indicated Solos error on port %d (starting up?)\\n\",\n-\t\t\t port);\n-\t\treturn 0;\n-\t}\n-\n-\terr = kstrtoint(str, 10, &rate_down);\n-\tif (err)\n-\t\treturn err;\n-\n-\tstr = next_string(skb);\n-\tif (!str)\n-\t\treturn -EIO;\n-\terr = kstrtoint(str, 10, &rate_up);\n-\tif (err)\n-\t\treturn err;\n-\n-\tstate_str = next_string(skb);\n-\tif (!state_str)\n-\t\treturn -EIO;\n-\n-\t/* Anything but 'Showtime' is down */\n-\tif (strcmp(state_str, \"Showtime\")) {\n-\t\tatm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_LOST);\n-\t\tdev_info(&card->dev->dev, \"Port %d: %s\\n\", port, state_str);\n-\t\treturn 0;\n-\t}\n-\n-\tsnr = next_string(skb);\n-\tif (!snr)\n-\t\treturn -EIO;\n-\tattn = next_string(skb);\n-\tif (!attn)\n-\t\treturn -EIO;\n-\n-\tdev_info(&card->dev->dev, \"Port %d: %s @%d/%d kb/s%s%s%s%s\\n\",\n-\t\t port, state_str, rate_down/1000, rate_up/1000,\n-\t\t snr[0]?\", SNR \":\"\", snr, attn[0]?\", Attn \":\"\", attn);\n-\t\n-\tcard->atmdev[port]->link_rate = rate_down / 424;\n-\tatm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_FOUND);\n-\n-\treturn 0;\n-}\n-\n-static int process_command(struct solos_card *card, int port, struct sk_buff *skb)\n-{\n-\tstruct solos_param *prm;\n-\tunsigned long flags;\n-\tint cmdpid;\n-\tint found = 0, err;\n-\n-\tif (skb->len < 7)\n-\t\treturn 0;\n-\n-\tif (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||\n-\t !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||\n-\t !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||\n-\t skb->data[6] != '\\n')\n-\t\treturn 0;\n-\n-\terr = kstrtoint(&skb->data[1], 10, &cmdpid);\n-\tif (err)\n-\t\treturn err;\n-\n-\tspin_lock_irqsave(&card->param_queue_lock, flags);\n-\tlist_for_each_entry(prm, &card->param_queue, list) {\n-\t\tif (prm->port == port && prm->pid == cmdpid) {\n-\t\t\tprm->response = skb;\n-\t\t\tskb_pull(skb, 7);\n-\t\t\twake_up(&card->param_wq);\n-\t\t\tfound = 1;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\tspin_unlock_irqrestore(&card->param_queue_lock, flags);\n-\treturn found;\n-}\n-\n-static ssize_t console_show(struct device *dev, struct device_attribute *attr,\n-\t\t\t char *buf)\n-{\n-\tstruct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);\n-\tstruct solos_card *card = atmdev->dev_data;\n-\tstruct sk_buff *skb;\n-\tunsigned int len;\n-\n-\tspin_lock_bh(&card->cli_queue_lock);\n-\tskb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);\n-\tspin_unlock_bh(&card->cli_queue_lock);\n-\tif(skb == NULL)\n-\t\treturn sprintf(buf, \"No data.\\n\");\n-\n-\tlen = skb->len;\n-\tmemcpy(buf, skb->data, len);\n-\n-\tkfree_skb(skb);\n-\treturn len;\n-}\n-\n-static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)\n-{\n-\tstruct sk_buff *skb;\n-\tstruct pkt_hdr *header;\n-\n-\tif (size > (BUF_SIZE - sizeof(*header))) {\n-\t\tdev_dbg(&card->dev->dev, \"Command is too big. Dropping request\\n\");\n-\t\treturn 0;\n-\t}\n-\tskb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);\n-\tif (!skb) {\n-\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff in send_command()\\n\");\n-\t\treturn 0;\n-\t}\n-\n-\theader = skb_put(skb, sizeof(*header));\n-\n-\theader->size = cpu_to_le16(size);\n-\theader->vpi = cpu_to_le16(0);\n-\theader->vci = cpu_to_le16(0);\n-\theader->type = cpu_to_le16(PKT_COMMAND);\n-\n-\tskb_put_data(skb, buf, size);\n-\n-\tfpga_queue(card, dev, skb, NULL);\n-\n-\treturn 0;\n-}\n-\n-static ssize_t console_store(struct device *dev, struct device_attribute *attr,\n-\t\t\t const char *buf, size_t count)\n-{\n-\tstruct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);\n-\tstruct solos_card *card = atmdev->dev_data;\n-\tint err;\n-\n-\terr = send_command(card, SOLOS_CHAN(atmdev), buf, count);\n-\n-\treturn err?:count;\n-}\n-\n-struct geos_gpio_attr {\n-\tstruct device_attribute attr;\n-\tint offset;\n-};\n-\n-#define SOLOS_GPIO_ATTR(_name, _mode, _show, _store, _offset)\t\\\n-\tstruct geos_gpio_attr gpio_attr_##_name = {\t\t\\\n-\t\t.attr = __ATTR(_name, _mode, _show, _store),\t\\\n-\t\t.offset = _offset }\n-\n-static ssize_t geos_gpio_store(struct device *dev, struct device_attribute *attr,\n-\t\t\t const char *buf, size_t count)\n-{\n-\tstruct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);\n-\tstruct solos_card *card = dev_get_drvdata(dev);\n-\tuint32_t data32;\n-\n-\tif (count != 1 && (count != 2 || buf[1] != '\\n'))\n-\t\treturn -EINVAL;\n-\n-\tspin_lock_irq(&card->param_queue_lock);\n-\tdata32 = ioread32(card->config_regs + GPIO_STATUS);\n-\tif (buf[0] == '1') {\n-\t\tdata32 |= 1 << gattr->offset;\n-\t\tiowrite32(data32, card->config_regs + GPIO_STATUS);\n-\t} else if (buf[0] == '0') {\n-\t\tdata32 &= ~(1 << gattr->offset);\n-\t\tiowrite32(data32, card->config_regs + GPIO_STATUS);\n-\t} else {\n-\t\tcount = -EINVAL;\n-\t}\n-\tspin_unlock_irq(&card->param_queue_lock);\n-\treturn count;\n-}\n-\n-static ssize_t geos_gpio_show(struct device *dev, struct device_attribute *attr,\n-\t\t\t char *buf)\n-{\n-\tstruct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);\n-\tstruct solos_card *card = dev_get_drvdata(dev);\n-\tuint32_t data32;\n-\n-\tdata32 = ioread32(card->config_regs + GPIO_STATUS);\n-\tdata32 = (data32 >> gattr->offset) & 1;\n-\n-\treturn sprintf(buf, \"%d\\n\", data32);\n-}\n-\n-static ssize_t hardware_show(struct device *dev, struct device_attribute *attr,\n-\t\t\t char *buf)\n-{\n-\tstruct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);\n-\tstruct solos_card *card = dev_get_drvdata(dev);\n-\tuint32_t data32;\n-\n-\tdata32 = ioread32(card->config_regs + GPIO_STATUS);\n-\tswitch (gattr->offset) {\n-\tcase 0:\n-\t\t/* HardwareVersion */\n-\t\tdata32 = data32 & 0x1F;\n-\t\tbreak;\n-\tcase 1:\n-\t\t/* HardwareVariant */\n-\t\tdata32 = (data32 >> 5) & 0x0F;\n-\t\tbreak;\n-\t}\n-\treturn sprintf(buf, \"%d\\n\", data32);\n-}\n-\n-static DEVICE_ATTR_RW(console);\n-\n-\n-#define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);\n-#define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);\n-\n-#include \"solos-attrlist.c\"\n-\n-static SOLOS_GPIO_ATTR(GPIO1, 0644, geos_gpio_show, geos_gpio_store, 9);\n-static SOLOS_GPIO_ATTR(GPIO2, 0644, geos_gpio_show, geos_gpio_store, 10);\n-static SOLOS_GPIO_ATTR(GPIO3, 0644, geos_gpio_show, geos_gpio_store, 11);\n-static SOLOS_GPIO_ATTR(GPIO4, 0644, geos_gpio_show, geos_gpio_store, 12);\n-static SOLOS_GPIO_ATTR(GPIO5, 0644, geos_gpio_show, geos_gpio_store, 13);\n-static SOLOS_GPIO_ATTR(PushButton, 0444, geos_gpio_show, NULL, 14);\n-static SOLOS_GPIO_ATTR(HardwareVersion, 0444, hardware_show, NULL, 0);\n-static SOLOS_GPIO_ATTR(HardwareVariant, 0444, hardware_show, NULL, 1);\n-#undef SOLOS_ATTR_RO\n-#undef SOLOS_ATTR_RW\n-\n-#define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,\n-#define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,\n-\n-static struct attribute *solos_attrs[] = {\n-#include \"solos-attrlist.c\"\n-\tNULL\n-};\n-\n-static const struct attribute_group solos_attr_group = {\n-\t.attrs = solos_attrs,\n-\t.name = \"parameters\",\n-};\n-\n-static struct attribute *gpio_attrs[] = {\n-\t&gpio_attr_GPIO1.attr.attr,\n-\t&gpio_attr_GPIO2.attr.attr,\n-\t&gpio_attr_GPIO3.attr.attr,\n-\t&gpio_attr_GPIO4.attr.attr,\n-\t&gpio_attr_GPIO5.attr.attr,\n-\t&gpio_attr_PushButton.attr.attr,\n-\t&gpio_attr_HardwareVersion.attr.attr,\n-\t&gpio_attr_HardwareVariant.attr.attr,\n-\tNULL\n-};\n-\n-static const struct attribute_group gpio_attr_group = {\n-\t.attrs = gpio_attrs,\n-\t.name = \"gpio\",\n-};\n-\n-static int flash_upgrade(struct solos_card *card, int chip)\n-{\n-\tconst struct firmware *fw;\n-\tconst char *fw_name;\n-\tint blocksize = 0;\n-\tint numblocks = 0;\n-\tint offset;\n-\n-\tswitch (chip) {\n-\tcase 0:\n-\t\tfw_name = \"solos-FPGA.bin\";\n-\t\tif (card->atmel_flash)\n-\t\t\tblocksize = ATMEL_FPGA_BLOCK;\n-\t\telse\n-\t\t\tblocksize = SPI_FLASH_BLOCK;\n-\t\tbreak;\n-\tcase 1:\n-\t\tfw_name = \"solos-Firmware.bin\";\n-\t\tif (card->atmel_flash)\n-\t\t\tblocksize = ATMEL_SOLOS_BLOCK;\n-\t\telse\n-\t\t\tblocksize = SPI_FLASH_BLOCK;\n-\t\tbreak;\n-\tcase 2:\n-\t\tif (card->fpga_version > LEGACY_BUFFERS){\n-\t\t\tfw_name = \"solos-db-FPGA.bin\";\n-\t\t\tif (card->atmel_flash)\n-\t\t\t\tblocksize = ATMEL_FPGA_BLOCK;\n-\t\t\telse\n-\t\t\t\tblocksize = SPI_FLASH_BLOCK;\n-\t\t} else {\n-\t\t\tdev_info(&card->dev->dev, \"FPGA version doesn't support\"\n-\t\t\t\t\t\" daughter board upgrades\\n\");\n-\t\t\treturn -EPERM;\n-\t\t}\n-\t\tbreak;\n-\tcase 3:\n-\t\tif (card->fpga_version > LEGACY_BUFFERS){\n-\t\t\tfw_name = \"solos-Firmware.bin\";\n-\t\t\tif (card->atmel_flash)\n-\t\t\t\tblocksize = ATMEL_SOLOS_BLOCK;\n-\t\t\telse\n-\t\t\t\tblocksize = SPI_FLASH_BLOCK;\n-\t\t} else {\n-\t\t\tdev_info(&card->dev->dev, \"FPGA version doesn't support\"\n-\t\t\t\t\t\" daughter board upgrades\\n\");\n-\t\t\treturn -EPERM;\n-\t\t}\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (request_firmware(&fw, fw_name, &card->dev->dev))\n-\t\treturn -ENOENT;\n-\n-\tdev_info(&card->dev->dev, \"Flash upgrade starting\\n\");\n-\n-\t/* New FPGAs require driver version before permitting flash upgrades */\n-\tiowrite32(DRIVER_VERSION, card->config_regs + DRIVER_VER);\n-\n-\tnumblocks = fw->size / blocksize;\n-\tdev_info(&card->dev->dev, \"Firmware size: %zd\\n\", fw->size);\n-\tdev_info(&card->dev->dev, \"Number of blocks: %d\\n\", numblocks);\n-\t\n-\tdev_info(&card->dev->dev, \"Changing FPGA to Update mode\\n\");\n-\tiowrite32(1, card->config_regs + FPGA_MODE);\n-\t(void) ioread32(card->config_regs + FPGA_MODE); \n-\n-\t/* Set mode to Chip Erase */\n-\tif(chip == 0 || chip == 2)\n-\t\tdev_info(&card->dev->dev, \"Set FPGA Flash mode to FPGA Chip Erase\\n\");\n-\tif(chip == 1 || chip == 3)\n-\t\tdev_info(&card->dev->dev, \"Set FPGA Flash mode to Solos Chip Erase\\n\");\n-\tiowrite32((chip * 2), card->config_regs + FLASH_MODE);\n-\n-\n-\tiowrite32(1, card->config_regs + WRITE_FLASH);\n-\twait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));\n-\n-\tfor (offset = 0; offset < fw->size; offset += blocksize) {\n-\t\tint i;\n-\n-\t\t/* Clear write flag */\n-\t\tiowrite32(0, card->config_regs + WRITE_FLASH);\n-\n-\t\t/* Set mode to Block Write */\n-\t\t/* dev_info(&card->dev->dev, \"Set FPGA Flash mode to Block Write\\n\"); */\n-\t\tiowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);\n-\n-\t\t/* Copy block to buffer, swapping each 16 bits for Atmel flash */\n-\t\tfor(i = 0; i < blocksize; i += 4) {\n-\t\t\tuint32_t word;\n-\t\t\tif (card->atmel_flash)\n-\t\t\t\tword = swahb32p((uint32_t *)(fw->data + offset + i));\n-\t\t\telse\n-\t\t\t\tword = *(uint32_t *)(fw->data + offset + i);\n-\t\t\tif(card->fpga_version > LEGACY_BUFFERS)\n-\t\t\t\tiowrite32(word, FLASH_BUF + i);\n-\t\t\telse\n-\t\t\t\tiowrite32(word, RX_BUF(card, 3) + i);\n-\t\t}\n-\n-\t\t/* Specify block number and then trigger flash write */\n-\t\tiowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);\n-\t\tiowrite32(1, card->config_regs + WRITE_FLASH);\n-\t\twait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));\n-\t}\n-\n-\trelease_firmware(fw);\n-\tiowrite32(0, card->config_regs + WRITE_FLASH);\n-\tiowrite32(0, card->config_regs + FPGA_MODE);\n-\tiowrite32(0, card->config_regs + FLASH_MODE);\n-\tdev_info(&card->dev->dev, \"Returning FPGA to Data mode\\n\");\n-\treturn 0;\n-}\n-\n-static irqreturn_t solos_irq(int irq, void *dev_id)\n-{\n-\tstruct solos_card *card = dev_id;\n-\tint handled = 1;\n-\n-\tiowrite32(0, card->config_regs + IRQ_CLEAR);\n-\n-\t/* If we're up and running, just kick the tasklet to process TX/RX */\n-\tif (card->atmdev[0])\n-\t\ttasklet_schedule(&card->tlet);\n-\telse\n-\t\twake_up(&card->fw_wq);\n-\n-\treturn IRQ_RETVAL(handled);\n-}\n-\n-static void solos_bh(unsigned long card_arg)\n-{\n-\tstruct solos_card *card = (void *)card_arg;\n-\tuint32_t card_flags;\n-\tuint32_t rx_done = 0;\n-\tint port;\n-\n-\t/*\n-\t * Since fpga_tx() is going to need to read the flags under its lock,\n-\t * it can return them to us so that we don't have to hit PCI MMIO\n-\t * again for the same information\n-\t */\n-\tcard_flags = fpga_tx(card);\n-\n-\tfor (port = 0; port < card->nr_ports; port++) {\n-\t\tif (card_flags & (0x10 << port)) {\n-\t\t\tstruct pkt_hdr _hdr, *header;\n-\t\t\tstruct sk_buff *skb;\n-\t\t\tstruct atm_vcc *vcc;\n-\t\t\tint size;\n-\n-\t\t\tif (card->using_dma) {\n-\t\t\t\tskb = card->rx_skb[port];\n-\t\t\t\tcard->rx_skb[port] = NULL;\n-\n-\t\t\t\tdma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,\n-\t\t\t\t\t\t RX_DMA_SIZE, DMA_FROM_DEVICE);\n-\n-\t\t\t\theader = (void *)skb->data;\n-\t\t\t\tsize = le16_to_cpu(header->size);\n-\t\t\t\tskb_put(skb, size + sizeof(*header));\n-\t\t\t\tskb_pull(skb, sizeof(*header));\n-\t\t\t} else {\n-\t\t\t\theader = &_hdr;\n-\n-\t\t\t\trx_done |= 0x10 << port;\n-\n-\t\t\t\tmemcpy_fromio(header, RX_BUF(card, port), sizeof(*header));\n-\n-\t\t\t\tsize = le16_to_cpu(header->size);\n-\t\t\t\tif (size > (card->buffer_size - sizeof(*header))){\n-\t\t\t\t\tdev_warn(&card->dev->dev, \"Invalid buffer size\\n\");\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\n-\t\t\t\t/* Use netdev_alloc_skb() because it adds NET_SKB_PAD of\n-\t\t\t\t * headroom, and ensures we can route packets back out an\n-\t\t\t\t * Ethernet interface (for example) without having to\n-\t\t\t\t * reallocate. Adding NET_IP_ALIGN also ensures that both\n-\t\t\t\t * PPPoATM and PPPoEoBR2684 packets end up aligned. */\n-\t\t\t\tskb = netdev_alloc_skb_ip_align(NULL, size + 1);\n-\t\t\t\tif (!skb) {\n-\t\t\t\t\tif (net_ratelimit())\n-\t\t\t\t\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff for RX\\n\");\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\n-\t\t\t\tmemcpy_fromio(skb_put(skb, size),\n-\t\t\t\t\t RX_BUF(card, port) + sizeof(*header),\n-\t\t\t\t\t size);\n-\t\t\t}\n-\t\t\tif (atmdebug) {\n-\t\t\t\tdev_info(&card->dev->dev, \"Received: port %d\\n\", port);\n-\t\t\t\tdev_info(&card->dev->dev, \"size: %d VPI: %d VCI: %d\\n\",\n-\t\t\t\t\t size, le16_to_cpu(header->vpi),\n-\t\t\t\t\t le16_to_cpu(header->vci));\n-\t\t\t\tprint_buffer(skb);\n-\t\t\t}\n-\n-\t\t\tswitch (le16_to_cpu(header->type)) {\n-\t\t\tcase PKT_DATA:\n-\t\t\t\tvcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),\n-\t\t\t\t\t le16_to_cpu(header->vci));\n-\t\t\t\tif (!vcc) {\n-\t\t\t\t\tif (net_ratelimit())\n-\t\t\t\t\t\tdev_warn(&card->dev->dev, \"Received packet for unknown VPI.VCI %d.%d on port %d\\n\",\n-\t\t\t\t\t\t\t le16_to_cpu(header->vpi), le16_to_cpu(header->vci),\n-\t\t\t\t\t\t\t port);\n-\t\t\t\t\tdev_kfree_skb_any(skb);\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t\tatm_charge(vcc, skb->truesize);\n-\t\t\t\tvcc->push(vcc, skb);\n-\t\t\t\tatomic_inc(&vcc->stats->rx);\n-\t\t\t\tbreak;\n-\n-\t\t\tcase PKT_STATUS:\n-\t\t\t\tif (process_status(card, port, skb) &&\n-\t\t\t\t net_ratelimit()) {\n-\t\t\t\t\tdev_warn(&card->dev->dev, \"Bad status packet of %d bytes on port %d:\\n\", skb->len, port);\n-\t\t\t\t\tprint_buffer(skb);\n-\t\t\t\t}\n-\t\t\t\tdev_kfree_skb_any(skb);\n-\t\t\t\tbreak;\n-\n-\t\t\tcase PKT_COMMAND:\n-\t\t\tdefault: /* FIXME: Not really, surely? */\n-\t\t\t\tif (process_command(card, port, skb))\n-\t\t\t\t\tbreak;\n-\t\t\t\tspin_lock(&card->cli_queue_lock);\n-\t\t\t\tif (skb_queue_len(&card->cli_queue[port]) > 10) {\n-\t\t\t\t\tif (net_ratelimit())\n-\t\t\t\t\t\tdev_warn(&card->dev->dev, \"Dropping console response on port %d\\n\",\n-\t\t\t\t\t\t\t port);\n-\t\t\t\t\tdev_kfree_skb_any(skb);\n-\t\t\t\t} else\n-\t\t\t\t\tskb_queue_tail(&card->cli_queue[port], skb);\n-\t\t\t\tspin_unlock(&card->cli_queue_lock);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t\t/* Allocate RX skbs for any ports which need them */\n-\t\tif (card->using_dma && card->atmdev[port] &&\n-\t\t !card->rx_skb[port]) {\n-\t\t\t/* Unlike the MMIO case (qv) we can't add NET_IP_ALIGN\n-\t\t\t * here; the FPGA can only DMA to addresses which are\n-\t\t\t * aligned to 4 bytes. */\n-\t\t\tstruct sk_buff *skb = dev_alloc_skb(RX_DMA_SIZE);\n-\t\t\tif (skb) {\n-\t\t\t\tSKB_CB(skb)->dma_addr =\n-\t\t\t\t\tdma_map_single(&card->dev->dev, skb->data,\n-\t\t\t\t\t\t RX_DMA_SIZE, DMA_FROM_DEVICE);\n-\t\t\t\tiowrite32(SKB_CB(skb)->dma_addr,\n-\t\t\t\t\t card->config_regs + RX_DMA_ADDR(port));\n-\t\t\t\tcard->rx_skb[port] = skb;\n-\t\t\t} else {\n-\t\t\t\tif (net_ratelimit())\n-\t\t\t\t\tdev_warn(&card->dev->dev, \"Failed to allocate RX skb\");\n-\n-\t\t\t\t/* We'll have to try again later */\n-\t\t\t\ttasklet_schedule(&card->tlet);\n-\t\t\t}\n-\t\t}\n-\t}\n-\tif (rx_done)\n-\t\tiowrite32(rx_done, card->config_regs + FLAGS_ADDR);\n-\n-\treturn;\n-}\n-\n-static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)\n-{\n-\tstruct hlist_head *head;\n-\tstruct atm_vcc *vcc = NULL;\n-\tstruct sock *s;\n-\n-\tread_lock(&vcc_sklist_lock);\n-\thead = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];\n-\tsk_for_each(s, head) {\n-\t\tvcc = atm_sk(s);\n-\t\tif (vcc->dev == dev && vcc->vci == vci &&\n-\t\t vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE &&\n-\t\t test_bit(ATM_VF_READY, &vcc->flags))\n-\t\t\tgoto out;\n-\t}\n-\tvcc = NULL;\n- out:\n-\tread_unlock(&vcc_sklist_lock);\n-\treturn vcc;\n-}\n-\n-static int popen(struct atm_vcc *vcc)\n-{\n-\tstruct solos_card *card = vcc->dev->dev_data;\n-\tstruct sk_buff *skb;\n-\tstruct pkt_hdr *header;\n-\n-\tif (vcc->qos.aal != ATM_AAL5) {\n-\t\tdev_warn(&card->dev->dev, \"Unsupported ATM type %d\\n\",\n-\t\t\t vcc->qos.aal);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tskb = alloc_skb(sizeof(*header), GFP_KERNEL);\n-\tif (!skb) {\n-\t\tif (net_ratelimit())\n-\t\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff in popen()\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\theader = skb_put(skb, sizeof(*header));\n-\n-\theader->size = cpu_to_le16(0);\n-\theader->vpi = cpu_to_le16(vcc->vpi);\n-\theader->vci = cpu_to_le16(vcc->vci);\n-\theader->type = cpu_to_le16(PKT_POPEN);\n-\n-\tfpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);\n-\n-\tset_bit(ATM_VF_ADDR, &vcc->flags);\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\n-\treturn 0;\n-}\n-\n-static void pclose(struct atm_vcc *vcc)\n-{\n-\tstruct solos_card *card = vcc->dev->dev_data;\n-\tunsigned char port = SOLOS_CHAN(vcc->dev);\n-\tstruct sk_buff *skb, *tmpskb;\n-\tstruct pkt_hdr *header;\n-\n-\t/* Remove any yet-to-be-transmitted packets from the pending queue */\n-\tspin_lock_bh(&card->tx_queue_lock);\n-\tskb_queue_walk_safe(&card->tx_queue[port], skb, tmpskb) {\n-\t\tif (SKB_CB(skb)->vcc == vcc) {\n-\t\t\tskb_unlink(skb, &card->tx_queue[port]);\n-\t\t\tsolos_pop(vcc, skb);\n-\t\t}\n-\t}\n-\tspin_unlock_bh(&card->tx_queue_lock);\n-\n-\tskb = alloc_skb(sizeof(*header), GFP_KERNEL);\n-\tif (!skb) {\n-\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff in pclose()\\n\");\n-\t\treturn;\n-\t}\n-\theader = skb_put(skb, sizeof(*header));\n-\n-\theader->size = cpu_to_le16(0);\n-\theader->vpi = cpu_to_le16(vcc->vpi);\n-\theader->vci = cpu_to_le16(vcc->vci);\n-\theader->type = cpu_to_le16(PKT_PCLOSE);\n-\n-\tskb_get(skb);\n-\tfpga_queue(card, port, skb, NULL);\n-\n-\tif (!wait_event_timeout(card->param_wq, !skb_shared(skb), 5 * HZ))\n-\t\tdev_warn(&card->dev->dev,\n-\t\t\t \"Timeout waiting for VCC close on port %d\\n\", port);\n-\n-\tdev_kfree_skb(skb);\n-\n-\t/* Hold up vcc_destroy_socket() (our caller) until solos_bh() in the\n-\t tasklet has finished processing any incoming packets (and, more to\n-\t the point, using the vcc pointer). */\n-\ttasklet_unlock_wait(&card->tlet);\n-\n-\tclear_bit(ATM_VF_ADDR, &vcc->flags);\n-\n-\treturn;\n-}\n-\n-static int print_buffer(struct sk_buff *buf)\n-{\n-\tint len,i;\n-\tchar msg[500];\n-\tchar item[10];\n-\n-\tlen = buf->len;\n-\tfor (i = 0; i < len; i++){\n-\t\tif(i % 8 == 0)\n-\t\t\tsprintf(msg, \"%02X: \", i);\n-\n-\t\tsprintf(item,\"%02X \",*(buf->data + i));\n-\t\tstrcat(msg, item);\n-\t\tif(i % 8 == 7) {\n-\t\t\tsprintf(item, \"\\n\");\n-\t\t\tstrcat(msg, item);\n-\t\t\tprintk(KERN_DEBUG \"%s\", msg);\n-\t\t}\n-\t}\n-\tif (i % 8 != 0) {\n-\t\tsprintf(item, \"\\n\");\n-\t\tstrcat(msg, item);\n-\t\tprintk(KERN_DEBUG \"%s\", msg);\n-\t}\n-\tprintk(KERN_DEBUG \"\\n\");\n-\n-\treturn 0;\n-}\n-\n-static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,\n-\t\t struct atm_vcc *vcc)\n-{\n-\tint old_len;\n-\tunsigned long flags;\n-\n-\tSKB_CB(skb)->vcc = vcc;\n-\n-\tspin_lock_irqsave(&card->tx_queue_lock, flags);\n-\told_len = skb_queue_len(&card->tx_queue[port]);\n-\tskb_queue_tail(&card->tx_queue[port], skb);\n-\tif (!old_len)\n-\t\tcard->tx_mask |= (1 << port);\n-\tspin_unlock_irqrestore(&card->tx_queue_lock, flags);\n-\n-\t/* Theoretically we could just schedule the tasklet here, but\n-\t that introduces latency we don't want -- it's noticeable */\n-\tif (!old_len)\n-\t\tfpga_tx(card);\n-}\n-\n-static uint32_t fpga_tx(struct solos_card *card)\n-{\n-\tuint32_t tx_pending, card_flags;\n-\tuint32_t tx_started = 0;\n-\tstruct sk_buff *skb;\n-\tstruct atm_vcc *vcc;\n-\tunsigned char port;\n-\tunsigned long flags;\n-\n-\tspin_lock_irqsave(&card->tx_lock, flags);\n-\t\n-\tcard_flags = ioread32(card->config_regs + FLAGS_ADDR);\n-\t/*\n-\t * The queue lock is required for _writing_ to tx_mask, but we're\n-\t * OK to read it here without locking. The only potential update\n-\t * that we could race with is in fpga_queue() where it sets a bit\n-\t * for a new port... but it's going to call this function again if\n-\t * it's doing that, anyway.\n-\t */\n-\ttx_pending = card->tx_mask & ~card_flags;\n-\n-\tfor (port = 0; tx_pending; tx_pending >>= 1, port++) {\n-\t\tif (tx_pending & 1) {\n-\t\t\tstruct sk_buff *oldskb = card->tx_skb[port];\n-\t\t\tif (oldskb) {\n-\t\t\t\tdma_unmap_single(&card->dev->dev, SKB_CB(oldskb)->dma_addr,\n-\t\t\t\t\t\t oldskb->len, DMA_TO_DEVICE);\n-\t\t\t\tcard->tx_skb[port] = NULL;\n-\t\t\t}\n-\t\t\tspin_lock(&card->tx_queue_lock);\n-\t\t\tskb = skb_dequeue(&card->tx_queue[port]);\n-\t\t\tif (!skb)\n-\t\t\t\tcard->tx_mask &= ~(1 << port);\n-\t\t\tspin_unlock(&card->tx_queue_lock);\n-\n-\t\t\tif (skb && !card->using_dma) {\n-\t\t\t\tmemcpy_toio(TX_BUF(card, port), skb->data, skb->len);\n-\t\t\t\ttx_started |= 1 << port;\n-\t\t\t\toldskb = skb; /* We're done with this skb already */\n-\t\t\t} else if (skb && card->using_dma) {\n-\t\t\t\tunsigned char *data = skb->data;\n-\t\t\t\tif ((unsigned long)data & card->dma_alignment) {\n-\t\t\t\t\tdata = card->dma_bounce + (BUF_SIZE * port);\n-\t\t\t\t\tmemcpy(data, skb->data, skb->len);\n-\t\t\t\t}\n-\t\t\t\tSKB_CB(skb)->dma_addr = dma_map_single(&card->dev->dev, data,\n-\t\t\t\t\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\t\t\t\tcard->tx_skb[port] = skb;\n-\t\t\t\tiowrite32(SKB_CB(skb)->dma_addr,\n-\t\t\t\t\t card->config_regs + TX_DMA_ADDR(port));\n-\t\t\t}\n-\n-\t\t\tif (!oldskb)\n-\t\t\t\tcontinue;\n-\n-\t\t\t/* Clean up and free oldskb now it's gone */\n-\t\t\tif (atmdebug) {\n-\t\t\t\tstruct pkt_hdr *header = (void *)oldskb->data;\n-\t\t\t\tint size = le16_to_cpu(header->size);\n-\n-\t\t\t\tskb_pull(oldskb, sizeof(*header));\n-\t\t\t\tdev_info(&card->dev->dev, \"Transmitted: port %d\\n\",\n-\t\t\t\t\t port);\n-\t\t\t\tdev_info(&card->dev->dev, \"size: %d VPI: %d VCI: %d\\n\",\n-\t\t\t\t\t size, le16_to_cpu(header->vpi),\n-\t\t\t\t\t le16_to_cpu(header->vci));\n-\t\t\t\tprint_buffer(oldskb);\n-\t\t\t}\n-\n-\t\t\tvcc = SKB_CB(oldskb)->vcc;\n-\n-\t\t\tif (vcc) {\n-\t\t\t\tatomic_inc(&vcc->stats->tx);\n-\t\t\t\tsolos_pop(vcc, oldskb);\n-\t\t\t} else {\n-\t\t\t\tdev_kfree_skb_irq(oldskb);\n-\t\t\t\twake_up(&card->param_wq);\n-\t\t\t}\n-\t\t}\n-\t}\n-\t/* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */\n-\tif (tx_started)\n-\t\tiowrite32(tx_started, card->config_regs + FLAGS_ADDR);\n-\n-\tspin_unlock_irqrestore(&card->tx_lock, flags);\n-\treturn card_flags;\n-}\n-\n-static int psend(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct solos_card *card = vcc->dev->dev_data;\n-\tstruct pkt_hdr *header;\n-\tint pktlen;\n-\n-\tpktlen = skb->len;\n-\tif (pktlen > (BUF_SIZE - sizeof(*header))) {\n-\t\tdev_warn(&card->dev->dev, \"Length of PDU is too large. Dropping PDU.\\n\");\n-\t\tsolos_pop(vcc, skb);\n-\t\treturn 0;\n-\t}\n-\n-\tif (!skb_clone_writable(skb, sizeof(*header))) {\n-\t\tint expand_by = 0;\n-\t\tint ret;\n-\n-\t\tif (skb_headroom(skb) < sizeof(*header))\n-\t\t\texpand_by = sizeof(*header) - skb_headroom(skb);\n-\n-\t\tret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);\n-\t\tif (ret) {\n-\t\t\tdev_warn(&card->dev->dev, \"pskb_expand_head failed.\\n\");\n-\t\t\tsolos_pop(vcc, skb);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\theader = skb_push(skb, sizeof(*header));\n-\n-\t/* This does _not_ include the size of the header */\n-\theader->size = cpu_to_le16(pktlen);\n-\theader->vpi = cpu_to_le16(vcc->vpi);\n-\theader->vci = cpu_to_le16(vcc->vci);\n-\theader->type = cpu_to_le16(PKT_DATA);\n-\n-\tfpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);\n-\n-\treturn 0;\n-}\n-\n-static const struct atmdev_ops fpga_ops = {\n-\t.open =\t\tpopen,\n-\t.close =\tpclose,\n-\t.ioctl =\tNULL,\n-\t.send =\t\tpsend,\n-\t.send_oam =\tNULL,\n-\t.phy_put =\tNULL,\n-\t.phy_get =\tNULL,\n-\t.change_qos =\tNULL,\n-\t.proc_read =\tNULL,\n-\t.owner =\tTHIS_MODULE\n-};\n-\n-static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)\n-{\n-\tint err;\n-\tuint16_t fpga_ver;\n-\tuint8_t major_ver, minor_ver;\n-\tuint32_t data32;\n-\tstruct solos_card *card;\n-\n-\tcard = kzalloc_obj(*card);\n-\tif (!card)\n-\t\treturn -ENOMEM;\n-\n-\tcard->dev = dev;\n-\tinit_waitqueue_head(&card->fw_wq);\n-\tinit_waitqueue_head(&card->param_wq);\n-\n-\terr = pci_enable_device(dev);\n-\tif (err) {\n-\t\tdev_warn(&dev->dev, \"Failed to enable PCI device\\n\");\n-\t\tgoto out;\n-\t}\n-\n-\terr = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));\n-\tif (err) {\n-\t\tdev_warn(&dev->dev, \"Failed to set 32-bit DMA mask\\n\");\n-\t\tgoto out;\n-\t}\n-\n-\terr = pci_request_regions(dev, \"solos\");\n-\tif (err) {\n-\t\tdev_warn(&dev->dev, \"Failed to request regions\\n\");\n-\t\tgoto out;\n-\t}\n-\n-\tcard->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);\n-\tif (!card->config_regs) {\n-\t\tdev_warn(&dev->dev, \"Failed to ioremap config registers\\n\");\n-\t\terr = -ENOMEM;\n-\t\tgoto out_release_regions;\n-\t}\n-\tcard->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);\n-\tif (!card->buffers) {\n-\t\tdev_warn(&dev->dev, \"Failed to ioremap data buffers\\n\");\n-\t\terr = -ENOMEM;\n-\t\tgoto out_unmap_config;\n-\t}\n-\n-\tif (reset) {\n-\t\tiowrite32(1, card->config_regs + FPGA_MODE);\n-\t\tioread32(card->config_regs + FPGA_MODE);\n-\n-\t\tiowrite32(0, card->config_regs + FPGA_MODE);\n-\t\tioread32(card->config_regs + FPGA_MODE);\n-\t}\n-\n-\tdata32 = ioread32(card->config_regs + FPGA_VER);\n-\tfpga_ver = (data32 & 0x0000FFFF);\n-\tmajor_ver = ((data32 & 0xFF000000) >> 24);\n-\tminor_ver = ((data32 & 0x00FF0000) >> 16);\n-\tcard->fpga_version = FPGA_VERSION(major_ver,minor_ver);\n-\tif (card->fpga_version > LEGACY_BUFFERS)\n-\t\tcard->buffer_size = BUF_SIZE;\n-\telse\n-\t\tcard->buffer_size = OLD_BUF_SIZE;\n-\tdev_info(&dev->dev, \"Solos FPGA Version %d.%02d svn-%d\\n\",\n-\t\t major_ver, minor_ver, fpga_ver);\n-\n-\tif (fpga_ver < 37 && (fpga_upgrade || firmware_upgrade ||\n-\t\t\t db_fpga_upgrade || db_firmware_upgrade)) {\n-\t\tdev_warn(&dev->dev,\n-\t\t\t \"FPGA too old; cannot upgrade flash. Use JTAG.\\n\");\n-\t\tfpga_upgrade = firmware_upgrade = 0;\n-\t\tdb_fpga_upgrade = db_firmware_upgrade = 0;\n-\t}\n-\n-\t/* Stopped using Atmel flash after 0.03-38 */\n-\tif (fpga_ver < 39)\n-\t\tcard->atmel_flash = 1;\n-\telse\n-\t\tcard->atmel_flash = 0;\n-\n-\tdata32 = ioread32(card->config_regs + PORTS);\n-\tcard->nr_ports = (data32 & 0x000000FF);\n-\n-\tif (card->fpga_version >= DMA_SUPPORTED) {\n-\t\tpci_set_master(dev);\n-\t\tcard->using_dma = 1;\n-\t\tif (1) { /* All known FPGA versions so far */\n-\t\t\tcard->dma_alignment = 3;\n-\t\t\tcard->dma_bounce = kmalloc_array(card->nr_ports,\n-\t\t\t\t\t\t\t BUF_SIZE, GFP_KERNEL);\n-\t\t\tif (!card->dma_bounce) {\n-\t\t\t\tdev_warn(&card->dev->dev, \"Failed to allocate DMA bounce buffers\\n\");\n-\t\t\t\terr = -ENOMEM;\n-\t\t\t\t/* Fallback to MMIO doesn't work */\n-\t\t\t\tgoto out_unmap_both;\n-\t\t\t}\n-\t\t}\n-\t} else {\n-\t\tcard->using_dma = 0;\n-\t\t/* Set RX empty flag for all ports */\n-\t\tiowrite32(0xF0, card->config_regs + FLAGS_ADDR);\n-\t}\n-\n-\tpci_set_drvdata(dev, card);\n-\n-\ttasklet_init(&card->tlet, solos_bh, (unsigned long)card);\n-\tspin_lock_init(&card->tx_lock);\n-\tspin_lock_init(&card->tx_queue_lock);\n-\tspin_lock_init(&card->cli_queue_lock);\n-\tspin_lock_init(&card->param_queue_lock);\n-\tINIT_LIST_HEAD(&card->param_queue);\n-\n-\terr = request_irq(dev->irq, solos_irq, IRQF_SHARED,\n-\t\t\t \"solos-pci\", card);\n-\tif (err) {\n-\t\tdev_dbg(&card->dev->dev, \"Failed to request interrupt IRQ: %d\\n\", dev->irq);\n-\t\tgoto out_unmap_both;\n-\t}\n-\n-\tiowrite32(1, card->config_regs + IRQ_EN_ADDR);\n-\n-\tif (fpga_upgrade)\n-\t\tflash_upgrade(card, 0);\n-\n-\tif (firmware_upgrade)\n-\t\tflash_upgrade(card, 1);\n-\n-\tif (db_fpga_upgrade)\n-\t\tflash_upgrade(card, 2);\n-\n-\tif (db_firmware_upgrade)\n-\t\tflash_upgrade(card, 3);\n-\n-\terr = atm_init(card, &dev->dev);\n-\tif (err)\n-\t\tgoto out_free_irq;\n-\n-\tif (card->fpga_version >= DMA_SUPPORTED &&\n-\t sysfs_create_group(&card->dev->dev.kobj, &gpio_attr_group))\n-\t\tdev_err(&card->dev->dev, \"Could not register parameter group for GPIOs\\n\");\n-\n-\treturn 0;\n-\n- out_free_irq:\n-\tiowrite32(0, card->config_regs + IRQ_EN_ADDR);\n-\tfree_irq(dev->irq, card);\n-\ttasklet_kill(&card->tlet);\n-\t\n- out_unmap_both:\n-\tkfree(card->dma_bounce);\n-\tpci_iounmap(dev, card->buffers);\n- out_unmap_config:\n-\tpci_iounmap(dev, card->config_regs);\n- out_release_regions:\n-\tpci_release_regions(dev);\n- out:\n-\tkfree(card);\n-\treturn err;\n-}\n-\n-static int atm_init(struct solos_card *card, struct device *parent)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < card->nr_ports; i++) {\n-\t\tstruct sk_buff *skb;\n-\t\tstruct pkt_hdr *header;\n-\n-\t\tskb_queue_head_init(&card->tx_queue[i]);\n-\t\tskb_queue_head_init(&card->cli_queue[i]);\n-\n-\t\tcard->atmdev[i] = atm_dev_register(\"solos-pci\", parent, &fpga_ops, -1, NULL);\n-\t\tif (!card->atmdev[i]) {\n-\t\t\tdev_err(&card->dev->dev, \"Could not register ATM device %d\\n\", i);\n-\t\t\tatm_remove(card);\n-\t\t\treturn -ENODEV;\n-\t\t}\n-\t\tif (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))\n-\t\t\tdev_err(&card->dev->dev, \"Could not register console for ATM device %d\\n\", i);\n-\t\tif (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))\n-\t\t\tdev_err(&card->dev->dev, \"Could not register parameter group for ATM device %d\\n\", i);\n-\n-\t\tdev_info(&card->dev->dev, \"Registered ATM device %d\\n\", card->atmdev[i]->number);\n-\n-\t\tcard->atmdev[i]->ci_range.vpi_bits = 8;\n-\t\tcard->atmdev[i]->ci_range.vci_bits = 16;\n-\t\tcard->atmdev[i]->dev_data = card;\n-\t\tcard->atmdev[i]->phy_data = (void *)(unsigned long)i;\n-\t\tatm_dev_signal_change(card->atmdev[i], ATM_PHY_SIG_FOUND);\n-\n-\t\tskb = alloc_skb(sizeof(*header), GFP_KERNEL);\n-\t\tif (!skb) {\n-\t\t\tdev_warn(&card->dev->dev, \"Failed to allocate sk_buff in atm_init()\\n\");\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\theader = skb_put(skb, sizeof(*header));\n-\n-\t\theader->size = cpu_to_le16(0);\n-\t\theader->vpi = cpu_to_le16(0);\n-\t\theader->vci = cpu_to_le16(0);\n-\t\theader->type = cpu_to_le16(PKT_STATUS);\n-\n-\t\tfpga_queue(card, i, skb, NULL);\n-\t}\n-\treturn 0;\n-}\n-\n-static void atm_remove(struct solos_card *card)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < card->nr_ports; i++) {\n-\t\tif (card->atmdev[i]) {\n-\t\t\tstruct sk_buff *skb;\n-\n-\t\t\tdev_info(&card->dev->dev, \"Unregistering ATM device %d\\n\", card->atmdev[i]->number);\n-\n-\t\t\tsysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);\n-\t\t\tatm_dev_deregister(card->atmdev[i]);\n-\n-\t\t\tskb = card->rx_skb[i];\n-\t\t\tif (skb) {\n-\t\t\t\tdma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,\n-\t\t\t\t\t\t RX_DMA_SIZE, DMA_FROM_DEVICE);\n-\t\t\t\tdev_kfree_skb(skb);\n-\t\t\t}\n-\t\t\tskb = card->tx_skb[i];\n-\t\t\tif (skb) {\n-\t\t\t\tdma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,\n-\t\t\t\t\t\t skb->len, DMA_TO_DEVICE);\n-\t\t\t\tdev_kfree_skb(skb);\n-\t\t\t}\n-\t\t\twhile ((skb = skb_dequeue(&card->tx_queue[i])))\n-\t\t\t\tdev_kfree_skb(skb);\n- \n-\t\t}\n-\t}\n-}\n-\n-static void fpga_remove(struct pci_dev *dev)\n-{\n-\tstruct solos_card *card = pci_get_drvdata(dev);\n-\t\n-\t/* Disable IRQs */\n-\tiowrite32(0, card->config_regs + IRQ_EN_ADDR);\n-\n-\t/* Reset FPGA */\n-\tiowrite32(1, card->config_regs + FPGA_MODE);\n-\t(void)ioread32(card->config_regs + FPGA_MODE); \n-\n-\tif (card->fpga_version >= DMA_SUPPORTED)\n-\t\tsysfs_remove_group(&card->dev->dev.kobj, &gpio_attr_group);\n-\n-\tatm_remove(card);\n-\n-\tfree_irq(dev->irq, card);\n-\ttasklet_kill(&card->tlet);\n-\n-\tkfree(card->dma_bounce);\n-\n-\t/* Release device from reset */\n-\tiowrite32(0, card->config_regs + FPGA_MODE);\n-\t(void)ioread32(card->config_regs + FPGA_MODE); \n-\n-\tpci_iounmap(dev, card->buffers);\n-\tpci_iounmap(dev, card->config_regs);\n-\n-\tpci_release_regions(dev);\n-\tpci_disable_device(dev);\n-\n-\tkfree(card);\n-}\n-\n-static const struct pci_device_id fpga_pci_tbl[] = {\n-\t{ 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },\n-\t{ 0, }\n-};\n-\n-MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);\n-\n-static struct pci_driver fpga_driver = {\n-\t.name =\t\t\"solos\",\n-\t.id_table =\tfpga_pci_tbl,\n-\t.probe =\tfpga_probe,\n-\t.remove =\tfpga_remove,\n-};\n-\n-\n-static int __init solos_pci_init(void)\n-{\n-\tBUILD_BUG_ON(sizeof(struct solos_skb_cb) > sizeof(((struct sk_buff *)0)->cb));\n-\n-\tprintk(KERN_INFO \"Solos PCI Driver Version %s\\n\", VERSION);\n-\treturn pci_register_driver(&fpga_driver);\n-}\n-\n-static void __exit solos_pci_exit(void)\n-{\n-\tpci_unregister_driver(&fpga_driver);\n-\tprintk(KERN_INFO \"Solos PCI Driver %s Unloaded\\n\", VERSION);\n-}\n-\n-module_init(solos_pci_init);\n-module_exit(solos_pci_exit);\ndiff --git a/drivers/atm/suni.c b/drivers/atm/suni.c\ndeleted file mode 100644\nindex bb588c98216d..000000000000\n--- a/drivers/atm/suni.c\n+++ /dev/null\n@@ -1,391 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * drivers/atm/suni.c - S/UNI PHY driver\n- *\n- * Supports the following:\n- * \tPMC PM5346 S/UNI LITE\n- * \tPMC PM5350 S/UNI 155 ULTRA\n- * \tPMC PM5355 S/UNI 622\n- */\n- \n-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#include \"suni.h\"\n-\n-\n-#if 0\n-#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)\n-#else\n-#define DPRINTK(format,args...)\n-#endif\n-\n-#define PRIV(dev) ((struct suni_priv *) dev->phy_data)\n-\n-#define PUT(val,reg) dev->ops->phy_put(dev,val,SUNI_##reg)\n-#define GET(reg) dev->ops->phy_get(dev,SUNI_##reg)\n-#define REG_CHANGE(mask,shift,value,reg) \\\n- PUT((GET(reg) & ~(mask)) | ((value) << (shift)),reg)\n-\n-\n-static struct timer_list poll_timer;\n-static struct suni_priv *sunis = NULL;\n-static DEFINE_SPINLOCK(sunis_lock);\n-\n-\n-#define ADD_LIMITED(s,v) \\\n- atomic_add((v),&stats->s); \\\n- if (atomic_read(&stats->s) < 0) atomic_set(&stats->s,INT_MAX);\n-\n-\n-static void suni_hz(struct timer_list *timer)\n-{\n-\tstruct suni_priv *walk;\n-\tstruct atm_dev *dev;\n-\tstruct k_sonet_stats *stats;\n-\n-\tfor (walk = sunis; walk; walk = walk->next) {\n-\t\tdev = walk->dev;\n-\t\tstats = &walk->sonet_stats;\n-\t\tPUT(0,MRI); /* latch counters */\n-\t\tudelay(1);\n-\t\tADD_LIMITED(section_bip,(GET(RSOP_SBL) & 0xff) |\n-\t\t ((GET(RSOP_SBM) & 0xff) << 8));\n-\t\tADD_LIMITED(line_bip,(GET(RLOP_LBL) & 0xff) |\n-\t\t ((GET(RLOP_LB) & 0xff) << 8) |\n-\t\t ((GET(RLOP_LBM) & 0xf) << 16));\n-\t\tADD_LIMITED(path_bip,(GET(RPOP_PBL) & 0xff) |\n-\t\t ((GET(RPOP_PBM) & 0xff) << 8));\n-\t\tADD_LIMITED(line_febe,(GET(RLOP_LFL) & 0xff) |\n-\t\t ((GET(RLOP_LF) & 0xff) << 8) |\n-\t\t ((GET(RLOP_LFM) & 0xf) << 16));\n-\t\tADD_LIMITED(path_febe,(GET(RPOP_PFL) & 0xff) |\n-\t\t ((GET(RPOP_PFM) & 0xff) << 8));\n-\t\tADD_LIMITED(corr_hcs,GET(RACP_CHEC) & 0xff);\n-\t\tADD_LIMITED(uncorr_hcs,GET(RACP_UHEC) & 0xff);\n-\t\tADD_LIMITED(rx_cells,(GET(RACP_RCCL) & 0xff) |\n-\t\t ((GET(RACP_RCC) & 0xff) << 8) |\n-\t\t ((GET(RACP_RCCM) & 7) << 16));\n-\t\tADD_LIMITED(tx_cells,(GET(TACP_TCCL) & 0xff) |\n-\t\t ((GET(TACP_TCC) & 0xff) << 8) |\n-\t\t ((GET(TACP_TCCM) & 7) << 16));\n-\t}\n-\tif (timer) mod_timer(&poll_timer,jiffies+HZ);\n-}\n-\n-\n-#undef ADD_LIMITED\n-\n-\n-static int fetch_stats(struct atm_dev *dev,struct sonet_stats __user *arg,int zero)\n-{\n-\tstruct sonet_stats tmp;\n-\tint error = 0;\n-\n-\tsonet_copy_stats(&PRIV(dev)->sonet_stats,&tmp);\n-\tif (arg) error = copy_to_user(arg,&tmp,sizeof(tmp));\n-\tif (zero && !error) sonet_subtract_stats(&PRIV(dev)->sonet_stats,&tmp);\n-\treturn error ? -EFAULT : 0;\n-}\n-\n-\n-#define HANDLE_FLAG(flag,reg,bit) \\\n- if (todo & flag) { \\\n- if (set) PUT(GET(reg) | bit,reg); \\\n- else PUT(GET(reg) & ~bit,reg); \\\n- todo &= ~flag; \\\n- }\n-\n-\n-static int change_diag(struct atm_dev *dev,void __user *arg,int set)\n-{\n-\tint todo;\n-\n-\tif (get_user(todo,(int __user *)arg)) return -EFAULT;\n-\tHANDLE_FLAG(SONET_INS_SBIP,TSOP_DIAG,SUNI_TSOP_DIAG_DBIP8);\n-\tHANDLE_FLAG(SONET_INS_LBIP,TLOP_DIAG,SUNI_TLOP_DIAG_DBIP);\n-\tHANDLE_FLAG(SONET_INS_PBIP,TPOP_CD,SUNI_TPOP_DIAG_DB3);\n-\tHANDLE_FLAG(SONET_INS_FRAME,RSOP_CIE,SUNI_RSOP_CIE_FOOF);\n-\tHANDLE_FLAG(SONET_INS_LAIS,TSOP_CTRL,SUNI_TSOP_CTRL_LAIS);\n-\tHANDLE_FLAG(SONET_INS_PAIS,TPOP_CD,SUNI_TPOP_DIAG_PAIS);\n-\tHANDLE_FLAG(SONET_INS_LOS,TSOP_DIAG,SUNI_TSOP_DIAG_DLOS);\n-\tHANDLE_FLAG(SONET_INS_HCS,TACP_CS,SUNI_TACP_CS_DHCS);\n-\treturn put_user(todo,(int __user *)arg) ? -EFAULT : 0;\n-}\n-\n-\n-#undef HANDLE_FLAG\n-\n-\n-static int get_diag(struct atm_dev *dev,void __user *arg)\n-{\n-\tint set;\n-\n-\tset = 0;\n-\tif (GET(TSOP_DIAG) & SUNI_TSOP_DIAG_DBIP8) set |= SONET_INS_SBIP;\n-\tif (GET(TLOP_DIAG) & SUNI_TLOP_DIAG_DBIP) set |= SONET_INS_LBIP;\n-\tif (GET(TPOP_CD) & SUNI_TPOP_DIAG_DB3) set |= SONET_INS_PBIP;\n-\t/* SONET_INS_FRAME is one-shot only */\n-\tif (GET(TSOP_CTRL) & SUNI_TSOP_CTRL_LAIS) set |= SONET_INS_LAIS;\n-\tif (GET(TPOP_CD) & SUNI_TPOP_DIAG_PAIS) set |= SONET_INS_PAIS;\n-\tif (GET(TSOP_DIAG) & SUNI_TSOP_DIAG_DLOS) set |= SONET_INS_LOS;\n-\tif (GET(TACP_CS) & SUNI_TACP_CS_DHCS) set |= SONET_INS_HCS;\n-\treturn put_user(set,(int __user *)arg) ? -EFAULT : 0;\n-}\n-\n-\n-static int set_loopback(struct atm_dev *dev,int mode)\n-{\n-\tunsigned char control;\n-\tint reg, dle, lle;\n-\n-\tif (PRIV(dev)->type == SUNI_MRI_TYPE_PM5355) {\n-\t\treg = SUNI_MCM;\n-\t\tdle = SUNI_MCM_DLE;\n-\t\tlle = SUNI_MCM_LLE;\n-\t} else {\n-\t\treg = SUNI_MCT;\n-\t\tdle = SUNI_MCT_DLE;\n-\t\tlle = SUNI_MCT_LLE;\n-\t}\n-\n-\tcontrol = dev->ops->phy_get(dev, reg) & ~(dle | lle);\n-\tswitch (mode) {\n-\t\tcase ATM_LM_NONE:\n-\t\t\tbreak;\n-\t\tcase ATM_LM_LOC_PHY:\n-\t\t\tcontrol |= dle;\n-\t\t\tbreak;\n-\t\tcase ATM_LM_RMT_PHY:\n-\t\t\tcontrol |= lle;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t}\n-\tdev->ops->phy_put(dev, control, reg);\n-\tPRIV(dev)->loop_mode = mode;\n-\treturn 0;\n-}\n-\n-/*\n- * SONET vs. SDH Configuration\n- *\n- * Z0INS (register 0x06): 0 for SONET, 1 for SDH\n- * ENSS (register 0x3D): 0 for SONET, 1 for SDH\n- * LEN16 (register 0x28): 0 for SONET, 1 for SDH (n/a for S/UNI 155 QUAD)\n- * LEN16 (register 0x50): 0 for SONET, 1 for SDH (n/a for S/UNI 155 QUAD)\n- * S[1:0] (register 0x46): 00 for SONET, 10 for SDH\n- */\n-\n-static int set_sonet(struct atm_dev *dev)\n-{\n-\tif (PRIV(dev)->type == SUNI_MRI_TYPE_PM5355) {\n-\t\tPUT(GET(RPOP_RC) & ~SUNI_RPOP_RC_ENSS, RPOP_RC);\n-\t\tPUT(GET(SSTB_CTRL) & ~SUNI_SSTB_CTRL_LEN16, SSTB_CTRL);\n-\t\tPUT(GET(SPTB_CTRL) & ~SUNI_SPTB_CTRL_LEN16, SPTB_CTRL);\n-\t}\n-\n-\tREG_CHANGE(SUNI_TPOP_APM_S, SUNI_TPOP_APM_S_SHIFT,\n-\t\t SUNI_TPOP_S_SONET, TPOP_APM);\n-\n-\treturn 0;\n-}\n-\n-static int set_sdh(struct atm_dev *dev)\n-{\n-\tif (PRIV(dev)->type == SUNI_MRI_TYPE_PM5355) {\n-\t\tPUT(GET(RPOP_RC) | SUNI_RPOP_RC_ENSS, RPOP_RC);\n-\t\tPUT(GET(SSTB_CTRL) | SUNI_SSTB_CTRL_LEN16, SSTB_CTRL);\n-\t\tPUT(GET(SPTB_CTRL) | SUNI_SPTB_CTRL_LEN16, SPTB_CTRL);\n-\t}\n-\n-\tREG_CHANGE(SUNI_TPOP_APM_S, SUNI_TPOP_APM_S_SHIFT,\n-\t\t SUNI_TPOP_S_SDH, TPOP_APM);\n-\n-\treturn 0;\n-}\n-\n-\n-static int get_framing(struct atm_dev *dev, void __user *arg)\n-{\n-\tint framing;\n-\tunsigned char s;\n-\n-\n-\ts = (GET(TPOP_APM) & SUNI_TPOP_APM_S) >> SUNI_TPOP_APM_S_SHIFT;\n-\tif (s == SUNI_TPOP_S_SONET)\n-\t\tframing = SONET_FRAME_SONET;\n-\telse\n-\t\tframing = SONET_FRAME_SDH;\n-\n-\treturn put_user(framing, (int __user *) arg) ? -EFAULT : 0;\n-}\n-\n-static int set_framing(struct atm_dev *dev, void __user *arg)\n-{\n-\tint mode;\n-\n-\tif (get_user(mode, (int __user *) arg))\n-\t\treturn -EFAULT;\n-\n-\tif (mode == SONET_FRAME_SONET)\n-\t\treturn set_sonet(dev);\n-\telse if (mode == SONET_FRAME_SDH)\n-\t\treturn set_sdh(dev);\n-\n-\treturn -EINVAL;\n-}\n-\n-\n-static int suni_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)\n-{\n-\tswitch (cmd) {\n-\t\tcase SONET_GETSTATZ:\n-\t\tcase SONET_GETSTAT:\n-\t\t\treturn fetch_stats(dev, arg, cmd == SONET_GETSTATZ);\n-\t\tcase SONET_SETDIAG:\n-\t\t\treturn change_diag(dev,arg,1);\n-\t\tcase SONET_CLRDIAG:\n-\t\t\treturn change_diag(dev,arg,0);\n-\t\tcase SONET_GETDIAG:\n-\t\t\treturn get_diag(dev,arg);\n-\t\tcase SONET_SETFRAMING:\n-\t\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\t\treturn -EPERM;\n-\t\t\treturn set_framing(dev, arg);\n-\t\tcase SONET_GETFRAMING:\n-\t\t\treturn get_framing(dev, arg);\n-\t\tcase SONET_GETFRSENSE:\n-\t\t\treturn -EINVAL;\n-\t\tcase ATM_SETLOOP:\n-\t\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\t\treturn -EPERM;\n-\t\t\treturn set_loopback(dev,(int)(unsigned long)arg);\n-\t\tcase ATM_GETLOOP:\n-\t\t\treturn put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?\n-\t\t\t -EFAULT : 0;\n-\t\tcase ATM_QUERYLOOP:\n-\t\t\treturn put_user(ATM_LM_LOC_PHY | ATM_LM_RMT_PHY,\n-\t\t\t (int __user *) arg) ? -EFAULT : 0;\n-\t\tdefault:\n-\t\t\treturn -ENOIOCTLCMD;\n-\t}\n-}\n-\n-\n-static void poll_los(struct atm_dev *dev)\n-{\n-\tatm_dev_signal_change(dev,\n-\t\tGET(RSOP_SIS) & SUNI_RSOP_SIS_LOSV ?\n-\t\tATM_PHY_SIG_LOST : ATM_PHY_SIG_FOUND);\n-}\n-\n-\n-static void suni_int(struct atm_dev *dev)\n-{\n-\tpoll_los(dev);\n-\tprintk(KERN_NOTICE \"%s(itf %d): signal %s\\n\",dev->type,dev->number,\n-\t dev->signal == ATM_PHY_SIG_LOST ? \"lost\" : \"detected again\");\n-}\n-\n-\n-static int suni_start(struct atm_dev *dev)\n-{\n-\tunsigned long flags;\n-\tint first;\n-\n-\tspin_lock_irqsave(&sunis_lock,flags);\n-\tfirst = !sunis;\n-\tPRIV(dev)->next = sunis;\n-\tsunis = PRIV(dev);\n-\tspin_unlock_irqrestore(&sunis_lock,flags);\n-\tmemset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats));\n-\tPUT(GET(RSOP_CIE) | SUNI_RSOP_CIE_LOSE,RSOP_CIE);\n-\t\t/* interrupt on loss of signal */\n-\tpoll_los(dev); /* ... and clear SUNI interrupts */\n-\tif (dev->signal == ATM_PHY_SIG_LOST)\n-\t\tprintk(KERN_WARNING \"%s(itf %d): no signal\\n\",dev->type,\n-\t\t dev->number);\n-\tPRIV(dev)->loop_mode = ATM_LM_NONE;\n-\tsuni_hz(NULL); /* clear SUNI counters */\n-\t(void) fetch_stats(dev,NULL,1); /* clear kernel counters */\n-\tif (first) {\n-\t\ttimer_setup(&poll_timer, suni_hz, 0);\n-\t\tpoll_timer.expires = jiffies+HZ;\n-#if 0\n-printk(KERN_DEBUG \"[u] p=0x%lx,n=0x%lx\\n\",(unsigned long) poll_timer.list.prev,\n- (unsigned long) poll_timer.list.next);\n-#endif\n-\t\tadd_timer(&poll_timer);\n-\t}\n-\treturn 0;\n-}\n-\n-\n-static int suni_stop(struct atm_dev *dev)\n-{\n-\tstruct suni_priv **walk;\n-\tunsigned long flags;\n-\n-\t/* let SAR driver worry about stopping interrupts */\n-\tspin_lock_irqsave(&sunis_lock,flags);\n-\tfor (walk = &sunis; *walk != PRIV(dev);\n-\t walk = &PRIV((*walk)->dev)->next);\n-\t*walk = PRIV((*walk)->dev)->next;\n-\tif (!sunis) timer_delete_sync(&poll_timer);\n-\tspin_unlock_irqrestore(&sunis_lock,flags);\n-\tkfree(PRIV(dev));\n-\n-\treturn 0;\n-}\n-\n-\n-static const struct atmphy_ops suni_ops = {\n-\t.start\t\t= suni_start,\n-\t.ioctl\t\t= suni_ioctl,\n-\t.interrupt\t= suni_int,\n-\t.stop\t\t= suni_stop,\n-};\n-\n-\n-int suni_init(struct atm_dev *dev)\n-{\n-\tunsigned char mri;\n-\n-\tif (!(dev->phy_data = kmalloc_obj(struct suni_priv)))\n-\t\treturn -ENOMEM;\n-\tPRIV(dev)->dev = dev;\n-\n-\tmri = GET(MRI); /* reset SUNI */\n-\tPRIV(dev)->type = (mri & SUNI_MRI_TYPE) >> SUNI_MRI_TYPE_SHIFT;\n-\tPUT(mri | SUNI_MRI_RESET,MRI);\n-\tPUT(mri,MRI);\n-\tPUT((GET(MT) & SUNI_MT_DS27_53),MT); /* disable all tests */\n- set_sonet(dev);\n-\tREG_CHANGE(SUNI_TACP_IUCHP_CLP,0,SUNI_TACP_IUCHP_CLP,\n-\t TACP_IUCHP); /* idle cells */\n-\tPUT(SUNI_IDLE_PATTERN,TACP_IUCPOP);\n-\tdev->phy = &suni_ops;\n-\n-\treturn 0;\n-}\n-\n-EXPORT_SYMBOL(suni_init);\n-\n-MODULE_DESCRIPTION(\"S/UNI PHY driver\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/net/atm/clip.c b/net/atm/clip.c\ndeleted file mode 100644\nindex 516b2214680b..000000000000\n--- a/net/atm/clip.c\n+++ /dev/null\n@@ -1,960 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/* net/atm/clip.c - RFC1577 Classical IP over ATM */\n-\n-/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */\n-\n-#define pr_fmt(fmt) KBUILD_MODNAME \":%s: \" fmt, __func__\n-\n-#include \n-#include \n-#include /* for UINT_MAX */\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include /* for some manifest constants */\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include /* for net/route.h */\n-#include /* for struct sockaddr_in */\n-#include /* for IFF_UP */\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include /* for struct rtable and routing */\n-#include /* icmp_send */\n-#include \n-#include /* for HZ */\n-#include \n-#include /* for htons etc. */\n-#include \n-\n-#include \"common.h\"\n-#include \"resources.h\"\n-#include \n-\n-static struct net_device *clip_devs;\n-static struct atm_vcc __rcu *atmarpd;\n-static DEFINE_MUTEX(atmarpd_lock);\n-static struct timer_list idle_timer;\n-static const struct neigh_ops clip_neigh_ops;\n-\n-static int to_atmarpd(enum atmarp_ctrl_type type, int itf, __be32 ip)\n-{\n-\tstruct sock *sk;\n-\tstruct atmarp_ctrl *ctrl;\n-\tstruct atm_vcc *vcc;\n-\tstruct sk_buff *skb;\n-\tint err = 0;\n-\n-\tpr_debug(\"(%d)\\n\", type);\n-\n-\trcu_read_lock();\n-\tvcc = rcu_dereference(atmarpd);\n-\tif (!vcc) {\n-\t\terr = -EUNATCH;\n-\t\tgoto unlock;\n-\t}\n-\tskb = alloc_skb(sizeof(struct atmarp_ctrl), GFP_ATOMIC);\n-\tif (!skb) {\n-\t\terr = -ENOMEM;\n-\t\tgoto unlock;\n-\t}\n-\tctrl = skb_put(skb, sizeof(struct atmarp_ctrl));\n-\tctrl->type = type;\n-\tctrl->itf_num = itf;\n-\tctrl->ip = ip;\n-\tatm_force_charge(vcc, skb->truesize);\n-\n-\tsk = sk_atm(vcc);\n-\tskb_queue_tail(&sk->sk_receive_queue, skb);\n-\tsk->sk_data_ready(sk);\n-unlock:\n-\trcu_read_unlock();\n-\treturn err;\n-}\n-\n-static void link_vcc(struct clip_vcc *clip_vcc, struct atmarp_entry *entry)\n-{\n-\tpr_debug(\"%p to entry %p (neigh %p)\\n\", clip_vcc, entry, entry->neigh);\n-\tclip_vcc->entry = entry;\n-\tclip_vcc->xoff = 0;\t/* @@@ may overrun buffer by one packet */\n-\tclip_vcc->next = entry->vccs;\n-\tentry->vccs = clip_vcc;\n-\tentry->neigh->used = jiffies;\n-}\n-\n-static void unlink_clip_vcc(struct clip_vcc *clip_vcc)\n-{\n-\tstruct atmarp_entry *entry = clip_vcc->entry;\n-\tstruct clip_vcc **walk;\n-\n-\tif (!entry) {\n-\t\tpr_err(\"!clip_vcc->entry (clip_vcc %p)\\n\", clip_vcc);\n-\t\treturn;\n-\t}\n-\tnetif_tx_lock_bh(entry->neigh->dev);\t/* block clip_start_xmit() */\n-\tentry->neigh->used = jiffies;\n-\tfor (walk = &entry->vccs; *walk; walk = &(*walk)->next)\n-\t\tif (*walk == clip_vcc) {\n-\t\t\tint error;\n-\n-\t\t\t*walk = clip_vcc->next;\t/* atomic */\n-\t\t\tclip_vcc->entry = NULL;\n-\t\t\tif (clip_vcc->xoff)\n-\t\t\t\tnetif_wake_queue(entry->neigh->dev);\n-\t\t\tif (entry->vccs)\n-\t\t\t\tgoto out;\n-\t\t\tentry->expires = jiffies - 1;\n-\t\t\t/* force resolution or expiration */\n-\t\t\terror = neigh_update(entry->neigh, NULL, NUD_NONE,\n-\t\t\t\t\t NEIGH_UPDATE_F_ADMIN, 0);\n-\t\t\tif (error)\n-\t\t\t\tpr_err(\"neigh_update failed with %d\\n\", error);\n-\t\t\tgoto out;\n-\t\t}\n-\tpr_err(\"ATMARP: failed (entry %p, vcc 0x%p)\\n\", entry, clip_vcc);\n-out:\n-\tnetif_tx_unlock_bh(entry->neigh->dev);\n-}\n-\n-/* The neighbour entry n->lock is held. */\n-static int neigh_check_cb(struct neighbour *n)\n-{\n-\tstruct atmarp_entry *entry = neighbour_priv(n);\n-\tstruct clip_vcc *cv;\n-\n-\tif (n->ops != &clip_neigh_ops)\n-\t\treturn 0;\n-\tfor (cv = entry->vccs; cv; cv = cv->next) {\n-\t\tunsigned long exp = cv->last_use + cv->idle_timeout;\n-\n-\t\tif (cv->idle_timeout && time_after(jiffies, exp)) {\n-\t\t\tpr_debug(\"releasing vcc %p->%p of entry %p\\n\",\n-\t\t\t\t cv, cv->vcc, entry);\n-\t\t\tvcc_release_async(cv->vcc, -ETIMEDOUT);\n-\t\t}\n-\t}\n-\n-\tif (entry->vccs || time_before(jiffies, entry->expires))\n-\t\treturn 0;\n-\n-\tif (refcount_read(&n->refcnt) > 1) {\n-\t\tstruct sk_buff *skb;\n-\n-\t\tpr_debug(\"destruction postponed with ref %d\\n\",\n-\t\t\t refcount_read(&n->refcnt));\n-\n-\t\twhile ((skb = skb_dequeue(&n->arp_queue)) != NULL)\n-\t\t\tdev_kfree_skb(skb);\n-\n-\t\treturn 0;\n-\t}\n-\n-\tpr_debug(\"expired neigh %p\\n\", n);\n-\treturn 1;\n-}\n-\n-static void idle_timer_check(struct timer_list *unused)\n-{\n-\tspin_lock(&arp_tbl.lock);\n-\t__neigh_for_each_release(&arp_tbl, neigh_check_cb);\n-\tmod_timer(&idle_timer, jiffies + CLIP_CHECK_INTERVAL * HZ);\n-\tspin_unlock(&arp_tbl.lock);\n-}\n-\n-static int clip_arp_rcv(struct sk_buff *skb)\n-{\n-\tstruct atm_vcc *vcc;\n-\n-\tpr_debug(\"\\n\");\n-\tvcc = ATM_SKB(skb)->vcc;\n-\tif (!vcc || !atm_charge(vcc, skb->truesize)) {\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn 0;\n-\t}\n-\tpr_debug(\"pushing to %p\\n\", vcc);\n-\tpr_debug(\"using %p\\n\", CLIP_VCC(vcc)->old_push);\n-\tCLIP_VCC(vcc)->old_push(vcc, skb);\n-\treturn 0;\n-}\n-\n-static const unsigned char llc_oui[] = {\n-\t0xaa,\t/* DSAP: non-ISO */\n-\t0xaa,\t/* SSAP: non-ISO */\n-\t0x03,\t/* Ctrl: Unnumbered Information Command PDU */\n-\t0x00,\t/* OUI: EtherType */\n-\t0x00,\n-\t0x00\n-};\n-\n-static void clip_push(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct clip_vcc *clip_vcc = CLIP_VCC(vcc);\n-\n-\tpr_debug(\"\\n\");\n-\n-\tif (!skb) {\n-\t\tpr_debug(\"removing VCC %p\\n\", clip_vcc);\n-\t\tif (clip_vcc->entry)\n-\t\t\tunlink_clip_vcc(clip_vcc);\n-\t\tclip_vcc->old_push(vcc, NULL);\t/* pass on the bad news */\n-\t\tkfree(clip_vcc);\n-\t\treturn;\n-\t}\n-\tatm_return(vcc, skb->truesize);\n-\tif (!clip_devs) {\n-\t\tkfree_skb(skb);\n-\t\treturn;\n-\t}\n-\n-\tskb->dev = clip_vcc->entry ? clip_vcc->entry->neigh->dev : clip_devs;\n-\t/* clip_vcc->entry == NULL if we don't have an IP address yet */\n-\tif (!skb->dev) {\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn;\n-\t}\n-\tATM_SKB(skb)->vcc = vcc;\n-\tskb_reset_mac_header(skb);\n-\tif (!clip_vcc->encap ||\n-\t skb->len < RFC1483LLC_LEN ||\n-\t memcmp(skb->data, llc_oui, sizeof(llc_oui)))\n-\t\tskb->protocol = htons(ETH_P_IP);\n-\telse {\n-\t\tskb->protocol = ((__be16 *)skb->data)[3];\n-\t\tskb_pull(skb, RFC1483LLC_LEN);\n-\t\tif (skb->protocol == htons(ETH_P_ARP)) {\n-\t\t\tskb->dev->stats.rx_packets++;\n-\t\t\tskb->dev->stats.rx_bytes += skb->len;\n-\t\t\tclip_arp_rcv(skb);\n-\t\t\treturn;\n-\t\t}\n-\t}\n-\tclip_vcc->last_use = jiffies;\n-\tskb->dev->stats.rx_packets++;\n-\tskb->dev->stats.rx_bytes += skb->len;\n-\tmemset(ATM_SKB(skb), 0, sizeof(struct atm_skb_data));\n-\tnetif_rx(skb);\n-}\n-\n-/*\n- * Note: these spinlocks _must_not_ block on non-SMP. The only goal is that\n- * clip_pop is atomic with respect to the critical section in clip_start_xmit.\n- */\n-\n-static void clip_pop(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct clip_vcc *clip_vcc = CLIP_VCC(vcc);\n-\tstruct net_device *dev = skb->dev;\n-\tint old;\n-\tunsigned long flags;\n-\n-\tpr_debug(\"(vcc %p)\\n\", vcc);\n-\tclip_vcc->old_pop(vcc, skb);\n-\t/* skb->dev == NULL in outbound ARP packets */\n-\tif (!dev)\n-\t\treturn;\n-\tspin_lock_irqsave(&PRIV(dev)->xoff_lock, flags);\n-\tif (atm_may_send(vcc, 0)) {\n-\t\told = xchg(&clip_vcc->xoff, 0);\n-\t\tif (old)\n-\t\t\tnetif_wake_queue(dev);\n-\t}\n-\tspin_unlock_irqrestore(&PRIV(dev)->xoff_lock, flags);\n-}\n-\n-static void clip_neigh_solicit(struct neighbour *neigh, struct sk_buff *skb)\n-{\n-\t__be32 *ip = (__be32 *) neigh->primary_key;\n-\n-\tpr_debug(\"(neigh %p, skb %p)\\n\", neigh, skb);\n-\tto_atmarpd(act_need, PRIV(neigh->dev)->number, *ip);\n-}\n-\n-static void clip_neigh_error(struct neighbour *neigh, struct sk_buff *skb)\n-{\n-#ifndef CONFIG_ATM_CLIP_NO_ICMP\n-\ticmp_send(skb, ICMP_DEST_UNREACH, ICMP_HOST_UNREACH, 0);\n-#endif\n-\tkfree_skb(skb);\n-}\n-\n-static const struct neigh_ops clip_neigh_ops = {\n-\t.family =\t\tAF_INET,\n-\t.solicit =\t\tclip_neigh_solicit,\n-\t.error_report =\t\tclip_neigh_error,\n-\t.output =\t\tneigh_direct_output,\n-\t.connected_output =\tneigh_direct_output,\n-};\n-\n-static int clip_constructor(struct net_device *dev, struct neighbour *neigh)\n-{\n-\tstruct atmarp_entry *entry = neighbour_priv(neigh);\n-\n-\tif (neigh->tbl->family != AF_INET)\n-\t\treturn -EINVAL;\n-\n-\tif (neigh->type != RTN_UNICAST)\n-\t\treturn -EINVAL;\n-\n-\tneigh->nud_state = NUD_NONE;\n-\tneigh->ops = &clip_neigh_ops;\n-\tneigh->output = neigh->ops->output;\n-\tentry->neigh = neigh;\n-\tentry->vccs = NULL;\n-\tentry->expires = jiffies - 1;\n-\n-\treturn 0;\n-}\n-\n-/* @@@ copy bh locking from arp.c -- need to bh-enable atm code before */\n-\n-/*\n- * We play with the resolve flag: 0 and 1 have the usual meaning, but -1 means\n- * to allocate the neighbour entry but not to ask atmarpd for resolution. Also,\n- * don't increment the usage count. This is used to create entries in\n- * clip_setentry.\n- */\n-\n-static int clip_encap(struct atm_vcc *vcc, int mode)\n-{\n-\tif (!CLIP_VCC(vcc))\n-\t\treturn -EBADFD;\n-\n-\tCLIP_VCC(vcc)->encap = mode;\n-\treturn 0;\n-}\n-\n-static netdev_tx_t clip_start_xmit(struct sk_buff *skb,\n-\t\t\t\t struct net_device *dev)\n-{\n-\tstruct clip_priv *clip_priv = PRIV(dev);\n-\tstruct dst_entry *dst = skb_dst(skb);\n-\tstruct atmarp_entry *entry;\n-\tstruct neighbour *n;\n-\tstruct atm_vcc *vcc;\n-\tstruct rtable *rt;\n-\t__be32 *daddr;\n-\tint old;\n-\tunsigned long flags;\n-\n-\tpr_debug(\"(skb %p)\\n\", skb);\n-\tif (!dst) {\n-\t\tpr_err(\"skb_dst(skb) == NULL\\n\");\n-\t\tdev_kfree_skb(skb);\n-\t\tdev->stats.tx_dropped++;\n-\t\treturn NETDEV_TX_OK;\n-\t}\n-\trt = dst_rtable(dst);\n-\tif (rt->rt_gw_family == AF_INET)\n-\t\tdaddr = &rt->rt_gw4;\n-\telse\n-\t\tdaddr = &ip_hdr(skb)->daddr;\n-\tn = dst_neigh_lookup(dst, daddr);\n-\tif (!n) {\n-\t\tpr_err(\"NO NEIGHBOUR !\\n\");\n-\t\tdev_kfree_skb(skb);\n-\t\tdev->stats.tx_dropped++;\n-\t\treturn NETDEV_TX_OK;\n-\t}\n-\tentry = neighbour_priv(n);\n-\tif (!entry->vccs) {\n-\t\tif (time_after(jiffies, entry->expires)) {\n-\t\t\t/* should be resolved */\n-\t\t\tentry->expires = jiffies + ATMARP_RETRY_DELAY * HZ;\n-\t\t\tto_atmarpd(act_need, PRIV(dev)->number, *((__be32 *)n->primary_key));\n-\t\t}\n-\t\tif (entry->neigh->arp_queue.qlen < ATMARP_MAX_UNRES_PACKETS)\n-\t\t\tskb_queue_tail(&entry->neigh->arp_queue, skb);\n-\t\telse {\n-\t\t\tdev_kfree_skb(skb);\n-\t\t\tdev->stats.tx_dropped++;\n-\t\t}\n-\t\tgoto out_release_neigh;\n-\t}\n-\tpr_debug(\"neigh %p, vccs %p\\n\", entry, entry->vccs);\n-\tATM_SKB(skb)->vcc = vcc = entry->vccs->vcc;\n-\tpr_debug(\"using neighbour %p, vcc %p\\n\", n, vcc);\n-\tif (entry->vccs->encap) {\n-\t\tvoid *here;\n-\n-\t\there = skb_push(skb, RFC1483LLC_LEN);\n-\t\tmemcpy(here, llc_oui, sizeof(llc_oui));\n-\t\t((__be16 *) here)[3] = skb->protocol;\n-\t}\n-\tatm_account_tx(vcc, skb);\n-\tentry->vccs->last_use = jiffies;\n-\tpr_debug(\"atm_skb(%p)->vcc(%p)->dev(%p)\\n\", skb, vcc, vcc->dev);\n-\told = xchg(&entry->vccs->xoff, 1);\t/* assume XOFF ... */\n-\tif (old) {\n-\t\tpr_warn(\"XOFF->XOFF transition\\n\");\n-\t\tgoto out_release_neigh;\n-\t}\n-\tdev->stats.tx_packets++;\n-\tdev->stats.tx_bytes += skb->len;\n-\tvcc->send(vcc, skb);\n-\tif (atm_may_send(vcc, 0)) {\n-\t\tentry->vccs->xoff = 0;\n-\t\tgoto out_release_neigh;\n-\t}\n-\tspin_lock_irqsave(&clip_priv->xoff_lock, flags);\n-\tnetif_stop_queue(dev);\t/* XOFF -> throttle immediately */\n-\tbarrier();\n-\tif (!entry->vccs->xoff)\n-\t\tnetif_start_queue(dev);\n-\t/* Oh, we just raced with clip_pop. netif_start_queue should be\n-\t good enough, because nothing should really be asleep because\n-\t of the brief netif_stop_queue. If this isn't true or if it\n-\t changes, use netif_wake_queue instead. */\n-\tspin_unlock_irqrestore(&clip_priv->xoff_lock, flags);\n-out_release_neigh:\n-\tneigh_release(n);\n-\treturn NETDEV_TX_OK;\n-}\n-\n-static int clip_mkip(struct atm_vcc *vcc, int timeout)\n-{\n-\tstruct clip_vcc *clip_vcc;\n-\n-\tif (!vcc->push)\n-\t\treturn -EBADFD;\n-\tif (vcc->user_back)\n-\t\treturn -EINVAL;\n-\tclip_vcc = kmalloc_obj(struct clip_vcc);\n-\tif (!clip_vcc)\n-\t\treturn -ENOMEM;\n-\tpr_debug(\"%p vcc %p\\n\", clip_vcc, vcc);\n-\tclip_vcc->vcc = vcc;\n-\tvcc->user_back = clip_vcc;\n-\tset_bit(ATM_VF_IS_CLIP, &vcc->flags);\n-\tclip_vcc->entry = NULL;\n-\tclip_vcc->xoff = 0;\n-\tclip_vcc->encap = 1;\n-\tclip_vcc->last_use = jiffies;\n-\tclip_vcc->idle_timeout = timeout * HZ;\n-\tclip_vcc->old_push = vcc->push;\n-\tclip_vcc->old_pop = vcc->pop;\n-\tvcc->push = clip_push;\n-\tvcc->pop = clip_pop;\n-\n-\t/* re-process everything received between connection setup and MKIP */\n-\tvcc_process_recv_queue(vcc);\n-\n-\treturn 0;\n-}\n-\n-static int clip_setentry(struct atm_vcc *vcc, __be32 ip)\n-{\n-\tstruct neighbour *neigh;\n-\tstruct atmarp_entry *entry;\n-\tint error;\n-\tstruct clip_vcc *clip_vcc;\n-\tstruct rtable *rt;\n-\n-\tif (vcc->push != clip_push) {\n-\t\tpr_warn(\"non-CLIP VCC\\n\");\n-\t\treturn -EBADF;\n-\t}\n-\tclip_vcc = CLIP_VCC(vcc);\n-\tif (!ip) {\n-\t\tif (!clip_vcc->entry) {\n-\t\t\tpr_err(\"hiding hidden ATMARP entry\\n\");\n-\t\t\treturn 0;\n-\t\t}\n-\t\tpr_debug(\"remove\\n\");\n-\t\tunlink_clip_vcc(clip_vcc);\n-\t\treturn 0;\n-\t}\n-\trt = ip_route_output(&init_net, ip, 0, 0, 0, RT_SCOPE_LINK);\n-\tif (IS_ERR(rt))\n-\t\treturn PTR_ERR(rt);\n-\tneigh = __neigh_lookup(&arp_tbl, &ip, rt->dst.dev, 1);\n-\tip_rt_put(rt);\n-\tif (!neigh)\n-\t\treturn -ENOMEM;\n-\tentry = neighbour_priv(neigh);\n-\tif (entry != clip_vcc->entry) {\n-\t\tif (!clip_vcc->entry)\n-\t\t\tpr_debug(\"add\\n\");\n-\t\telse {\n-\t\t\tpr_debug(\"update\\n\");\n-\t\t\tunlink_clip_vcc(clip_vcc);\n-\t\t}\n-\t\tlink_vcc(clip_vcc, entry);\n-\t}\n-\terror = neigh_update(neigh, llc_oui, NUD_PERMANENT,\n-\t\t\t NEIGH_UPDATE_F_OVERRIDE | NEIGH_UPDATE_F_ADMIN, 0);\n-\tneigh_release(neigh);\n-\treturn error;\n-}\n-\n-static const struct net_device_ops clip_netdev_ops = {\n-\t.ndo_start_xmit\t\t= clip_start_xmit,\n-\t.ndo_neigh_construct\t= clip_constructor,\n-};\n-\n-static void clip_setup(struct net_device *dev)\n-{\n-\tdev->netdev_ops = &clip_netdev_ops;\n-\tdev->type = ARPHRD_ATM;\n-\tdev->neigh_priv_len = sizeof(struct atmarp_entry);\n-\tdev->hard_header_len = RFC1483LLC_LEN;\n-\tdev->mtu = RFC1626_MTU;\n-\tdev->tx_queue_len = 100;\t/* \"normal\" queue (packets) */\n-\t/* When using a \"real\" qdisc, the qdisc determines the queue */\n-\t/* length. tx_queue_len is only used for the default case, */\n-\t/* without any more elaborate queuing. 100 is a reasonable */\n-\t/* compromise between decent burst-tolerance and protection */\n-\t/* against memory hogs. */\n-\tnetif_keep_dst(dev);\n-}\n-\n-static int clip_create(int number)\n-{\n-\tstruct net_device *dev;\n-\tstruct clip_priv *clip_priv;\n-\tint error;\n-\n-\tif (number != -1) {\n-\t\tfor (dev = clip_devs; dev; dev = PRIV(dev)->next)\n-\t\t\tif (PRIV(dev)->number == number)\n-\t\t\t\treturn -EEXIST;\n-\t} else {\n-\t\tnumber = 0;\n-\t\tfor (dev = clip_devs; dev; dev = PRIV(dev)->next)\n-\t\t\tif (PRIV(dev)->number >= number)\n-\t\t\t\tnumber = PRIV(dev)->number + 1;\n-\t}\n-\tdev = alloc_netdev(sizeof(struct clip_priv), \"\", NET_NAME_UNKNOWN,\n-\t\t\t clip_setup);\n-\tif (!dev)\n-\t\treturn -ENOMEM;\n-\tclip_priv = PRIV(dev);\n-\tsprintf(dev->name, \"atm%d\", number);\n-\tspin_lock_init(&clip_priv->xoff_lock);\n-\tclip_priv->number = number;\n-\terror = register_netdev(dev);\n-\tif (error) {\n-\t\tfree_netdev(dev);\n-\t\treturn error;\n-\t}\n-\tclip_priv->next = clip_devs;\n-\tclip_devs = dev;\n-\tpr_debug(\"registered (net:%s)\\n\", dev->name);\n-\treturn number;\n-}\n-\n-static int clip_device_event(struct notifier_block *this, unsigned long event,\n-\t\t\t void *ptr)\n-{\n-\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n-\n-\tif (!net_eq(dev_net(dev), &init_net))\n-\t\treturn NOTIFY_DONE;\n-\n-\tif (event == NETDEV_UNREGISTER)\n-\t\treturn NOTIFY_DONE;\n-\n-\t/* ignore non-CLIP devices */\n-\tif (dev->type != ARPHRD_ATM || dev->netdev_ops != &clip_netdev_ops)\n-\t\treturn NOTIFY_DONE;\n-\n-\tswitch (event) {\n-\tcase NETDEV_UP:\n-\t\tpr_debug(\"NETDEV_UP\\n\");\n-\t\tto_atmarpd(act_up, PRIV(dev)->number, 0);\n-\t\tbreak;\n-\tcase NETDEV_GOING_DOWN:\n-\t\tpr_debug(\"NETDEV_DOWN\\n\");\n-\t\tto_atmarpd(act_down, PRIV(dev)->number, 0);\n-\t\tbreak;\n-\tcase NETDEV_CHANGE:\n-\tcase NETDEV_CHANGEMTU:\n-\t\tpr_debug(\"NETDEV_CHANGE*\\n\");\n-\t\tto_atmarpd(act_change, PRIV(dev)->number, 0);\n-\t\tbreak;\n-\t}\n-\treturn NOTIFY_DONE;\n-}\n-\n-static int clip_inet_event(struct notifier_block *this, unsigned long event,\n-\t\t\t void *ifa)\n-{\n-\tstruct in_device *in_dev;\n-\tstruct netdev_notifier_info info;\n-\n-\tin_dev = ((struct in_ifaddr *)ifa)->ifa_dev;\n-\t/*\n-\t * Transitions are of the down-change-up type, so it's sufficient to\n-\t * handle the change on up.\n-\t */\n-\tif (event != NETDEV_UP)\n-\t\treturn NOTIFY_DONE;\n-\tnetdev_notifier_info_init(&info, in_dev->dev);\n-\treturn clip_device_event(this, NETDEV_CHANGE, &info);\n-}\n-\n-static struct notifier_block clip_dev_notifier = {\n-\t.notifier_call = clip_device_event,\n-};\n-\n-\n-\n-static struct notifier_block clip_inet_notifier = {\n-\t.notifier_call = clip_inet_event,\n-};\n-\n-\n-\n-static void atmarpd_close(struct atm_vcc *vcc)\n-{\n-\tpr_debug(\"\\n\");\n-\n-\tmutex_lock(&atmarpd_lock);\n-\tRCU_INIT_POINTER(atmarpd, NULL);\n-\tmutex_unlock(&atmarpd_lock);\n-\n-\tsynchronize_rcu();\n-\tskb_queue_purge(&sk_atm(vcc)->sk_receive_queue);\n-\n-\tpr_debug(\"(done)\\n\");\n-\tmodule_put(THIS_MODULE);\n-}\n-\n-static int atmarpd_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tatm_return_tx(vcc, skb);\n-\tdev_kfree_skb_any(skb);\n-\treturn 0;\n-}\n-\n-static const struct atmdev_ops atmarpd_dev_ops = {\n-\t.close = atmarpd_close,\n-\t.send = atmarpd_send\n-};\n-\n-\n-static struct atm_dev atmarpd_dev = {\n-\t.ops =\t\t\t&atmarpd_dev_ops,\n-\t.type =\t\t\t\"arpd\",\n-\t.number = \t\t999,\n-\t.lock =\t\t\t__SPIN_LOCK_UNLOCKED(atmarpd_dev.lock)\n-};\n-\n-\n-static int atm_init_atmarp(struct atm_vcc *vcc)\n-{\n-\tif (vcc->push == clip_push)\n-\t\treturn -EINVAL;\n-\n-\tmutex_lock(&atmarpd_lock);\n-\tif (atmarpd) {\n-\t\tmutex_unlock(&atmarpd_lock);\n-\t\treturn -EADDRINUSE;\n-\t}\n-\n-\tmod_timer(&idle_timer, jiffies + CLIP_CHECK_INTERVAL * HZ);\n-\n-\trcu_assign_pointer(atmarpd, vcc);\n-\tset_bit(ATM_VF_META, &vcc->flags);\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\t /* allow replies and avoid getting closed if signaling dies */\n-\tvcc->dev = &atmarpd_dev;\n-\tvcc_insert_socket(sk_atm(vcc));\n-\tvcc->push = NULL;\n-\tvcc->pop = NULL; /* crash */\n-\tvcc->push_oam = NULL; /* crash */\n-\tmutex_unlock(&atmarpd_lock);\n-\treturn 0;\n-}\n-\n-static int clip_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)\n-{\n-\tstruct atm_vcc *vcc = ATM_SD(sock);\n-\tstruct sock *sk = sock->sk;\n-\tint err = 0;\n-\n-\tswitch (cmd) {\n-\tcase SIOCMKCLIP:\n-\tcase ATMARPD_CTRL:\n-\tcase ATMARP_MKIP:\n-\tcase ATMARP_SETENTRY:\n-\tcase ATMARP_ENCAP:\n-\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\treturn -EPERM;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -ENOIOCTLCMD;\n-\t}\n-\n-\tswitch (cmd) {\n-\tcase SIOCMKCLIP:\n-\t\terr = clip_create(arg);\n-\t\tbreak;\n-\tcase ATMARPD_CTRL:\n-\t\tlock_sock(sk);\n-\t\terr = atm_init_atmarp(vcc);\n-\t\tif (!err) {\n-\t\t\tsock->state = SS_CONNECTED;\n-\t\t\t__module_get(THIS_MODULE);\n-\t\t}\n-\t\trelease_sock(sk);\n-\t\tbreak;\n-\tcase ATMARP_MKIP:\n-\t\tlock_sock(sk);\n-\t\terr = clip_mkip(vcc, arg);\n-\t\trelease_sock(sk);\n-\t\tbreak;\n-\tcase ATMARP_SETENTRY:\n-\t\terr = clip_setentry(vcc, (__force __be32)arg);\n-\t\tbreak;\n-\tcase ATMARP_ENCAP:\n-\t\terr = clip_encap(vcc, arg);\n-\t\tbreak;\n-\t}\n-\treturn err;\n-}\n-\n-static struct atm_ioctl clip_ioctl_ops = {\n-\t.owner = THIS_MODULE,\n-\t.ioctl = clip_ioctl,\n-};\n-\n-#ifdef CONFIG_PROC_FS\n-\n-static void svc_addr(struct seq_file *seq, struct sockaddr_atmsvc *addr)\n-{\n-\tstatic int code[] = { 1, 2, 10, 6, 1, 0 };\n-\tstatic int e164[] = { 1, 8, 4, 6, 1, 0 };\n-\n-\tif (*addr->sas_addr.pub) {\n-\t\tseq_printf(seq, \"%s\", addr->sas_addr.pub);\n-\t\tif (*addr->sas_addr.prv)\n-\t\t\tseq_putc(seq, '+');\n-\t} else if (!*addr->sas_addr.prv) {\n-\t\tseq_printf(seq, \"%s\", \"(none)\");\n-\t\treturn;\n-\t}\n-\tif (*addr->sas_addr.prv) {\n-\t\tunsigned char *prv = addr->sas_addr.prv;\n-\t\tint *fields;\n-\t\tint i, j;\n-\n-\t\tfields = *prv == ATM_AFI_E164 ? e164 : code;\n-\t\tfor (i = 0; fields[i]; i++) {\n-\t\t\tfor (j = fields[i]; j; j--)\n-\t\t\t\tseq_printf(seq, \"%02X\", *prv++);\n-\t\t\tif (fields[i + 1])\n-\t\t\t\tseq_putc(seq, '.');\n-\t\t}\n-\t}\n-}\n-\n-/* This means the neighbour entry has no attached VCC objects. */\n-#define SEQ_NO_VCC_TOKEN\t((void *) 2)\n-\n-static void atmarp_info(struct seq_file *seq, struct neighbour *n,\n-\t\t\tstruct atmarp_entry *entry, struct clip_vcc *clip_vcc)\n-{\n-\tstruct net_device *dev = n->dev;\n-\tunsigned long exp;\n-\tchar buf[17];\n-\tint svc, llc, off;\n-\n-\tsvc = ((clip_vcc == SEQ_NO_VCC_TOKEN) ||\n-\t (sk_atm(clip_vcc->vcc)->sk_family == AF_ATMSVC));\n-\n-\tllc = ((clip_vcc == SEQ_NO_VCC_TOKEN) || clip_vcc->encap);\n-\n-\tif (clip_vcc == SEQ_NO_VCC_TOKEN)\n-\t\texp = entry->neigh->used;\n-\telse\n-\t\texp = clip_vcc->last_use;\n-\n-\texp = (jiffies - exp) / HZ;\n-\n-\tseq_printf(seq, \"%-6s%-4s%-4s%5ld \",\n-\t\t dev->name, svc ? \"SVC\" : \"PVC\", llc ? \"LLC\" : \"NULL\", exp);\n-\n-\toff = scnprintf(buf, sizeof(buf) - 1, \"%pI4\", n->primary_key);\n-\twhile (off < 16)\n-\t\tbuf[off++] = ' ';\n-\tbuf[off] = '\\0';\n-\tseq_printf(seq, \"%s\", buf);\n-\n-\tif (clip_vcc == SEQ_NO_VCC_TOKEN) {\n-\t\tif (time_before(jiffies, entry->expires))\n-\t\t\tseq_printf(seq, \"(resolving)\\n\");\n-\t\telse\n-\t\t\tseq_printf(seq, \"(expired, ref %d)\\n\",\n-\t\t\t\t refcount_read(&entry->neigh->refcnt));\n-\t} else if (!svc) {\n-\t\tseq_printf(seq, \"%d.%d.%d\\n\",\n-\t\t\t clip_vcc->vcc->dev->number,\n-\t\t\t clip_vcc->vcc->vpi, clip_vcc->vcc->vci);\n-\t} else {\n-\t\tsvc_addr(seq, &clip_vcc->vcc->remote);\n-\t\tseq_putc(seq, '\\n');\n-\t}\n-}\n-\n-struct clip_seq_state {\n-\t/* This member must be first. */\n-\tstruct neigh_seq_state ns;\n-\n-\t/* Local to clip specific iteration. */\n-\tstruct clip_vcc *vcc;\n-};\n-\n-static struct clip_vcc *clip_seq_next_vcc(struct atmarp_entry *e,\n-\t\t\t\t\t struct clip_vcc *curr)\n-{\n-\tif (!curr) {\n-\t\tcurr = e->vccs;\n-\t\tif (!curr)\n-\t\t\treturn SEQ_NO_VCC_TOKEN;\n-\t\treturn curr;\n-\t}\n-\tif (curr == SEQ_NO_VCC_TOKEN)\n-\t\treturn NULL;\n-\n-\tcurr = curr->next;\n-\n-\treturn curr;\n-}\n-\n-static void *clip_seq_vcc_walk(struct clip_seq_state *state,\n-\t\t\t struct atmarp_entry *e, loff_t * pos)\n-{\n-\tstruct clip_vcc *vcc = state->vcc;\n-\n-\tvcc = clip_seq_next_vcc(e, vcc);\n-\tif (vcc && pos != NULL) {\n-\t\twhile (*pos) {\n-\t\t\tvcc = clip_seq_next_vcc(e, vcc);\n-\t\t\tif (!vcc)\n-\t\t\t\tbreak;\n-\t\t\t--(*pos);\n-\t\t}\n-\t}\n-\tstate->vcc = vcc;\n-\n-\treturn vcc;\n-}\n-\n-static void *clip_seq_sub_iter(struct neigh_seq_state *_state,\n-\t\t\t struct neighbour *n, loff_t * pos)\n-{\n-\tstruct clip_seq_state *state = (struct clip_seq_state *)_state;\n-\n-\tif (n->dev->type != ARPHRD_ATM)\n-\t\treturn NULL;\n-\n-\treturn clip_seq_vcc_walk(state, neighbour_priv(n), pos);\n-}\n-\n-static void *clip_seq_start(struct seq_file *seq, loff_t * pos)\n-{\n-\tstruct clip_seq_state *state = seq->private;\n-\tstate->ns.neigh_sub_iter = clip_seq_sub_iter;\n-\treturn neigh_seq_start(seq, pos, &arp_tbl, NEIGH_SEQ_NEIGH_ONLY);\n-}\n-\n-static int clip_seq_show(struct seq_file *seq, void *v)\n-{\n-\tstatic char atm_arp_banner[] =\n-\t \"IPitf TypeEncp Idle IP address ATM address\\n\";\n-\n-\tif (v == SEQ_START_TOKEN) {\n-\t\tseq_puts(seq, atm_arp_banner);\n-\t} else {\n-\t\tstruct clip_seq_state *state = seq->private;\n-\t\tstruct clip_vcc *vcc = state->vcc;\n-\t\tstruct neighbour *n = v;\n-\n-\t\tatmarp_info(seq, n, neighbour_priv(n), vcc);\n-\t}\n-\treturn 0;\n-}\n-\n-static const struct seq_operations arp_seq_ops = {\n-\t.start\t= clip_seq_start,\n-\t.next\t= neigh_seq_next,\n-\t.stop\t= neigh_seq_stop,\n-\t.show\t= clip_seq_show,\n-};\n-#endif\n-\n-static void atm_clip_exit_noproc(void);\n-\n-static int __init atm_clip_init(void)\n-{\n-\tregister_atm_ioctl(&clip_ioctl_ops);\n-\tregister_netdevice_notifier(&clip_dev_notifier);\n-\tregister_inetaddr_notifier(&clip_inet_notifier);\n-\n-\ttimer_setup(&idle_timer, idle_timer_check, 0);\n-\n-#ifdef CONFIG_PROC_FS\n-\t{\n-\t\tstruct proc_dir_entry *p;\n-\n-\t\tp = proc_create_net(\"arp\", 0444, atm_proc_root, &arp_seq_ops,\n-\t\t\t\tsizeof(struct clip_seq_state));\n-\t\tif (!p) {\n-\t\t\tpr_err(\"Unable to initialize /proc/net/atm/arp\\n\");\n-\t\t\tatm_clip_exit_noproc();\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-#endif\n-\n-\treturn 0;\n-}\n-\n-static void atm_clip_exit_noproc(void)\n-{\n-\tstruct net_device *dev, *next;\n-\n-\tunregister_inetaddr_notifier(&clip_inet_notifier);\n-\tunregister_netdevice_notifier(&clip_dev_notifier);\n-\n-\tderegister_atm_ioctl(&clip_ioctl_ops);\n-\n-\t/* First, stop the idle timer, so it stops banging\n-\t * on the table.\n-\t */\n-\ttimer_delete_sync(&idle_timer);\n-\n-\tdev = clip_devs;\n-\twhile (dev) {\n-\t\tnext = PRIV(dev)->next;\n-\t\tunregister_netdev(dev);\n-\t\tfree_netdev(dev);\n-\t\tdev = next;\n-\t}\n-}\n-\n-static void __exit atm_clip_exit(void)\n-{\n-\tremove_proc_entry(\"arp\", atm_proc_root);\n-\n-\tatm_clip_exit_noproc();\n-}\n-\n-module_init(atm_clip_init);\n-module_exit(atm_clip_exit);\n-MODULE_AUTHOR(\"Werner Almesberger\");\n-MODULE_DESCRIPTION(\"Classical/IP over ATM interface\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/net/atm/lec.c b/net/atm/lec.c\ndeleted file mode 100644\nindex 10e260acf602..000000000000\n--- a/net/atm/lec.c\n+++ /dev/null\n@@ -1,2274 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * lec.c: Lan Emulation driver\n- *\n- * Marko Kiiskila \n- */\n-\n-#define pr_fmt(fmt) KBUILD_MODNAME \":%s: \" fmt, __func__\n-\n-#include \n-#include \n-#include \n-#include \n-\n-/* We are ethernet device */\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-/* And atm device */\n-#include \n-#include \n-\n-/* Proxy LEC knows about bridging */\n-#if IS_ENABLED(CONFIG_BRIDGE)\n-#include \"../bridge/br_private.h\"\n-\n-static unsigned char bridge_ula_lec[] = { 0x01, 0x80, 0xc2, 0x00, 0x00 };\n-#endif\n-\n-/* Modular too */\n-#include \n-#include \n-\n-/* Hardening for Spectre-v1 */\n-#include \n-\n-#include \"lec.h\"\n-#include \"lec_arpc.h\"\n-#include \"resources.h\"\n-\n-#define DUMP_PACKETS 0\t\t/*\n-\t\t\t\t * 0 = None,\n-\t\t\t\t * 1 = 30 first bytes\n-\t\t\t\t * 2 = Whole packet\n-\t\t\t\t */\n-\n-#define LEC_UNRES_QUE_LEN 8\t/*\n-\t\t\t\t * number of tx packets to queue for a\n-\t\t\t\t * single destination while waiting for SVC\n-\t\t\t\t */\n-\n-static int lec_open(struct net_device *dev);\n-static netdev_tx_t lec_start_xmit(struct sk_buff *skb,\n-\t\t\t\t struct net_device *dev);\n-static int lec_close(struct net_device *dev);\n-static struct lec_arp_table *lec_arp_find(struct lec_priv *priv,\n-\t\t\t\t\t const unsigned char *mac_addr);\n-static int lec_arp_remove(struct lec_priv *priv,\n-\t\t\t struct lec_arp_table *to_remove);\n-/* LANE2 functions */\n-static void lane2_associate_ind(struct net_device *dev, const u8 *mac_address,\n-\t\t\t\tconst u8 *tlvs, u32 sizeoftlvs);\n-static int lane2_resolve(struct net_device *dev, const u8 *dst_mac, int force,\n-\t\t\t u8 **tlvs, u32 *sizeoftlvs);\n-static int lane2_associate_req(struct net_device *dev, const u8 *lan_dst,\n-\t\t\t const u8 *tlvs, u32 sizeoftlvs);\n-\n-static int lec_addr_delete(struct lec_priv *priv, const unsigned char *atm_addr,\n-\t\t\t unsigned long permanent);\n-static void lec_arp_check_empties(struct lec_priv *priv,\n-\t\t\t\t struct atm_vcc *vcc, struct sk_buff *skb);\n-static void lec_arp_destroy(struct lec_priv *priv);\n-static void lec_arp_init(struct lec_priv *priv);\n-static struct atm_vcc *lec_arp_resolve(struct lec_priv *priv,\n-\t\t\t\t const unsigned char *mac_to_find,\n-\t\t\t\t int is_rdesc,\n-\t\t\t\t struct lec_arp_table **ret_entry);\n-static void lec_arp_update(struct lec_priv *priv, const unsigned char *mac_addr,\n-\t\t\t const unsigned char *atm_addr,\n-\t\t\t unsigned long remoteflag,\n-\t\t\t unsigned int targetless_le_arp);\n-static void lec_flush_complete(struct lec_priv *priv, unsigned long tran_id);\n-static int lec_mcast_make(struct lec_priv *priv, struct atm_vcc *vcc);\n-static void lec_set_flush_tran_id(struct lec_priv *priv,\n-\t\t\t\t const unsigned char *atm_addr,\n-\t\t\t\t unsigned long tran_id);\n-static void lec_vcc_added(struct lec_priv *priv,\n-\t\t\t const struct atmlec_ioc *ioc_data,\n-\t\t\t struct atm_vcc *vcc,\n-\t\t\t void (*old_push)(struct atm_vcc *vcc,\n-\t\t\t\t\t struct sk_buff *skb));\n-static void lec_vcc_close(struct lec_priv *priv, struct atm_vcc *vcc);\n-\n-/* must be done under lec_arp_lock */\n-static inline void lec_arp_hold(struct lec_arp_table *entry)\n-{\n-\trefcount_inc(&entry->usage);\n-}\n-\n-static inline void lec_arp_put(struct lec_arp_table *entry)\n-{\n-\tif (refcount_dec_and_test(&entry->usage))\n-\t\tkfree(entry);\n-}\n-\n-static struct lane2_ops lane2_ops = {\n-\t.resolve = lane2_resolve,\t\t/* spec 3.1.3 */\n-\t.associate_req = lane2_associate_req,\t/* spec 3.1.4 */\n-\t.associate_indicator = NULL /* spec 3.1.5 */\n-};\n-\n-static unsigned char bus_mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };\n-\n-/* Device structures */\n-static struct net_device *dev_lec[MAX_LEC_ITF];\n-static DEFINE_MUTEX(lec_mutex);\n-\n-#if IS_ENABLED(CONFIG_BRIDGE)\n-static void lec_handle_bridge(struct sk_buff *skb, struct net_device *dev)\n-{\n-\tchar *buff;\n-\tstruct lec_priv *priv;\n-\n-\t/*\n-\t * Check if this is a BPDU. If so, ask zeppelin to send\n-\t * LE_TOPOLOGY_REQUEST with the same value of Topology Change bit\n-\t * as the Config BPDU has\n-\t */\n-\tbuff = skb->data + skb->dev->hard_header_len;\n-\tif (*buff++ == 0x42 && *buff++ == 0x42 && *buff++ == 0x03) {\n-\t\tstruct sock *sk;\n-\t\tstruct sk_buff *skb2;\n-\t\tstruct atmlec_msg *mesg;\n-\n-\t\tskb2 = alloc_skb(sizeof(struct atmlec_msg), GFP_ATOMIC);\n-\t\tif (skb2 == NULL)\n-\t\t\treturn;\n-\t\tskb2->len = sizeof(struct atmlec_msg);\n-\t\tmesg = (struct atmlec_msg *)skb2->data;\n-\t\tmesg->type = l_topology_change;\n-\t\tbuff += 4;\n-\t\tmesg->content.normal.flag = *buff & 0x01;\n-\t\t\t\t\t/* 0x01 is topology change */\n-\n-\t\tpriv = netdev_priv(dev);\n-\t\tstruct atm_vcc *vcc;\n-\n-\t\trcu_read_lock();\n-\t\tvcc = rcu_dereference(priv->lecd);\n-\t\tif (vcc) {\n-\t\t\tatm_force_charge(vcc, skb2->truesize);\n-\t\t\tsk = sk_atm(vcc);\n-\t\t\tskb_queue_tail(&sk->sk_receive_queue, skb2);\n-\t\t\tsk->sk_data_ready(sk);\n-\t\t} else {\n-\t\t\tdev_kfree_skb(skb2);\n-\t\t}\n-\t\trcu_read_unlock();\n-\t}\n-}\n-#endif /* IS_ENABLED(CONFIG_BRIDGE) */\n-\n-/*\n- * Open/initialize the netdevice. This is called (in the current kernel)\n- * sometime after booting when the 'ifconfig' program is run.\n- *\n- * This routine should set everything up anew at each open, even\n- * registers that \"should\" only need to be set once at boot, so that\n- * there is non-reboot way to recover if something goes wrong.\n- */\n-\n-static int lec_open(struct net_device *dev)\n-{\n-\tnetif_start_queue(dev);\n-\n-\treturn 0;\n-}\n-\n-static void\n-lec_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct net_device *dev = skb->dev;\n-\tunsigned int len = skb->len;\n-\n-\tATM_SKB(skb)->vcc = vcc;\n-\tatm_account_tx(vcc, skb);\n-\n-\tif (vcc->send(vcc, skb) < 0) {\n-\t\tdev->stats.tx_dropped++;\n-\t\treturn;\n-\t}\n-\n-\tdev->stats.tx_packets++;\n-\tdev->stats.tx_bytes += len;\n-}\n-\n-static void lec_tx_timeout(struct net_device *dev, unsigned int txqueue)\n-{\n-\tpr_info(\"%s\\n\", dev->name);\n-\tnetif_trans_update(dev);\n-\tnetif_wake_queue(dev);\n-}\n-\n-static netdev_tx_t lec_start_xmit(struct sk_buff *skb,\n-\t\t\t\t struct net_device *dev)\n-{\n-\tstruct sk_buff *skb2;\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-\tstruct lecdatahdr_8023 *lec_h;\n-\tstruct atm_vcc *vcc;\n-\tstruct lec_arp_table *entry;\n-\tunsigned char *dst;\n-\tint min_frame_size;\n-\tint is_rdesc;\n-\n-\tpr_debug(\"called\\n\");\n-\tif (!rcu_access_pointer(priv->lecd)) {\n-\t\tpr_info(\"%s:No lecd attached\\n\", dev->name);\n-\t\tdev->stats.tx_errors++;\n-\t\tnetif_stop_queue(dev);\n-\t\tkfree_skb(skb);\n-\t\treturn NETDEV_TX_OK;\n-\t}\n-\n-\tpr_debug(\"skbuff head:%lx data:%lx tail:%lx end:%lx\\n\",\n-\t\t (long)skb->head, (long)skb->data, (long)skb_tail_pointer(skb),\n-\t\t (long)skb_end_pointer(skb));\n-#if IS_ENABLED(CONFIG_BRIDGE)\n-\tif (memcmp(skb->data, bridge_ula_lec, sizeof(bridge_ula_lec)) == 0)\n-\t\tlec_handle_bridge(skb, dev);\n-#endif\n-\n-\t/* Make sure we have room for lec_id */\n-\tif (skb_headroom(skb) < 2) {\n-\t\tpr_debug(\"reallocating skb\\n\");\n-\t\tskb2 = skb_realloc_headroom(skb, LEC_HEADER_LEN);\n-\t\tif (unlikely(!skb2)) {\n-\t\t\tkfree_skb(skb);\n-\t\t\treturn NETDEV_TX_OK;\n-\t\t}\n-\t\tconsume_skb(skb);\n-\t\tskb = skb2;\n-\t}\n-\tskb_push(skb, 2);\n-\n-\t/* Put le header to place */\n-\tlec_h = (struct lecdatahdr_8023 *)skb->data;\n-\tlec_h->le_header = htons(priv->lecid);\n-\n-#if DUMP_PACKETS >= 2\n-#define MAX_DUMP_SKB 99\n-#elif DUMP_PACKETS >= 1\n-#define MAX_DUMP_SKB 30\n-#endif\n-#if DUMP_PACKETS >= 1\n-\tprintk(KERN_DEBUG \"%s: send datalen:%ld lecid:%4.4x\\n\",\n-\t dev->name, skb->len, priv->lecid);\n-\tprint_hex_dump(KERN_DEBUG, \"\", DUMP_OFFSET, 16, 1,\n-\t\t skb->data, min(skb->len, MAX_DUMP_SKB), true);\n-#endif /* DUMP_PACKETS >= 1 */\n-\n-\t/* Minimum ethernet-frame size */\n-\tmin_frame_size = LEC_MINIMUM_8023_SIZE;\n-\tif (skb->len < min_frame_size) {\n-\t\tif ((skb->len + skb_tailroom(skb)) < min_frame_size) {\n-\t\t\tskb2 = skb_copy_expand(skb, 0,\n-\t\t\t\t\t min_frame_size - skb->truesize,\n-\t\t\t\t\t GFP_ATOMIC);\n-\t\t\tdev_kfree_skb(skb);\n-\t\t\tif (skb2 == NULL) {\n-\t\t\t\tdev->stats.tx_dropped++;\n-\t\t\t\treturn NETDEV_TX_OK;\n-\t\t\t}\n-\t\t\tskb = skb2;\n-\t\t}\n-\t\tskb_put(skb, min_frame_size - skb->len);\n-\t}\n-\n-\t/* Send to right vcc */\n-\tis_rdesc = 0;\n-\tdst = lec_h->h_dest;\n-\tentry = NULL;\n-\tvcc = lec_arp_resolve(priv, dst, is_rdesc, &entry);\n-\tpr_debug(\"%s:vcc:%p vcc_flags:%lx, entry:%p\\n\",\n-\t\t dev->name, vcc, vcc ? vcc->flags : 0, entry);\n-\tif (!vcc || !test_bit(ATM_VF_READY, &vcc->flags)) {\n-\t\tif (entry && (entry->tx_wait.qlen < LEC_UNRES_QUE_LEN)) {\n-\t\t\tpr_debug(\"%s:queuing packet, MAC address %pM\\n\",\n-\t\t\t\t dev->name, lec_h->h_dest);\n-\t\t\tskb_queue_tail(&entry->tx_wait, skb);\n-\t\t} else {\n-\t\t\tpr_debug(\"%s:tx queue full or no arp entry, dropping, MAC address: %pM\\n\",\n-\t\t\t\t dev->name, lec_h->h_dest);\n-\t\t\tdev->stats.tx_dropped++;\n-\t\t\tdev_kfree_skb(skb);\n-\t\t}\n-\t\tgoto out;\n-\t}\n-#if DUMP_PACKETS > 0\n-\tprintk(KERN_DEBUG \"%s:sending to vpi:%d vci:%d\\n\",\n-\t dev->name, vcc->vpi, vcc->vci);\n-#endif /* DUMP_PACKETS > 0 */\n-\n-\twhile (entry && (skb2 = skb_dequeue(&entry->tx_wait))) {\n-\t\tpr_debug(\"emptying tx queue, MAC address %pM\\n\", lec_h->h_dest);\n-\t\tlec_send(vcc, skb2);\n-\t}\n-\n-\tlec_send(vcc, skb);\n-\n-\tif (!atm_may_send(vcc, 0)) {\n-\t\tstruct lec_vcc_priv *vpriv = LEC_VCC_PRIV(vcc);\n-\n-\t\tvpriv->xoff = 1;\n-\t\tnetif_stop_queue(dev);\n-\n-\t\t/*\n-\t\t * vcc->pop() might have occurred in between, making\n-\t\t * the vcc usuable again. Since xmit is serialized,\n-\t\t * this is the only situation we have to re-test.\n-\t\t */\n-\n-\t\tif (atm_may_send(vcc, 0))\n-\t\t\tnetif_wake_queue(dev);\n-\t}\n-\n-out:\n-\tif (entry)\n-\t\tlec_arp_put(entry);\n-\tnetif_trans_update(dev);\n-\treturn NETDEV_TX_OK;\n-}\n-\n-/* The inverse routine to net_open(). */\n-static int lec_close(struct net_device *dev)\n-{\n-\tnetif_stop_queue(dev);\n-\treturn 0;\n-}\n-\n-static int lec_atm_send(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstatic const u8 zero_addr[ETH_ALEN] = {};\n-\tunsigned long flags;\n-\tstruct net_device *dev = (struct net_device *)vcc->proto_data;\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-\tstruct atmlec_msg *mesg;\n-\tstruct lec_arp_table *entry;\n-\tchar *tmp;\t\t/* FIXME */\n-\n-\tWARN_ON(refcount_sub_and_test(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc));\n-\tmesg = (struct atmlec_msg *)skb->data;\n-\ttmp = skb->data;\n-\ttmp += sizeof(struct atmlec_msg);\n-\tpr_debug(\"%s: msg from zeppelin:%d\\n\", dev->name, mesg->type);\n-\tswitch (mesg->type) {\n-\tcase l_set_mac_addr:\n-\t\teth_hw_addr_set(dev, mesg->content.normal.mac_addr);\n-\t\tbreak;\n-\tcase l_del_mac_addr:\n-\t\teth_hw_addr_set(dev, zero_addr);\n-\t\tbreak;\n-\tcase l_addr_delete:\n-\t\tlec_addr_delete(priv, mesg->content.normal.atm_addr,\n-\t\t\t\tmesg->content.normal.flag);\n-\t\tbreak;\n-\tcase l_topology_change:\n-\t\tpriv->topology_change = mesg->content.normal.flag;\n-\t\tbreak;\n-\tcase l_flush_complete:\n-\t\tlec_flush_complete(priv, mesg->content.normal.flag);\n-\t\tbreak;\n-\tcase l_narp_req:\t/* LANE2: see 7.1.35 in the lane2 spec */\n-\t\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\t\tentry = lec_arp_find(priv, mesg->content.normal.mac_addr);\n-\t\tlec_arp_remove(priv, entry);\n-\t\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\n-\t\tif (mesg->content.normal.no_source_le_narp)\n-\t\t\tbreak;\n-\t\tfallthrough;\n-\tcase l_arp_update:\n-\t\tlec_arp_update(priv, mesg->content.normal.mac_addr,\n-\t\t\t mesg->content.normal.atm_addr,\n-\t\t\t mesg->content.normal.flag,\n-\t\t\t mesg->content.normal.targetless_le_arp);\n-\t\tpr_debug(\"in l_arp_update\\n\");\n-\t\tif (mesg->sizeoftlvs != 0) {\t/* LANE2 3.1.5 */\n-\t\t\tpr_debug(\"LANE2 3.1.5, got tlvs, size %d\\n\",\n-\t\t\t\t mesg->sizeoftlvs);\n-\t\t\tlane2_associate_ind(dev, mesg->content.normal.mac_addr,\n-\t\t\t\t\t tmp, mesg->sizeoftlvs);\n-\t\t}\n-\t\tbreak;\n-\tcase l_config:\n-\t\tpriv->maximum_unknown_frame_count =\n-\t\t mesg->content.config.maximum_unknown_frame_count;\n-\t\tpriv->max_unknown_frame_time =\n-\t\t (mesg->content.config.max_unknown_frame_time * HZ);\n-\t\tpriv->max_retry_count = mesg->content.config.max_retry_count;\n-\t\tpriv->aging_time = (mesg->content.config.aging_time * HZ);\n-\t\tpriv->forward_delay_time =\n-\t\t (mesg->content.config.forward_delay_time * HZ);\n-\t\tpriv->arp_response_time =\n-\t\t (mesg->content.config.arp_response_time * HZ);\n-\t\tpriv->flush_timeout = (mesg->content.config.flush_timeout * HZ);\n-\t\tpriv->path_switching_delay =\n-\t\t (mesg->content.config.path_switching_delay * HZ);\n-\t\tpriv->lane_version = mesg->content.config.lane_version;\n-\t\t\t\t\t/* LANE2 */\n-\t\tpriv->lane2_ops = NULL;\n-\t\tif (priv->lane_version > 1)\n-\t\t\tpriv->lane2_ops = &lane2_ops;\n-\t\trtnl_lock();\n-\t\tif (dev_set_mtu(dev, mesg->content.config.mtu))\n-\t\t\tpr_info(\"%s: change_mtu to %d failed\\n\",\n-\t\t\t\tdev->name, mesg->content.config.mtu);\n-\t\trtnl_unlock();\n-\t\tpriv->is_proxy = mesg->content.config.is_proxy;\n-\t\tbreak;\n-\tcase l_flush_tran_id:\n-\t\tlec_set_flush_tran_id(priv, mesg->content.normal.atm_addr,\n-\t\t\t\t mesg->content.normal.flag);\n-\t\tbreak;\n-\tcase l_set_lecid:\n-\t\tpriv->lecid =\n-\t\t (unsigned short)(0xffff & mesg->content.normal.flag);\n-\t\tbreak;\n-\tcase l_should_bridge:\n-#if IS_ENABLED(CONFIG_BRIDGE)\n-\t{\n-\t\tpr_debug(\"%s: bridge zeppelin asks about %pM\\n\",\n-\t\t\t dev->name, mesg->content.proxy.mac_addr);\n-\n-\t\tif (br_fdb_test_addr_hook == NULL)\n-\t\t\tbreak;\n-\n-\t\tif (br_fdb_test_addr_hook(dev, mesg->content.proxy.mac_addr)) {\n-\t\t\t/* hit from bridge table, send LE_ARP_RESPONSE */\n-\t\t\tstruct sk_buff *skb2;\n-\t\t\tstruct sock *sk;\n-\n-\t\t\tpr_debug(\"%s: entry found, responding to zeppelin\\n\",\n-\t\t\t\t dev->name);\n-\t\t\tskb2 = alloc_skb(sizeof(struct atmlec_msg), GFP_ATOMIC);\n-\t\t\tif (skb2 == NULL)\n-\t\t\t\tbreak;\n-\t\t\tskb2->len = sizeof(struct atmlec_msg);\n-\t\t\tskb_copy_to_linear_data(skb2, mesg, sizeof(*mesg));\n-\t\t\tstruct atm_vcc *vcc;\n-\n-\t\t\trcu_read_lock();\n-\t\t\tvcc = rcu_dereference(priv->lecd);\n-\t\t\tif (vcc) {\n-\t\t\t\tatm_force_charge(vcc, skb2->truesize);\n-\t\t\t\tsk = sk_atm(vcc);\n-\t\t\t\tskb_queue_tail(&sk->sk_receive_queue, skb2);\n-\t\t\t\tsk->sk_data_ready(sk);\n-\t\t\t} else {\n-\t\t\t\tdev_kfree_skb(skb2);\n-\t\t\t}\n-\t\t\trcu_read_unlock();\n-\t\t}\n-\t}\n-#endif /* IS_ENABLED(CONFIG_BRIDGE) */\n-\t\tbreak;\n-\tdefault:\n-\t\tpr_info(\"%s: Unknown message type %d\\n\", dev->name, mesg->type);\n-\t\tdev_kfree_skb(skb);\n-\t\treturn -EINVAL;\n-\t}\n-\tdev_kfree_skb(skb);\n-\treturn 0;\n-}\n-\n-static void lec_atm_close(struct atm_vcc *vcc)\n-{\n-\tstruct net_device *dev = (struct net_device *)vcc->proto_data;\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-\n-\trcu_assign_pointer(priv->lecd, NULL);\n-\tsynchronize_rcu();\n-\t/* Do something needful? */\n-\n-\tnetif_stop_queue(dev);\n-\tlec_arp_destroy(priv);\n-\n-\tpr_info(\"%s: Shut down!\\n\", dev->name);\n-\tmodule_put(THIS_MODULE);\n-}\n-\n-static const struct atmdev_ops lecdev_ops = {\n-\t.close = lec_atm_close,\n-\t.send = lec_atm_send\n-};\n-\n-static struct atm_dev lecatm_dev = {\n-\t.ops = &lecdev_ops,\n-\t.type = \"lec\",\n-\t.number = 999,\t\t/* dummy device number */\n-\t.lock = __SPIN_LOCK_UNLOCKED(lecatm_dev.lock)\n-};\n-\n-/*\n- * LANE2: new argument struct sk_buff *data contains\n- * the LE_ARP based TLVs introduced in the LANE2 spec\n- */\n-static int\n-send_to_lecd(struct lec_priv *priv, atmlec_msg_type type,\n-\t const unsigned char *mac_addr, const unsigned char *atm_addr,\n-\t struct sk_buff *data)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct sock *sk;\n-\tstruct sk_buff *skb;\n-\tstruct atmlec_msg *mesg;\n-\n-\tif (!priv || !rcu_access_pointer(priv->lecd))\n-\t\treturn -1;\n-\n-\tskb = alloc_skb(sizeof(struct atmlec_msg), GFP_ATOMIC);\n-\tif (!skb)\n-\t\treturn -1;\n-\tskb->len = sizeof(struct atmlec_msg);\n-\tmesg = (struct atmlec_msg *)skb->data;\n-\tmemset(mesg, 0, sizeof(struct atmlec_msg));\n-\tmesg->type = type;\n-\tif (data != NULL)\n-\t\tmesg->sizeoftlvs = data->len;\n-\tif (mac_addr)\n-\t\tether_addr_copy(mesg->content.normal.mac_addr, mac_addr);\n-\telse\n-\t\tmesg->content.normal.targetless_le_arp = 1;\n-\tif (atm_addr)\n-\t\tmemcpy(&mesg->content.normal.atm_addr, atm_addr, ATM_ESA_LEN);\n-\n-\trcu_read_lock();\n-\tvcc = rcu_dereference(priv->lecd);\n-\tif (!vcc) {\n-\t\trcu_read_unlock();\n-\t\tkfree_skb(skb);\n-\t\treturn -1;\n-\t}\n-\n-\tatm_force_charge(vcc, skb->truesize);\n-\tsk = sk_atm(vcc);\n-\tskb_queue_tail(&sk->sk_receive_queue, skb);\n-\tsk->sk_data_ready(sk);\n-\n-\tif (data != NULL) {\n-\t\tpr_debug(\"about to send %d bytes of data\\n\", data->len);\n-\t\tatm_force_charge(vcc, data->truesize);\n-\t\tskb_queue_tail(&sk->sk_receive_queue, data);\n-\t\tsk->sk_data_ready(sk);\n-\t}\n-\n-\trcu_read_unlock();\n-\treturn 0;\n-}\n-\n-static void lec_set_multicast_list(struct net_device *dev)\n-{\n-\t/*\n-\t * by default, all multicast frames arrive over the bus.\n-\t * eventually support selective multicast service\n-\t */\n-}\n-\n-static const struct net_device_ops lec_netdev_ops = {\n-\t.ndo_open\t\t= lec_open,\n-\t.ndo_stop\t\t= lec_close,\n-\t.ndo_start_xmit\t\t= lec_start_xmit,\n-\t.ndo_tx_timeout\t\t= lec_tx_timeout,\n-\t.ndo_set_rx_mode\t= lec_set_multicast_list,\n-};\n-\n-static const unsigned char lec_ctrl_magic[] = {\n-\t0xff,\n-\t0x00,\n-\t0x01,\n-\t0x01\n-};\n-\n-#define LEC_DATA_DIRECT_8023 2\n-#define LEC_DATA_DIRECT_8025 3\n-\n-static int lec_is_data_direct(struct atm_vcc *vcc)\n-{\n-\treturn ((vcc->sap.blli[0].l3.tr9577.snap[4] == LEC_DATA_DIRECT_8023) ||\n-\t\t(vcc->sap.blli[0].l3.tr9577.snap[4] == LEC_DATA_DIRECT_8025));\n-}\n-\n-static void lec_push(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tunsigned long flags;\n-\tstruct net_device *dev = (struct net_device *)vcc->proto_data;\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-\n-#if DUMP_PACKETS > 0\n-\tprintk(KERN_DEBUG \"%s: vcc vpi:%d vci:%d\\n\",\n-\t dev->name, vcc->vpi, vcc->vci);\n-#endif\n-\tif (!skb) {\n-\t\tpr_debug(\"%s: null skb\\n\", dev->name);\n-\t\tlec_vcc_close(priv, vcc);\n-\t\treturn;\n-\t}\n-#if DUMP_PACKETS >= 2\n-#define MAX_SKB_DUMP 99\n-#elif DUMP_PACKETS >= 1\n-#define MAX_SKB_DUMP 30\n-#endif\n-#if DUMP_PACKETS > 0\n-\tprintk(KERN_DEBUG \"%s: rcv datalen:%ld lecid:%4.4x\\n\",\n-\t dev->name, skb->len, priv->lecid);\n-\tprint_hex_dump(KERN_DEBUG, \"\", DUMP_OFFSET, 16, 1,\n-\t\t skb->data, min(MAX_SKB_DUMP, skb->len), true);\n-#endif /* DUMP_PACKETS > 0 */\n-\tif (memcmp(skb->data, lec_ctrl_magic, 4) == 0) {\n-\t\t\t\t/* Control frame, to daemon */\n-\t\tstruct sock *sk = sk_atm(vcc);\n-\n-\t\tpr_debug(\"%s: To daemon\\n\", dev->name);\n-\t\tskb_queue_tail(&sk->sk_receive_queue, skb);\n-\t\tsk->sk_data_ready(sk);\n-\t} else {\t\t/* Data frame, queue to protocol handlers */\n-\t\tstruct lec_arp_table *entry;\n-\t\tunsigned char *src, *dst;\n-\n-\t\tatm_return(vcc, skb->truesize);\n-\t\tif (*(__be16 *) skb->data == htons(priv->lecid) ||\n-\t\t !rcu_access_pointer(priv->lecd) || !(dev->flags & IFF_UP)) {\n-\t\t\t/*\n-\t\t\t * Probably looping back, or if lecd is missing,\n-\t\t\t * lecd has gone down\n-\t\t\t */\n-\t\t\tpr_debug(\"Ignoring frame...\\n\");\n-\t\t\tdev_kfree_skb(skb);\n-\t\t\treturn;\n-\t\t}\n-\t\tdst = ((struct lecdatahdr_8023 *)skb->data)->h_dest;\n-\n-\t\t/*\n-\t\t * If this is a Data Direct VCC, and the VCC does not match\n-\t\t * the LE_ARP cache entry, delete the LE_ARP cache entry.\n-\t\t */\n-\t\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\t\tif (lec_is_data_direct(vcc)) {\n-\t\t\tsrc = ((struct lecdatahdr_8023 *)skb->data)->h_source;\n-\t\t\tentry = lec_arp_find(priv, src);\n-\t\t\tif (entry && entry->vcc != vcc) {\n-\t\t\t\tlec_arp_remove(priv, entry);\n-\t\t\t\tlec_arp_put(entry);\n-\t\t\t}\n-\t\t}\n-\t\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\n-\t\tif (!(dst[0] & 0x01) &&\t/* Never filter Multi/Broadcast */\n-\t\t !priv->is_proxy &&\t/* Proxy wants all the packets */\n-\t\t memcmp(dst, dev->dev_addr, dev->addr_len)) {\n-\t\t\tdev_kfree_skb(skb);\n-\t\t\treturn;\n-\t\t}\n-\t\tif (!hlist_empty(&priv->lec_arp_empty_ones))\n-\t\t\tlec_arp_check_empties(priv, vcc, skb);\n-\t\tskb_pull(skb, 2);\t/* skip lec_id */\n-\t\tskb->protocol = eth_type_trans(skb, dev);\n-\t\tdev->stats.rx_packets++;\n-\t\tdev->stats.rx_bytes += skb->len;\n-\t\tmemset(ATM_SKB(skb), 0, sizeof(struct atm_skb_data));\n-\t\tnetif_rx(skb);\n-\t}\n-}\n-\n-static void lec_pop(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct lec_vcc_priv *vpriv = LEC_VCC_PRIV(vcc);\n-\tstruct net_device *dev = skb->dev;\n-\n-\tif (vpriv == NULL) {\n-\t\tpr_info(\"vpriv = NULL!?!?!?\\n\");\n-\t\treturn;\n-\t}\n-\n-\tvpriv->old_pop(vcc, skb);\n-\n-\tif (vpriv->xoff && atm_may_send(vcc, 0)) {\n-\t\tvpriv->xoff = 0;\n-\t\tif (netif_running(dev) && netif_queue_stopped(dev))\n-\t\t\tnetif_wake_queue(dev);\n-\t}\n-}\n-\n-static int lec_vcc_attach(struct atm_vcc *vcc, void __user *arg)\n-{\n-\tstruct lec_vcc_priv *vpriv;\n-\tint bytes_left;\n-\tstruct atmlec_ioc ioc_data;\n-\n-\tlockdep_assert_held(&lec_mutex);\n-\t/* Lecd must be up in this case */\n-\tbytes_left = copy_from_user(&ioc_data, arg, sizeof(struct atmlec_ioc));\n-\tif (bytes_left != 0)\n-\t\tpr_info(\"copy from user failed for %d bytes\\n\", bytes_left);\n-\tif (ioc_data.dev_num < 0 || ioc_data.dev_num >= MAX_LEC_ITF)\n-\t\treturn -EINVAL;\n-\tioc_data.dev_num = array_index_nospec(ioc_data.dev_num, MAX_LEC_ITF);\n-\tif (!dev_lec[ioc_data.dev_num])\n-\t\treturn -EINVAL;\n-\tvpriv = kmalloc_obj(struct lec_vcc_priv);\n-\tif (!vpriv)\n-\t\treturn -ENOMEM;\n-\tvpriv->xoff = 0;\n-\tvpriv->old_pop = vcc->pop;\n-\tvcc->user_back = vpriv;\n-\tvcc->pop = lec_pop;\n-\tlec_vcc_added(netdev_priv(dev_lec[ioc_data.dev_num]),\n-\t\t &ioc_data, vcc, vcc->push);\n-\tvcc->proto_data = dev_lec[ioc_data.dev_num];\n-\tvcc->push = lec_push;\n-\treturn 0;\n-}\n-\n-static int lec_mcast_attach(struct atm_vcc *vcc, int arg)\n-{\n-\tlockdep_assert_held(&lec_mutex);\n-\tif (arg < 0 || arg >= MAX_LEC_ITF)\n-\t\treturn -EINVAL;\n-\targ = array_index_nospec(arg, MAX_LEC_ITF);\n-\tif (!dev_lec[arg])\n-\t\treturn -EINVAL;\n-\tvcc->proto_data = dev_lec[arg];\n-\treturn lec_mcast_make(netdev_priv(dev_lec[arg]), vcc);\n-}\n-\n-/* Initialize device. */\n-static int lecd_attach(struct atm_vcc *vcc, int arg)\n-{\n-\tint i;\n-\tstruct lec_priv *priv;\n-\n-\tlockdep_assert_held(&lec_mutex);\n-\tif (arg < 0)\n-\t\targ = 0;\n-\tif (arg >= MAX_LEC_ITF)\n-\t\treturn -EINVAL;\n-\ti = array_index_nospec(arg, MAX_LEC_ITF);\n-\tif (!dev_lec[i]) {\n-\t\tint size;\n-\n-\t\tsize = sizeof(struct lec_priv);\n-\t\tdev_lec[i] = alloc_etherdev(size);\n-\t\tif (!dev_lec[i])\n-\t\t\treturn -ENOMEM;\n-\t\tdev_lec[i]->netdev_ops = &lec_netdev_ops;\n-\t\tdev_lec[i]->max_mtu = 18190;\n-\t\tsnprintf(dev_lec[i]->name, IFNAMSIZ, \"lec%d\", i);\n-\t\tif (register_netdev(dev_lec[i])) {\n-\t\t\tfree_netdev(dev_lec[i]);\n-\t\t\tdev_lec[i] = NULL;\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tpriv = netdev_priv(dev_lec[i]);\n-\t} else {\n-\t\tpriv = netdev_priv(dev_lec[i]);\n-\t\tif (rcu_access_pointer(priv->lecd))\n-\t\t\treturn -EADDRINUSE;\n-\t}\n-\tlec_arp_init(priv);\n-\tpriv->itfnum = i;\t/* LANE2 addition */\n-\trcu_assign_pointer(priv->lecd, vcc);\n-\tvcc->dev = &lecatm_dev;\n-\tvcc_insert_socket(sk_atm(vcc));\n-\n-\tvcc->proto_data = dev_lec[i];\n-\tset_bit(ATM_VF_META, &vcc->flags);\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\n-\t/* Set default values to these variables */\n-\tpriv->maximum_unknown_frame_count = 1;\n-\tpriv->max_unknown_frame_time = (1 * HZ);\n-\tpriv->vcc_timeout_period = (1200 * HZ);\n-\tpriv->max_retry_count = 1;\n-\tpriv->aging_time = (300 * HZ);\n-\tpriv->forward_delay_time = (15 * HZ);\n-\tpriv->topology_change = 0;\n-\tpriv->arp_response_time = (1 * HZ);\n-\tpriv->flush_timeout = (4 * HZ);\n-\tpriv->path_switching_delay = (6 * HZ);\n-\n-\tif (dev_lec[i]->flags & IFF_UP)\n-\t\tnetif_start_queue(dev_lec[i]);\n-\t__module_get(THIS_MODULE);\n-\treturn i;\n-}\n-\n-#ifdef CONFIG_PROC_FS\n-static const char *lec_arp_get_status_string(unsigned char status)\n-{\n-\tstatic const char *const lec_arp_status_string[] = {\n-\t\t\"ESI_UNKNOWN \",\n-\t\t\"ESI_ARP_PENDING \",\n-\t\t\"ESI_VC_PENDING \",\n-\t\t\" \",\n-\t\t\"ESI_FLUSH_PENDING \",\n-\t\t\"ESI_FORWARD_DIRECT\"\n-\t};\n-\n-\tif (status > ESI_FORWARD_DIRECT)\n-\t\tstatus = 3;\t/* ESI_UNDEFINED */\n-\treturn lec_arp_status_string[status];\n-}\n-\n-static void lec_info(struct seq_file *seq, struct lec_arp_table *entry)\n-{\n-\tseq_printf(seq, \"%pM \", entry->mac_addr);\n-\tseq_printf(seq, \"%*phN \", ATM_ESA_LEN, entry->atm_addr);\n-\tseq_printf(seq, \"%s %4.4x\", lec_arp_get_status_string(entry->status),\n-\t\t entry->flags & 0xffff);\n-\tif (entry->vcc)\n-\t\tseq_printf(seq, \"%3d %3d \", entry->vcc->vpi, entry->vcc->vci);\n-\telse\n-\t\tseq_printf(seq, \" \");\n-\tif (entry->recv_vcc) {\n-\t\tseq_printf(seq, \" %3d %3d\", entry->recv_vcc->vpi,\n-\t\t\t entry->recv_vcc->vci);\n-\t}\n-\tseq_putc(seq, '\\n');\n-}\n-\n-struct lec_state {\n-\tunsigned long flags;\n-\tstruct lec_priv *locked;\n-\tstruct hlist_node *node;\n-\tstruct net_device *dev;\n-\tint itf;\n-\tint arp_table;\n-\tint misc_table;\n-};\n-\n-static void *lec_tbl_walk(struct lec_state *state, struct hlist_head *tbl,\n-\t\t\t loff_t *l)\n-{\n-\tstruct hlist_node *e = state->node;\n-\n-\tif (!e)\n-\t\te = tbl->first;\n-\tif (e == SEQ_START_TOKEN) {\n-\t\te = tbl->first;\n-\t\t--*l;\n-\t}\n-\n-\tfor (; e; e = e->next) {\n-\t\tif (--*l < 0)\n-\t\t\tbreak;\n-\t}\n-\tstate->node = e;\n-\n-\treturn (*l < 0) ? state : NULL;\n-}\n-\n-static void *lec_arp_walk(struct lec_state *state, loff_t *l,\n-\t\t\t struct lec_priv *priv)\n-{\n-\tvoid *v = NULL;\n-\tint p;\n-\n-\tfor (p = state->arp_table; p < LEC_ARP_TABLE_SIZE; p++) {\n-\t\tv = lec_tbl_walk(state, &priv->lec_arp_tables[p], l);\n-\t\tif (v)\n-\t\t\tbreak;\n-\t}\n-\tstate->arp_table = p;\n-\treturn v;\n-}\n-\n-static void *lec_misc_walk(struct lec_state *state, loff_t *l,\n-\t\t\t struct lec_priv *priv)\n-{\n-\tstruct hlist_head *lec_misc_tables[] = {\n-\t\t&priv->lec_arp_empty_ones,\n-\t\t&priv->lec_no_forward,\n-\t\t&priv->mcast_fwds\n-\t};\n-\tvoid *v = NULL;\n-\tint q;\n-\n-\tfor (q = state->misc_table; q < ARRAY_SIZE(lec_misc_tables); q++) {\n-\t\tv = lec_tbl_walk(state, lec_misc_tables[q], l);\n-\t\tif (v)\n-\t\t\tbreak;\n-\t}\n-\tstate->misc_table = q;\n-\treturn v;\n-}\n-\n-static void *lec_priv_walk(struct lec_state *state, loff_t *l,\n-\t\t\t struct lec_priv *priv)\n-{\n-\tif (!state->locked) {\n-\t\tstate->locked = priv;\n-\t\tspin_lock_irqsave(&priv->lec_arp_lock, state->flags);\n-\t}\n-\tif (!lec_arp_walk(state, l, priv) && !lec_misc_walk(state, l, priv)) {\n-\t\tspin_unlock_irqrestore(&priv->lec_arp_lock, state->flags);\n-\t\tstate->locked = NULL;\n-\t\t/* Partial state reset for the next time we get called */\n-\t\tstate->arp_table = state->misc_table = 0;\n-\t}\n-\treturn state->locked;\n-}\n-\n-static void *lec_itf_walk(struct lec_state *state, loff_t *l)\n-{\n-\tstruct net_device *dev;\n-\tvoid *v;\n-\n-\tdev = state->dev ? state->dev : dev_lec[state->itf];\n-\tv = (dev && netdev_priv(dev)) ?\n-\t\tlec_priv_walk(state, l, netdev_priv(dev)) : NULL;\n-\tif (!v && dev) {\n-\t\t/* Partial state reset for the next time we get called */\n-\t\tdev = NULL;\n-\t}\n-\tstate->dev = dev;\n-\treturn v;\n-}\n-\n-static void *lec_get_idx(struct lec_state *state, loff_t l)\n-{\n-\tvoid *v = NULL;\n-\n-\tfor (; state->itf < MAX_LEC_ITF; state->itf++) {\n-\t\tv = lec_itf_walk(state, &l);\n-\t\tif (v)\n-\t\t\tbreak;\n-\t}\n-\treturn v;\n-}\n-\n-static void *lec_seq_start(struct seq_file *seq, loff_t *pos)\n-{\n-\tstruct lec_state *state = seq->private;\n-\n-\tmutex_lock(&lec_mutex);\n-\tstate->itf = 0;\n-\tstate->dev = NULL;\n-\tstate->locked = NULL;\n-\tstate->arp_table = 0;\n-\tstate->misc_table = 0;\n-\tstate->node = SEQ_START_TOKEN;\n-\n-\treturn *pos ? lec_get_idx(state, *pos) : SEQ_START_TOKEN;\n-}\n-\n-static void lec_seq_stop(struct seq_file *seq, void *v)\n-{\n-\tstruct lec_state *state = seq->private;\n-\n-\tif (state->dev) {\n-\t\tspin_unlock_irqrestore(&state->locked->lec_arp_lock,\n-\t\t\t\t state->flags);\n-\t\tstate->dev = NULL;\n-\t}\n-\tmutex_unlock(&lec_mutex);\n-}\n-\n-static void *lec_seq_next(struct seq_file *seq, void *v, loff_t *pos)\n-{\n-\tstruct lec_state *state = seq->private;\n-\n-\t++*pos;\n-\treturn lec_get_idx(state, 1);\n-}\n-\n-static int lec_seq_show(struct seq_file *seq, void *v)\n-{\n-\tstatic const char lec_banner[] =\n-\t \"Itf MAC ATM destination\"\n-\t \" Status Flags \"\n-\t \"VPI/VCI Recv VPI/VCI\\n\";\n-\n-\tif (v == SEQ_START_TOKEN)\n-\t\tseq_puts(seq, lec_banner);\n-\telse {\n-\t\tstruct lec_state *state = seq->private;\n-\t\tstruct net_device *dev = state->dev;\n-\t\tstruct lec_arp_table *entry = hlist_entry(state->node,\n-\t\t\t\t\t\t\t struct lec_arp_table,\n-\t\t\t\t\t\t\t next);\n-\n-\t\tseq_printf(seq, \"%s \", dev->name);\n-\t\tlec_info(seq, entry);\n-\t}\n-\treturn 0;\n-}\n-\n-static const struct seq_operations lec_seq_ops = {\n-\t.start = lec_seq_start,\n-\t.next = lec_seq_next,\n-\t.stop = lec_seq_stop,\n-\t.show = lec_seq_show,\n-};\n-#endif\n-\n-static int lane_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)\n-{\n-\tstruct atm_vcc *vcc = ATM_SD(sock);\n-\tint err = 0;\n-\n-\tswitch (cmd) {\n-\tcase ATMLEC_CTRL:\n-\tcase ATMLEC_MCAST:\n-\tcase ATMLEC_DATA:\n-\t\tif (!capable(CAP_NET_ADMIN))\n-\t\t\treturn -EPERM;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -ENOIOCTLCMD;\n-\t}\n-\n-\tmutex_lock(&lec_mutex);\n-\tswitch (cmd) {\n-\tcase ATMLEC_CTRL:\n-\t\terr = lecd_attach(vcc, (int)arg);\n-\t\tif (err >= 0)\n-\t\t\tsock->state = SS_CONNECTED;\n-\t\tbreak;\n-\tcase ATMLEC_MCAST:\n-\t\terr = lec_mcast_attach(vcc, (int)arg);\n-\t\tbreak;\n-\tcase ATMLEC_DATA:\n-\t\terr = lec_vcc_attach(vcc, (void __user *)arg);\n-\t\tbreak;\n-\t}\n-\n-\tmutex_unlock(&lec_mutex);\n-\treturn err;\n-}\n-\n-static struct atm_ioctl lane_ioctl_ops = {\n-\t.owner = THIS_MODULE,\n-\t.ioctl = lane_ioctl,\n-};\n-\n-static int __init lane_module_init(void)\n-{\n-#ifdef CONFIG_PROC_FS\n-\tstruct proc_dir_entry *p;\n-\n-\tp = proc_create_seq_private(\"lec\", 0444, atm_proc_root, &lec_seq_ops,\n-\t\t\tsizeof(struct lec_state), NULL);\n-\tif (!p) {\n-\t\tpr_err(\"Unable to initialize /proc/net/atm/lec\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-#endif\n-\n-\tregister_atm_ioctl(&lane_ioctl_ops);\n-\tpr_info(\"lec.c: initialized\\n\");\n-\treturn 0;\n-}\n-\n-static void __exit lane_module_cleanup(void)\n-{\n-\tint i;\n-\n-#ifdef CONFIG_PROC_FS\n-\tremove_proc_entry(\"lec\", atm_proc_root);\n-#endif\n-\n-\tderegister_atm_ioctl(&lane_ioctl_ops);\n-\n-\tfor (i = 0; i < MAX_LEC_ITF; i++) {\n-\t\tif (dev_lec[i] != NULL) {\n-\t\t\tunregister_netdev(dev_lec[i]);\n-\t\t\tfree_netdev(dev_lec[i]);\n-\t\t\tdev_lec[i] = NULL;\n-\t\t}\n-\t}\n-}\n-\n-module_init(lane_module_init);\n-module_exit(lane_module_cleanup);\n-\n-/*\n- * LANE2: 3.1.3, LE_RESOLVE.request\n- * Non force allocates memory and fills in *tlvs, fills in *sizeoftlvs.\n- * If sizeoftlvs == NULL the default TLVs associated with this\n- * lec will be used.\n- * If dst_mac == NULL, targetless LE_ARP will be sent\n- */\n-static int lane2_resolve(struct net_device *dev, const u8 *dst_mac, int force,\n-\t\t\t u8 **tlvs, u32 *sizeoftlvs)\n-{\n-\tunsigned long flags;\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-\tstruct lec_arp_table *table;\n-\tstruct sk_buff *skb;\n-\tint retval;\n-\n-\tif (force == 0) {\n-\t\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\t\ttable = lec_arp_find(priv, dst_mac);\n-\t\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\t\tif (table == NULL)\n-\t\t\treturn -1;\n-\n-\t\t*tlvs = kmemdup(table->tlvs, table->sizeoftlvs, GFP_ATOMIC);\n-\t\tif (*tlvs == NULL)\n-\t\t\treturn -1;\n-\n-\t\t*sizeoftlvs = table->sizeoftlvs;\n-\n-\t\treturn 0;\n-\t}\n-\n-\tif (sizeoftlvs == NULL)\n-\t\tretval = send_to_lecd(priv, l_arp_xmt, dst_mac, NULL, NULL);\n-\n-\telse {\n-\t\tskb = alloc_skb(*sizeoftlvs, GFP_ATOMIC);\n-\t\tif (skb == NULL)\n-\t\t\treturn -1;\n-\t\tskb->len = *sizeoftlvs;\n-\t\tskb_copy_to_linear_data(skb, *tlvs, *sizeoftlvs);\n-\t\tretval = send_to_lecd(priv, l_arp_xmt, dst_mac, NULL, skb);\n-\t}\n-\treturn retval;\n-}\n-\n-/*\n- * LANE2: 3.1.4, LE_ASSOCIATE.request\n- * Associate the *tlvs with the *lan_dst address.\n- * Will overwrite any previous association\n- * Returns 1 for success, 0 for failure (out of memory)\n- *\n- */\n-static int lane2_associate_req(struct net_device *dev, const u8 *lan_dst,\n-\t\t\t const u8 *tlvs, u32 sizeoftlvs)\n-{\n-\tint retval;\n-\tstruct sk_buff *skb;\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-\n-\tif (!ether_addr_equal(lan_dst, dev->dev_addr))\n-\t\treturn 0;\t/* not our mac address */\n-\n-\tkfree(priv->tlvs);\t/* NULL if there was no previous association */\n-\n-\tpriv->tlvs = kmemdup(tlvs, sizeoftlvs, GFP_KERNEL);\n-\tif (priv->tlvs == NULL)\n-\t\treturn 0;\n-\tpriv->sizeoftlvs = sizeoftlvs;\n-\n-\tskb = alloc_skb(sizeoftlvs, GFP_ATOMIC);\n-\tif (skb == NULL)\n-\t\treturn 0;\n-\tskb->len = sizeoftlvs;\n-\tskb_copy_to_linear_data(skb, tlvs, sizeoftlvs);\n-\tretval = send_to_lecd(priv, l_associate_req, NULL, NULL, skb);\n-\tif (retval != 0)\n-\t\tpr_info(\"lec.c: lane2_associate_req() failed\\n\");\n-\t/*\n-\t * If the previous association has changed we must\n-\t * somehow notify other LANE entities about the change\n-\t */\n-\treturn 1;\n-}\n-\n-/*\n- * LANE2: 3.1.5, LE_ASSOCIATE.indication\n- *\n- */\n-static void lane2_associate_ind(struct net_device *dev, const u8 *mac_addr,\n-\t\t\t\tconst u8 *tlvs, u32 sizeoftlvs)\n-{\n-#if 0\n-\tint i = 0;\n-#endif\n-\tstruct lec_priv *priv = netdev_priv(dev);\n-#if 0\t\t\t\t/*\n-\t\t\t\t * Why have the TLVs in LE_ARP entries\n-\t\t\t\t * since we do not use them? When you\n-\t\t\t\t * uncomment this code, make sure the\n-\t\t\t\t * TLVs get freed when entry is killed\n-\t\t\t\t */\n-\tstruct lec_arp_table *entry = lec_arp_find(priv, mac_addr);\n-\n-\tif (entry == NULL)\n-\t\treturn;\t\t/* should not happen */\n-\n-\tkfree(entry->tlvs);\n-\n-\tentry->tlvs = kmemdup(tlvs, sizeoftlvs, GFP_KERNEL);\n-\tif (entry->tlvs == NULL)\n-\t\treturn;\n-\tentry->sizeoftlvs = sizeoftlvs;\n-#endif\n-#if 0\n-\tpr_info(\"\\n\");\n-\tpr_info(\"dump of tlvs, sizeoftlvs=%d\\n\", sizeoftlvs);\n-\twhile (i < sizeoftlvs)\n-\t\tpr_cont(\"%02x \", tlvs[i++]);\n-\n-\tpr_cont(\"\\n\");\n-#endif\n-\n-\t/* tell MPOA about the TLVs we saw */\n-\tif (priv->lane2_ops && priv->lane2_ops->associate_indicator) {\n-\t\tpriv->lane2_ops->associate_indicator(dev, mac_addr,\n-\t\t\t\t\t\t tlvs, sizeoftlvs);\n-\t}\n-}\n-\n-/*\n- * Here starts what used to lec_arpc.c\n- *\n- * lec_arpc.c was added here when making\n- * lane client modular. October 1997\n- */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#if 0\n-#define pr_debug(format, args...)\n-/*\n- #define pr_debug printk\n-*/\n-#endif\n-#define DEBUG_ARP_TABLE 0\n-\n-#define LEC_ARP_REFRESH_INTERVAL (3*HZ)\n-\n-static void lec_arp_check_expire(struct work_struct *work);\n-static void lec_arp_expire_arp(struct timer_list *t);\n-\n-/*\n- * Arp table funcs\n- */\n-\n-#define HASH(ch) (ch & (LEC_ARP_TABLE_SIZE - 1))\n-\n-/*\n- * Initialization of arp-cache\n- */\n-static void lec_arp_init(struct lec_priv *priv)\n-{\n-\tunsigned short i;\n-\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++)\n-\t\tINIT_HLIST_HEAD(&priv->lec_arp_tables[i]);\n-\tINIT_HLIST_HEAD(&priv->lec_arp_empty_ones);\n-\tINIT_HLIST_HEAD(&priv->lec_no_forward);\n-\tINIT_HLIST_HEAD(&priv->mcast_fwds);\n-\tspin_lock_init(&priv->lec_arp_lock);\n-\tINIT_DELAYED_WORK(&priv->lec_arp_work, lec_arp_check_expire);\n-\tschedule_delayed_work(&priv->lec_arp_work, LEC_ARP_REFRESH_INTERVAL);\n-}\n-\n-static void lec_arp_clear_vccs(struct lec_arp_table *entry)\n-{\n-\tif (entry->vcc) {\n-\t\tstruct atm_vcc *vcc = entry->vcc;\n-\t\tstruct lec_vcc_priv *vpriv = LEC_VCC_PRIV(vcc);\n-\t\tstruct net_device *dev = (struct net_device *)vcc->proto_data;\n-\n-\t\tif (vpriv) {\n-\t\t\tvcc->pop = vpriv->old_pop;\n-\t\t\tif (vpriv->xoff)\n-\t\t\t\tnetif_wake_queue(dev);\n-\t\t\tkfree(vpriv);\n-\t\t\tvcc->user_back = NULL;\n-\t\t\tvcc->push = entry->old_push;\n-\t\t\tvcc_release_async(vcc, -EPIPE);\n-\t\t}\n-\t\tentry->vcc = NULL;\n-\t}\n-\tif (entry->recv_vcc) {\n-\t\tstruct atm_vcc *vcc = entry->recv_vcc;\n-\t\tstruct lec_vcc_priv *vpriv = LEC_VCC_PRIV(vcc);\n-\n-\t\tif (vpriv) {\n-\t\t\tkfree(vpriv);\n-\t\t\tvcc->user_back = NULL;\n-\n-\t\t\tentry->recv_vcc->push = entry->old_recv_push;\n-\t\t\tvcc_release_async(entry->recv_vcc, -EPIPE);\n-\t\t}\n-\t\tentry->recv_vcc = NULL;\n-\t}\n-}\n-\n-/*\n- * Insert entry to lec_arp_table\n- * LANE2: Add to the end of the list to satisfy 8.1.13\n- */\n-static inline void\n-lec_arp_add(struct lec_priv *priv, struct lec_arp_table *entry)\n-{\n-\tstruct hlist_head *tmp;\n-\n-\ttmp = &priv->lec_arp_tables[HASH(entry->mac_addr[ETH_ALEN - 1])];\n-\thlist_add_head(&entry->next, tmp);\n-\n-\tpr_debug(\"Added entry:%pM\\n\", entry->mac_addr);\n-}\n-\n-/*\n- * Remove entry from lec_arp_table\n- */\n-static int\n-lec_arp_remove(struct lec_priv *priv, struct lec_arp_table *to_remove)\n-{\n-\tstruct lec_arp_table *entry;\n-\tint i, remove_vcc = 1;\n-\n-\tif (!to_remove)\n-\t\treturn -1;\n-\n-\thlist_del(&to_remove->next);\n-\ttimer_delete(&to_remove->timer);\n-\n-\t/*\n-\t * If this is the only MAC connected to this VCC,\n-\t * also tear down the VCC\n-\t */\n-\tif (to_remove->status >= ESI_FLUSH_PENDING) {\n-\t\t/*\n-\t\t * ESI_FLUSH_PENDING, ESI_FORWARD_DIRECT\n-\t\t */\n-\t\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\t\thlist_for_each_entry(entry,\n-\t\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\t\tif (memcmp(to_remove->atm_addr,\n-\t\t\t\t\t entry->atm_addr, ATM_ESA_LEN) == 0) {\n-\t\t\t\t\tremove_vcc = 0;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t\tif (remove_vcc)\n-\t\t\tlec_arp_clear_vccs(to_remove);\n-\t}\n-\tskb_queue_purge(&to_remove->tx_wait);\t/* FIXME: good place for this? */\n-\n-\tpr_debug(\"Removed entry:%pM\\n\", to_remove->mac_addr);\n-\treturn 0;\n-}\n-\n-#if DEBUG_ARP_TABLE\n-static const char *get_status_string(unsigned char st)\n-{\n-\tswitch (st) {\n-\tcase ESI_UNKNOWN:\n-\t\treturn \"ESI_UNKNOWN\";\n-\tcase ESI_ARP_PENDING:\n-\t\treturn \"ESI_ARP_PENDING\";\n-\tcase ESI_VC_PENDING:\n-\t\treturn \"ESI_VC_PENDING\";\n-\tcase ESI_FLUSH_PENDING:\n-\t\treturn \"ESI_FLUSH_PENDING\";\n-\tcase ESI_FORWARD_DIRECT:\n-\t\treturn \"ESI_FORWARD_DIRECT\";\n-\t}\n-\treturn \"\";\n-}\n-\n-static void dump_arp_table(struct lec_priv *priv)\n-{\n-\tstruct lec_arp_table *rulla;\n-\tchar buf[256];\n-\tint i, offset;\n-\n-\tpr_info(\"Dump %p:\\n\", priv);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry(rulla,\n-\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\toffset = 0;\n-\t\t\toffset += sprintf(buf, \"%d: %p\\n\", i, rulla);\n-\t\t\toffset += sprintf(buf + offset, \"Mac: %pM \",\n-\t\t\t\t\t rulla->mac_addr);\n-\t\t\toffset += sprintf(buf + offset, \"Atm: %*ph \", ATM_ESA_LEN,\n-\t\t\t\t\t rulla->atm_addr);\n-\t\t\toffset += sprintf(buf + offset,\n-\t\t\t\t\t \"Vcc vpi:%d vci:%d, Recv_vcc vpi:%d vci:%d Last_used:%lx, Timestamp:%lx, No_tries:%d \",\n-\t\t\t\t\t rulla->vcc ? rulla->vcc->vpi : 0,\n-\t\t\t\t\t rulla->vcc ? rulla->vcc->vci : 0,\n-\t\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->\n-\t\t\t\t\t vpi : 0,\n-\t\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->\n-\t\t\t\t\t vci : 0, rulla->last_used,\n-\t\t\t\t\t rulla->timestamp, rulla->no_tries);\n-\t\t\toffset +=\n-\t\t\t sprintf(buf + offset,\n-\t\t\t\t \"Flags:%x, Packets_flooded:%x, Status: %s \",\n-\t\t\t\t rulla->flags, rulla->packets_flooded,\n-\t\t\t\t get_status_string(rulla->status));\n-\t\t\tpr_info(\"%s\\n\", buf);\n-\t\t}\n-\t}\n-\n-\tif (!hlist_empty(&priv->lec_no_forward))\n-\t\tpr_info(\"No forward\\n\");\n-\thlist_for_each_entry(rulla, &priv->lec_no_forward, next) {\n-\t\toffset = 0;\n-\t\toffset += sprintf(buf + offset, \"Mac: %pM \", rulla->mac_addr);\n-\t\toffset += sprintf(buf + offset, \"Atm: %*ph \", ATM_ESA_LEN,\n-\t\t\t\t rulla->atm_addr);\n-\t\toffset += sprintf(buf + offset,\n-\t\t\t\t \"Vcc vpi:%d vci:%d, Recv_vcc vpi:%d vci:%d Last_used:%lx, Timestamp:%lx, No_tries:%d \",\n-\t\t\t\t rulla->vcc ? rulla->vcc->vpi : 0,\n-\t\t\t\t rulla->vcc ? rulla->vcc->vci : 0,\n-\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->vpi : 0,\n-\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->vci : 0,\n-\t\t\t\t rulla->last_used,\n-\t\t\t\t rulla->timestamp, rulla->no_tries);\n-\t\toffset += sprintf(buf + offset,\n-\t\t\t\t \"Flags:%x, Packets_flooded:%x, Status: %s \",\n-\t\t\t\t rulla->flags, rulla->packets_flooded,\n-\t\t\t\t get_status_string(rulla->status));\n-\t\tpr_info(\"%s\\n\", buf);\n-\t}\n-\n-\tif (!hlist_empty(&priv->lec_arp_empty_ones))\n-\t\tpr_info(\"Empty ones\\n\");\n-\thlist_for_each_entry(rulla, &priv->lec_arp_empty_ones, next) {\n-\t\toffset = 0;\n-\t\toffset += sprintf(buf + offset, \"Mac: %pM \", rulla->mac_addr);\n-\t\toffset += sprintf(buf + offset, \"Atm: %*ph \", ATM_ESA_LEN,\n-\t\t\t\t rulla->atm_addr);\n-\t\toffset += sprintf(buf + offset,\n-\t\t\t\t \"Vcc vpi:%d vci:%d, Recv_vcc vpi:%d vci:%d Last_used:%lx, Timestamp:%lx, No_tries:%d \",\n-\t\t\t\t rulla->vcc ? rulla->vcc->vpi : 0,\n-\t\t\t\t rulla->vcc ? rulla->vcc->vci : 0,\n-\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->vpi : 0,\n-\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->vci : 0,\n-\t\t\t\t rulla->last_used,\n-\t\t\t\t rulla->timestamp, rulla->no_tries);\n-\t\toffset += sprintf(buf + offset,\n-\t\t\t\t \"Flags:%x, Packets_flooded:%x, Status: %s \",\n-\t\t\t\t rulla->flags, rulla->packets_flooded,\n-\t\t\t\t get_status_string(rulla->status));\n-\t\tpr_info(\"%s\", buf);\n-\t}\n-\n-\tif (!hlist_empty(&priv->mcast_fwds))\n-\t\tpr_info(\"Multicast Forward VCCs\\n\");\n-\thlist_for_each_entry(rulla, &priv->mcast_fwds, next) {\n-\t\toffset = 0;\n-\t\toffset += sprintf(buf + offset, \"Mac: %pM \", rulla->mac_addr);\n-\t\toffset += sprintf(buf + offset, \"Atm: %*ph \", ATM_ESA_LEN,\n-\t\t\t\t rulla->atm_addr);\n-\t\toffset += sprintf(buf + offset,\n-\t\t\t\t \"Vcc vpi:%d vci:%d, Recv_vcc vpi:%d vci:%d Last_used:%lx, Timestamp:%lx, No_tries:%d \",\n-\t\t\t\t rulla->vcc ? rulla->vcc->vpi : 0,\n-\t\t\t\t rulla->vcc ? rulla->vcc->vci : 0,\n-\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->vpi : 0,\n-\t\t\t\t rulla->recv_vcc ? rulla->recv_vcc->vci : 0,\n-\t\t\t\t rulla->last_used,\n-\t\t\t\t rulla->timestamp, rulla->no_tries);\n-\t\toffset += sprintf(buf + offset,\n-\t\t\t\t \"Flags:%x, Packets_flooded:%x, Status: %s \",\n-\t\t\t\t rulla->flags, rulla->packets_flooded,\n-\t\t\t\t get_status_string(rulla->status));\n-\t\tpr_info(\"%s\\n\", buf);\n-\t}\n-\n-}\n-#else\n-#define dump_arp_table(priv) do { } while (0)\n-#endif\n-\n-/*\n- * Destruction of arp-cache\n- */\n-static void lec_arp_destroy(struct lec_priv *priv)\n-{\n-\tunsigned long flags;\n-\tstruct hlist_node *next;\n-\tstruct lec_arp_table *entry;\n-\tint i;\n-\n-\tcancel_delayed_work_sync(&priv->lec_arp_work);\n-\n-\t/*\n-\t * Remove all entries\n-\t */\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tlec_arp_remove(priv, entry);\n-\t\t\tlec_arp_put(entry);\n-\t\t}\n-\t\tINIT_HLIST_HEAD(&priv->lec_arp_tables[i]);\n-\t}\n-\n-\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t &priv->lec_arp_empty_ones, next) {\n-\t\ttimer_delete_sync(&entry->timer);\n-\t\tlec_arp_clear_vccs(entry);\n-\t\thlist_del(&entry->next);\n-\t\tlec_arp_put(entry);\n-\t}\n-\tINIT_HLIST_HEAD(&priv->lec_arp_empty_ones);\n-\n-\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t &priv->lec_no_forward, next) {\n-\t\ttimer_delete_sync(&entry->timer);\n-\t\tlec_arp_clear_vccs(entry);\n-\t\thlist_del(&entry->next);\n-\t\tlec_arp_put(entry);\n-\t}\n-\tINIT_HLIST_HEAD(&priv->lec_no_forward);\n-\n-\thlist_for_each_entry_safe(entry, next, &priv->mcast_fwds, next) {\n-\t\t/* No timer, LANEv2 7.1.20 and 2.3.5.3 */\n-\t\tlec_arp_clear_vccs(entry);\n-\t\thlist_del(&entry->next);\n-\t\tlec_arp_put(entry);\n-\t}\n-\tINIT_HLIST_HEAD(&priv->mcast_fwds);\n-\tpriv->mcast_vcc = NULL;\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-}\n-\n-/*\n- * Find entry by mac_address\n- */\n-static struct lec_arp_table *lec_arp_find(struct lec_priv *priv,\n-\t\t\t\t\t const unsigned char *mac_addr)\n-{\n-\tstruct hlist_head *head;\n-\tstruct lec_arp_table *entry;\n-\n-\tpr_debug(\"%pM\\n\", mac_addr);\n-\n-\thead = &priv->lec_arp_tables[HASH(mac_addr[ETH_ALEN - 1])];\n-\thlist_for_each_entry(entry, head, next) {\n-\t\tif (ether_addr_equal(mac_addr, entry->mac_addr))\n-\t\t\treturn entry;\n-\t}\n-\treturn NULL;\n-}\n-\n-static struct lec_arp_table *make_entry(struct lec_priv *priv,\n-\t\t\t\t\tconst unsigned char *mac_addr)\n-{\n-\tstruct lec_arp_table *to_return;\n-\n-\tto_return = kzalloc_obj(struct lec_arp_table, GFP_ATOMIC);\n-\tif (!to_return)\n-\t\treturn NULL;\n-\tether_addr_copy(to_return->mac_addr, mac_addr);\n-\tINIT_HLIST_NODE(&to_return->next);\n-\ttimer_setup(&to_return->timer, lec_arp_expire_arp, 0);\n-\tto_return->last_used = jiffies;\n-\tto_return->priv = priv;\n-\tskb_queue_head_init(&to_return->tx_wait);\n-\trefcount_set(&to_return->usage, 1);\n-\treturn to_return;\n-}\n-\n-/* Arp sent timer expired */\n-static void lec_arp_expire_arp(struct timer_list *t)\n-{\n-\tstruct lec_arp_table *entry;\n-\n-\tentry = timer_container_of(entry, t, timer);\n-\n-\tpr_debug(\"\\n\");\n-\tif (entry->status == ESI_ARP_PENDING) {\n-\t\tif (entry->no_tries <= entry->priv->max_retry_count) {\n-\t\t\tif (entry->is_rdesc)\n-\t\t\t\tsend_to_lecd(entry->priv, l_rdesc_arp_xmt,\n-\t\t\t\t\t entry->mac_addr, NULL, NULL);\n-\t\t\telse\n-\t\t\t\tsend_to_lecd(entry->priv, l_arp_xmt,\n-\t\t\t\t\t entry->mac_addr, NULL, NULL);\n-\t\t\tentry->no_tries++;\n-\t\t}\n-\t\tmod_timer(&entry->timer, jiffies + (1 * HZ));\n-\t}\n-}\n-\n-/* Unknown/unused vcc expire, remove associated entry */\n-static void lec_arp_expire_vcc(struct timer_list *t)\n-{\n-\tunsigned long flags;\n-\tstruct lec_arp_table *to_remove = timer_container_of(to_remove, t,\n-\t\t\t\t\t\t\t timer);\n-\tstruct lec_priv *priv = to_remove->priv;\n-\n-\ttimer_delete(&to_remove->timer);\n-\n-\tpr_debug(\"%p %p: vpi:%d vci:%d\\n\",\n-\t\t to_remove, priv,\n-\t\t to_remove->vcc ? to_remove->recv_vcc->vpi : 0,\n-\t\t to_remove->vcc ? to_remove->recv_vcc->vci : 0);\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\thlist_del(&to_remove->next);\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\n-\tlec_arp_clear_vccs(to_remove);\n-\tlec_arp_put(to_remove);\n-}\n-\n-static bool __lec_arp_check_expire(struct lec_arp_table *entry,\n-\t\t\t\t unsigned long now,\n-\t\t\t\t struct lec_priv *priv)\n-{\n-\tunsigned long time_to_check;\n-\n-\tif ((entry->flags) & LEC_REMOTE_FLAG && priv->topology_change)\n-\t\ttime_to_check = priv->forward_delay_time;\n-\telse\n-\t\ttime_to_check = priv->aging_time;\n-\n-\tpr_debug(\"About to expire: %lx - %lx > %lx\\n\",\n-\t\t now, entry->last_used, time_to_check);\n-\tif (time_after(now, entry->last_used + time_to_check) &&\n-\t !(entry->flags & LEC_PERMANENT_FLAG) &&\n-\t !(entry->mac_addr[0] & 0x01)) {\t/* LANE2: 7.1.20 */\n-\t\t/* Remove entry */\n-\t\tpr_debug(\"Entry timed out\\n\");\n-\t\tlec_arp_remove(priv, entry);\n-\t\tlec_arp_put(entry);\n-\t} else {\n-\t\t/* Something else */\n-\t\tif ((entry->status == ESI_VC_PENDING ||\n-\t\t entry->status == ESI_ARP_PENDING) &&\n-\t\t time_after_eq(now, entry->timestamp +\n-\t\t\t\t priv->max_unknown_frame_time)) {\n-\t\t\tentry->timestamp = jiffies;\n-\t\t\tentry->packets_flooded = 0;\n-\t\t\tif (entry->status == ESI_VC_PENDING)\n-\t\t\t\tsend_to_lecd(priv, l_svc_setup,\n-\t\t\t\t\t entry->mac_addr,\n-\t\t\t\t\t entry->atm_addr,\n-\t\t\t\t\t NULL);\n-\t\t}\n-\t\tif (entry->status == ESI_FLUSH_PENDING &&\n-\t\t time_after_eq(now, entry->timestamp +\n-\t\t\t\t priv->path_switching_delay)) {\n-\t\t\tlec_arp_hold(entry);\n-\t\t\treturn true;\n-\t\t}\n-\t}\n-\n-\treturn false;\n-}\n-/*\n- * Expire entries.\n- * 1. Re-set timer\n- * 2. For each entry, delete entries that have aged past the age limit.\n- * 3. For each entry, depending on the status of the entry, perform\n- * the following maintenance.\n- * a. If status is ESI_VC_PENDING or ESI_ARP_PENDING then if the\n- * tick_count is above the max_unknown_frame_time, clear\n- * the tick_count to zero and clear the packets_flooded counter\n- * to zero. This supports the packet rate limit per address\n- * while flooding unknowns.\n- * b. If the status is ESI_FLUSH_PENDING and the tick_count is greater\n- * than or equal to the path_switching_delay, change the status\n- * to ESI_FORWARD_DIRECT. This causes the flush period to end\n- * regardless of the progress of the flush protocol.\n- */\n-static void lec_arp_check_expire(struct work_struct *work)\n-{\n-\tunsigned long flags;\n-\tstruct lec_priv *priv =\n-\t\tcontainer_of(work, struct lec_priv, lec_arp_work.work);\n-\tstruct hlist_node *next;\n-\tstruct lec_arp_table *entry;\n-\tunsigned long now;\n-\tint i;\n-\n-\tpr_debug(\"%p\\n\", priv);\n-\tnow = jiffies;\n-restart:\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (__lec_arp_check_expire(entry, now, priv)) {\n-\t\t\t\tstruct sk_buff *skb;\n-\t\t\t\tstruct atm_vcc *vcc = entry->vcc;\n-\n-\t\t\t\tspin_unlock_irqrestore(&priv->lec_arp_lock,\n-\t\t\t\t\t\t flags);\n-\t\t\t\twhile ((skb = skb_dequeue(&entry->tx_wait)))\n-\t\t\t\t\tlec_send(vcc, skb);\n-\t\t\t\tentry->last_used = jiffies;\n-\t\t\t\tentry->status = ESI_FORWARD_DIRECT;\n-\t\t\t\tlec_arp_put(entry);\n-\n-\t\t\t\tgoto restart;\n-\t\t\t}\n-\t\t}\n-\t}\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\n-\tschedule_delayed_work(&priv->lec_arp_work, LEC_ARP_REFRESH_INTERVAL);\n-}\n-\n-/*\n- * Try to find vcc where mac_address is attached.\n- *\n- */\n-static struct atm_vcc *lec_arp_resolve(struct lec_priv *priv,\n-\t\t\t\t const unsigned char *mac_to_find,\n-\t\t\t\t int is_rdesc,\n-\t\t\t\t struct lec_arp_table **ret_entry)\n-{\n-\tunsigned long flags;\n-\tstruct lec_arp_table *entry;\n-\tstruct atm_vcc *found;\n-\n-\tif (mac_to_find[0] & 0x01) {\n-\t\tswitch (priv->lane_version) {\n-\t\tcase 1:\n-\t\t\treturn priv->mcast_vcc;\n-\t\tcase 2:\t/* LANE2 wants arp for multicast addresses */\n-\t\t\tif (ether_addr_equal(mac_to_find, bus_mac))\n-\t\t\t\treturn priv->mcast_vcc;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tentry = lec_arp_find(priv, mac_to_find);\n-\n-\tif (entry) {\n-\t\tif (entry->status == ESI_FORWARD_DIRECT) {\n-\t\t\t/* Connection Ok */\n-\t\t\tentry->last_used = jiffies;\n-\t\t\tlec_arp_hold(entry);\n-\t\t\t*ret_entry = entry;\n-\t\t\tfound = entry->vcc;\n-\t\t\tgoto out;\n-\t\t}\n-\t\t/*\n-\t\t * If the LE_ARP cache entry is still pending, reset count to 0\n-\t\t * so another LE_ARP request can be made for this frame.\n-\t\t */\n-\t\tif (entry->status == ESI_ARP_PENDING)\n-\t\t\tentry->no_tries = 0;\n-\t\t/*\n-\t\t * Data direct VC not yet set up, check to see if the unknown\n-\t\t * frame count is greater than the limit. If the limit has\n-\t\t * not been reached, allow the caller to send packet to\n-\t\t * BUS.\n-\t\t */\n-\t\tif (entry->status != ESI_FLUSH_PENDING &&\n-\t\t entry->packets_flooded <\n-\t\t priv->maximum_unknown_frame_count) {\n-\t\t\tentry->packets_flooded++;\n-\t\t\tpr_debug(\"Flooding..\\n\");\n-\t\t\tfound = priv->mcast_vcc;\n-\t\t\tgoto out;\n-\t\t}\n-\t\t/*\n-\t\t * We got here because entry->status == ESI_FLUSH_PENDING\n-\t\t * or BUS flood limit was reached for an entry which is\n-\t\t * in ESI_ARP_PENDING or ESI_VC_PENDING state.\n-\t\t */\n-\t\tlec_arp_hold(entry);\n-\t\t*ret_entry = entry;\n-\t\tpr_debug(\"entry->status %d entry->vcc %p\\n\", entry->status,\n-\t\t\t entry->vcc);\n-\t\tfound = NULL;\n-\t} else {\n-\t\t/* No matching entry was found */\n-\t\tentry = make_entry(priv, mac_to_find);\n-\t\tpr_debug(\"Making entry\\n\");\n-\t\tif (!entry) {\n-\t\t\tfound = priv->mcast_vcc;\n-\t\t\tgoto out;\n-\t\t}\n-\t\tlec_arp_add(priv, entry);\n-\t\t/* We want arp-request(s) to be sent */\n-\t\tentry->packets_flooded = 1;\n-\t\tentry->status = ESI_ARP_PENDING;\n-\t\tentry->no_tries = 1;\n-\t\tentry->last_used = entry->timestamp = jiffies;\n-\t\tentry->is_rdesc = is_rdesc;\n-\t\tif (entry->is_rdesc)\n-\t\t\tsend_to_lecd(priv, l_rdesc_arp_xmt, mac_to_find, NULL,\n-\t\t\t\t NULL);\n-\t\telse\n-\t\t\tsend_to_lecd(priv, l_arp_xmt, mac_to_find, NULL, NULL);\n-\t\tentry->timer.expires = jiffies + (1 * HZ);\n-\t\tentry->timer.function = lec_arp_expire_arp;\n-\t\tadd_timer(&entry->timer);\n-\t\tfound = priv->mcast_vcc;\n-\t}\n-\n-out:\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\treturn found;\n-}\n-\n-static int\n-lec_addr_delete(struct lec_priv *priv, const unsigned char *atm_addr,\n-\t\tunsigned long permanent)\n-{\n-\tunsigned long flags;\n-\tstruct hlist_node *next;\n-\tstruct lec_arp_table *entry;\n-\tint i;\n-\n-\tpr_debug(\"\\n\");\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (!memcmp(atm_addr, entry->atm_addr, ATM_ESA_LEN) &&\n-\t\t\t (permanent ||\n-\t\t\t !(entry->flags & LEC_PERMANENT_FLAG))) {\n-\t\t\t\tlec_arp_remove(priv, entry);\n-\t\t\t\tlec_arp_put(entry);\n-\t\t\t}\n-\t\t\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\treturn -1;\n-}\n-\n-/*\n- * Notifies: Response to arp_request (atm_addr != NULL)\n- */\n-static void\n-lec_arp_update(struct lec_priv *priv, const unsigned char *mac_addr,\n-\t const unsigned char *atm_addr, unsigned long remoteflag,\n-\t unsigned int targetless_le_arp)\n-{\n-\tunsigned long flags;\n-\tstruct hlist_node *next;\n-\tstruct lec_arp_table *entry, *tmp;\n-\tint i;\n-\n-\tpr_debug(\"%smac:%pM\\n\",\n-\t\t (targetless_le_arp) ? \"targetless \" : \"\", mac_addr);\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tentry = lec_arp_find(priv, mac_addr);\n-\tif (entry == NULL && targetless_le_arp)\n-\t\tgoto out;\t/*\n-\t\t\t\t * LANE2: ignore targetless LE_ARPs for which\n-\t\t\t\t * we have no entry in the cache. 7.1.30\n-\t\t\t\t */\n-\tif (!hlist_empty(&priv->lec_arp_empty_ones)) {\n-\t\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t\t &priv->lec_arp_empty_ones, next) {\n-\t\t\tif (memcmp(entry->atm_addr, atm_addr, ATM_ESA_LEN) == 0) {\n-\t\t\t\thlist_del(&entry->next);\n-\t\t\t\ttimer_delete(&entry->timer);\n-\t\t\t\ttmp = lec_arp_find(priv, mac_addr);\n-\t\t\t\tif (tmp) {\n-\t\t\t\t\ttimer_delete(&tmp->timer);\n-\t\t\t\t\ttmp->status = ESI_FORWARD_DIRECT;\n-\t\t\t\t\tmemcpy(tmp->atm_addr, atm_addr, ATM_ESA_LEN);\n-\t\t\t\t\ttmp->vcc = entry->vcc;\n-\t\t\t\t\ttmp->old_push = entry->old_push;\n-\t\t\t\t\ttmp->last_used = jiffies;\n-\t\t\t\t\ttimer_delete(&entry->timer);\n-\t\t\t\t\tlec_arp_put(entry);\n-\t\t\t\t\tentry = tmp;\n-\t\t\t\t} else {\n-\t\t\t\t\tentry->status = ESI_FORWARD_DIRECT;\n-\t\t\t\t\tether_addr_copy(entry->mac_addr,\n-\t\t\t\t\t\t\tmac_addr);\n-\t\t\t\t\tentry->last_used = jiffies;\n-\t\t\t\t\tlec_arp_add(priv, entry);\n-\t\t\t\t}\n-\t\t\t\tif (remoteflag)\n-\t\t\t\t\tentry->flags |= LEC_REMOTE_FLAG;\n-\t\t\t\telse\n-\t\t\t\t\tentry->flags &= ~LEC_REMOTE_FLAG;\n-\t\t\t\tpr_debug(\"After update\\n\");\n-\t\t\t\tdump_arp_table(priv);\n-\t\t\t\tgoto out;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tentry = lec_arp_find(priv, mac_addr);\n-\tif (!entry) {\n-\t\tentry = make_entry(priv, mac_addr);\n-\t\tif (!entry)\n-\t\t\tgoto out;\n-\t\tentry->status = ESI_UNKNOWN;\n-\t\tlec_arp_add(priv, entry);\n-\t\t/* Temporary, changes before end of function */\n-\t}\n-\tmemcpy(entry->atm_addr, atm_addr, ATM_ESA_LEN);\n-\ttimer_delete(&entry->timer);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry(tmp,\n-\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (entry != tmp &&\n-\t\t\t !memcmp(tmp->atm_addr, atm_addr, ATM_ESA_LEN)) {\n-\t\t\t\t/* Vcc to this host exists */\n-\t\t\t\tif (tmp->status > ESI_VC_PENDING) {\n-\t\t\t\t\t/*\n-\t\t\t\t\t * ESI_FLUSH_PENDING,\n-\t\t\t\t\t * ESI_FORWARD_DIRECT\n-\t\t\t\t\t */\n-\t\t\t\t\tentry->vcc = tmp->vcc;\n-\t\t\t\t\tentry->old_push = tmp->old_push;\n-\t\t\t\t}\n-\t\t\t\tentry->status = tmp->status;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t}\n-\tif (remoteflag)\n-\t\tentry->flags |= LEC_REMOTE_FLAG;\n-\telse\n-\t\tentry->flags &= ~LEC_REMOTE_FLAG;\n-\tif (entry->status == ESI_ARP_PENDING || entry->status == ESI_UNKNOWN) {\n-\t\tentry->status = ESI_VC_PENDING;\n-\t\tsend_to_lecd(priv, l_svc_setup, entry->mac_addr, atm_addr, NULL);\n-\t}\n-\tpr_debug(\"After update2\\n\");\n-\tdump_arp_table(priv);\n-out:\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-}\n-\n-/*\n- * Notifies: Vcc setup ready\n- */\n-static void\n-lec_vcc_added(struct lec_priv *priv, const struct atmlec_ioc *ioc_data,\n-\t struct atm_vcc *vcc,\n-\t void (*old_push) (struct atm_vcc *vcc, struct sk_buff *skb))\n-{\n-\tunsigned long flags;\n-\tstruct lec_arp_table *entry;\n-\tint i, found_entry = 0;\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\t/* Vcc for Multicast Forward. No timer, LANEv2 7.1.20 and 2.3.5.3 */\n-\tif (ioc_data->receive == 2) {\n-\t\tpr_debug(\"LEC_ARP: Attaching mcast forward\\n\");\n-#if 0\n-\t\tentry = lec_arp_find(priv, bus_mac);\n-\t\tif (!entry) {\n-\t\t\tpr_info(\"LEC_ARP: Multicast entry not found!\\n\");\n-\t\t\tgoto out;\n-\t\t}\n-\t\tmemcpy(entry->atm_addr, ioc_data->atm_addr, ATM_ESA_LEN);\n-\t\tentry->recv_vcc = vcc;\n-\t\tentry->old_recv_push = old_push;\n-#endif\n-\t\tentry = make_entry(priv, bus_mac);\n-\t\tif (entry == NULL)\n-\t\t\tgoto out;\n-\t\ttimer_delete(&entry->timer);\n-\t\tmemcpy(entry->atm_addr, ioc_data->atm_addr, ATM_ESA_LEN);\n-\t\tentry->recv_vcc = vcc;\n-\t\tentry->old_recv_push = old_push;\n-\t\thlist_add_head(&entry->next, &priv->mcast_fwds);\n-\t\tgoto out;\n-\t} else if (ioc_data->receive == 1) {\n-\t\t/*\n-\t\t * Vcc which we don't want to make default vcc,\n-\t\t * attach it anyway.\n-\t\t */\n-\t\tpr_debug(\"LEC_ARP:Attaching data direct, not default: %*phN\\n\",\n-\t\t\t ATM_ESA_LEN, ioc_data->atm_addr);\n-\t\tentry = make_entry(priv, bus_mac);\n-\t\tif (entry == NULL)\n-\t\t\tgoto out;\n-\t\tmemcpy(entry->atm_addr, ioc_data->atm_addr, ATM_ESA_LEN);\n-\t\teth_zero_addr(entry->mac_addr);\n-\t\tentry->recv_vcc = vcc;\n-\t\tentry->old_recv_push = old_push;\n-\t\tentry->status = ESI_UNKNOWN;\n-\t\tentry->timer.expires = jiffies + priv->vcc_timeout_period;\n-\t\tentry->timer.function = lec_arp_expire_vcc;\n-\t\thlist_add_head(&entry->next, &priv->lec_no_forward);\n-\t\tadd_timer(&entry->timer);\n-\t\tdump_arp_table(priv);\n-\t\tgoto out;\n-\t}\n-\tpr_debug(\"LEC_ARP:Attaching data direct, default: %*phN\\n\",\n-\t\t ATM_ESA_LEN, ioc_data->atm_addr);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry(entry,\n-\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (memcmp\n-\t\t\t (ioc_data->atm_addr, entry->atm_addr,\n-\t\t\t ATM_ESA_LEN) == 0) {\n-\t\t\t\tpr_debug(\"LEC_ARP: Attaching data direct\\n\");\n-\t\t\t\tpr_debug(\"Currently -> Vcc: %d, Rvcc:%d\\n\",\n-\t\t\t\t\t entry->vcc ? entry->vcc->vci : 0,\n-\t\t\t\t\t entry->recv_vcc ? entry->recv_vcc->\n-\t\t\t\t\t vci : 0);\n-\t\t\t\tfound_entry = 1;\n-\t\t\t\ttimer_delete(&entry->timer);\n-\t\t\t\tentry->vcc = vcc;\n-\t\t\t\tentry->old_push = old_push;\n-\t\t\t\tif (entry->status == ESI_VC_PENDING) {\n-\t\t\t\t\tif (priv->maximum_unknown_frame_count\n-\t\t\t\t\t == 0)\n-\t\t\t\t\t\tentry->status =\n-\t\t\t\t\t\t ESI_FORWARD_DIRECT;\n-\t\t\t\t\telse {\n-\t\t\t\t\t\tentry->timestamp = jiffies;\n-\t\t\t\t\t\tentry->status =\n-\t\t\t\t\t\t ESI_FLUSH_PENDING;\n-#if 0\n-\t\t\t\t\t\tsend_to_lecd(priv, l_flush_xmt,\n-\t\t\t\t\t\t\t NULL,\n-\t\t\t\t\t\t\t entry->atm_addr,\n-\t\t\t\t\t\t\t NULL);\n-#endif\n-\t\t\t\t\t}\n-\t\t\t\t} else {\n-\t\t\t\t\t/*\n-\t\t\t\t\t * They were forming a connection\n-\t\t\t\t\t * to us, and we to them. Our\n-\t\t\t\t\t * ATM address is numerically lower\n-\t\t\t\t\t * than theirs, so we make connection\n-\t\t\t\t\t * we formed into default VCC (8.1.11).\n-\t\t\t\t\t * Connection they made gets torn\n-\t\t\t\t\t * down. This might confuse some\n-\t\t\t\t\t * clients. Can be changed if\n-\t\t\t\t\t * someone reports trouble...\n-\t\t\t\t\t */\n-\t\t\t\t\t;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t}\n-\tif (found_entry) {\n-\t\tpr_debug(\"After vcc was added\\n\");\n-\t\tdump_arp_table(priv);\n-\t\tgoto out;\n-\t}\n-\t/*\n-\t * Not found, snatch address from first data packet that arrives\n-\t * from this vcc\n-\t */\n-\tentry = make_entry(priv, bus_mac);\n-\tif (!entry)\n-\t\tgoto out;\n-\tentry->vcc = vcc;\n-\tentry->old_push = old_push;\n-\tmemcpy(entry->atm_addr, ioc_data->atm_addr, ATM_ESA_LEN);\n-\teth_zero_addr(entry->mac_addr);\n-\tentry->status = ESI_UNKNOWN;\n-\thlist_add_head(&entry->next, &priv->lec_arp_empty_ones);\n-\tentry->timer.expires = jiffies + priv->vcc_timeout_period;\n-\tentry->timer.function = lec_arp_expire_vcc;\n-\tadd_timer(&entry->timer);\n-\tpr_debug(\"After vcc was added\\n\");\n-\tdump_arp_table(priv);\n-out:\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-}\n-\n-static void lec_flush_complete(struct lec_priv *priv, unsigned long tran_id)\n-{\n-\tunsigned long flags;\n-\tstruct lec_arp_table *entry;\n-\tint i;\n-\n-\tpr_debug(\"%lx\\n\", tran_id);\n-restart:\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry(entry,\n-\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (entry->flush_tran_id == tran_id &&\n-\t\t\t entry->status == ESI_FLUSH_PENDING) {\n-\t\t\t\tstruct sk_buff *skb;\n-\t\t\t\tstruct atm_vcc *vcc = entry->vcc;\n-\n-\t\t\t\tlec_arp_hold(entry);\n-\t\t\t\tspin_unlock_irqrestore(&priv->lec_arp_lock,\n-\t\t\t\t\t\t flags);\n-\t\t\t\twhile ((skb = skb_dequeue(&entry->tx_wait)))\n-\t\t\t\t\tlec_send(vcc, skb);\n-\t\t\t\tentry->last_used = jiffies;\n-\t\t\t\tentry->status = ESI_FORWARD_DIRECT;\n-\t\t\t\tlec_arp_put(entry);\n-\t\t\t\tpr_debug(\"LEC_ARP: Flushed\\n\");\n-\t\t\t\tgoto restart;\n-\t\t\t}\n-\t\t}\n-\t}\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\tdump_arp_table(priv);\n-}\n-\n-static void\n-lec_set_flush_tran_id(struct lec_priv *priv,\n-\t\t const unsigned char *atm_addr, unsigned long tran_id)\n-{\n-\tunsigned long flags;\n-\tstruct lec_arp_table *entry;\n-\tint i;\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++)\n-\t\thlist_for_each_entry(entry,\n-\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (!memcmp(atm_addr, entry->atm_addr, ATM_ESA_LEN)) {\n-\t\t\t\tentry->flush_tran_id = tran_id;\n-\t\t\t\tpr_debug(\"Set flush transaction id to %lx for %p\\n\",\n-\t\t\t\t\t tran_id, entry);\n-\t\t\t}\n-\t\t}\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-}\n-\n-static int lec_mcast_make(struct lec_priv *priv, struct atm_vcc *vcc)\n-{\n-\tunsigned long flags;\n-\tunsigned char mac_addr[] = {\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff\n-\t};\n-\tstruct lec_arp_table *to_add;\n-\tstruct lec_vcc_priv *vpriv;\n-\tint err = 0;\n-\n-\tvpriv = kmalloc_obj(struct lec_vcc_priv);\n-\tif (!vpriv)\n-\t\treturn -ENOMEM;\n-\tvpriv->xoff = 0;\n-\tvpriv->old_pop = vcc->pop;\n-\tvcc->user_back = vpriv;\n-\tvcc->pop = lec_pop;\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\tto_add = make_entry(priv, mac_addr);\n-\tif (!to_add) {\n-\t\tvcc->pop = vpriv->old_pop;\n-\t\tkfree(vpriv);\n-\t\terr = -ENOMEM;\n-\t\tgoto out;\n-\t}\n-\tmemcpy(to_add->atm_addr, vcc->remote.sas_addr.prv, ATM_ESA_LEN);\n-\tto_add->status = ESI_FORWARD_DIRECT;\n-\tto_add->flags |= LEC_PERMANENT_FLAG;\n-\tto_add->vcc = vcc;\n-\tto_add->old_push = vcc->push;\n-\tvcc->push = lec_push;\n-\tpriv->mcast_vcc = vcc;\n-\tlec_arp_add(priv, to_add);\n-out:\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\treturn err;\n-}\n-\n-static void lec_vcc_close(struct lec_priv *priv, struct atm_vcc *vcc)\n-{\n-\tunsigned long flags;\n-\tstruct hlist_node *next;\n-\tstruct lec_arp_table *entry;\n-\tint i;\n-\n-\tpr_debug(\"LEC_ARP: lec_vcc_close vpi:%d vci:%d\\n\", vcc->vpi, vcc->vci);\n-\tdump_arp_table(priv);\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\n-\tfor (i = 0; i < LEC_ARP_TABLE_SIZE; i++) {\n-\t\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t\t &priv->lec_arp_tables[i], next) {\n-\t\t\tif (vcc == entry->vcc) {\n-\t\t\t\tlec_arp_remove(priv, entry);\n-\t\t\t\tlec_arp_put(entry);\n-\t\t\t\tif (priv->mcast_vcc == vcc)\n-\t\t\t\t\tpriv->mcast_vcc = NULL;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t &priv->lec_arp_empty_ones, next) {\n-\t\tif (entry->vcc == vcc) {\n-\t\t\tlec_arp_clear_vccs(entry);\n-\t\t\ttimer_delete(&entry->timer);\n-\t\t\thlist_del(&entry->next);\n-\t\t\tlec_arp_put(entry);\n-\t\t}\n-\t}\n-\n-\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t &priv->lec_no_forward, next) {\n-\t\tif (entry->recv_vcc == vcc) {\n-\t\t\tlec_arp_clear_vccs(entry);\n-\t\t\ttimer_delete(&entry->timer);\n-\t\t\thlist_del(&entry->next);\n-\t\t\tlec_arp_put(entry);\n-\t\t}\n-\t}\n-\n-\thlist_for_each_entry_safe(entry, next, &priv->mcast_fwds, next) {\n-\t\tif (entry->recv_vcc == vcc) {\n-\t\t\tlec_arp_clear_vccs(entry);\n-\t\t\t/* No timer, LANEv2 7.1.20 and 2.3.5.3 */\n-\t\t\thlist_del(&entry->next);\n-\t\t\tlec_arp_put(entry);\n-\t\t}\n-\t}\n-\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-\tdump_arp_table(priv);\n-}\n-\n-static void\n-lec_arp_check_empties(struct lec_priv *priv,\n-\t\t struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tunsigned long flags;\n-\tstruct hlist_node *next;\n-\tstruct lec_arp_table *entry, *tmp;\n-\tstruct lecdatahdr_8023 *hdr = (struct lecdatahdr_8023 *)skb->data;\n-\tunsigned char *src = hdr->h_source;\n-\n-\tspin_lock_irqsave(&priv->lec_arp_lock, flags);\n-\thlist_for_each_entry_safe(entry, next,\n-\t\t\t\t &priv->lec_arp_empty_ones, next) {\n-\t\tif (vcc == entry->vcc) {\n-\t\t\ttimer_delete(&entry->timer);\n-\t\t\tether_addr_copy(entry->mac_addr, src);\n-\t\t\tentry->status = ESI_FORWARD_DIRECT;\n-\t\t\tentry->last_used = jiffies;\n-\t\t\t/* We might have got an entry */\n-\t\t\ttmp = lec_arp_find(priv, src);\n-\t\t\tif (tmp) {\n-\t\t\t\tlec_arp_remove(priv, tmp);\n-\t\t\t\tlec_arp_put(tmp);\n-\t\t\t}\n-\t\t\thlist_del(&entry->next);\n-\t\t\tlec_arp_add(priv, entry);\n-\t\t\tgoto out;\n-\t\t}\n-\t}\n-\tpr_debug(\"LEC_ARP: Arp_check_empties: entry not found!\\n\");\n-out:\n-\tspin_unlock_irqrestore(&priv->lec_arp_lock, flags);\n-}\n-\n-MODULE_DESCRIPTION(\"ATM LAN Emulation (LANE) support\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/net/atm/mpc.c b/net/atm/mpc.c\ndeleted file mode 100644\nindex ce8e9780373b..000000000000\n--- a/net/atm/mpc.c\n+++ /dev/null\n@@ -1,1538 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-#define pr_fmt(fmt) KBUILD_MODNAME \":%s: \" fmt, __func__\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-/* We are an ethernet device */\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include /* for ip_fast_csum() */\n-#include \n-#include \n-#include \n-\n-/* And atm device */\n-#include \n-#include \n-#include \n-/* Modular too */\n-#include \n-\n-#include \"lec.h\"\n-#include \"mpc.h\"\n-#include \"resources.h\"\n-\n-/*\n- * mpc.c: Implementation of MPOA client kernel part\n- */\n-\n-#if 0\n-#define dprintk(format, args...) \\\n-\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __func__, ##args)\n-#define dprintk_cont(format, args...) printk(KERN_CONT format, ##args)\n-#else\n-#define dprintk(format, args...)\t\t\t\t\t\\\n-\tdo { if (0)\t\t\t\t\t\t\t\\\n-\t\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __func__, ##args);\\\n-\t} while (0)\n-#define dprintk_cont(format, args...)\t\t\t\\\n-\tdo { if (0) printk(KERN_CONT format, ##args); } while (0)\n-#endif\n-\n-#if 0\n-#define ddprintk(format, args...) \\\n-\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __func__, ##args)\n-#define ddprintk_cont(format, args...) printk(KERN_CONT format, ##args)\n-#else\n-#define ddprintk(format, args...)\t\t\t\t\t\\\n-\tdo { if (0)\t\t\t\t\t\t\t\\\n-\t\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __func__, ##args);\\\n-\t} while (0)\n-#define ddprintk_cont(format, args...)\t\t\t\\\n-\tdo { if (0) printk(KERN_CONT format, ##args); } while (0)\n-#endif\n-\n-/* mpc_daemon -> kernel */\n-static void MPOA_trigger_rcvd(struct k_message *msg, struct mpoa_client *mpc);\n-static void MPOA_res_reply_rcvd(struct k_message *msg, struct mpoa_client *mpc);\n-static void ingress_purge_rcvd(struct k_message *msg, struct mpoa_client *mpc);\n-static void egress_purge_rcvd(struct k_message *msg, struct mpoa_client *mpc);\n-static void mps_death(struct k_message *msg, struct mpoa_client *mpc);\n-static void clean_up(struct k_message *msg, struct mpoa_client *mpc,\n-\t\t int action);\n-static void MPOA_cache_impos_rcvd(struct k_message *msg,\n-\t\t\t\t struct mpoa_client *mpc);\n-static void set_mpc_ctrl_addr_rcvd(struct k_message *mesg,\n-\t\t\t\t struct mpoa_client *mpc);\n-static void set_mps_mac_addr_rcvd(struct k_message *mesg,\n-\t\t\t\t struct mpoa_client *mpc);\n-\n-static const uint8_t *copy_macs(struct mpoa_client *mpc,\n-\t\t\t\tconst uint8_t *router_mac,\n-\t\t\t\tconst uint8_t *tlvs, uint8_t mps_macs,\n-\t\t\t\tuint8_t device_type);\n-static void purge_egress_shortcut(struct atm_vcc *vcc, eg_cache_entry *entry);\n-\n-static void send_set_mps_ctrl_addr(const char *addr, struct mpoa_client *mpc);\n-static void mpoad_close(struct atm_vcc *vcc);\n-static int msg_from_mpoad(struct atm_vcc *vcc, struct sk_buff *skb);\n-\n-static void mpc_push(struct atm_vcc *vcc, struct sk_buff *skb);\n-static netdev_tx_t mpc_send_packet(struct sk_buff *skb,\n-\t\t\t\t struct net_device *dev);\n-static int mpoa_event_listener(struct notifier_block *mpoa_notifier,\n-\t\t\t unsigned long event, void *dev);\n-static void mpc_timer_refresh(void);\n-static void mpc_cache_check(struct timer_list *unused);\n-\n-static struct llc_snap_hdr llc_snap_mpoa_ctrl = {\n-\t0xaa, 0xaa, 0x03,\n-\t{0x00, 0x00, 0x5e},\n-\t{0x00, 0x03} /* For MPOA control PDUs */\n-};\n-static struct llc_snap_hdr llc_snap_mpoa_data = {\n-\t0xaa, 0xaa, 0x03,\n-\t{0x00, 0x00, 0x00},\n-\t{0x08, 0x00} /* This is for IP PDUs only */\n-};\n-static struct llc_snap_hdr llc_snap_mpoa_data_tagged = {\n-\t0xaa, 0xaa, 0x03,\n-\t{0x00, 0x00, 0x00},\n-\t{0x88, 0x4c} /* This is for tagged data PDUs */\n-};\n-\n-static struct notifier_block mpoa_notifier = {\n-\tmpoa_event_listener,\n-\tNULL,\n-\t0\n-};\n-\n-struct mpoa_client *mpcs = NULL; /* FIXME */\n-static struct atm_mpoa_qos *qos_head = NULL;\n-static DEFINE_TIMER(mpc_timer, mpc_cache_check);\n-\n-\n-static struct mpoa_client *find_mpc_by_itfnum(int itf)\n-{\n-\tstruct mpoa_client *mpc;\n-\n-\tmpc = mpcs; /* our global linked list */\n-\twhile (mpc != NULL) {\n-\t\tif (mpc->dev_num == itf)\n-\t\t\treturn mpc;\n-\t\tmpc = mpc->next;\n-\t}\n-\n-\treturn NULL; /* not found */\n-}\n-\n-static struct mpoa_client *find_mpc_by_vcc(struct atm_vcc *vcc)\n-{\n-\tstruct mpoa_client *mpc;\n-\n-\tmpc = mpcs; /* our global linked list */\n-\twhile (mpc != NULL) {\n-\t\tif (mpc->mpoad_vcc == vcc)\n-\t\t\treturn mpc;\n-\t\tmpc = mpc->next;\n-\t}\n-\n-\treturn NULL; /* not found */\n-}\n-\n-static struct mpoa_client *find_mpc_by_lec(struct net_device *dev)\n-{\n-\tstruct mpoa_client *mpc;\n-\n-\tmpc = mpcs; /* our global linked list */\n-\twhile (mpc != NULL) {\n-\t\tif (mpc->dev == dev)\n-\t\t\treturn mpc;\n-\t\tmpc = mpc->next;\n-\t}\n-\n-\treturn NULL; /* not found */\n-}\n-\n-/*\n- * Functions for managing QoS list\n- */\n-\n-/*\n- * Overwrites the old entry or makes a new one.\n- */\n-struct atm_mpoa_qos *atm_mpoa_add_qos(__be32 dst_ip, struct atm_qos *qos)\n-{\n-\tstruct atm_mpoa_qos *entry;\n-\n-\tentry = atm_mpoa_search_qos(dst_ip);\n-\tif (entry != NULL) {\n-\t\tentry->qos = *qos;\n-\t\treturn entry;\n-\t}\n-\n-\tentry = kmalloc_obj(struct atm_mpoa_qos);\n-\tif (entry == NULL) {\n-\t\tpr_info(\"mpoa: out of memory\\n\");\n-\t\treturn entry;\n-\t}\n-\n-\tentry->ipaddr = dst_ip;\n-\tentry->qos = *qos;\n-\n-\tentry->next = qos_head;\n-\tqos_head = entry;\n-\n-\treturn entry;\n-}\n-\n-struct atm_mpoa_qos *atm_mpoa_search_qos(__be32 dst_ip)\n-{\n-\tstruct atm_mpoa_qos *qos;\n-\n-\tqos = qos_head;\n-\twhile (qos) {\n-\t\tif (qos->ipaddr == dst_ip)\n-\t\t\tbreak;\n-\t\tqos = qos->next;\n-\t}\n-\n-\treturn qos;\n-}\n-\n-/*\n- * Returns 0 for failure\n- */\n-int atm_mpoa_delete_qos(struct atm_mpoa_qos *entry)\n-{\n-\tstruct atm_mpoa_qos *curr;\n-\n-\tif (entry == NULL)\n-\t\treturn 0;\n-\tif (entry == qos_head) {\n-\t\tqos_head = qos_head->next;\n-\t\tkfree(entry);\n-\t\treturn 1;\n-\t}\n-\n-\tcurr = qos_head;\n-\twhile (curr != NULL) {\n-\t\tif (curr->next == entry) {\n-\t\t\tcurr->next = entry->next;\n-\t\t\tkfree(entry);\n-\t\t\treturn 1;\n-\t\t}\n-\t\tcurr = curr->next;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* this is buggered - we need locking for qos_head */\n-void atm_mpoa_disp_qos(struct seq_file *m)\n-{\n-\tstruct atm_mpoa_qos *qos;\n-\n-\tqos = qos_head;\n-\tseq_printf(m, \"QoS entries for shortcuts:\\n\");\n-\tseq_printf(m, \"IP address\\n TX:max_pcr pcr min_pcr max_cdv max_sdu\\n RX:max_pcr pcr min_pcr max_cdv max_sdu\\n\");\n-\n-\twhile (qos != NULL) {\n-\t\tseq_printf(m, \"%pI4\\n %-7d %-7d %-7d %-7d %-7d\\n %-7d %-7d %-7d %-7d %-7d\\n\",\n-\t\t\t &qos->ipaddr,\n-\t\t\t qos->qos.txtp.max_pcr,\n-\t\t\t qos->qos.txtp.pcr,\n-\t\t\t qos->qos.txtp.min_pcr,\n-\t\t\t qos->qos.txtp.max_cdv,\n-\t\t\t qos->qos.txtp.max_sdu,\n-\t\t\t qos->qos.rxtp.max_pcr,\n-\t\t\t qos->qos.rxtp.pcr,\n-\t\t\t qos->qos.rxtp.min_pcr,\n-\t\t\t qos->qos.rxtp.max_cdv,\n-\t\t\t qos->qos.rxtp.max_sdu);\n-\t\tqos = qos->next;\n-\t}\n-}\n-\n-static struct net_device *find_lec_by_itfnum(int itf)\n-{\n-\tstruct net_device *dev;\n-\tchar name[IFNAMSIZ];\n-\n-\tsprintf(name, \"lec%d\", itf);\n-\tdev = dev_get_by_name(&init_net, name);\n-\n-\treturn dev;\n-}\n-\n-static struct mpoa_client *alloc_mpc(void)\n-{\n-\tstruct mpoa_client *mpc;\n-\n-\tmpc = kzalloc_obj(struct mpoa_client);\n-\tif (mpc == NULL)\n-\t\treturn NULL;\n-\trwlock_init(&mpc->ingress_lock);\n-\trwlock_init(&mpc->egress_lock);\n-\tmpc->next = mpcs;\n-\tatm_mpoa_init_cache(mpc);\n-\n-\tmpc->parameters.mpc_p1 = MPC_P1;\n-\tmpc->parameters.mpc_p2 = MPC_P2;\n-\tmemset(mpc->parameters.mpc_p3, 0, sizeof(mpc->parameters.mpc_p3));\n-\tmpc->parameters.mpc_p4 = MPC_P4;\n-\tmpc->parameters.mpc_p5 = MPC_P5;\n-\tmpc->parameters.mpc_p6 = MPC_P6;\n-\n-\tmpcs = mpc;\n-\n-\treturn mpc;\n-}\n-\n-/*\n- *\n- * start_mpc() puts the MPC on line. All the packets destined\n- * to the lec underneath us are now being monitored and\n- * shortcuts will be established.\n- *\n- */\n-static void start_mpc(struct mpoa_client *mpc, struct net_device *dev)\n-{\n-\n-\tdprintk(\"(%s)\\n\", mpc->dev->name);\n-\tif (!dev->netdev_ops)\n-\t\tpr_info(\"(%s) not starting\\n\", dev->name);\n-\telse {\n-\t\tmpc->old_ops = dev->netdev_ops;\n-\t\tmpc->new_ops = *mpc->old_ops;\n-\t\tmpc->new_ops.ndo_start_xmit = mpc_send_packet;\n-\t\tdev->netdev_ops = &mpc->new_ops;\n-\t}\n-}\n-\n-static void stop_mpc(struct mpoa_client *mpc)\n-{\n-\tstruct net_device *dev = mpc->dev;\n-\tdprintk(\"(%s)\", mpc->dev->name);\n-\n-\t/* Lets not nullify lec device's dev->hard_start_xmit */\n-\tif (dev->netdev_ops != &mpc->new_ops) {\n-\t\tdprintk_cont(\" mpc already stopped, not fatal\\n\");\n-\t\treturn;\n-\t}\n-\tdprintk_cont(\"\\n\");\n-\n-\tdev->netdev_ops = mpc->old_ops;\n-\tmpc->old_ops = NULL;\n-\n-\t/* close_shortcuts(mpc); ??? FIXME */\n-}\n-\n-static const char *mpoa_device_type_string(char type) __attribute__ ((unused));\n-\n-static const char *mpoa_device_type_string(char type)\n-{\n-\tswitch (type) {\n-\tcase NON_MPOA:\n-\t\treturn \"non-MPOA device\";\n-\tcase MPS:\n-\t\treturn \"MPS\";\n-\tcase MPC:\n-\t\treturn \"MPC\";\n-\tcase MPS_AND_MPC:\n-\t\treturn \"both MPS and MPC\";\n-\t}\n-\n-\treturn \"unspecified (non-MPOA) device\";\n-}\n-\n-/*\n- * lec device calls this via its netdev_priv(dev)->lane2_ops\n- * ->associate_indicator() when it sees a TLV in LE_ARP packet.\n- * We fill in the pointer above when we see a LANE2 lec initializing\n- * See LANE2 spec 3.1.5\n- *\n- * Quite a big and ugly function but when you look at it\n- * all it does is to try to locate and parse MPOA Device\n- * Type TLV.\n- * We give our lec a pointer to this function and when the\n- * lec sees a TLV it uses the pointer to call this function.\n- *\n- */\n-static void lane2_assoc_ind(struct net_device *dev, const u8 *mac_addr,\n-\t\t\t const u8 *tlvs, u32 sizeoftlvs)\n-{\n-\tuint32_t type;\n-\tuint8_t length, mpoa_device_type, number_of_mps_macs;\n-\tconst uint8_t *end_of_tlvs;\n-\tstruct mpoa_client *mpc;\n-\n-\tmpoa_device_type = number_of_mps_macs = 0; /* silence gcc */\n-\tdprintk(\"(%s) received TLV(s), \", dev->name);\n-\tdprintk(\"total length of all TLVs %d\\n\", sizeoftlvs);\n-\tmpc = find_mpc_by_lec(dev); /* Sampo-Fix: moved here from below */\n-\tif (mpc == NULL) {\n-\t\tpr_info(\"(%s) no mpc\\n\", dev->name);\n-\t\treturn;\n-\t}\n-\tend_of_tlvs = tlvs + sizeoftlvs;\n-\twhile (end_of_tlvs - tlvs >= 5) {\n-\t\ttype = ((tlvs[0] << 24) | (tlvs[1] << 16) |\n-\t\t\t(tlvs[2] << 8) | tlvs[3]);\n-\t\tlength = tlvs[4];\n-\t\ttlvs += 5;\n-\t\tdprintk(\" type 0x%x length %02x\\n\", type, length);\n-\t\tif (tlvs + length > end_of_tlvs) {\n-\t\t\tpr_info(\"TLV value extends past its buffer, aborting parse\\n\");\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tif (type == 0) {\n-\t\t\tpr_info(\"mpoa: (%s) TLV type was 0, returning\\n\",\n-\t\t\t\tdev->name);\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tif (type != TLV_MPOA_DEVICE_TYPE) {\n-\t\t\ttlvs += length;\n-\t\t\tcontinue; /* skip other TLVs */\n-\t\t}\n-\t\tmpoa_device_type = *tlvs++;\n-\t\tnumber_of_mps_macs = *tlvs++;\n-\t\tdprintk(\"(%s) MPOA device type '%s', \",\n-\t\t\tdev->name, mpoa_device_type_string(mpoa_device_type));\n-\t\tif (mpoa_device_type == MPS_AND_MPC &&\n-\t\t length < (42 + number_of_mps_macs*ETH_ALEN)) { /* :) */\n-\t\t\tpr_info(\"(%s) short MPOA Device Type TLV\\n\",\n-\t\t\t\tdev->name);\n-\t\t\tcontinue;\n-\t\t}\n-\t\tif ((mpoa_device_type == MPS || mpoa_device_type == MPC) &&\n-\t\t length < 22 + number_of_mps_macs*ETH_ALEN) {\n-\t\t\tpr_info(\"(%s) short MPOA Device Type TLV\\n\", dev->name);\n-\t\t\tcontinue;\n-\t\t}\n-\t\tif (mpoa_device_type != MPS &&\n-\t\t mpoa_device_type != MPS_AND_MPC) {\n-\t\t\tdprintk(\"ignoring non-MPS device \");\n-\t\t\tif (mpoa_device_type == MPC)\n-\t\t\t\ttlvs += 20;\n-\t\t\tcontinue; /* we are only interested in MPSs */\n-\t\t}\n-\t\tif (number_of_mps_macs == 0 &&\n-\t\t mpoa_device_type == MPS_AND_MPC) {\n-\t\t\tpr_info(\"(%s) MPS_AND_MPC has zero MACs\\n\", dev->name);\n-\t\t\tcontinue; /* someone should read the spec */\n-\t\t}\n-\t\tdprintk_cont(\"this MPS has %d MAC addresses\\n\",\n-\t\t\t number_of_mps_macs);\n-\n-\t\t/*\n-\t\t * ok, now we can go and tell our daemon\n-\t\t * the control address of MPS\n-\t\t */\n-\t\tsend_set_mps_ctrl_addr(tlvs, mpc);\n-\n-\t\ttlvs = copy_macs(mpc, mac_addr, tlvs,\n-\t\t\t\t number_of_mps_macs, mpoa_device_type);\n-\t\tif (tlvs == NULL)\n-\t\t\treturn;\n-\t}\n-\tif (end_of_tlvs - tlvs != 0)\n-\t\tpr_info(\"(%s) ignoring %zd bytes of trailing TLV garbage\\n\",\n-\t\t\tdev->name, end_of_tlvs - tlvs);\n-}\n-\n-/*\n- * Store at least advertizing router's MAC address\n- * plus the possible MAC address(es) to mpc->mps_macs.\n- * For a freshly allocated MPOA client mpc->mps_macs == 0.\n- */\n-static const uint8_t *copy_macs(struct mpoa_client *mpc,\n-\t\t\t\tconst uint8_t *router_mac,\n-\t\t\t\tconst uint8_t *tlvs, uint8_t mps_macs,\n-\t\t\t\tuint8_t device_type)\n-{\n-\tint num_macs;\n-\tnum_macs = (mps_macs > 1) ? mps_macs : 1;\n-\n-\tif (mpc->number_of_mps_macs != num_macs) { /* need to reallocate? */\n-\t\tif (mpc->number_of_mps_macs != 0)\n-\t\t\tkfree(mpc->mps_macs);\n-\t\tmpc->number_of_mps_macs = 0;\n-\t\tmpc->mps_macs = kmalloc_array(ETH_ALEN, num_macs, GFP_KERNEL);\n-\t\tif (mpc->mps_macs == NULL) {\n-\t\t\tpr_info(\"(%s) out of mem\\n\", mpc->dev->name);\n-\t\t\treturn NULL;\n-\t\t}\n-\t}\n-\tether_addr_copy(mpc->mps_macs, router_mac);\n-\ttlvs += 20; if (device_type == MPS_AND_MPC) tlvs += 20;\n-\tif (mps_macs > 0)\n-\t\tmemcpy(mpc->mps_macs, tlvs, mps_macs*ETH_ALEN);\n-\ttlvs += mps_macs*ETH_ALEN;\n-\tmpc->number_of_mps_macs = num_macs;\n-\n-\treturn tlvs;\n-}\n-\n-static int send_via_shortcut(struct sk_buff *skb, struct mpoa_client *mpc)\n-{\n-\tin_cache_entry *entry;\n-\tstruct iphdr *iph;\n-\tchar *buff;\n-\t__be32 ipaddr = 0;\n-\n-\tstatic struct {\n-\t\tstruct llc_snap_hdr hdr;\n-\t\t__be32 tag;\n-\t} tagged_llc_snap_hdr = {\n-\t\t{0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}, {0x88, 0x4c}},\n-\t\t0\n-\t};\n-\n-\tbuff = skb->data + mpc->dev->hard_header_len;\n-\tiph = (struct iphdr *)buff;\n-\tipaddr = iph->daddr;\n-\n-\tddprintk(\"(%s) ipaddr 0x%x\\n\",\n-\t\t mpc->dev->name, ipaddr);\n-\n-\tentry = mpc->in_ops->get(ipaddr, mpc);\n-\tif (entry == NULL) {\n-\t\tentry = mpc->in_ops->add_entry(ipaddr, mpc);\n-\t\tif (entry != NULL)\n-\t\t\tmpc->in_ops->put(entry);\n-\t\treturn 1;\n-\t}\n-\t/* threshold not exceeded or VCC not ready */\n-\tif (mpc->in_ops->cache_hit(entry, mpc) != OPEN) {\n-\t\tddprintk(\"(%s) cache_hit: returns != OPEN\\n\",\n-\t\t\t mpc->dev->name);\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn 1;\n-\t}\n-\n-\tddprintk(\"(%s) using shortcut\\n\",\n-\t\t mpc->dev->name);\n-\t/* MPOA spec A.1.4, MPOA client must decrement IP ttl at least by one */\n-\tif (iph->ttl <= 1) {\n-\t\tddprintk(\"(%s) IP ttl = %u, using LANE\\n\",\n-\t\t\t mpc->dev->name, iph->ttl);\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn 1;\n-\t}\n-\tiph->ttl--;\n-\tiph->check = 0;\n-\tiph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);\n-\n-\tif (entry->ctrl_info.tag != 0) {\n-\t\tddprintk(\"(%s) adding tag 0x%x\\n\",\n-\t\t\t mpc->dev->name, entry->ctrl_info.tag);\n-\t\ttagged_llc_snap_hdr.tag = entry->ctrl_info.tag;\n-\t\tskb_pull(skb, ETH_HLEN);\t/* get rid of Eth header */\n-\t\tskb_push(skb, sizeof(tagged_llc_snap_hdr));\n-\t\t\t\t\t\t/* add LLC/SNAP header */\n-\t\tskb_copy_to_linear_data(skb, &tagged_llc_snap_hdr,\n-\t\t\t\t\tsizeof(tagged_llc_snap_hdr));\n-\t} else {\n-\t\tskb_pull(skb, ETH_HLEN);\t/* get rid of Eth header */\n-\t\tskb_push(skb, sizeof(struct llc_snap_hdr));\n-\t\t\t\t\t\t/* add LLC/SNAP header + tag */\n-\t\tskb_copy_to_linear_data(skb, &llc_snap_mpoa_data,\n-\t\t\t\t\tsizeof(struct llc_snap_hdr));\n-\t}\n-\n-\tatm_account_tx(entry->shortcut, skb);\n-\tentry->shortcut->send(entry->shortcut, skb);\n-\tentry->packets_fwded++;\n-\tmpc->in_ops->put(entry);\n-\n-\treturn 0;\n-}\n-\n-/*\n- * Probably needs some error checks and locking, not sure...\n- */\n-static netdev_tx_t mpc_send_packet(struct sk_buff *skb,\n-\t\t\t\t\t struct net_device *dev)\n-{\n-\tstruct mpoa_client *mpc;\n-\tstruct ethhdr *eth;\n-\tint i = 0;\n-\n-\tmpc = find_mpc_by_lec(dev); /* this should NEVER fail */\n-\tif (mpc == NULL) {\n-\t\tpr_info(\"(%s) no MPC found\\n\", dev->name);\n-\t\tgoto non_ip;\n-\t}\n-\n-\teth = (struct ethhdr *)skb->data;\n-\tif (eth->h_proto != htons(ETH_P_IP))\n-\t\tgoto non_ip; /* Multi-Protocol Over ATM :-) */\n-\n-\t/* Weed out funny packets (e.g., AF_PACKET or raw). */\n-\tif (skb->len < ETH_HLEN + sizeof(struct iphdr))\n-\t\tgoto non_ip;\n-\tskb_set_network_header(skb, ETH_HLEN);\n-\tif (skb->len < ETH_HLEN + ip_hdr(skb)->ihl * 4 || ip_hdr(skb)->ihl < 5)\n-\t\tgoto non_ip;\n-\n-\twhile (i < mpc->number_of_mps_macs) {\n-\t\tif (ether_addr_equal(eth->h_dest, mpc->mps_macs + i * ETH_ALEN))\n-\t\t\tif (send_via_shortcut(skb, mpc) == 0) /* try shortcut */\n-\t\t\t\treturn NETDEV_TX_OK;\n-\t\ti++;\n-\t}\n-\n-non_ip:\n-\treturn __netdev_start_xmit(mpc->old_ops, skb, dev, false);\n-}\n-\n-static int atm_mpoa_vcc_attach(struct atm_vcc *vcc, void __user *arg)\n-{\n-\tint bytes_left;\n-\tstruct mpoa_client *mpc;\n-\tstruct atmmpc_ioc ioc_data;\n-\tin_cache_entry *in_entry;\n-\t__be32 ipaddr;\n-\n-\tbytes_left = copy_from_user(&ioc_data, arg, sizeof(struct atmmpc_ioc));\n-\tif (bytes_left != 0) {\n-\t\tpr_info(\"mpoa:Short read (missed %d bytes) from userland\\n\",\n-\t\t\tbytes_left);\n-\t\treturn -EFAULT;\n-\t}\n-\tipaddr = ioc_data.ipaddr;\n-\tif (ioc_data.dev_num < 0 || ioc_data.dev_num >= MAX_LEC_ITF)\n-\t\treturn -EINVAL;\n-\n-\tmpc = find_mpc_by_itfnum(ioc_data.dev_num);\n-\tif (mpc == NULL)\n-\t\treturn -EINVAL;\n-\n-\tif (ioc_data.type == MPC_SOCKET_INGRESS) {\n-\t\tin_entry = mpc->in_ops->get(ipaddr, mpc);\n-\t\tif (in_entry == NULL ||\n-\t\t in_entry->entry_state < INGRESS_RESOLVED) {\n-\t\t\tpr_info(\"(%s) did not find RESOLVED entry from ingress cache\\n\",\n-\t\t\t\tmpc->dev->name);\n-\t\t\tif (in_entry != NULL)\n-\t\t\t\tmpc->in_ops->put(in_entry);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tpr_info(\"(%s) attaching ingress SVC, entry = %pI4\\n\",\n-\t\t\tmpc->dev->name, &in_entry->ctrl_info.in_dst_ip);\n-\t\tin_entry->shortcut = vcc;\n-\t\tmpc->in_ops->put(in_entry);\n-\t} else {\n-\t\tpr_info(\"(%s) attaching egress SVC\\n\", mpc->dev->name);\n-\t}\n-\n-\tvcc->proto_data = mpc->dev;\n-\tvcc->push = mpc_push;\n-\n-\treturn 0;\n-}\n-\n-/*\n- *\n- */\n-static void mpc_vcc_close(struct atm_vcc *vcc, struct net_device *dev)\n-{\n-\tstruct mpoa_client *mpc;\n-\tin_cache_entry *in_entry;\n-\teg_cache_entry *eg_entry;\n-\n-\tmpc = find_mpc_by_lec(dev);\n-\tif (mpc == NULL) {\n-\t\tpr_info(\"(%s) close for unknown MPC\\n\", dev->name);\n-\t\treturn;\n-\t}\n-\n-\tdprintk(\"(%s)\\n\", dev->name);\n-\tin_entry = mpc->in_ops->get_by_vcc(vcc, mpc);\n-\tif (in_entry) {\n-\t\tdprintk(\"(%s) ingress SVC closed ip = %pI4\\n\",\n-\t\t\tmpc->dev->name, &in_entry->ctrl_info.in_dst_ip);\n-\t\tin_entry->shortcut = NULL;\n-\t\tmpc->in_ops->put(in_entry);\n-\t}\n-\teg_entry = mpc->eg_ops->get_by_vcc(vcc, mpc);\n-\tif (eg_entry) {\n-\t\tdprintk(\"(%s) egress SVC closed\\n\", mpc->dev->name);\n-\t\teg_entry->shortcut = NULL;\n-\t\tmpc->eg_ops->put(eg_entry);\n-\t}\n-\n-\tif (in_entry == NULL && eg_entry == NULL)\n-\t\tdprintk(\"(%s) unused vcc closed\\n\", dev->name);\n-}\n-\n-static void mpc_push(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\tstruct net_device *dev = (struct net_device *)vcc->proto_data;\n-\tstruct sk_buff *new_skb;\n-\teg_cache_entry *eg;\n-\tstruct mpoa_client *mpc;\n-\t__be32 tag;\n-\tchar *tmp;\n-\n-\tddprintk(\"(%s)\\n\", dev->name);\n-\tif (skb == NULL) {\n-\t\tdprintk(\"(%s) null skb, closing VCC\\n\", dev->name);\n-\t\tmpc_vcc_close(vcc, dev);\n-\t\treturn;\n-\t}\n-\n-\tskb->dev = dev;\n-\tif (memcmp(skb->data, &llc_snap_mpoa_ctrl,\n-\t\t sizeof(struct llc_snap_hdr)) == 0) {\n-\t\tstruct sock *sk = sk_atm(vcc);\n-\n-\t\tdprintk(\"(%s) control packet arrived\\n\", dev->name);\n-\t\t/* Pass control packets to daemon */\n-\t\tskb_queue_tail(&sk->sk_receive_queue, skb);\n-\t\tsk->sk_data_ready(sk);\n-\t\treturn;\n-\t}\n-\n-\t/* data coming over the shortcut */\n-\tatm_return(vcc, skb->truesize);\n-\n-\tmpc = find_mpc_by_lec(dev);\n-\tif (mpc == NULL) {\n-\t\tpr_info(\"(%s) unknown MPC\\n\", dev->name);\n-\t\treturn;\n-\t}\n-\n-\tif (memcmp(skb->data, &llc_snap_mpoa_data_tagged,\n-\t\t sizeof(struct llc_snap_hdr)) == 0) { /* MPOA tagged data */\n-\t\tddprintk(\"(%s) tagged data packet arrived\\n\", dev->name);\n-\n-\t} else if (memcmp(skb->data, &llc_snap_mpoa_data,\n-\t\t\t sizeof(struct llc_snap_hdr)) == 0) { /* MPOA data */\n-\t\tpr_info(\"(%s) Unsupported non-tagged data packet arrived. Purging\\n\",\n-\t\t\tdev->name);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn;\n-\t} else {\n-\t\tpr_info(\"(%s) garbage arrived, purging\\n\", dev->name);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn;\n-\t}\n-\n-\ttmp = skb->data + sizeof(struct llc_snap_hdr);\n-\ttag = *(__be32 *)tmp;\n-\n-\teg = mpc->eg_ops->get_by_tag(tag, mpc);\n-\tif (eg == NULL) {\n-\t\tpr_info(\"mpoa: (%s) Didn't find egress cache entry, tag = %u\\n\",\n-\t\t\tdev->name, tag);\n-\t\tpurge_egress_shortcut(vcc, NULL);\n-\t\tdev_kfree_skb_any(skb);\n-\t\treturn;\n-\t}\n-\n-\t/*\n-\t * See if ingress MPC is using shortcut we opened as a return channel.\n-\t * This means we have a bi-directional vcc opened by us.\n-\t */\n-\tif (eg->shortcut == NULL) {\n-\t\teg->shortcut = vcc;\n-\t\tpr_info(\"(%s) egress SVC in use\\n\", dev->name);\n-\t}\n-\n-\tskb_pull(skb, sizeof(struct llc_snap_hdr) + sizeof(tag));\n-\t\t\t\t\t/* get rid of LLC/SNAP header */\n-\tnew_skb = skb_realloc_headroom(skb, eg->ctrl_info.DH_length);\n-\t\t\t\t\t/* LLC/SNAP is shorter than MAC header :( */\n-\tdev_kfree_skb_any(skb);\n-\tif (new_skb == NULL) {\n-\t\tmpc->eg_ops->put(eg);\n-\t\treturn;\n-\t}\n-\tskb_push(new_skb, eg->ctrl_info.DH_length); /* add MAC header */\n-\tskb_copy_to_linear_data(new_skb, eg->ctrl_info.DLL_header,\n-\t\t\t\teg->ctrl_info.DH_length);\n-\tnew_skb->protocol = eth_type_trans(new_skb, dev);\n-\tskb_reset_network_header(new_skb);\n-\n-\teg->latest_ip_addr = ip_hdr(new_skb)->saddr;\n-\teg->packets_rcvd++;\n-\tmpc->eg_ops->put(eg);\n-\n-\tmemset(ATM_SKB(new_skb), 0, sizeof(struct atm_skb_data));\n-\tnetif_rx(new_skb);\n-}\n-\n-static const struct atmdev_ops mpc_ops = { /* only send is required */\n-\t.close\t= mpoad_close,\n-\t.send\t= msg_from_mpoad\n-};\n-\n-static struct atm_dev mpc_dev = {\n-\t.ops\t= &mpc_ops,\n-\t.type\t= \"mpc\",\n-\t.number\t= 42,\n-\t.lock\t= __SPIN_LOCK_UNLOCKED(mpc_dev.lock)\n-\t/* members not explicitly initialised will be 0 */\n-};\n-\n-static int atm_mpoa_mpoad_attach(struct atm_vcc *vcc, int arg)\n-{\n-\tstruct mpoa_client *mpc;\n-\tstruct lec_priv *priv;\n-\tint err;\n-\n-\tif (mpcs == NULL) {\n-\t\tmpc_timer_refresh();\n-\n-\t\t/* This lets us now how our LECs are doing */\n-\t\terr = register_netdevice_notifier(&mpoa_notifier);\n-\t\tif (err < 0) {\n-\t\t\ttimer_delete(&mpc_timer);\n-\t\t\treturn err;\n-\t\t}\n-\t}\n-\n-\tmpc = find_mpc_by_itfnum(arg);\n-\tif (mpc == NULL) {\n-\t\tdprintk(\"allocating new mpc for itf %d\\n\", arg);\n-\t\tmpc = alloc_mpc();\n-\t\tif (mpc == NULL)\n-\t\t\treturn -ENOMEM;\n-\t\tmpc->dev_num = arg;\n-\t\tmpc->dev = find_lec_by_itfnum(arg);\n-\t\t\t\t\t/* NULL if there was no lec */\n-\t}\n-\tif (mpc->mpoad_vcc) {\n-\t\tpr_info(\"mpoad is already present for itf %d\\n\", arg);\n-\t\treturn -EADDRINUSE;\n-\t}\n-\n-\tif (mpc->dev) { /* check if the lec is LANE2 capable */\n-\t\tpriv = netdev_priv(mpc->dev);\n-\t\tif (priv->lane_version < 2) {\n-\t\t\tdev_put(mpc->dev);\n-\t\t\tmpc->dev = NULL;\n-\t\t} else\n-\t\t\tpriv->lane2_ops->associate_indicator = lane2_assoc_ind;\n-\t}\n-\n-\tmpc->mpoad_vcc = vcc;\n-\tvcc->dev = &mpc_dev;\n-\tvcc_insert_socket(sk_atm(vcc));\n-\tset_bit(ATM_VF_META, &vcc->flags);\n-\tset_bit(ATM_VF_READY, &vcc->flags);\n-\n-\tif (mpc->dev) {\n-\t\tchar empty[ATM_ESA_LEN];\n-\t\tmemset(empty, 0, ATM_ESA_LEN);\n-\n-\t\tstart_mpc(mpc, mpc->dev);\n-\t\t/* set address if mpcd e.g. gets killed and restarted.\n-\t\t * If we do not do it now we have to wait for the next LE_ARP\n-\t\t */\n-\t\tif (memcmp(mpc->mps_ctrl_addr, empty, ATM_ESA_LEN) != 0)\n-\t\t\tsend_set_mps_ctrl_addr(mpc->mps_ctrl_addr, mpc);\n-\t}\n-\n-\t__module_get(THIS_MODULE);\n-\treturn arg;\n-}\n-\n-static void send_set_mps_ctrl_addr(const char *addr, struct mpoa_client *mpc)\n-{\n-\tstruct k_message mesg;\n-\n-\tmemcpy(mpc->mps_ctrl_addr, addr, ATM_ESA_LEN);\n-\n-\tmesg.type = SET_MPS_CTRL_ADDR;\n-\tmemcpy(mesg.MPS_ctrl, addr, ATM_ESA_LEN);\n-\tmsg_to_mpoad(&mesg, mpc);\n-}\n-\n-static void mpoad_close(struct atm_vcc *vcc)\n-{\n-\tstruct mpoa_client *mpc;\n-\tstruct sk_buff *skb;\n-\n-\tmpc = find_mpc_by_vcc(vcc);\n-\tif (mpc == NULL) {\n-\t\tpr_info(\"did not find MPC\\n\");\n-\t\treturn;\n-\t}\n-\tif (!mpc->mpoad_vcc) {\n-\t\tpr_info(\"close for non-present mpoad\\n\");\n-\t\treturn;\n-\t}\n-\n-\tmpc->mpoad_vcc = NULL;\n-\tif (mpc->dev) {\n-\t\tstruct lec_priv *priv = netdev_priv(mpc->dev);\n-\t\tpriv->lane2_ops->associate_indicator = NULL;\n-\t\tstop_mpc(mpc);\n-\t\tdev_put(mpc->dev);\n-\t}\n-\n-\tmpc->in_ops->destroy_cache(mpc);\n-\tmpc->eg_ops->destroy_cache(mpc);\n-\n-\twhile ((skb = skb_dequeue(&sk_atm(vcc)->sk_receive_queue))) {\n-\t\tatm_return(vcc, skb->truesize);\n-\t\tkfree_skb(skb);\n-\t}\n-\n-\tpr_info(\"(%s) going down\\n\",\n-\t\t(mpc->dev) ? mpc->dev->name : \"\");\n-\tmodule_put(THIS_MODULE);\n-}\n-\n-/*\n- *\n- */\n-static int msg_from_mpoad(struct atm_vcc *vcc, struct sk_buff *skb)\n-{\n-\n-\tstruct mpoa_client *mpc = find_mpc_by_vcc(vcc);\n-\tstruct k_message *mesg = (struct k_message *)skb->data;\n-\tWARN_ON(refcount_sub_and_test(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc));\n-\n-\tif (mpc == NULL) {\n-\t\tpr_info(\"no mpc found\\n\");\n-\t\treturn 0;\n-\t}\n-\tdprintk(\"(%s)\", mpc->dev ? mpc->dev->name : \"\");\n-\tswitch (mesg->type) {\n-\tcase MPOA_RES_REPLY_RCVD:\n-\t\tdprintk_cont(\"mpoa_res_reply_rcvd\\n\");\n-\t\tMPOA_res_reply_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase MPOA_TRIGGER_RCVD:\n-\t\tdprintk_cont(\"mpoa_trigger_rcvd\\n\");\n-\t\tMPOA_trigger_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase INGRESS_PURGE_RCVD:\n-\t\tdprintk_cont(\"nhrp_purge_rcvd\\n\");\n-\t\tingress_purge_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase EGRESS_PURGE_RCVD:\n-\t\tdprintk_cont(\"egress_purge_reply_rcvd\\n\");\n-\t\tegress_purge_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase MPS_DEATH:\n-\t\tdprintk_cont(\"mps_death\\n\");\n-\t\tmps_death(mesg, mpc);\n-\t\tbreak;\n-\tcase CACHE_IMPOS_RCVD:\n-\t\tdprintk_cont(\"cache_impos_rcvd\\n\");\n-\t\tMPOA_cache_impos_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase SET_MPC_CTRL_ADDR:\n-\t\tdprintk_cont(\"set_mpc_ctrl_addr\\n\");\n-\t\tset_mpc_ctrl_addr_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase SET_MPS_MAC_ADDR:\n-\t\tdprintk_cont(\"set_mps_mac_addr\\n\");\n-\t\tset_mps_mac_addr_rcvd(mesg, mpc);\n-\t\tbreak;\n-\tcase CLEAN_UP_AND_EXIT:\n-\t\tdprintk_cont(\"clean_up_and_exit\\n\");\n-\t\tclean_up(mesg, mpc, DIE);\n-\t\tbreak;\n-\tcase RELOAD:\n-\t\tdprintk_cont(\"reload\\n\");\n-\t\tclean_up(mesg, mpc, RELOAD);\n-\t\tbreak;\n-\tcase SET_MPC_PARAMS:\n-\t\tdprintk_cont(\"set_mpc_params\\n\");\n-\t\tmpc->parameters = mesg->content.params;\n-\t\tbreak;\n-\tdefault:\n-\t\tdprintk_cont(\"unknown message %d\\n\", mesg->type);\n-\t\tbreak;\n-\t}\n-\tkfree_skb(skb);\n-\n-\treturn 0;\n-}\n-\n-/* Remember that this function may not do things that sleep */\n-int msg_to_mpoad(struct k_message *mesg, struct mpoa_client *mpc)\n-{\n-\tstruct sk_buff *skb;\n-\tstruct sock *sk;\n-\n-\tif (mpc == NULL || !mpc->mpoad_vcc) {\n-\t\tpr_info(\"mesg %d to a non-existent mpoad\\n\", mesg->type);\n-\t\treturn -ENXIO;\n-\t}\n-\n-\tskb = alloc_skb(sizeof(struct k_message), GFP_ATOMIC);\n-\tif (skb == NULL)\n-\t\treturn -ENOMEM;\n-\tskb_put(skb, sizeof(struct k_message));\n-\tskb_copy_to_linear_data(skb, mesg, sizeof(*mesg));\n-\tatm_force_charge(mpc->mpoad_vcc, skb->truesize);\n-\n-\tsk = sk_atm(mpc->mpoad_vcc);\n-\tskb_queue_tail(&sk->sk_receive_queue, skb);\n-\tsk->sk_data_ready(sk);\n-\n-\treturn 0;\n-}\n-\n-static int mpoa_event_listener(struct notifier_block *mpoa_notifier,\n-\t\t\t unsigned long event, void *ptr)\n-{\n-\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n-\tstruct mpoa_client *mpc;\n-\tstruct lec_priv *priv;\n-\n-\tif (!net_eq(dev_net(dev), &init_net))\n-\t\treturn NOTIFY_DONE;\n-\n-\tif (strncmp(dev->name, \"lec\", 3))\n-\t\treturn NOTIFY_DONE; /* we are only interested in lec:s */\n-\n-\tswitch (event) {\n-\tcase NETDEV_REGISTER: /* a new lec device was allocated */\n-\t\tpriv = netdev_priv(dev);\n-\t\tif (priv->lane_version < 2)\n-\t\t\tbreak;\n-\t\tpriv->lane2_ops->associate_indicator = lane2_assoc_ind;\n-\t\tmpc = find_mpc_by_itfnum(priv->itfnum);\n-\t\tif (mpc == NULL) {\n-\t\t\tdprintk(\"allocating new mpc for %s\\n\", dev->name);\n-\t\t\tmpc = alloc_mpc();\n-\t\t\tif (mpc == NULL) {\n-\t\t\t\tpr_info(\"no new mpc\");\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t\tmpc->dev_num = priv->itfnum;\n-\t\tmpc->dev = dev;\n-\t\tdev_hold(dev);\n-\t\tdprintk(\"(%s) was initialized\\n\", dev->name);\n-\t\tbreak;\n-\tcase NETDEV_UNREGISTER:\n-\t\t/* the lec device was deallocated */\n-\t\tmpc = find_mpc_by_lec(dev);\n-\t\tif (mpc == NULL)\n-\t\t\tbreak;\n-\t\tdprintk(\"device (%s) was deallocated\\n\", dev->name);\n-\t\tstop_mpc(mpc);\n-\t\tdev_put(mpc->dev);\n-\t\tmpc->dev = NULL;\n-\t\tbreak;\n-\tcase NETDEV_UP:\n-\t\t/* the dev was ifconfig'ed up */\n-\t\tmpc = find_mpc_by_lec(dev);\n-\t\tif (mpc == NULL)\n-\t\t\tbreak;\n-\t\tif (mpc->mpoad_vcc != NULL)\n-\t\t\tstart_mpc(mpc, dev);\n-\t\tbreak;\n-\tcase NETDEV_DOWN:\n-\t\t/* the dev was ifconfig'ed down */\n-\t\t/* this means that the flow of packets from the\n-\t\t * upper layer stops\n-\t\t */\n-\t\tmpc = find_mpc_by_lec(dev);\n-\t\tif (mpc == NULL)\n-\t\t\tbreak;\n-\t\tif (mpc->mpoad_vcc != NULL)\n-\t\t\tstop_mpc(mpc);\n-\t\tbreak;\n-\tcase NETDEV_REBOOT:\n-\tcase NETDEV_CHANGE:\n-\tcase NETDEV_CHANGEMTU:\n-\tcase NETDEV_CHANGEADDR:\n-\tcase NETDEV_GOING_DOWN:\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n-\treturn NOTIFY_DONE;\n-}\n-\n-/*\n- * Functions which are called after a message is received from mpcd.\n- * Msg is reused on purpose.\n- */\n-\n-\n-static void MPOA_trigger_rcvd(struct k_message *msg, struct mpoa_client *mpc)\n-{\n-\t__be32 dst_ip = msg->content.in_info.in_dst_ip;\n-\tin_cache_entry *entry;\n-\n-\tentry = mpc->in_ops->get(dst_ip, mpc);\n-\tif (entry == NULL) {\n-\t\tentry = mpc->in_ops->add_entry(dst_ip, mpc);\n-\t\tentry->entry_state = INGRESS_RESOLVING;\n-\t\tmsg->type = SND_MPOA_RES_RQST;\n-\t\tmsg->content.in_info = entry->ctrl_info;\n-\t\tmsg_to_mpoad(msg, mpc);\n-\t\tentry->reply_wait = ktime_get_seconds();\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn;\n-\t}\n-\n-\tif (entry->entry_state == INGRESS_INVALID) {\n-\t\tentry->entry_state = INGRESS_RESOLVING;\n-\t\tmsg->type = SND_MPOA_RES_RQST;\n-\t\tmsg->content.in_info = entry->ctrl_info;\n-\t\tmsg_to_mpoad(msg, mpc);\n-\t\tentry->reply_wait = ktime_get_seconds();\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn;\n-\t}\n-\n-\tpr_info(\"(%s) entry already in resolving state\\n\",\n-\t\t(mpc->dev) ? mpc->dev->name : \"\");\n-\tmpc->in_ops->put(entry);\n-}\n-\n-/*\n- * Things get complicated because we have to check if there's an egress\n- * shortcut with suitable traffic parameters we could use.\n- */\n-static void check_qos_and_open_shortcut(struct k_message *msg,\n-\t\t\t\t\tstruct mpoa_client *client,\n-\t\t\t\t\tin_cache_entry *entry)\n-{\n-\t__be32 dst_ip = msg->content.in_info.in_dst_ip;\n-\tstruct atm_mpoa_qos *qos = atm_mpoa_search_qos(dst_ip);\n-\teg_cache_entry *eg_entry = client->eg_ops->get_by_src_ip(dst_ip, client);\n-\n-\tif (eg_entry && eg_entry->shortcut) {\n-\t\tif (eg_entry->shortcut->qos.txtp.traffic_class &\n-\t\t msg->qos.txtp.traffic_class &\n-\t\t (qos ? qos->qos.txtp.traffic_class : ATM_UBR | ATM_CBR)) {\n-\t\t\tif (eg_entry->shortcut->qos.txtp.traffic_class == ATM_UBR)\n-\t\t\t\tentry->shortcut = eg_entry->shortcut;\n-\t\t\telse if (eg_entry->shortcut->qos.txtp.max_pcr > 0)\n-\t\t\t\tentry->shortcut = eg_entry->shortcut;\n-\t\t}\n-\t\tif (entry->shortcut) {\n-\t\t\tdprintk(\"(%s) using egress SVC to reach %pI4\\n\",\n-\t\t\t\tclient->dev->name, &dst_ip);\n-\t\t\tclient->eg_ops->put(eg_entry);\n-\t\t\treturn;\n-\t\t}\n-\t}\n-\tif (eg_entry != NULL)\n-\t\tclient->eg_ops->put(eg_entry);\n-\n-\t/* No luck in the egress cache we must open an ingress SVC */\n-\tmsg->type = OPEN_INGRESS_SVC;\n-\tif (qos &&\n-\t (qos->qos.txtp.traffic_class == msg->qos.txtp.traffic_class)) {\n-\t\tmsg->qos = qos->qos;\n-\t\tpr_info(\"(%s) trying to get a CBR shortcut\\n\",\n-\t\t\tclient->dev->name);\n-\t} else\n-\t\tmemset(&msg->qos, 0, sizeof(struct atm_qos));\n-\tmsg_to_mpoad(msg, client);\n-}\n-\n-static void MPOA_res_reply_rcvd(struct k_message *msg, struct mpoa_client *mpc)\n-{\n-\t__be32 dst_ip = msg->content.in_info.in_dst_ip;\n-\tin_cache_entry *entry = mpc->in_ops->get(dst_ip, mpc);\n-\n-\tdprintk(\"(%s) ip %pI4\\n\",\n-\t\tmpc->dev->name, &dst_ip);\n-\tddprintk(\"(%s) entry = %p\",\n-\t\t mpc->dev->name, entry);\n-\tif (entry == NULL) {\n-\t\tpr_info(\"(%s) ARGH, received res. reply for an entry that doesn't exist.\\n\",\n-\t\t\tmpc->dev->name);\n-\t\treturn;\n-\t}\n-\tddprintk_cont(\" entry_state = %d \", entry->entry_state);\n-\n-\tif (entry->entry_state == INGRESS_RESOLVED) {\n-\t\tpr_info(\"(%s) RESOLVED entry!\\n\", mpc->dev->name);\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn;\n-\t}\n-\n-\tentry->ctrl_info = msg->content.in_info;\n-\tentry->time = ktime_get_seconds();\n-\t/* Used in refreshing func from now on */\n-\tentry->reply_wait = ktime_get_seconds();\n-\tentry->refresh_time = 0;\n-\tddprintk_cont(\"entry->shortcut = %p\\n\", entry->shortcut);\n-\n-\tif (entry->entry_state == INGRESS_RESOLVING &&\n-\t entry->shortcut != NULL) {\n-\t\tentry->entry_state = INGRESS_RESOLVED;\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn; /* Shortcut already open... */\n-\t}\n-\n-\tif (entry->shortcut != NULL) {\n-\t\tpr_info(\"(%s) entry->shortcut != NULL, impossible!\\n\",\n-\t\t\tmpc->dev->name);\n-\t\tmpc->in_ops->put(entry);\n-\t\treturn;\n-\t}\n-\n-\tcheck_qos_and_open_shortcut(msg, mpc, entry);\n-\tentry->entry_state = INGRESS_RESOLVED;\n-\tmpc->in_ops->put(entry);\n-\n-\treturn;\n-\n-}\n-\n-static void ingress_purge_rcvd(struct k_message *msg, struct mpoa_client *mpc)\n-{\n-\t__be32 dst_ip = msg->content.in_info.in_dst_ip;\n-\t__be32 mask = msg->ip_mask;\n-\tin_cache_entry *entry = mpc->in_ops->get_with_mask(dst_ip, mpc, mask);\n-\n-\tif (entry == NULL) {\n-\t\tpr_info(\"(%s) purge for a non-existing entry, ip = %pI4\\n\",\n-\t\t\tmpc->dev->name, &dst_ip);\n-\t\treturn;\n-\t}\n-\n-\tdo {\n-\t\tdprintk(\"(%s) removing an ingress entry, ip = %pI4\\n\",\n-\t\t\tmpc->dev->name, &dst_ip);\n-\t\twrite_lock_bh(&mpc->ingress_lock);\n-\t\tmpc->in_ops->remove_entry(entry, mpc);\n-\t\twrite_unlock_bh(&mpc->ingress_lock);\n-\t\tmpc->in_ops->put(entry);\n-\t\tentry = mpc->in_ops->get_with_mask(dst_ip, mpc, mask);\n-\t} while (entry != NULL);\n-}\n-\n-static void egress_purge_rcvd(struct k_message *msg, struct mpoa_client *mpc)\n-{\n-\t__be32 cache_id = msg->content.eg_info.cache_id;\n-\teg_cache_entry *entry = mpc->eg_ops->get_by_cache_id(cache_id, mpc);\n-\n-\tif (entry == NULL) {\n-\t\tdprintk(\"(%s) purge for a non-existing entry\\n\",\n-\t\t\tmpc->dev->name);\n-\t\treturn;\n-\t}\n-\n-\twrite_lock_irq(&mpc->egress_lock);\n-\tmpc->eg_ops->remove_entry(entry, mpc);\n-\twrite_unlock_irq(&mpc->egress_lock);\n-\n-\tmpc->eg_ops->put(entry);\n-}\n-\n-static void purge_egress_shortcut(struct atm_vcc *vcc, eg_cache_entry *entry)\n-{\n-\tstruct sock *sk;\n-\tstruct k_message *purge_msg;\n-\tstruct sk_buff *skb;\n-\n-\tdprintk(\"entering\\n\");\n-\tif (vcc == NULL) {\n-\t\tpr_info(\"vcc == NULL\\n\");\n-\t\treturn;\n-\t}\n-\n-\tskb = alloc_skb(sizeof(struct k_message), GFP_ATOMIC);\n-\tif (skb == NULL) {\n-\t\tpr_info(\"out of memory\\n\");\n-\t\treturn;\n-\t}\n-\n-\tskb_put(skb, sizeof(struct k_message));\n-\tmemset(skb->data, 0, sizeof(struct k_message));\n-\tpurge_msg = (struct k_message *)skb->data;\n-\tpurge_msg->type = DATA_PLANE_PURGE;\n-\tif (entry != NULL)\n-\t\tpurge_msg->content.eg_info = entry->ctrl_info;\n-\n-\tatm_force_charge(vcc, skb->truesize);\n-\n-\tsk = sk_atm(vcc);\n-\tskb_queue_tail(&sk->sk_receive_queue, skb);\n-\tsk->sk_data_ready(sk);\n-\tdprintk(\"exiting\\n\");\n-}\n-\n-/*\n- * Our MPS died. Tell our daemon to send NHRP data plane purge to each\n- * of the egress shortcuts we have.\n- */\n-static void mps_death(struct k_message *msg, struct mpoa_client *mpc)\n-{\n-\teg_cache_entry *entry;\n-\n-\tdprintk(\"(%s)\\n\", mpc->dev->name);\n-\n-\tif (memcmp(msg->MPS_ctrl, mpc->mps_ctrl_addr, ATM_ESA_LEN)) {\n-\t\tpr_info(\"(%s) wrong MPS\\n\", mpc->dev->name);\n-\t\treturn;\n-\t}\n-\n-\t/* FIXME: This knows too much of the cache structure */\n-\tread_lock_irq(&mpc->egress_lock);\n-\tentry = mpc->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tpurge_egress_shortcut(entry->shortcut, entry);\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_irq(&mpc->egress_lock);\n-\n-\tmpc->in_ops->destroy_cache(mpc);\n-\tmpc->eg_ops->destroy_cache(mpc);\n-}\n-\n-static void MPOA_cache_impos_rcvd(struct k_message *msg,\n-\t\t\t\t struct mpoa_client *mpc)\n-{\n-\tuint16_t holding_time;\n-\teg_cache_entry *entry = mpc->eg_ops->get_by_cache_id(msg->content.eg_info.cache_id, mpc);\n-\n-\tholding_time = msg->content.eg_info.holding_time;\n-\tdprintk(\"(%s) entry = %p, holding_time = %u\\n\",\n-\t\tmpc->dev->name, entry, holding_time);\n-\tif (entry == NULL && !holding_time)\n-\t\treturn;\n-\tif (entry == NULL && holding_time) {\n-\t\tentry = mpc->eg_ops->add_entry(msg, mpc);\n-\t\tmpc->eg_ops->put(entry);\n-\t\treturn;\n-\t}\n-\tif (holding_time) {\n-\t\tmpc->eg_ops->update(entry, holding_time);\n-\t\treturn;\n-\t}\n-\n-\twrite_lock_irq(&mpc->egress_lock);\n-\tmpc->eg_ops->remove_entry(entry, mpc);\n-\twrite_unlock_irq(&mpc->egress_lock);\n-\n-\tmpc->eg_ops->put(entry);\n-}\n-\n-static void set_mpc_ctrl_addr_rcvd(struct k_message *mesg,\n-\t\t\t\t struct mpoa_client *mpc)\n-{\n-\tstruct lec_priv *priv;\n-\tint i, retval ;\n-\n-\tuint8_t tlv[4 + 1 + 1 + 1 + ATM_ESA_LEN];\n-\n-\ttlv[0] = 00; tlv[1] = 0xa0; tlv[2] = 0x3e; tlv[3] = 0x2a; /* type */\n-\ttlv[4] = 1 + 1 + ATM_ESA_LEN; /* length */\n-\ttlv[5] = 0x02; /* MPOA client */\n-\ttlv[6] = 0x00; /* number of MPS MAC addresses */\n-\n-\tmemcpy(&tlv[7], mesg->MPS_ctrl, ATM_ESA_LEN); /* MPC ctrl ATM addr */\n-\tmemcpy(mpc->our_ctrl_addr, mesg->MPS_ctrl, ATM_ESA_LEN);\n-\n-\tdprintk(\"(%s) setting MPC ctrl ATM address to\",\n-\t\tmpc->dev ? mpc->dev->name : \"\");\n-\tfor (i = 7; i < sizeof(tlv); i++)\n-\t\tdprintk_cont(\" %02x\", tlv[i]);\n-\tdprintk_cont(\"\\n\");\n-\n-\tif (mpc->dev) {\n-\t\tpriv = netdev_priv(mpc->dev);\n-\t\tretval = priv->lane2_ops->associate_req(mpc->dev,\n-\t\t\t\t\t\t\tmpc->dev->dev_addr,\n-\t\t\t\t\t\t\ttlv, sizeof(tlv));\n-\t\tif (retval == 0)\n-\t\t\tpr_info(\"(%s) MPOA device type TLV association failed\\n\",\n-\t\t\t\tmpc->dev->name);\n-\t\tretval = priv->lane2_ops->resolve(mpc->dev, NULL, 1, NULL, NULL);\n-\t\tif (retval < 0)\n-\t\t\tpr_info(\"(%s) targetless LE_ARP request failed\\n\",\n-\t\t\t\tmpc->dev->name);\n-\t}\n-}\n-\n-static void set_mps_mac_addr_rcvd(struct k_message *msg,\n-\t\t\t\t struct mpoa_client *client)\n-{\n-\n-\tif (client->number_of_mps_macs)\n-\t\tkfree(client->mps_macs);\n-\tclient->number_of_mps_macs = 0;\n-\tclient->mps_macs = kmemdup(msg->MPS_ctrl, ETH_ALEN, GFP_KERNEL);\n-\tif (client->mps_macs == NULL) {\n-\t\tpr_info(\"out of memory\\n\");\n-\t\treturn;\n-\t}\n-\tclient->number_of_mps_macs = 1;\n-}\n-\n-/*\n- * purge egress cache and tell daemon to 'action' (DIE, RELOAD)\n- */\n-static void clean_up(struct k_message *msg, struct mpoa_client *mpc, int action)\n-{\n-\n-\teg_cache_entry *entry;\n-\tmsg->type = SND_EGRESS_PURGE;\n-\n-\n-\t/* FIXME: This knows too much of the cache structure */\n-\tread_lock_irq(&mpc->egress_lock);\n-\tentry = mpc->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tmsg->content.eg_info = entry->ctrl_info;\n-\t\tdprintk(\"cache_id %u\\n\", entry->ctrl_info.cache_id);\n-\t\tmsg_to_mpoad(msg, mpc);\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_irq(&mpc->egress_lock);\n-\n-\tmsg->type = action;\n-\tmsg_to_mpoad(msg, mpc);\n-}\n-\n-static unsigned long checking_time;\n-\n-static void mpc_timer_refresh(void)\n-{\n-\tmpc_timer.expires = jiffies + (MPC_P2 * HZ);\n-\tchecking_time = mpc_timer.expires;\n-\tadd_timer(&mpc_timer);\n-}\n-\n-static void mpc_cache_check(struct timer_list *unused)\n-{\n-\tstruct mpoa_client *mpc = mpcs;\n-\tstatic unsigned long previous_resolving_check_time;\n-\tstatic unsigned long previous_refresh_time;\n-\n-\twhile (mpc != NULL) {\n-\t\tmpc->in_ops->clear_count(mpc);\n-\t\tmpc->eg_ops->clear_expired(mpc);\n-\t\tif (checking_time - previous_resolving_check_time >\n-\t\t mpc->parameters.mpc_p4 * HZ) {\n-\t\t\tmpc->in_ops->check_resolving(mpc);\n-\t\t\tprevious_resolving_check_time = checking_time;\n-\t\t}\n-\t\tif (checking_time - previous_refresh_time >\n-\t\t mpc->parameters.mpc_p5 * HZ) {\n-\t\t\tmpc->in_ops->refresh(mpc);\n-\t\t\tprevious_refresh_time = checking_time;\n-\t\t}\n-\t\tmpc = mpc->next;\n-\t}\n-\tmpc_timer_refresh();\n-}\n-\n-static int atm_mpoa_ioctl(struct socket *sock, unsigned int cmd,\n-\t\t\t unsigned long arg)\n-{\n-\tint err = 0;\n-\tstruct atm_vcc *vcc = ATM_SD(sock);\n-\n-\tif (cmd != ATMMPC_CTRL && cmd != ATMMPC_DATA)\n-\t\treturn -ENOIOCTLCMD;\n-\n-\tif (!capable(CAP_NET_ADMIN))\n-\t\treturn -EPERM;\n-\n-\tswitch (cmd) {\n-\tcase ATMMPC_CTRL:\n-\t\terr = atm_mpoa_mpoad_attach(vcc, (int)arg);\n-\t\tif (err >= 0)\n-\t\t\tsock->state = SS_CONNECTED;\n-\t\tbreak;\n-\tcase ATMMPC_DATA:\n-\t\terr = atm_mpoa_vcc_attach(vcc, (void __user *)arg);\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\treturn err;\n-}\n-\n-static struct atm_ioctl atm_ioctl_ops = {\n-\t.owner\t= THIS_MODULE,\n-\t.ioctl\t= atm_mpoa_ioctl,\n-};\n-\n-static __init int atm_mpoa_init(void)\n-{\n-\tregister_atm_ioctl(&atm_ioctl_ops);\n-\n-\tif (mpc_proc_init() != 0)\n-\t\tpr_info(\"failed to initialize /proc/mpoa\\n\");\n-\n-\tpr_info(\"mpc.c: initialized\\n\");\n-\n-\treturn 0;\n-}\n-\n-static void __exit atm_mpoa_cleanup(void)\n-{\n-\tstruct mpoa_client *mpc, *tmp;\n-\tstruct atm_mpoa_qos *qos, *nextqos;\n-\tstruct lec_priv *priv;\n-\n-\tmpc_proc_clean();\n-\n-\ttimer_delete_sync(&mpc_timer);\n-\tunregister_netdevice_notifier(&mpoa_notifier);\n-\tderegister_atm_ioctl(&atm_ioctl_ops);\n-\n-\tmpc = mpcs;\n-\tmpcs = NULL;\n-\twhile (mpc != NULL) {\n-\t\ttmp = mpc->next;\n-\t\tif (mpc->dev != NULL) {\n-\t\t\tstop_mpc(mpc);\n-\t\t\tpriv = netdev_priv(mpc->dev);\n-\t\t\tif (priv->lane2_ops != NULL)\n-\t\t\t\tpriv->lane2_ops->associate_indicator = NULL;\n-\t\t}\n-\t\tddprintk(\"about to clear caches\\n\");\n-\t\tmpc->in_ops->destroy_cache(mpc);\n-\t\tmpc->eg_ops->destroy_cache(mpc);\n-\t\tddprintk(\"caches cleared\\n\");\n-\t\tkfree(mpc->mps_macs);\n-\t\tmemset(mpc, 0, sizeof(struct mpoa_client));\n-\t\tddprintk(\"about to kfree %p\\n\", mpc);\n-\t\tkfree(mpc);\n-\t\tddprintk(\"next mpc is at %p\\n\", tmp);\n-\t\tmpc = tmp;\n-\t}\n-\n-\tqos = qos_head;\n-\tqos_head = NULL;\n-\twhile (qos != NULL) {\n-\t\tnextqos = qos->next;\n-\t\tdprintk(\"freeing qos entry %p\\n\", qos);\n-\t\tkfree(qos);\n-\t\tqos = nextqos;\n-\t}\n-}\n-\n-module_init(atm_mpoa_init);\n-module_exit(atm_mpoa_cleanup);\n-\n-MODULE_DESCRIPTION(\"Multi-Protocol Over ATM (MPOA) driver\");\n-MODULE_LICENSE(\"GPL\");\ndiff --git a/net/atm/mpoa_caches.c b/net/atm/mpoa_caches.c\ndeleted file mode 100644\nindex c8d4e6f2e831..000000000000\n--- a/net/atm/mpoa_caches.c\n+++ /dev/null\n@@ -1,565 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-#include \n-#include \n-#include \n-#include \n-\n-#include \"mpoa_caches.h\"\n-#include \"mpc.h\"\n-\n-/*\n- * mpoa_caches.c: Implementation of ingress and egress cache\n- * handling functions\n- */\n-\n-#if 0\n-#define dprintk(format, args...)\t\t\t\t\t\\\n-\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args) /* debug */\n-#else\n-#define dprintk(format, args...)\t\t\t\t\t\\\n-\tdo { if (0)\t\t\t\t\t\t\t\\\n-\t\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args);\\\n-\t} while (0)\n-#endif\n-\n-#if 0\n-#define ddprintk(format, args...)\t\t\t\t\t\\\n-\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args) /* debug */\n-#else\n-#define ddprintk(format, args...)\t\t\t\t\t\\\n-\tdo { if (0)\t\t\t\t\t\t\t\\\n-\t\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args);\\\n-\t} while (0)\n-#endif\n-\n-static in_cache_entry *in_cache_get(__be32 dst_ip,\n-\t\t\t\t struct mpoa_client *client)\n-{\n-\tin_cache_entry *entry;\n-\n-\tread_lock_bh(&client->ingress_lock);\n-\tentry = client->in_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->ctrl_info.in_dst_ip == dst_ip) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_bh(&client->ingress_lock);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_bh(&client->ingress_lock);\n-\n-\treturn NULL;\n-}\n-\n-static in_cache_entry *in_cache_get_with_mask(__be32 dst_ip,\n-\t\t\t\t\t struct mpoa_client *client,\n-\t\t\t\t\t __be32 mask)\n-{\n-\tin_cache_entry *entry;\n-\n-\tread_lock_bh(&client->ingress_lock);\n-\tentry = client->in_cache;\n-\twhile (entry != NULL) {\n-\t\tif ((entry->ctrl_info.in_dst_ip & mask) == (dst_ip & mask)) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_bh(&client->ingress_lock);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_bh(&client->ingress_lock);\n-\n-\treturn NULL;\n-\n-}\n-\n-static in_cache_entry *in_cache_get_by_vcc(struct atm_vcc *vcc,\n-\t\t\t\t\t struct mpoa_client *client)\n-{\n-\tin_cache_entry *entry;\n-\n-\tread_lock_bh(&client->ingress_lock);\n-\tentry = client->in_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->shortcut == vcc) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_bh(&client->ingress_lock);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_bh(&client->ingress_lock);\n-\n-\treturn NULL;\n-}\n-\n-static in_cache_entry *in_cache_add_entry(__be32 dst_ip,\n-\t\t\t\t\t struct mpoa_client *client)\n-{\n-\tin_cache_entry *entry = kzalloc_obj(in_cache_entry);\n-\n-\tif (entry == NULL) {\n-\t\tpr_info(\"mpoa: mpoa_caches.c: new_in_cache_entry: out of memory\\n\");\n-\t\treturn NULL;\n-\t}\n-\n-\tdprintk(\"adding an ingress entry, ip = %pI4\\n\", &dst_ip);\n-\n-\trefcount_set(&entry->use, 1);\n-\tdprintk(\"new_in_cache_entry: about to lock\\n\");\n-\twrite_lock_bh(&client->ingress_lock);\n-\tentry->next = client->in_cache;\n-\tentry->prev = NULL;\n-\tif (client->in_cache != NULL)\n-\t\tclient->in_cache->prev = entry;\n-\tclient->in_cache = entry;\n-\n-\tmemcpy(entry->MPS_ctrl_ATM_addr, client->mps_ctrl_addr, ATM_ESA_LEN);\n-\tentry->ctrl_info.in_dst_ip = dst_ip;\n-\tentry->time = ktime_get_seconds();\n-\tentry->retry_time = client->parameters.mpc_p4;\n-\tentry->count = 1;\n-\tentry->entry_state = INGRESS_INVALID;\n-\tentry->ctrl_info.holding_time = HOLDING_TIME_DEFAULT;\n-\trefcount_inc(&entry->use);\n-\n-\twrite_unlock_bh(&client->ingress_lock);\n-\tdprintk(\"new_in_cache_entry: unlocked\\n\");\n-\n-\treturn entry;\n-}\n-\n-static int cache_hit(in_cache_entry *entry, struct mpoa_client *mpc)\n-{\n-\tstruct atm_mpoa_qos *qos;\n-\tstruct k_message msg;\n-\n-\tentry->count++;\n-\tif (entry->entry_state == INGRESS_RESOLVED && entry->shortcut != NULL)\n-\t\treturn OPEN;\n-\n-\tif (entry->entry_state == INGRESS_REFRESHING) {\n-\t\tif (entry->count > mpc->parameters.mpc_p1) {\n-\t\t\tmsg.type = SND_MPOA_RES_RQST;\n-\t\t\tmsg.content.in_info = entry->ctrl_info;\n-\t\t\tmemcpy(msg.MPS_ctrl, mpc->mps_ctrl_addr, ATM_ESA_LEN);\n-\t\t\tqos = atm_mpoa_search_qos(entry->ctrl_info.in_dst_ip);\n-\t\t\tif (qos != NULL)\n-\t\t\t\tmsg.qos = qos->qos;\n-\t\t\tmsg_to_mpoad(&msg, mpc);\n-\t\t\tentry->reply_wait = ktime_get_seconds();\n-\t\t\tentry->entry_state = INGRESS_RESOLVING;\n-\t\t}\n-\t\tif (entry->shortcut != NULL)\n-\t\t\treturn OPEN;\n-\t\treturn CLOSED;\n-\t}\n-\n-\tif (entry->entry_state == INGRESS_RESOLVING && entry->shortcut != NULL)\n-\t\treturn OPEN;\n-\n-\tif (entry->count > mpc->parameters.mpc_p1 &&\n-\t entry->entry_state == INGRESS_INVALID) {\n-\t\tdprintk(\"(%s) threshold exceeded for ip %pI4, sending MPOA res req\\n\",\n-\t\t\tmpc->dev->name, &entry->ctrl_info.in_dst_ip);\n-\t\tentry->entry_state = INGRESS_RESOLVING;\n-\t\tmsg.type = SND_MPOA_RES_RQST;\n-\t\tmemcpy(msg.MPS_ctrl, mpc->mps_ctrl_addr, ATM_ESA_LEN);\n-\t\tmsg.content.in_info = entry->ctrl_info;\n-\t\tqos = atm_mpoa_search_qos(entry->ctrl_info.in_dst_ip);\n-\t\tif (qos != NULL)\n-\t\t\tmsg.qos = qos->qos;\n-\t\tmsg_to_mpoad(&msg, mpc);\n-\t\tentry->reply_wait = ktime_get_seconds();\n-\t}\n-\n-\treturn CLOSED;\n-}\n-\n-static void in_cache_put(in_cache_entry *entry)\n-{\n-\tif (refcount_dec_and_test(&entry->use)) {\n-\t\tkfree_sensitive(entry);\n-\t}\n-}\n-\n-/*\n- * This should be called with write lock on\n- */\n-static void in_cache_remove_entry(in_cache_entry *entry,\n-\t\t\t\t struct mpoa_client *client)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct k_message msg;\n-\n-\tvcc = entry->shortcut;\n-\tdprintk(\"removing an ingress entry, ip = %pI4\\n\",\n-\t\t&entry->ctrl_info.in_dst_ip);\n-\n-\tif (entry->prev != NULL)\n-\t\tentry->prev->next = entry->next;\n-\telse\n-\t\tclient->in_cache = entry->next;\n-\tif (entry->next != NULL)\n-\t\tentry->next->prev = entry->prev;\n-\tclient->in_ops->put(entry);\n-\tif (client->in_cache == NULL && client->eg_cache == NULL) {\n-\t\tmsg.type = STOP_KEEP_ALIVE_SM;\n-\t\tmsg_to_mpoad(&msg, client);\n-\t}\n-\n-\t/* Check if the egress side still uses this VCC */\n-\tif (vcc != NULL) {\n-\t\teg_cache_entry *eg_entry = client->eg_ops->get_by_vcc(vcc,\n-\t\t\t\t\t\t\t\t client);\n-\t\tif (eg_entry != NULL) {\n-\t\t\tclient->eg_ops->put(eg_entry);\n-\t\t\treturn;\n-\t\t}\n-\t\tvcc_release_async(vcc, -EPIPE);\n-\t}\n-}\n-\n-/* Call this every MPC-p2 seconds... Not exactly correct solution,\n- but an easy one... */\n-static void clear_count_and_expired(struct mpoa_client *client)\n-{\n-\tin_cache_entry *entry, *next_entry;\n-\ttime64_t now;\n-\n-\tnow = ktime_get_seconds();\n-\n-\twrite_lock_bh(&client->ingress_lock);\n-\tentry = client->in_cache;\n-\twhile (entry != NULL) {\n-\t\tentry->count = 0;\n-\t\tnext_entry = entry->next;\n-\t\tif ((now - entry->time) > entry->ctrl_info.holding_time) {\n-\t\t\tdprintk(\"holding time expired, ip = %pI4\\n\",\n-\t\t\t\t&entry->ctrl_info.in_dst_ip);\n-\t\t\tclient->in_ops->remove_entry(entry, client);\n-\t\t}\n-\t\tentry = next_entry;\n-\t}\n-\twrite_unlock_bh(&client->ingress_lock);\n-}\n-\n-/* Call this every MPC-p4 seconds. */\n-static void check_resolving_entries(struct mpoa_client *client)\n-{\n-\n-\tstruct atm_mpoa_qos *qos;\n-\tin_cache_entry *entry;\n-\ttime64_t now;\n-\tstruct k_message msg;\n-\n-\tnow = ktime_get_seconds();\n-\n-\tread_lock_bh(&client->ingress_lock);\n-\tentry = client->in_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->entry_state == INGRESS_RESOLVING) {\n-\n-\t\t\tif ((now - entry->hold_down)\n-\t\t\t\t\t< client->parameters.mpc_p6) {\n-\t\t\t\tentry = entry->next;\t/* Entry in hold down */\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tif ((now - entry->reply_wait) > entry->retry_time) {\n-\t\t\t\tentry->retry_time = MPC_C1 * (entry->retry_time);\n-\t\t\t\t/*\n-\t\t\t\t * Retry time maximum exceeded,\n-\t\t\t\t * put entry in hold down.\n-\t\t\t\t */\n-\t\t\t\tif (entry->retry_time > client->parameters.mpc_p5) {\n-\t\t\t\t\tentry->hold_down = ktime_get_seconds();\n-\t\t\t\t\tentry->retry_time = client->parameters.mpc_p4;\n-\t\t\t\t\tentry = entry->next;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\t\t\t\t/* Ask daemon to send a resolution request. */\n-\t\t\t\tmemset(&entry->hold_down, 0, sizeof(time64_t));\n-\t\t\t\tmsg.type = SND_MPOA_RES_RTRY;\n-\t\t\t\tmemcpy(msg.MPS_ctrl, client->mps_ctrl_addr, ATM_ESA_LEN);\n-\t\t\t\tmsg.content.in_info = entry->ctrl_info;\n-\t\t\t\tqos = atm_mpoa_search_qos(entry->ctrl_info.in_dst_ip);\n-\t\t\t\tif (qos != NULL)\n-\t\t\t\t\tmsg.qos = qos->qos;\n-\t\t\t\tmsg_to_mpoad(&msg, client);\n-\t\t\t\tentry->reply_wait = ktime_get_seconds();\n-\t\t\t}\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_bh(&client->ingress_lock);\n-}\n-\n-/* Call this every MPC-p5 seconds. */\n-static void refresh_entries(struct mpoa_client *client)\n-{\n-\ttime64_t now;\n-\tstruct in_cache_entry *entry = client->in_cache;\n-\n-\tddprintk(\"refresh_entries\\n\");\n-\tnow = ktime_get_seconds();\n-\n-\tread_lock_bh(&client->ingress_lock);\n-\twhile (entry != NULL) {\n-\t\tif (entry->entry_state == INGRESS_RESOLVED) {\n-\t\t\tif (!(entry->refresh_time))\n-\t\t\t\tentry->refresh_time = (2 * (entry->ctrl_info.holding_time))/3;\n-\t\t\tif ((now - entry->reply_wait) >\n-\t\t\t entry->refresh_time) {\n-\t\t\t\tdprintk(\"refreshing an entry.\\n\");\n-\t\t\t\tentry->entry_state = INGRESS_REFRESHING;\n-\n-\t\t\t}\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_bh(&client->ingress_lock);\n-}\n-\n-static void in_destroy_cache(struct mpoa_client *mpc)\n-{\n-\twrite_lock_irq(&mpc->ingress_lock);\n-\twhile (mpc->in_cache != NULL)\n-\t\tmpc->in_ops->remove_entry(mpc->in_cache, mpc);\n-\twrite_unlock_irq(&mpc->ingress_lock);\n-}\n-\n-static eg_cache_entry *eg_cache_get_by_cache_id(__be32 cache_id,\n-\t\t\t\t\t\tstruct mpoa_client *mpc)\n-{\n-\teg_cache_entry *entry;\n-\n-\tread_lock_irq(&mpc->egress_lock);\n-\tentry = mpc->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->ctrl_info.cache_id == cache_id) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_irq(&mpc->egress_lock);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_irq(&mpc->egress_lock);\n-\n-\treturn NULL;\n-}\n-\n-/* This can be called from any context since it saves CPU flags */\n-static eg_cache_entry *eg_cache_get_by_tag(__be32 tag, struct mpoa_client *mpc)\n-{\n-\tunsigned long flags;\n-\teg_cache_entry *entry;\n-\n-\tread_lock_irqsave(&mpc->egress_lock, flags);\n-\tentry = mpc->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->ctrl_info.tag == tag) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_irqrestore(&mpc->egress_lock, flags);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_irqrestore(&mpc->egress_lock, flags);\n-\n-\treturn NULL;\n-}\n-\n-/* This can be called from any context since it saves CPU flags */\n-static eg_cache_entry *eg_cache_get_by_vcc(struct atm_vcc *vcc,\n-\t\t\t\t\t struct mpoa_client *mpc)\n-{\n-\tunsigned long flags;\n-\teg_cache_entry *entry;\n-\n-\tread_lock_irqsave(&mpc->egress_lock, flags);\n-\tentry = mpc->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->shortcut == vcc) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_irqrestore(&mpc->egress_lock, flags);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_irqrestore(&mpc->egress_lock, flags);\n-\n-\treturn NULL;\n-}\n-\n-static eg_cache_entry *eg_cache_get_by_src_ip(__be32 ipaddr,\n-\t\t\t\t\t struct mpoa_client *mpc)\n-{\n-\teg_cache_entry *entry;\n-\n-\tread_lock_irq(&mpc->egress_lock);\n-\tentry = mpc->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tif (entry->latest_ip_addr == ipaddr) {\n-\t\t\trefcount_inc(&entry->use);\n-\t\t\tread_unlock_irq(&mpc->egress_lock);\n-\t\t\treturn entry;\n-\t\t}\n-\t\tentry = entry->next;\n-\t}\n-\tread_unlock_irq(&mpc->egress_lock);\n-\n-\treturn NULL;\n-}\n-\n-static void eg_cache_put(eg_cache_entry *entry)\n-{\n-\tif (refcount_dec_and_test(&entry->use)) {\n-\t\tkfree_sensitive(entry);\n-\t}\n-}\n-\n-/*\n- * This should be called with write lock on\n- */\n-static void eg_cache_remove_entry(eg_cache_entry *entry,\n-\t\t\t\t struct mpoa_client *client)\n-{\n-\tstruct atm_vcc *vcc;\n-\tstruct k_message msg;\n-\n-\tvcc = entry->shortcut;\n-\tdprintk(\"removing an egress entry.\\n\");\n-\tif (entry->prev != NULL)\n-\t\tentry->prev->next = entry->next;\n-\telse\n-\t\tclient->eg_cache = entry->next;\n-\tif (entry->next != NULL)\n-\t\tentry->next->prev = entry->prev;\n-\tclient->eg_ops->put(entry);\n-\tif (client->in_cache == NULL && client->eg_cache == NULL) {\n-\t\tmsg.type = STOP_KEEP_ALIVE_SM;\n-\t\tmsg_to_mpoad(&msg, client);\n-\t}\n-\n-\t/* Check if the ingress side still uses this VCC */\n-\tif (vcc != NULL) {\n-\t\tin_cache_entry *in_entry = client->in_ops->get_by_vcc(vcc, client);\n-\t\tif (in_entry != NULL) {\n-\t\t\tclient->in_ops->put(in_entry);\n-\t\t\treturn;\n-\t\t}\n-\t\tvcc_release_async(vcc, -EPIPE);\n-\t}\n-}\n-\n-static eg_cache_entry *eg_cache_add_entry(struct k_message *msg,\n-\t\t\t\t\t struct mpoa_client *client)\n-{\n-\teg_cache_entry *entry = kzalloc_obj(eg_cache_entry);\n-\n-\tif (entry == NULL) {\n-\t\tpr_info(\"out of memory\\n\");\n-\t\treturn NULL;\n-\t}\n-\n-\tdprintk(\"adding an egress entry, ip = %pI4, this should be our IP\\n\",\n-\t\t&msg->content.eg_info.eg_dst_ip);\n-\n-\trefcount_set(&entry->use, 1);\n-\tdprintk(\"new_eg_cache_entry: about to lock\\n\");\n-\twrite_lock_irq(&client->egress_lock);\n-\tentry->next = client->eg_cache;\n-\tentry->prev = NULL;\n-\tif (client->eg_cache != NULL)\n-\t\tclient->eg_cache->prev = entry;\n-\tclient->eg_cache = entry;\n-\n-\tmemcpy(entry->MPS_ctrl_ATM_addr, client->mps_ctrl_addr, ATM_ESA_LEN);\n-\tentry->ctrl_info = msg->content.eg_info;\n-\tentry->time = ktime_get_seconds();\n-\tentry->entry_state = EGRESS_RESOLVED;\n-\tdprintk(\"new_eg_cache_entry cache_id %u\\n\",\n-\t\tntohl(entry->ctrl_info.cache_id));\n-\tdprintk(\"mps_ip = %pI4\\n\", &entry->ctrl_info.mps_ip);\n-\trefcount_inc(&entry->use);\n-\n-\twrite_unlock_irq(&client->egress_lock);\n-\tdprintk(\"new_eg_cache_entry: unlocked\\n\");\n-\n-\treturn entry;\n-}\n-\n-static void update_eg_cache_entry(eg_cache_entry *entry, uint16_t holding_time)\n-{\n-\tentry->time = ktime_get_seconds();\n-\tentry->entry_state = EGRESS_RESOLVED;\n-\tentry->ctrl_info.holding_time = holding_time;\n-}\n-\n-static void clear_expired(struct mpoa_client *client)\n-{\n-\teg_cache_entry *entry, *next_entry;\n-\ttime64_t now;\n-\tstruct k_message msg;\n-\n-\tnow = ktime_get_seconds();\n-\n-\twrite_lock_irq(&client->egress_lock);\n-\tentry = client->eg_cache;\n-\twhile (entry != NULL) {\n-\t\tnext_entry = entry->next;\n-\t\tif ((now - entry->time) > entry->ctrl_info.holding_time) {\n-\t\t\tmsg.type = SND_EGRESS_PURGE;\n-\t\t\tmsg.content.eg_info = entry->ctrl_info;\n-\t\t\tdprintk(\"egress_cache: holding time expired, cache_id = %u.\\n\",\n-\t\t\t\tntohl(entry->ctrl_info.cache_id));\n-\t\t\tmsg_to_mpoad(&msg, client);\n-\t\t\tclient->eg_ops->remove_entry(entry, client);\n-\t\t}\n-\t\tentry = next_entry;\n-\t}\n-\twrite_unlock_irq(&client->egress_lock);\n-}\n-\n-static void eg_destroy_cache(struct mpoa_client *mpc)\n-{\n-\twrite_lock_irq(&mpc->egress_lock);\n-\twhile (mpc->eg_cache != NULL)\n-\t\tmpc->eg_ops->remove_entry(mpc->eg_cache, mpc);\n-\twrite_unlock_irq(&mpc->egress_lock);\n-}\n-\n-\n-static const struct in_cache_ops ingress_ops = {\n-\t.add_entry = in_cache_add_entry,\n-\t.get = in_cache_get,\n-\t.get_with_mask = in_cache_get_with_mask,\n-\t.get_by_vcc = in_cache_get_by_vcc,\n-\t.put = in_cache_put,\n-\t.remove_entry = in_cache_remove_entry,\n-\t.cache_hit = cache_hit,\n-\t.clear_count = clear_count_and_expired,\n-\t.check_resolving = check_resolving_entries,\n-\t.refresh = refresh_entries,\n-\t.destroy_cache = in_destroy_cache\n-};\n-\n-static const struct eg_cache_ops egress_ops = {\n-\t.add_entry = eg_cache_add_entry,\n-\t.get_by_cache_id = eg_cache_get_by_cache_id,\n-\t.get_by_tag = eg_cache_get_by_tag,\n-\t.get_by_vcc = eg_cache_get_by_vcc,\n-\t.get_by_src_ip = eg_cache_get_by_src_ip,\n-\t.put = eg_cache_put,\n-\t.remove_entry = eg_cache_remove_entry,\n-\t.update = update_eg_cache_entry,\n-\t.clear_expired = clear_expired,\n-\t.destroy_cache = eg_destroy_cache\n-};\n-\n-void atm_mpoa_init_cache(struct mpoa_client *mpc)\n-{\n-\tmpc->in_ops = &ingress_ops;\n-\tmpc->eg_ops = &egress_ops;\n-}\ndiff --git a/net/atm/mpoa_proc.c b/net/atm/mpoa_proc.c\ndeleted file mode 100644\nindex aaf64b953915..000000000000\n--- a/net/atm/mpoa_proc.c\n+++ /dev/null\n@@ -1,307 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-#define pr_fmt(fmt) KBUILD_MODNAME \":%s: \" fmt, __func__\n-\n-#ifdef CONFIG_PROC_FS\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \"mpc.h\"\n-#include \"mpoa_caches.h\"\n-\n-/*\n- * mpoa_proc.c: Implementation MPOA client's proc\n- * file system statistics\n- */\n-\n-#if 1\n-#define dprintk(format, args...)\t\t\t\t\t\\\n-\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args) /* debug */\n-#else\n-#define dprintk(format, args...)\t\t\t\t\t\\\n-\tdo { if (0)\t\t\t\t\t\t\t\\\n-\t\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args);\\\n-\t} while (0)\n-#endif\n-\n-#if 0\n-#define ddprintk(format, args...)\t\t\t\t\t\\\n-\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args) /* debug */\n-#else\n-#define ddprintk(format, args...)\t\t\t\t\t\\\n-\tdo { if (0)\t\t\t\t\t\t\t\\\n-\t\tprintk(KERN_DEBUG \"mpoa:%s: \" format, __FILE__, ##args);\\\n-\t} while (0)\n-#endif\n-\n-#define STAT_FILE_NAME \"mpc\" /* Our statistic file's name */\n-\n-extern struct mpoa_client *mpcs;\n-extern struct proc_dir_entry *atm_proc_root; /* from proc.c. */\n-\n-static int proc_mpc_open(struct inode *inode, struct file *file);\n-static ssize_t proc_mpc_write(struct file *file, const char __user *buff,\n-\t\t\t size_t nbytes, loff_t *ppos);\n-\n-static int parse_qos(const char *buff);\n-\n-static const struct proc_ops mpc_proc_ops = {\n-\t.proc_open\t= proc_mpc_open,\n-\t.proc_read\t= seq_read,\n-\t.proc_lseek\t= seq_lseek,\n-\t.proc_write\t= proc_mpc_write,\n-\t.proc_release\t= seq_release,\n-};\n-\n-/*\n- * Returns the state of an ingress cache entry as a string\n- */\n-static const char *ingress_state_string(int state)\n-{\n-\tswitch (state) {\n-\tcase INGRESS_RESOLVING:\n-\t\treturn \"resolving \";\n-\tcase INGRESS_RESOLVED:\n-\t\treturn \"resolved \";\n-\tcase INGRESS_INVALID:\n-\t\treturn \"invalid \";\n-\tcase INGRESS_REFRESHING:\n-\t\treturn \"refreshing \";\n-\t}\n-\n-\treturn \"\";\n-}\n-\n-/*\n- * Returns the state of an egress cache entry as a string\n- */\n-static const char *egress_state_string(int state)\n-{\n-\tswitch (state) {\n-\tcase EGRESS_RESOLVED:\n-\t\treturn \"resolved \";\n-\tcase EGRESS_PURGE:\n-\t\treturn \"purge \";\n-\tcase EGRESS_INVALID:\n-\t\treturn \"invalid \";\n-\t}\n-\n-\treturn \"\";\n-}\n-\n-/*\n- * FIXME: mpcs (and per-mpc lists) have no locking whatsoever.\n- */\n-\n-static void *mpc_start(struct seq_file *m, loff_t *pos)\n-{\n-\tloff_t l = *pos;\n-\tstruct mpoa_client *mpc;\n-\n-\tif (!l--)\n-\t\treturn SEQ_START_TOKEN;\n-\tfor (mpc = mpcs; mpc; mpc = mpc->next)\n-\t\tif (!l--)\n-\t\t\treturn mpc;\n-\treturn NULL;\n-}\n-\n-static void *mpc_next(struct seq_file *m, void *v, loff_t *pos)\n-{\n-\tstruct mpoa_client *p = v;\n-\t(*pos)++;\n-\treturn v == SEQ_START_TOKEN ? mpcs : p->next;\n-}\n-\n-static void mpc_stop(struct seq_file *m, void *v)\n-{\n-}\n-\n-/*\n- * READING function - called when the /proc/atm/mpoa file is read from.\n- */\n-static int mpc_show(struct seq_file *m, void *v)\n-{\n-\tstruct mpoa_client *mpc = v;\n-\tint i;\n-\tin_cache_entry *in_entry;\n-\teg_cache_entry *eg_entry;\n-\ttime64_t now;\n-\tunsigned char ip_string[16];\n-\n-\tif (v == SEQ_START_TOKEN) {\n-\t\tatm_mpoa_disp_qos(m);\n-\t\treturn 0;\n-\t}\n-\n-\tseq_printf(m, \"\\nInterface %d:\\n\\n\", mpc->dev_num);\n-\tseq_printf(m, \"Ingress Entries:\\nIP address State Holding time Packets fwded VPI VCI\\n\");\n-\tnow = ktime_get_seconds();\n-\n-\tfor (in_entry = mpc->in_cache; in_entry; in_entry = in_entry->next) {\n-\t\tunsigned long seconds_delta = now - in_entry->time;\n-\n-\t\tsprintf(ip_string, \"%pI4\", &in_entry->ctrl_info.in_dst_ip);\n-\t\tseq_printf(m, \"%-16s%s%-14lu%-12u\",\n-\t\t\t ip_string,\n-\t\t\t ingress_state_string(in_entry->entry_state),\n-\t\t\t in_entry->ctrl_info.holding_time -\n-\t\t\t seconds_delta,\n-\t\t\t in_entry->packets_fwded);\n-\t\tif (in_entry->shortcut)\n-\t\t\tseq_printf(m, \" %-3d %-3d\",\n-\t\t\t\t in_entry->shortcut->vpi,\n-\t\t\t\t in_entry->shortcut->vci);\n-\t\tseq_printf(m, \"\\n\");\n-\t}\n-\n-\tseq_printf(m, \"\\n\");\n-\tseq_printf(m, \"Egress Entries:\\nIngress MPC ATM addr\\nCache-id State Holding time Packets recvd Latest IP addr VPI VCI\\n\");\n-\tfor (eg_entry = mpc->eg_cache; eg_entry; eg_entry = eg_entry->next) {\n-\t\tunsigned char *p = eg_entry->ctrl_info.in_MPC_data_ATM_addr;\n-\t\tunsigned long seconds_delta = now - eg_entry->time;\n-\n-\t\tfor (i = 0; i < ATM_ESA_LEN; i++)\n-\t\t\tseq_printf(m, \"%02x\", p[i]);\n-\t\tseq_printf(m, \"\\n%-16lu%s%-14lu%-15u\",\n-\t\t\t (unsigned long)ntohl(eg_entry->ctrl_info.cache_id),\n-\t\t\t egress_state_string(eg_entry->entry_state),\n-\t\t\t (eg_entry->ctrl_info.holding_time - seconds_delta),\n-\t\t\t eg_entry->packets_rcvd);\n-\n-\t\t/* latest IP address */\n-\t\tsprintf(ip_string, \"%pI4\", &eg_entry->latest_ip_addr);\n-\t\tseq_printf(m, \"%-16s\", ip_string);\n-\n-\t\tif (eg_entry->shortcut)\n-\t\t\tseq_printf(m, \" %-3d %-3d\",\n-\t\t\t\t eg_entry->shortcut->vpi,\n-\t\t\t\t eg_entry->shortcut->vci);\n-\t\tseq_printf(m, \"\\n\");\n-\t}\n-\tseq_printf(m, \"\\n\");\n-\treturn 0;\n-}\n-\n-static const struct seq_operations mpc_op = {\n-\t.start =\tmpc_start,\n-\t.next =\t\tmpc_next,\n-\t.stop =\t\tmpc_stop,\n-\t.show =\t\tmpc_show\n-};\n-\n-static int proc_mpc_open(struct inode *inode, struct file *file)\n-{\n-\treturn seq_open(file, &mpc_op);\n-}\n-\n-static ssize_t proc_mpc_write(struct file *file, const char __user *buff,\n-\t\t\t size_t nbytes, loff_t *ppos)\n-{\n-\tchar *page, *p;\n-\tunsigned int len;\n-\n-\tif (nbytes == 0)\n-\t\treturn 0;\n-\n-\tif (nbytes >= PAGE_SIZE)\n-\t\tnbytes = PAGE_SIZE-1;\n-\n-\tpage = (char *)__get_free_page(GFP_KERNEL);\n-\tif (!page)\n-\t\treturn -ENOMEM;\n-\n-\tfor (p = page, len = 0; len < nbytes; p++) {\n-\t\tif (get_user(*p, buff++)) {\n-\t\t\tfree_page((unsigned long)page);\n-\t\t\treturn -EFAULT;\n-\t\t}\n-\t\tlen += 1;\n-\t\tif (*p == '\\0' || *p == '\\n')\n-\t\t\tbreak;\n-\t}\n-\n-\t*p = '\\0';\n-\n-\tif (!parse_qos(page))\n-\t\tprintk(\"mpoa: proc_mpc_write: could not parse '%s'\\n\", page);\n-\n-\tfree_page((unsigned long)page);\n-\n-\treturn len;\n-}\n-\n-static int parse_qos(const char *buff)\n-{\n-\t/* possible lines look like this\n-\t * add 130.230.54.142 tx=max_pcr,max_sdu rx=max_pcr,max_sdu\n-\t */\n-\tunsigned char ip[4];\n-\tint tx_pcr, tx_sdu, rx_pcr, rx_sdu;\n-\t__be32 ipaddr;\n-\tstruct atm_qos qos;\n-\n-\tmemset(&qos, 0, sizeof(struct atm_qos));\n-\n-\tif (sscanf(buff, \"del %hhu.%hhu.%hhu.%hhu\",\n-\t\t\tip, ip+1, ip+2, ip+3) == 4) {\n-\t\tipaddr = *(__be32 *)ip;\n-\t\treturn atm_mpoa_delete_qos(atm_mpoa_search_qos(ipaddr));\n-\t}\n-\n-\tif (sscanf(buff, \"add %hhu.%hhu.%hhu.%hhu tx=%d,%d rx=tx\",\n-\t\t\tip, ip+1, ip+2, ip+3, &tx_pcr, &tx_sdu) == 6) {\n-\t\trx_pcr = tx_pcr;\n-\t\trx_sdu = tx_sdu;\n-\t} else if (sscanf(buff, \"add %hhu.%hhu.%hhu.%hhu tx=%d,%d rx=%d,%d\",\n-\t\tip, ip+1, ip+2, ip+3, &tx_pcr, &tx_sdu, &rx_pcr, &rx_sdu) != 8)\n-\t\treturn 0;\n-\n-\tipaddr = *(__be32 *)ip;\n-\tqos.txtp.traffic_class = ATM_CBR;\n-\tqos.txtp.max_pcr = tx_pcr;\n-\tqos.txtp.max_sdu = tx_sdu;\n-\tqos.rxtp.traffic_class = ATM_CBR;\n-\tqos.rxtp.max_pcr = rx_pcr;\n-\tqos.rxtp.max_sdu = rx_sdu;\n-\tqos.aal = ATM_AAL5;\n-\tdprintk(\"parse_qos(): setting qos parameters to tx=%d,%d rx=%d,%d\\n\",\n-\t\tqos.txtp.max_pcr, qos.txtp.max_sdu,\n-\t\tqos.rxtp.max_pcr, qos.rxtp.max_sdu);\n-\n-\tatm_mpoa_add_qos(ipaddr, &qos);\n-\treturn 1;\n-}\n-\n-/*\n- * INITIALIZATION function - called when module is initialized/loaded.\n- */\n-int mpc_proc_init(void)\n-{\n-\tstruct proc_dir_entry *p;\n-\n-\tp = proc_create(STAT_FILE_NAME, 0, atm_proc_root, &mpc_proc_ops);\n-\tif (!p) {\n-\t\tpr_err(\"Unable to initialize /proc/atm/%s\\n\", STAT_FILE_NAME);\n-\t\treturn -ENOMEM;\n-\t}\n-\treturn 0;\n-}\n-\n-/*\n- * DELETING function - called when module is removed.\n- */\n-void mpc_proc_clean(void)\n-{\n-\tremove_proc_entry(STAT_FILE_NAME, atm_proc_root);\n-}\n-\n-#endif /* CONFIG_PROC_FS */\ndiff --git a/net/bridge/br.c b/net/bridge/br.c\nindex c37e52e2f29a..a5e5b2db110e 100644\n--- a/net/bridge/br.c\n+++ b/net/bridge/br.c\n@@ -464,10 +464,6 @@ static int __init br_init(void)\n \n \tbrioctl_set(br_ioctl_stub);\n \n-#if IS_ENABLED(CONFIG_ATM_LANE)\n-\tbr_fdb_test_addr_hook = br_fdb_test_addr;\n-#endif\n-\n #if IS_MODULE(CONFIG_BRIDGE_NETFILTER)\n \tpr_info(\"bridge: filtering via arp/ip/ip6tables is no longer available \"\n \t\t\"by default. Update your scripts to load br_netfilter if you \"\n@@ -506,9 +502,6 @@ static void __exit br_deinit(void)\n \trcu_barrier(); /* Wait for completion of call_rcu()'s */\n \n \tbr_nf_core_fini();\n-#if IS_ENABLED(CONFIG_ATM_LANE)\n-\tbr_fdb_test_addr_hook = NULL;\n-#endif\n \tbr_fdb_fini();\n }\n \ndiff --git a/net/bridge/br_fdb.c b/net/bridge/br_fdb.c\nindex e2c17f620f00..9bcf6243914b 100644\n--- a/net/bridge/br_fdb.c\n+++ b/net/bridge/br_fdb.c\n@@ -892,35 +892,6 @@ void br_fdb_delete_by_port(struct net_bridge *br,\n \tspin_unlock_bh(&br->hash_lock);\n }\n \n-#if IS_ENABLED(CONFIG_ATM_LANE)\n-/* Interface used by ATM LANE hook to test\n- * if an addr is on some other bridge port */\n-int br_fdb_test_addr(struct net_device *dev, unsigned char *addr)\n-{\n-\tstruct net_bridge_fdb_entry *fdb;\n-\tstruct net_bridge_port *port;\n-\tint ret;\n-\n-\trcu_read_lock();\n-\tport = br_port_get_rcu(dev);\n-\tif (!port)\n-\t\tret = 0;\n-\telse {\n-\t\tconst struct net_bridge_port *dst = NULL;\n-\n-\t\tfdb = br_fdb_find_rcu(port->br, addr, 0);\n-\t\tif (fdb)\n-\t\t\tdst = READ_ONCE(fdb->dst);\n-\n-\t\tret = dst && dst->dev != dev &&\n-\t\t dst->state == BR_STATE_FORWARDING;\n-\t}\n-\trcu_read_unlock();\n-\n-\treturn ret;\n-}\n-#endif /* CONFIG_ATM_LANE */\n-\n /*\n * Fill buffer with forwarding table records in\n * the API format.\ndiff --git a/net/core/dev.c b/net/core/dev.c\nindex e59f6025067c..1be81928d6c7 100644\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -5862,13 +5862,6 @@ static __latent_entropy void net_tx_action(void)\n \txfrm_dev_backlog(sd);\n }\n \n-#if IS_ENABLED(CONFIG_BRIDGE) && IS_ENABLED(CONFIG_ATM_LANE)\n-/* This hook is defined here for ATM LANE */\n-int (*br_fdb_test_addr_hook)(struct net_device *dev,\n-\t\t\t unsigned char *addr) __read_mostly;\n-EXPORT_SYMBOL_GPL(br_fdb_test_addr_hook);\n-#endif\n-\n /**\n *\tnetdev_is_rx_handler_busy - check if receive handler is registered\n *\t@dev: device to check\ndiff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig\nindex 81199dddcde7..950b48c3b111 100644\n--- a/arch/arm/configs/ixp4xx_defconfig\n+++ b/arch/arm/configs/ixp4xx_defconfig\n@@ -52,10 +52,6 @@ CONFIG_IP_NF_MANGLE=m\n CONFIG_IP_NF_ARPTABLES=m\n CONFIG_IP_NF_ARPFILTER=m\n CONFIG_ATM=y\n-CONFIG_ATM_CLIP=y\n-CONFIG_ATM_LANE=m\n-CONFIG_ATM_MPOA=m\n-CONFIG_ATM_BR2684=m\n CONFIG_BRIDGE=m\n CONFIG_VLAN_8021Q=m\n CONFIG_ATALK=m\n@@ -108,7 +104,6 @@ CONFIG_ATA=y\n CONFIG_PATA_IXP4XX_CF=y\n CONFIG_NETDEVICES=y\n CONFIG_DUMMY=y\n-CONFIG_ATM_TCP=m\n CONFIG_IXP4XX_ETH=y\n CONFIG_WAN=y\n CONFIG_HDLC=y\ndiff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig\nindex fdd28a89e336..8097974489e3 100644\n--- a/arch/mips/configs/gpr_defconfig\n+++ b/arch/mips/configs/gpr_defconfig\n@@ -87,10 +87,6 @@ CONFIG_BRIDGE_EBT_LOG=m\n CONFIG_IP_SCTP=m\n CONFIG_TIPC=m\n CONFIG_ATM=y\n-CONFIG_ATM_CLIP=y\n-CONFIG_ATM_LANE=m\n-CONFIG_ATM_MPOA=m\n-CONFIG_ATM_BR2684=m\n CONFIG_BRIDGE=m\n CONFIG_VLAN_8021Q=m\n CONFIG_LLC2=m\n@@ -167,15 +163,6 @@ CONFIG_SCSI_SAS_LIBSAS=m\n CONFIG_NETDEVICES=y\n CONFIG_NET_FC=y\n CONFIG_NETCONSOLE=m\n-CONFIG_ATM_TCP=m\n-CONFIG_ATM_LANAI=m\n-CONFIG_ATM_ENI=m\n-CONFIG_ATM_NICSTAR=m\n-CONFIG_ATM_IDT77252=m\n-CONFIG_ATM_IA=m\n-CONFIG_ATM_FORE200E=m\n-CONFIG_ATM_HE=m\n-CONFIG_ATM_HE_USE_SUNI=y\n CONFIG_MIPS_AU1X00_ENET=y\n CONFIG_CICADA_PHY=m\n CONFIG_DAVICOM_PHY=m\ndiff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig\nindex 72568f8ae653..63787b8b733e 100644\n--- a/arch/mips/configs/mtx1_defconfig\n+++ b/arch/mips/configs/mtx1_defconfig\n@@ -133,10 +133,6 @@ CONFIG_BRIDGE_EBT_LOG=m\n CONFIG_IP_SCTP=m\n CONFIG_TIPC=m\n CONFIG_ATM=y\n-CONFIG_ATM_CLIP=y\n-CONFIG_ATM_LANE=m\n-CONFIG_ATM_MPOA=m\n-CONFIG_ATM_BR2684=m\n CONFIG_BRIDGE=m\n CONFIG_VLAN_8021Q=m\n CONFIG_LLC2=m\n@@ -243,15 +239,6 @@ CONFIG_ARCNET_RIM_I=m\n CONFIG_ARCNET_COM20020=m\n CONFIG_ARCNET_COM20020_PCI=m\n CONFIG_ARCNET_COM20020_CS=m\n-CONFIG_ATM_TCP=m\n-CONFIG_ATM_LANAI=m\n-CONFIG_ATM_ENI=m\n-CONFIG_ATM_NICSTAR=m\n-CONFIG_ATM_IDT77252=m\n-CONFIG_ATM_IA=m\n-CONFIG_ATM_FORE200E=m\n-CONFIG_ATM_HE=m\n-CONFIG_ATM_HE_USE_SUNI=y\n CONFIG_PCMCIA_3C574=m\n CONFIG_PCMCIA_3C589=m\n CONFIG_VORTEX=m\ndiff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig\nindex 6f40a275b7a9..02cc17e353a3 100644\n--- a/arch/powerpc/configs/ppc6xx_defconfig\n+++ b/arch/powerpc/configs/ppc6xx_defconfig\n@@ -227,9 +227,6 @@ CONFIG_BRIDGE_EBT_LOG=m\n CONFIG_BRIDGE_EBT_NFLOG=m\n CONFIG_TIPC=m\n CONFIG_ATM=m\n-CONFIG_ATM_CLIP=m\n-CONFIG_ATM_LANE=m\n-CONFIG_ATM_BR2684=m\n CONFIG_BRIDGE=m\n CONFIG_VLAN_8021Q=m\n CONFIG_ATALK=m\n@@ -398,12 +395,6 @@ CONFIG_NETCONSOLE=m\n CONFIG_TUN=m\n CONFIG_VETH=m\n CONFIG_VIRTIO_NET=m\n-CONFIG_ATM_TCP=m\n-CONFIG_ATM_LANAI=m\n-CONFIG_ATM_ENI=m\n-CONFIG_ATM_NICSTAR=m\n-CONFIG_ATM_IDT77252=m\n-CONFIG_ATM_HE=m\n CONFIG_EL3=m\n CONFIG_PCMCIA_3C574=m\n CONFIG_PCMCIA_3C589=m\ndiff --git a/drivers/atm/.gitignore b/drivers/atm/.gitignore\ndeleted file mode 100644\nindex ddd374e91965..000000000000\n--- a/drivers/atm/.gitignore\n+++ /dev/null\n@@ -1,5 +0,0 @@\n-# SPDX-License-Identifier: GPL-2.0-only\n-fore200e_mkfirm\n-fore200e_pca_fw.c\n-pca200e.bin\n-pca200e_ecd.bin2\ndiff --git a/drivers/atm/nicstarmac.copyright b/drivers/atm/nicstarmac.copyright\ndeleted file mode 100644\nindex 180531a83c62..000000000000\n--- a/drivers/atm/nicstarmac.copyright\n+++ /dev/null\n@@ -1,61 +0,0 @@\n-/* nicstar.c v0.22 Jawaid Bazyar (bazyar@hypermall.com)\n- * nicstar.c, M. Welsh (matt.welsh@cl.cam.ac.uk)\n- *\n- * Hacked October, 1997 by Jawaid Bazyar, Interlink Advertising Services Inc.\n- * \thttp://www.hypermall.com/\n- * 10/1/97 - commented out CFG_PHYIE bit - we don't care when the PHY\n- *\tinterrupts us (except possibly for removal/insertion of the cable?)\n- * 10/4/97 - began heavy inline documentation of the code. Corrected typos\n- *\tand spelling mistakes.\n- * 10/5/97 - added code to handle PHY interrupts, disable PHY on\n- *\tloss of link, and correctly re-enable PHY when link is\n- *\tre-established. (put back CFG_PHYIE)\n- *\n- * Modified to work with the IDT7721 nicstar -- AAL5 (tested) only.\n- *\n- * R. D. Rechenmacher , Aug. 6, 1997\n- *\n- * Linux driver for the IDT77201 NICStAR PCI ATM controller.\n- * PHY component is expected to be 155 Mbps S/UNI-Lite or IDT 77155;\n- * see init_nicstar() for PHY initialization to change this. This driver\n- * expects the Linux ATM stack to support scatter-gather lists \n- * (skb->atm.iovcnt != 0) for Rx skb's passed to vcc->push.\n- *\n- * Implementing minimal-copy of received data:\n- * IDT always receives data into a small buffer, then large buffers\n- * as needed. This means that data must always be copied to create\n- * the linear buffer needed by most non-ATM protocol stacks (e.g. IP)\n- * Fix is simple: make large buffers large enough to hold entire\n- * SDU, and leave bytes empty at the start. Then\n- * copy small buffer contents to head of large buffer.\n- * Trick is to avoid fragmenting Linux, due to need for a lot of large\n- * buffers. This is done by 2 things:\n- * 1) skb->destructor / skb->atm.recycle_buffer\n- * combined, allow nicstar_free_rx_skb to be called to\n- * recycle large data buffers\n- * 2) skb_clone of received buffers\n- * See nicstar_free_rx_skb and linearize_buffer for implementation\n- * details.\n- *\n- *\n- *\n- * Copyright (c) 1996 University of Cambridge Computer Laboratory\n- *\n- * This program is free software; you can redistribute it and/or modify\n- * it under the terms of the GNU General Public License as published by\n- * the Free Software Foundation; either version 2 of the License, or\n- * (at your option) any later version.\n- * \n- * This program is distributed in the hope that it will be useful,\n- * but WITHOUT ANY WARRANTY; without even the implied warranty of\n- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- * GNU General Public License for more details.\n- *\n- * You should have received a copy of the GNU General Public License\n- * along with this program; if not, write to the Free Software\n- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n- *\n- * M. Welsh, 6 July 1996\n- *\n- *\n- */\n","prefixes":["net-deletions","v2"]}