{"id":2226042,"url":"http://patchwork.ozlabs.org/api/patches/2226042/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1776825522-6390-2-git-send-email-shawn.lin@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1776825522-6390-2-git-send-email-shawn.lin@rock-chips.com>","list_archive_url":null,"date":"2026-04-22T02:38:40","name":"[RESEND,v3,1/3] PCI/MSI: Add Devres managed IRQ vectors allocation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"934fb1521caced24d8a6bd604d8c331d53676e27","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/people/66993/?format=json","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1776825522-6390-2-git-send-email-shawn.lin@rock-chips.com/mbox/","series":[{"id":500916,"url":"http://patchwork.ozlabs.org/api/series/500916/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500916","date":"2026-04-22T02:38:41","name":"Add Devres managed IRQ vectors allocation","version":3,"mbox":"http://patchwork.ozlabs.org/series/500916/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226042/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226042/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=fJyHiIb4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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arc=none smtp.client-ip=220.197.32.118","From":"Shawn Lin ","To":"Bjorn Helgaas ","Cc":"Nirmal Patel ,\n\tJonathan Derrick ,\n\tKurt Schwemmer ,\n\tLogan Gunthorpe ,\n\tPhilipp Stanner ,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin ","Subject":"[RESEND PATCH v3 1/3] PCI/MSI: Add Devres managed IRQ vectors\n allocation","Date":"Wed, 22 Apr 2026 10:38:40 +0800","Message-Id":"<1776825522-6390-2-git-send-email-shawn.lin@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1776825522-6390-1-git-send-email-shawn.lin@rock-chips.com>","References":"<1776825522-6390-1-git-send-email-shawn.lin@rock-chips.com>","X-HM-Tid":"0a9db30e14d509cckunm3ea616f516de6f","X-HM-MType":"1","X-HM-Spam-Status":"e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDSBhKVkoaHkIZGUJPSB5JTlYVFAkWGhdVEwETFh\n\toSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSktLVU\n\tpCS0tZBg++","DKIM-Signature":"a=rsa-sha256;\n\tb=fJyHiIb4tGeGJvYAq47nO6IMF7/lPIFh5T15S9j/lvgs2rE+ZY/DxqvJWu+CD9HxtBTq8ofxXAt8S/rtQkuV7UYRtIsTOIzd71/YourUzMKZPSm5lFX5p//WVeU78psxciCeGpkt4uapeIv3vaW6csYYyHWuMX6CMu2SEsFTOkA=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=2aqE0MBh0FaAxOR49x5tQGdA0sVkV8vV6mSKwJwQz6c=;\n\th=date:mime-version:subject:message-id:from;","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""},"content":"The PCI/MSI subsystem suffers from a long-standing design issue where\nthe implicit, automatic management of IRQ vectors by the devres\nframework conflicts with explicit driver cleanup, leading to ambiguous\nownership and potential resource management bugs.\n\nHistorically, pcim_enable_device() not only manages standard PCI\nresources (BARs) via devres but also implicitly sets the is_msi_managed\nflag if calling pci_alloc_irq_vectors*(). This registers pcim_msi_release()\nas a cleanup action, creating a hybrid ownership model.\n\nThis ambiguity causes problems when drivers follow a common but\nhazardous pattern:\n1. Using pcim_enable_device() (which implicitly marks IRQs as managed)\n2. Explicitly calling pci_alloc_irq_vectors() for IRQ allocation\n3. Also calling pci_free_irq_vectors() in error paths or remove routines\n\nIn this scenario, the devres framework may attempt to free the IRQ\nvectors a second time upon device release, leading to double-free\nissues. Analysis of the tree shows this hazardous pattern exists\nin multiple drivers, while 35 other drivers correctly rely solely\non the implicit cleanup.\n\nTo resolve this ambiguity, introduce explicit managed APIs for IRQ\nvector allocation:\n- pcim_alloc_irq_vectors()\n- pcim_alloc_irq_vectors_affinity()\n\nThese functions are the devres-managed counterparts to\npci_alloc_irq_vectors[_affinity](). Drivers that wish to have\ndevres-managed IRQ vectors should use these new APIs instead.\n\nThe long-term goal is to convert all drivers which use pcim_enable_device()\nas well as pci_alloc_irq_vectors[_affinity]() to use these managed\nfunctions, and eventually remove the problematic hybrid management\npattern from pcim_enable_device() and pcim_setup_msi_release() entirely.\nThis patch lays the foundation by introducing the APIs.\n\nSuggested-by: Philipp Stanner \nSigned-off-by: Shawn Lin \n\n---\n\nChanges in v3:\n- Rework the commit message and function doc (Philipp)\n- Remove setting is_msi_managed flag from new APIs (Philipp)\n\nChanges in v2:\n- Rebase\n- Introduce patches only for PCI subsystem to convert the API\n\n drivers/pci/msi/api.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++\n include/linux/pci.h | 22 ++++++++++++++++++++++\n 2 files changed, 69 insertions(+)","diff":"diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c\nindex c18559b..90b67f5 100644\n--- a/drivers/pci/msi/api.c\n+++ b/drivers/pci/msi/api.c\n@@ -297,6 +297,53 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,\n EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);\n \n /**\n+ * pcim_alloc_irq_vectors - devres managed pci_alloc_irq_vectors()\n+ * @dev: the PCI device to operate on\n+ * @min_vecs: minimum number of vectors required (must be >= 1)\n+ * @max_vecs: maximum (desired) number of vectors\n+ * @flags: flags for this allocation, see pci_alloc_irq_vectors()\n+ *\n+ * This is a device resource managed version of pci_alloc_irq_vectors().\n+ * Interrupt vectors are automatically freed on driver detach by the\n+ * devres. Drivers do not need to explicitly call pci_free_irq_vectors().\n+ *\n+ * Returns number of vectors allocated (which might be smaller than\n+ * @max_vecs) on success, or a negative error code on failure.\n+ */\n+int pcim_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,\n+\t\t\t unsigned int max_vecs, unsigned int flags)\n+{\n+\treturn pcim_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,\n+\t\t\t\t\t flags, NULL);\n+}\n+EXPORT_SYMBOL(pcim_alloc_irq_vectors);\n+\n+/**\n+ * pcim_alloc_irq_vectors_affinity - devres managed pci_alloc_irq_vectors_affinity()\n+ * @dev: the PCI device to operate on\n+ * @min_vecs: minimum number of vectors required (must be >= 1)\n+ * @max_vecs: maximum (desired) number of vectors\n+ * @flags: flags for this allocation, see pci_alloc_irq_vectors()\n+ * @affd: optional description of the affinity requirements\n+ *\n+ * This is a device resource managed version of pci_alloc_irq_vectors_affinity().\n+ * Interrupt vectors are automatically freed on driver detach by the devres\n+ * machinery. Drivers which use pcim_enable_device() as well as this function,\n+ * do not need to explicitly call pci_free_irq_vectors() currently.\n+ *\n+ * Returns number of vectors allocated (which might be smaller than\n+ * @max_vecs) on success, or a negative error code on failure.\n+ */\n+int pcim_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,\n+\t\t\t\t unsigned int max_vecs, unsigned int flags,\n+\t\t\t\t struct irq_affinity *affd)\n+{\n+\treturn pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,\n+\t\t\t\t\t flags, affd);\n+}\n+EXPORT_SYMBOL(pcim_alloc_irq_vectors_affinity);\n+\n+/**\n * pci_irq_vector() - Get Linux IRQ number of a device interrupt vector\n * @dev: the PCI device to operate on\n * @nr: device-relative interrupt vector index (0-based); has different\ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 2c44545..3716c67 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -1770,6 +1770,12 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,\n \t\t\t\t unsigned int max_vecs, unsigned int flags,\n \t\t\t\t struct irq_affinity *affd);\n \n+int pcim_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,\n+\t\t\t unsigned int max_vecs, unsigned int flags);\n+int pcim_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,\n+\t\t\t\t unsigned int max_vecs, unsigned int flags,\n+\t\t\t\t struct irq_affinity *affd);\n+\n bool pci_msix_can_alloc_dyn(struct pci_dev *dev);\n struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,\n \t\t\t\t const struct irq_affinity_desc *affdesc);\n@@ -1812,6 +1818,22 @@ pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,\n \t\t\t\t\t flags, NULL);\n }\n \n+static inline int\n+pcim_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,\n+\t\t\t unsigned int max_vecs, unsigned int flags,\n+\t\t\t struct irq_affinity *aff_desc)\n+{\n+\treturn pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,\n+\t\t\t\t\t flags, aff_desc);\n+}\n+static inline int\n+pcim_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,\n+\t\t unsigned int max_vecs, unsigned int flags)\n+{\n+\treturn pcim_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,\n+\t\t\t\t\t flags, NULL);\n+}\n+\n static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)\n { return false; }\n static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,\n","prefixes":["RESEND","v3","1/3"]}