{"id":2225876,"url":"http://patchwork.ozlabs.org/api/patches/2225876/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-5-a0791df188c9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mips-octeon-missing-insns-v2-v2-5-a0791df188c9@gmail.com>","list_archive_url":null,"date":"2026-04-21T17:27:32","name":"[v2,05/13] target/mips: add Octeon arithmetic and memory instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e6e41d658b23f892df89bb99009bc88e6af1c53b","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-5-a0791df188c9@gmail.com/mbox/","series":[{"id":500858,"url":"http://patchwork.ozlabs.org/api/series/500858/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858","date":"2026-04-21T17:27:27","name":"target/mips: add missing Octeon user-mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/500858/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225876/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225876/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Bm9F9t0a;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Message-Id":"\n <20260421-mips-octeon-missing-insns-v2-v2-5-a0791df188c9@gmail.com>","References":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","In-Reply-To":"\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier ,\n Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2001:4860:4864:20::33;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x33.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Octeon CPUs define additional integer, memory, and multiply operations\nbeyond the base MIPS64 ISA. Add the missing decode and helper support\nfor the remaining regular Octeon instructions used by existing user-mode\nworkloads.\n\nThis covers the indexed load forms, cache block zero operations, the\nOcteon multiply family, population count handling, and related\narithmetic and atomic memory operations in the translator and helper\nlayer.\n\nAdd a TCG smoke test that exercises the arithmetic, compare, population\ncount, and multiplier instructions introduced here.\n\nSigned-off-by: James Hilliard \n\n---\n\nChanges v1 -> v2:\n\n - Fold the initial Octeon arithmetic and multiplier smoke test into\n this patch.\n\n - Keep SAA/SAAD atomics naturally aligned for Octeon L2 transactions.\n\n - Split pre-existing BADDU/DMUL and SEQ/SNE translator changes into\n preliminary patches. (suggested by Philippe Mathieu-Daudé)\n\n - Store Octeon multiplier state in uint64_t arrays instead of\n target_ulong scalar fields. (suggested by Philippe Mathieu-Daudé)\n\n - Keep Octeon68XX CPU feature exposure out of this patch. (suggested\n by Philippe Mathieu-Daudé)\n---\n MAINTAINERS | 2 +\n target/mips/cpu.h | 4 +\n target/mips/helper.h | 3 +\n target/mips/system/machine.c | 33 +++++\n target/mips/tcg/octeon.decode | 22 ++++\n target/mips/tcg/octeon_translate.c | 166 ++++++++++++++++++++++++++\n target/mips/tcg/op_helper.c | 99 +++++++++++++++\n tests/tcg/mips/Makefile.target | 11 ++\n tests/tcg/mips/user/isa/octeon/octeon-insns.c | 145 ++++++++++++++++++++++\n tests/tcg/mips64/Makefile.target | 20 ++++\n tests/tcg/mips64el/Makefile.target | 8 ++\n 11 files changed, 513 insertions(+)","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex ad215eced8..3cfb10d076 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -306,6 +306,8 @@ F: target/mips/\n F: disas/*mips.c\n F: docs/system/cpu-models-mips.rst.inc\n F: tests/tcg/mips/\n+F: tests/tcg/mips64/\n+F: tests/tcg/mips64el/\n \n OpenRISC TCG CPUs\n M: Stafford Horne \ndiff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex ac81470576..540edf2906 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -497,6 +497,10 @@ struct TCState {\n target_ulong CP0_TCScheFBack;\n int32_t CP0_Debug_tcstatus;\n target_ulong CP0_UserLocal;\n+ struct {\n+ uint64_t MPL[2 * 3];\n+ uint64_t P[2 * 3];\n+ } octeon;\n \n int32_t msacsr;\n \ndiff --git a/target/mips/helper.h b/target/mips/helper.h\nindex b6cd53c853..756ef92bfd 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -24,6 +24,9 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)\n DEF_HELPER_3(crc32, tl, tl, tl, i32)\n DEF_HELPER_3(crc32c, tl, tl, tl, i32)\n DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)\n+DEF_HELPER_3(octeon_vmulu, i64, env, i64, i64)\n+DEF_HELPER_3(octeon_vmm0, i64, env, i64, i64)\n+DEF_HELPER_3(octeon_v3mulu, i64, env, i64, i64)\n \n /* microMIPS functions */\n DEF_HELPER_4(lwm, void, env, tl, tl, i32)\ndiff --git a/target/mips/system/machine.c b/target/mips/system/machine.c\nindex 473d3ab036..c29b7c56fa 100644\n--- a/target/mips/system/machine.c\n+++ b/target/mips/system/machine.c\n@@ -118,6 +118,17 @@ static const VMStateDescription vmstate_inactive_tc = {\n .fields = vmstate_tc_fields\n };\n \n+static const VMStateDescription vmstate_octeon_multiplier_tc = {\n+ .name = \"cpu/tc/octeon_multiplier\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT64_ARRAY(octeon.MPL, TCState, 2 * 3),\n+ VMSTATE_UINT64_ARRAY(octeon.P, TCState, 2 * 3),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n /* MVP state */\n \n static const VMStateDescription vmstate_mvp = {\n@@ -237,6 +248,27 @@ static const VMStateDescription mips_vmstate_timer = {\n }\n };\n \n+static bool mips_octeon_needed(void *opaque)\n+{\n+ MIPSCPU *cpu = opaque;\n+\n+ return cpu->env.insn_flags & INSN_OCTEON;\n+}\n+\n+static const VMStateDescription mips_vmstate_octeon_multiplier = {\n+ .name = \"cpu/octeon_multiplier\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = mips_octeon_needed,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1,\n+ vmstate_octeon_multiplier_tc, TCState),\n+ VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,\n+ vmstate_octeon_multiplier_tc, TCState),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n const VMStateDescription vmstate_mips_cpu = {\n .name = \"cpu\",\n .version_id = 21,\n@@ -353,6 +385,7 @@ const VMStateDescription vmstate_mips_cpu = {\n },\n .subsections = (const VMStateDescription * const []) {\n &mips_vmstate_timer,\n+ &mips_vmstate_octeon_multiplier,\n NULL\n }\n };\ndiff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 8a262feb1d..2eb15aa17f 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -44,10 +44,32 @@ SEQ 011100 rs:5 rt:5 rd:5 00000 101010 &cmp3 ne=0\n SNE 011100 rs:5 rt:5 rd:5 00000 101011 &cmp3 ne=1\n SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi ne=0\n SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi ne=1\n+&r2 rs rt\n+MTM0 011100 rs:5 rt:5 00000 00000 001000 &r2\n+MTP0 011100 rs:5 rt:5 00000 00000 001001 &r2\n+MTP1 011100 rs:5 rt:5 00000 00000 001010 &r2\n+MTP2 011100 rs:5 rt:5 00000 00000 001011 &r2\n+MTM1 011100 rs:5 rt:5 00000 00000 001100 &r2\n+MTM2 011100 rs:5 rt:5 00000 00000 001101 &r2\n+VMULU 011100 ..... ..... ..... 00000 001111 @r3\n+VMM0 011100 ..... ..... ..... 00000 010000 @r3\n+V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n+\n+&saa base rt\n+@saa ...... base:5 rt:5 ................ &saa\n+SAA 011100 ..... ..... 00000 00000 011000 @saa\n+SAAD 011100 ..... ..... 00000 00000 011001 @saa\n+\n+&zcb base\n+ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n+ZCBT 011100 base:5 00000 00000 11101 011111 &zcb\n \n &lx base index rd\n @lx ...... base:5 index:5 rd:5 ...... ..... &lx\n LWX 011111 ..... ..... ..... 00000 001010 @lx\n LHX 011111 ..... ..... ..... 00100 001010 @lx\n+LHUX 011111 ..... ..... ..... 10100 001010 @lx\n LBUX 011111 ..... ..... ..... 00110 001010 @lx\n+LWUX 011111 ..... ..... ..... 10000 001010 @lx\n+LBX 011111 ..... ..... ..... 10110 001010 @lx\n LDX 011111 ..... ..... ..... 01000 001010 @lx\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 73090ce6d8..cdb4d36c8e 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -13,6 +13,8 @@\n /* Include the auto-generated decoder. */\n #include \"decode-octeon.c.inc\"\n \n+typedef void gen_helper_lmi(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);\n+\n static bool octeon_check_64(DisasContext *ctx)\n {\n check_mips_64(ctx);\n@@ -222,7 +224,171 @@ static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)\n return true;\n }\n \n+static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n+{\n+ if (mop == MO_UQ && !octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+ MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;\n+\n+ gen_base_offset_addr(ctx, addr, a->base, 0);\n+\n+ if (mop == MO_UQ) {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+ TCGv_i64 old = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, a->rt);\n+ tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);\n+ } else {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old = tcg_temp_new_i32();\n+\n+ gen_load_gpr(value, a->rt);\n+ tcg_gen_extrl_i64_i32(value32, value);\n+ tcg_gen_atomic_fetch_add_i32(old, addr, value32, ctx->mem_idx, amo);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)\n+{\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+ TCGv_i64 line = tcg_temp_new_i64();\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ gen_base_offset_addr(ctx, addr, a->base, 0);\n+\n+ /*\n+ * QEMU models ZCB/ZCBT as zeroing the containing 128-byte cache line\n+ * in guest memory.\n+ */\n+ tcg_gen_andi_i64(line, addr, ~0x7fULL);\n+\n+ for (int i = 0; i < 16; i++) {\n+ TCGv_i64 slot = tcg_temp_new_i64();\n+\n+ tcg_gen_addi_i64(slot, line, i * 8);\n+ tcg_gen_qemu_st_i64(zero, slot, ctx->mem_idx, mo_endian(ctx) | MO_UQ);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_ZCBT(DisasContext *ctx, arg_zcb *a)\n+{\n+ return trans_ZCB(ctx, a);\n+}\n+\n+static ptrdiff_t octeon_tc_mpl_offset(unsigned int index)\n+{\n+ return offsetof(CPUMIPSState, active_tc.octeon.MPL[index]);\n+}\n+\n+static ptrdiff_t octeon_tc_p_offset(unsigned int index)\n+{\n+ return offsetof(CPUMIPSState, active_tc.octeon.P[index]);\n+}\n+\n+static void octeon_store_tc_field(ptrdiff_t offset, TCGv_i64 value)\n+{\n+ tcg_gen_st_i64(value, tcg_env, offset);\n+}\n+\n+static void octeon_zero_partial_product_state(void)\n+{\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ for (int i = 0; i < 2 * 3; i++) {\n+ octeon_store_tc_field(octeon_tc_p_offset(i), zero);\n+ }\n+}\n+\n+static void octeon_clear_upper_multiplier_state(void)\n+{\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ /*\n+ * MTM0 starts a new multiplier chain. Guest code relies on a single\n+ * MTM0 load making the remaining multiplier limbs zero unless later\n+ * MTM1/MTM2 instructions explicitly populate them.\n+ */\n+ octeon_store_tc_field(octeon_tc_mpl_offset(1), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(2), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(4), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(5), zero);\n+}\n+\n+static bool trans_mtm(DisasContext *ctx, arg_r2 *a, unsigned int index)\n+{\n+ if (!octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, a->rs);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(index), value);\n+ gen_load_gpr(value, a->rt);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(index + 3), value);\n+ if (index == 0) {\n+ octeon_clear_upper_multiplier_state();\n+ }\n+ octeon_zero_partial_product_state();\n+ return true;\n+}\n+\n+static bool trans_mtp(DisasContext *ctx, arg_r2 *a, unsigned int index)\n+{\n+ if (!octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, a->rs);\n+ octeon_store_tc_field(octeon_tc_p_offset(index), value);\n+ gen_load_gpr(value, a->rt);\n+ octeon_store_tc_field(octeon_tc_p_offset(index + 3), value);\n+ return true;\n+}\n+\n+static bool trans_vmul(DisasContext *ctx, arg_decode_ext_octeon1 *a,\n+ gen_helper_lmi *helper)\n+{\n+ if (!octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n+ TCGv_i64 rs = tcg_temp_new_i64();\n+ TCGv_i64 rt = tcg_temp_new_i64();\n+ TCGv_i64 rd = tcg_temp_new_i64();\n+\n+ gen_load_gpr(rs, a->rs);\n+ gen_load_gpr(rt, a->rt);\n+ helper(rd, tcg_env, rs, rt);\n+ gen_store_gpr(rd, a->rd);\n+ return true;\n+}\n+\n+TRANS(SAA, trans_saa, MO_UL);\n+TRANS(SAAD, trans_saa, MO_UQ);\n+TRANS(LBX, trans_lx, MO_SB);\n TRANS(LBUX, trans_lx, MO_UB);\n TRANS(LHX, trans_lx, MO_SW);\n+TRANS(LHUX, trans_lx, MO_UW);\n TRANS(LWX, trans_lx, MO_SL);\n+TRANS(LWUX, trans_lx, MO_UL);\n TRANS(LDX, trans_lx, MO_UQ);\n+TRANS(MTM0, trans_mtm, 0);\n+TRANS(MTM1, trans_mtm, 1);\n+TRANS(MTM2, trans_mtm, 2);\n+TRANS(MTP0, trans_mtp, 0);\n+TRANS(MTP1, trans_mtp, 1);\n+TRANS(MTP2, trans_mtp, 2);\n+TRANS(VMULU, trans_vmul, gen_helper_octeon_vmulu);\n+TRANS(VMM0, trans_vmul, gen_helper_octeon_vmm0);\n+TRANS(V3MULU, trans_vmul, gen_helper_octeon_v3mulu);\ndiff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c\nindex 4502ae2b5b..47b13a583c 100644\n--- a/target/mips/tcg/op_helper.c\n+++ b/target/mips/tcg/op_helper.c\n@@ -144,6 +144,105 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,\n return (int64_t)(int32_t)(uint32_t)tmp5;\n }\n \n+static void octeon_add_limb(uint64_t *sum, int limb_count,\n+ uint64_t value, int limb)\n+{\n+ while (limb < limb_count) {\n+ uint64_t old = sum[limb];\n+\n+ sum[limb] += value;\n+ if (sum[limb] >= old) {\n+ break;\n+ }\n+ value = 1;\n+ limb++;\n+ }\n+}\n+\n+uint64_t helper_octeon_vmulu(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t lo, hi;\n+ uint64_t sum[3] = {};\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[0], rs);\n+ sum[0] = lo;\n+ sum[1] = hi;\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[1], rs);\n+ octeon_add_limb(sum, 3, lo, 1);\n+ octeon_add_limb(sum, 3, hi, 2);\n+\n+ octeon_add_limb(sum, 3, rt, 0);\n+ octeon_add_limb(sum, 3, env->active_tc.octeon.P[0], 0);\n+ octeon_add_limb(sum, 3, env->active_tc.octeon.P[1], 1);\n+\n+ env->active_tc.octeon.P[0] = sum[1];\n+ env->active_tc.octeon.P[1] = sum[2];\n+ return sum[0];\n+}\n+\n+uint64_t helper_octeon_vmm0(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t lo = helper_octeon_vmulu(env, rs, rt);\n+\n+ /*\n+ * Complete the VMULU accumulation, then apply the MTM0-style state\n+ * update with the low result and a zero high operand.\n+ */\n+ env->active_tc.octeon.MPL[0] = lo;\n+ env->active_tc.octeon.MPL[3] = 0;\n+ for (int i = 0; i < 2 * 3; i++) {\n+ env->active_tc.octeon.P[i] = 0;\n+ }\n+ return lo;\n+}\n+\n+uint64_t helper_octeon_v3mulu(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t lo, hi;\n+ uint64_t sum[7] = {};\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[0], rs);\n+ sum[0] = lo;\n+ sum[1] = hi;\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[1], rs);\n+ octeon_add_limb(sum, 7, lo, 1);\n+ octeon_add_limb(sum, 7, hi, 2);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[2], rs);\n+ octeon_add_limb(sum, 7, lo, 2);\n+ octeon_add_limb(sum, 7, hi, 3);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[3], rs);\n+ octeon_add_limb(sum, 7, lo, 3);\n+ octeon_add_limb(sum, 7, hi, 4);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[4], rs);\n+ octeon_add_limb(sum, 7, lo, 4);\n+ octeon_add_limb(sum, 7, hi, 5);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[5], rs);\n+ octeon_add_limb(sum, 7, lo, 5);\n+ octeon_add_limb(sum, 7, hi, 6);\n+\n+ octeon_add_limb(sum, 7, rt, 0);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[0], 0);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[1], 1);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[2], 2);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[3], 3);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[4], 4);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[5], 5);\n+\n+ env->active_tc.octeon.P[0] = sum[1];\n+ env->active_tc.octeon.P[1] = sum[2];\n+ env->active_tc.octeon.P[2] = sum[3];\n+ env->active_tc.octeon.P[3] = sum[4];\n+ env->active_tc.octeon.P[4] = sum[5];\n+ env->active_tc.octeon.P[5] = sum[6];\n+ return sum[0];\n+}\n+\n /* these crc32 functions are based on target/loongarch/tcg/op_helper.c */\n target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)\n {\ndiff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target\nindex 5d17c1706e..d9dc16f8ec 100644\n--- a/tests/tcg/mips/Makefile.target\n+++ b/tests/tcg/mips/Makefile.target\n@@ -8,6 +8,17 @@ MIPS_SRC=$(SRC_PATH)/tests/tcg/mips\n # Set search path for all sources\n VPATH \t\t+= $(MIPS_SRC)\n \n+ifneq ($(findstring 64,$(TARGET_NAME)),)\n+VPATH += $(MIPS_SRC)/user/isa/octeon\n+\n+MIPS64_TESTS=octeon-insns\n+\n+TESTS += $(MIPS64_TESTS)\n+\n+octeon-insns: CFLAGS+=-mabi=64\n+run-octeon-insns: QEMU_OPTS+=-cpu Octeon68XX\n+endif\n+\n # hello-mips is 32 bit only\n ifeq ($(findstring 64,$(TARGET_NAME)),)\n MIPS_TESTS=hello-mips\ndiff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips/user/isa/octeon/octeon-insns.c\nnew file mode 100644\nindex 0000000000..e9db93d1b6\n--- /dev/null\n+++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c\n@@ -0,0 +1,145 @@\n+/*\n+ * Test Octeon-specific user-mode instructions.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \n+#include \n+\n+static uint64_t octeon_baddu(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x71095028\\n\\t\" /* baddu $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_dmul(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x71095003\\n\\t\" /* dmul $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_dpop(uint64_t rs)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \".word 0x7100502d\\n\\t\" /* dpop $10, $8 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs)\n+ : \"$8\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_seq(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x7109502a\\n\\t\" /* seq $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_sne(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x7109502b\\n\\t\" /* sne $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_vmulu(uint64_t mpl0, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[mpl0]\\n\\t\"\n+ \"move $9, $0\\n\\t\"\n+ \".word 0x71090008\\n\\t\" /* mtm0 $8, $9 */\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x7109500f\\n\\t\" /* vmulu $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [mpl0] \"r\" (mpl0), [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_vmm0(uint64_t mpl0, uint64_t p0,\n+ uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[mpl0]\\n\\t\"\n+ \"move $9, $0\\n\\t\"\n+ \".word 0x71090008\\n\\t\" /* mtm0 $8, $9 */\n+ \"move $8, %[p0]\\n\\t\"\n+ \"move $9, $0\\n\\t\"\n+ \".word 0x71090009\\n\\t\" /* mtp0 $8, $9 */\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x71095010\\n\\t\" /* vmm0 $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [mpl0] \"r\" (mpl0), [p0] \"r\" (p0),\n+ [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+int main(void)\n+{\n+ assert(octeon_baddu(0x123, 0x0f0) == 0x13);\n+ assert(octeon_dmul(0x12345678, 0x10) == 0x123456780);\n+ assert(octeon_dpop(0xf0f0f0f0f0f0f0f0ULL) == 32);\n+ assert(octeon_seq(0xabc, 0xabc) == 1);\n+ assert(octeon_seq(0xabc, 0xdef) == 0);\n+ assert(octeon_sne(0xabc, 0xabc) == 0);\n+ assert(octeon_sne(0xabc, 0xdef) == 1);\n+ assert(octeon_vmulu(5, 7, 11) == 46);\n+ assert(octeon_vmm0(5, 13, 7, 11) == 59);\n+\n+ return 0;\n+}\ndiff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target\nnew file mode 100644\nindex 0000000000..042855844a\n--- /dev/null\n+++ b/tests/tcg/mips64/Makefile.target\n@@ -0,0 +1,20 @@\n+# -*- Mode: makefile -*-\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# MIPS64 - included from tests/tcg/Makefile.target\n+#\n+\n+MIPS64_SRC=$(SRC_PATH)/tests/tcg/mips64\n+MIPS_OCTEON_SRC=$(SRC_PATH)/tests/tcg/mips/user/isa/octeon\n+\n+# Set search path for all sources\n+VPATH \t\t+= $(MIPS64_SRC) $(MIPS_OCTEON_SRC)\n+\n+MIPS64_TESTS=octeon-insns\n+\n+TESTS += $(MIPS64_TESTS)\n+\n+$(MIPS64_TESTS): CFLAGS+=-mabi=64\n+\n+run-octeon-insns: QEMU_OPTS+=-cpu Octeon68XX\ndiff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target\nnew file mode 100644\nindex 0000000000..dbc5f8dc5f\n--- /dev/null\n+++ b/tests/tcg/mips64el/Makefile.target\n@@ -0,0 +1,8 @@\n+# -*- Mode: makefile -*-\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# MIPS64 little-endian - included from tests/tcg/Makefile.target\n+#\n+\n+include $(SRC_PATH)/tests/tcg/mips64/Makefile.target\n","prefixes":["v2","05/13"]}